Lua script-based electronic load automatic test system and method

Abstract

The application relates to the technical field of electronic instrument automatic test, and discloses an electronic load automatic test system and method based on a Lua script. The system intercepts a discrete waveform instruction, extracts a transient change rate matrix, predicts an overvoltage risk, calculates a target steepness limited by a non-zero lower limit boundary by using an electrothermal reconstruction model, performs geometric interpolation on the instruction, smoothes a current change rate to limit a recoil voltage, bypasses a kernel state to write bottom layer data into a static storage mapping area by using a direct memory mapping mechanism, converts a sampling interrupt into a coroutine awakening instruction, and triggers a test coroutine to directly read data. The application eliminates operating system polling delay, realizes clock cycle alignment of software assertion and hardware sampling, and prevents hardware overload damage and system deadlock.

Description

Technical Field

[0001] This invention relates to the field of automated testing technology for electronic instruments, and in particular to an automated testing system and method for electronic loads based on Lua scripts. Background Technology

[0002] In existing automated testing of electronic loads, discrete step level control logic is typically used for waveform command issuance. During high-frequency load testing, the discrete step commands issued by the script layer directly drive the underlying hardware of the electronic load device. Due to the inherent parasitic inductance within the actual power circuit, the discrete step commands generate extremely high current change rates, inducing transient backflash voltages across the parasitic inductors. Simultaneously, existing test systems typically employ a kernel-user bus polling mechanism when transmitting status data back to the script layer. This bus polling mechanism involves task scheduling and memory copying, inevitably introducing time delays. When a transient backflash voltage occurs, the time delay of the bus polling mechanism causes a time misalignment between the script layer's reading node and the underlying hardware's sampling node. This time misalignment prevents the test script from accurately capturing transient extreme values, ultimately leading to incorrect status judgments. Summary of the Invention

[0003] This invention provides an automated testing system and method for electronic loads based on Lua scripts, in order to solve the technical problems in existing electronic load testing systems, such as the risk of hardware overload caused by transient backflash voltage induced by discrete step instructions in parasitic inductance circuits, and the time delay introduced by the traditional bus polling mechanism causing time misalignment between script reading nodes and hardware sampling nodes, resulting in inaccurate state determination conclusions.

[0004] In view of the above problems, the present invention provides an automated testing system for electronic loads based on Lua scripts. The system includes an electronic load device body, which houses a main control chip. Logically, the system, from bottom to top, includes a bottom-level driver layer, a physical perception and timing scheduling agent hub, an API encapsulation layer, a Lua engine layer, and a script application layer. The physical perception and timing scheduling agent hub includes: The discrete step feature extraction unit is configured to intercept the discrete waveform instruction sequence issued by the script application layer, extract the transient rate of change matrix of the discrete waveform instruction sequence, compare the transient rate of change matrix with a preset first physical threshold set, and generate a first trigger flag bit. The parasitic parameter coupled waveform reconstruction unit is configured to acquire the parasitic parameters and thermal state data of the electronic load device body, and in response to the continuous calculation of the transient rate of change matrix, substitute the discrete waveform instruction sequence, the parasitic parameters and the thermal state data into a preset electrothermal reconstruction model for calculation. The electrothermal reconstruction model adaptively adjusts the reconstruction amplitude based on the value of the first trigger flag, generates a target reconstruction signal sequence, and sends the target reconstruction signal sequence to the underlying driver layer. The timing interrupt mapping unit is configured to intercept the asynchronous sampling interrupt signal and queue data stream generated by the underlying driver layer after executing the target reconstruction signal sequence, use the direct memory mapping mechanism to write the queue data stream into the static storage mapping area to generate the target data block, and convert the asynchronous sampling interrupt signal into a coroutine wake-up instruction vector. The coroutine-state closed-loop assertion unit is configured to use the coroutine wake-up instruction vector as the trigger source to release the suspended state of the target test coroutine in the Lua engine layer, read the target data block in the static storage mapping area through the target test coroutine, and compare the target data block based on the assertion conditions preset by the script application layer to generate a status judgment word.

[0005] The technical solution provided in this application has at least the following technical effects: This invention calculates the target steepness using an electrothermal reconstruction model and performs geometric interpolation on discrete instructions, smoothing the transient current change rate of the underlying hardware. This limits the backlash voltage caused by parasitic inductance to within the breakdown voltage threshold of the controlled device, thus avoiding hardware overload damage.

[0006] This invention forces the target steepness to maintain a value greater than 0 under extreme overheating or overpressure conditions by setting a non-zero lower limit boundary determined by a preset lower limit coefficient composite, thus avoiding the waveform drive data from dropping to 0 and preventing system deadlock interruption caused by the stagnation of the underlying load action.

[0007] This invention uses a direct memory mapping mechanism to write underlying data and uses hardware interrupts to trigger coroutine wake-up instructions, eliminating the kernel-mode memory copying and task polling waiting steps of traditional operating systems. It achieves clock cycle alignment between software assertion comparison nodes and hardware sampling nodes, eliminates the phenomenon of missed transient data detection caused by time delay, and improves the accuracy of status judgment word output. Attached Figure Description

[0008] Figure 1 A flowchart of an automated electronic load testing method based on Lua scripts provided in an embodiment of the present invention; Figure 2 The logical architecture diagram of the automated electronic load testing system based on Lua script provided in the embodiments of the present invention is shown. Detailed Implementation

[0009] The above technical solutions will now be described in detail with reference to the accompanying drawings and specific embodiments to provide a better understanding of them. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. It should be understood that the present invention is not limited to the exemplary embodiments used only to explain the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Furthermore, it should be noted that, for ease of description, only the parts related to the present invention are shown in the drawings, not all of them.

[0010] Example: Please refer to Figure 1 and Figure 2 The electronic load device itself is equipped with a main control chip. The physical topology of the main control chip is divided into a hardware resource area that carries the analog-to-digital converter, digital-to-analog converter, and power circuit, and an application layer resource area that executes the Lua engine layer. The physical sensing and timing scheduling agent hub is deployed between the underlying driver layer and the API encapsulation layer, and the physical sensing and timing scheduling agent hub constructs an isolation gateway between the hardware resource area and the application layer resource area.

[0011] As the script application layer issues a discrete waveform instruction sequence, the discrete step feature extraction unit intercepts it. This unit extracts the target amplitude difference and time interval between adjacent instruction breakpoints, performs a division operation on the target amplitude difference and time interval to calculate the step slope, and outputs a transient rate of change matrix. The parasitic parameter coupled waveform reconstruction unit receives the transient rate of change matrix, extracts parasitic parameters and thermal state data, and substitutes these data into the electrothermal reconstruction model to perform mathematical calculations, outputting a target reconstructed signal sequence. The underlying driver layer receives the target reconstructed signal sequence, executes it, and triggers an asynchronous sampling interrupt signal. The timing interrupt mapping unit intercepts the asynchronous sampling interrupt signal, initiates a direct memory mapping mechanism to write the underlying queue data stream into the static storage mapping area, and synchronously converts the asynchronous sampling interrupt signal into a coroutine wake-up instruction vector. The coroutine-state closed-loop assertion unit receives the coroutine wake-up instruction vector and releases the suspended state of the target test coroutine within the Lua engine layer. The target test coroutine reads data from the static storage mapping area, performs assertion condition comparison, and outputs a status judgment word. Control data flow transmission skips the operating system kernel-mode and user-mode bus polling phases, and the judgment action execution node and asynchronous sampling interrupt signal complete timestamp alignment at the main control chip clock cycle node.

[0012] In response to the continuous calculation of the transient rate of change matrix, the parasitic parameter coupled waveform reconstruction unit performs continuous calculations of the electrothermal reconstruction model based on the state of the first trigger flag. When the first trigger flag is in an invalid state (0), the internal calculation formula of the electrothermal reconstruction model truncates the thermal intervention link, the target steepness approximates the base steepness, and the system maintains the original base waveform driving capability; when the first trigger flag is in an valid state (1), the electrothermal reconstruction model initiates thermal boundary suppression calculations. The parasitic parameter coupled waveform reconstruction unit sends the target reconstruction signal sequence to the underlying driving layer.

[0013] To generate the first trigger flag, the Discrete Step Feature Extraction Unit reads the parasitic inductance parameters preset in the power circuit of the electronic load device. The parasitic inductance parameters are separated from the dynamic real-time measurement steps during operation. The parasitic inductance parameters are extracted from the impedance sweep calibration results performed by the hardware impedance analyzer during the factory manufacturing phase. The calibration results are converted into a static constant data type and written into a pre-allocated hardware register within the physical sensing and timing scheduling agent center. The Discrete Step Feature Extraction Unit retrieves the parasitic inductance parameters from the hardware register and multiplies them with each numerical element in the transient rate of change matrix, outputting the expected voltage sequence. When any numerical element in the expected voltage sequence is greater than the breakdown voltage threshold of the controlled device, the Discrete Step Feature Extraction Unit assigns a high-level 1 value to the first trigger flag; if all numerical elements in the expected voltage sequence are not greater than the breakdown voltage threshold of the controlled device, the Discrete Step Feature Extraction Unit assigns a low-level 0 value to the first trigger flag.

[0014] When the first trigger flag is in valid state 1, the parasitic parameter coupling waveform reconstruction unit initiates the parasitic parameter and thermal state data extraction command. Addressing the thermal conduction hysteresis response of the physical thermistor component, the parasitic parameter coupling waveform reconstruction unit internally wakes up the state observer to perform transient junction temperature deduction. The state observer reads the reference ambient temperature collected by the thermistor component. Simultaneously, the state observer extracts the power loop load current value returned by the underlying driver layer. The state observer performs a time-domain integration operation on the square of the load current value and multiplies the integration result with the equivalent internal resistance of the power loop to obtain Joule heat dissipation energy data. The state observer inputs the Joule heat dissipation energy data into the first-order equivalent thermal impedance network model. The Joule heat dissipation energy data is multiplied by the preset thermal resistance parameter of the first-order equivalent thermal impedance network model and divided by the heat capacity parameter, outputting the instantaneous heat dissipation temperature rise value. The parasitic parameter coupling waveform reconstruction unit performs an addition operation on the reference ambient temperature value and the instantaneous heat dissipation temperature rise value to generate the real-time junction temperature value. The parasitic parameter coupled waveform reconstruction unit performs a division operation between the difference between the real-time junction temperature and the reference ambient temperature and the difference between the limit junction temperature of the electronic load device body and the reference ambient temperature, and outputs the normalized thermal index.

[0015] The parasitic parameter coupled waveform reconstruction unit reads the corresponding element values ​​within the expected voltage sequence. It then performs a division operation between these values ​​and the controlled device breakdown voltage threshold, outputting a normalized overvoltage term. The aforementioned normalized heat index is defined as follows: .

[0016] Accompanied by normalized heat index With normalized overpressure term The generation of parasitic parameter coupled waveform reconstruction unit initiates electrothermal reconstruction model, and the target kurtosis is calculated using the following mathematical formula. :

[0017] in, Based on the steepness, The value of the first trigger flag. The preset first lower bound coefficient is included within the non-zero lower bound boundary. The preset second lower limit coefficient is included within the non-zero lower limit boundary. As the first weighting factor, is the second weighting factor, tanh is the hyperbolic tangent function, and exp is the natural exponential function.

[0018] To make the target steep The parasitic parameter-coupled waveform reconstruction unit converts the data into underlying physical level drive data and imports the target kurtosis into a preset Bézier curve generator. The parasitic parameter-coupled waveform reconstruction unit sets the first and second control points of the Bézier curve. The target kurtosis is set as the upper limit of the ratio of the difference between the ordinate and the abscissa values ​​between the first and second control points, constituting a maximum first derivative constraint. Using this maximum first derivative constraint, the parasitic parameter-coupled waveform reconstruction unit performs geometric interpolation on the step breakpoints of the discrete waveform command sequence, outputting a discrete numerical point array. This numerical point array constitutes the target reconstruction signal sequence, which the parasitic parameter-coupled waveform reconstruction unit sends to the digital-to-analog converter configured within the underlying drive layer. The digital-to-analog converter converts the numerical point array into a physical electrical signal output.

[0019] Before the underlying driver layer executes physical electrical signal output and triggers the analog-to-digital converter sampling action, the static random access memory (SRAM) inside the main control chip performs a physical address segment allocation operation. This operation allocates contiguous unmanaged static storage media within the system storage topology. This unmanaged static storage media is configured as a static memory mapping area. This static memory mapping area is separated from the dynamically garbage-collected memory stack within the Lua engine layer in terms of physical address addressing routing. The static memory mapping area is immune to memory pointer erasure and write operations by the dynamic garbage collection mechanism.

[0020] When the analog-to-digital converter inside the underlying driver layer completes its hardware sampling cycle, the underlying driver layer generates an asynchronous sampling interrupt signal. The timing interrupt mapping unit intercepts the asynchronous sampling interrupt signal and triggers the direct memory mapping mechanism controller inside the main control chip. The direct memory mapping mechanism controller takes over the memory bus control and writes the queue data stream from the queue buffer inside the underlying driver layer, bypassing the central processing unit kernel-mode transport node, into the static memory mapping area to generate the target data block. With the completion of the physical write operation of the target data block, the timing interrupt mapping unit reads the allocated starting address offset in the static memory mapping area. The timing interrupt mapping unit converts the starting address offset type to a Lua engine-compatible external function interface pointer. The timing interrupt mapping unit performs a bit-field concatenation operation between the external function interface pointer and the underlying clock timestamp, outputting a coroutine wake-up instruction vector.

[0021] The coroutine-state closed-loop assertion unit receives the coroutine wake-up instruction vector and extracts the external function interface pointer and underlying clock timestamp from within the instruction vector. It pushes the program counter pointer of the main control chip kernel onto the stack, and the hardware interrupt vector table guides the program counter to jump to the physical address of the system-preset coroutine wake-up function. Simultaneously, the external function interface pointer is pushed into the main control chip's general-purpose register as an input parameter. The coroutine wake-up function executes within a preset clock cycle threshold, significantly smaller than the conventional operating system kernel-state scheduling latency. The execution context of the target test coroutine within the Lua engine layer is reloaded, and the suspended state of the target test coroutine is released. The target test coroutine extracts the external function interface pointer from the general-purpose register, bypasses the kernel-state memory copy stage, and reads the target data block from the static storage mapping area in user mode. The target test coroutine imports the target data block into the script application layer's preset assertion conditions for logical comparison operations and outputs a status judgment word. Based on the function jump instruction vector of the coroutine wake-up instruction, the generation node of the status decision word and the trigger node of the underlying hardware asynchronous sampling interrupt signal are aligned with the physical clock cycle on the system time axis.

[0022] The parasitic parameter coupled waveform reconstruction unit has preset physical boundary protection parameters. The preset first lower limit coefficient is calibrated based on the minimum drive response capability required to be retained by the electronic load device under extreme thermal stress conditions. The preset second lower limit coefficient is calibrated based on the minimum resonance suppression margin required to be retained under transient recoil voltage extreme scenarios. The first and second lower limit coefficients together set the non-zero bottom line boundary of the underlying mathematical operations of the electrothermal reconstruction model. The parasitic parameter coupled waveform reconstruction unit extracts a first weighting factor and a second weighting factor. The first weighting factor is calibrated within a range greater than 3 to ensure that the output value of the hyperbolic tangent function approaches the saturation upper limit of 1 when the normalized thermal exponent approaches 1. The second weighting factor is mapped and calibrated based on the natural exponential function to meet the dimensionality reduction convergence rate requirements of the transient recoil voltage extreme.

[0023] As external hardware testing conditions generate physical extreme value inputs, the electrothermal reconstruction model within the parasitic parameter coupled waveform reconstruction unit performs mathematical anti-collapse deduction calculations. When the real-time junction temperature approaches the limiting junction temperature of the electronic load device, the normalized thermal index approaches 1. Based on the calibration attribute that the first weighting factor is greater than 3, the product of the first weighting factor and the normalized thermal index is input into the hyperbolic tangent function for calculation, and the algebraic extreme value output by the hyperbolic tangent function approaches 1. As the value within the expected voltage sequence increases, the value of the normalized overvoltage term approaches positive infinity. The product of the negative value of the second weighting factor and the normalized overvoltage term is input into the natural exponential function for calculation, and the algebraic extreme value output by the natural exponential function converges to 0.

[0024] When the first trigger flag is high (1), the formula for calculating the thermal intervention multiplier within the electrothermal reconstruction model converges to the first lower bound coefficient. The formula for calculating the resonance suppression multiplier within the electrothermal reconstruction model converges to the second lower bound coefficient. The parasitic parameter coupled waveform reconstruction unit extracts the basic kurtosis, the first lower bound coefficient, and the second lower bound coefficient. The parasitic parameter coupled waveform reconstruction unit then performs a multiplication operation on the basic kurtosis, the first lower bound coefficient, and the second lower bound coefficient. The lower limit extremum of the target kurtosis is equal to the algebraic product of the basic kurtosis, the first lower bound coefficient, and the second lower bound coefficient.

[0025] Based on the fact that the basic kurtosis, the first lower limit coefficient, and the second lower limit coefficient are all constants greater than 0, the final output of the electrothermal reconstruction model has a target kurtosis value greater than 0. This target kurtosis value greater than 0 cuts off the computational path where the first-order derivative constraint becomes a zero vector. The first-order derivative constraint ensures that the discrete numerical point array output by the digital-to-analog converter maintains an increasing or decreasing geometric slope, the underlying load action maintains a continuous current transition state, and the system bus data flow cuts off any stagnant or interrupted links.

[0026] When the missing state signal of the floating-point arithmetic hardware unit in the main control chip core is triggered, the electrothermal reconstruction model in the parasitic parameter coupled waveform reconstruction unit loads a discrete lookup table to perform routing. The calculation trajectories of the hyperbolic tangent function and the natural exponential function are transformed to generate a first one-dimensional discrete mapping array and a second one-dimensional discrete mapping array. The first one-dimensional discrete mapping array and the second one-dimensional discrete mapping array are burned into the read-only memory (ROM) medium of the main control chip. The parasitic parameter coupled waveform reconstruction unit extracts the normalized thermal index and the normalized overvoltage term, and inputs the normalized thermal index and the normalized overvoltage term as memory address offsets into the ROM. The ROM returns the adjacent discrete array key values ​​according to the memory address offsets. The parasitic parameter coupled waveform reconstruction unit performs linear interpolation algebra operations on the adjacent discrete array key values ​​to generate thermal interference multipliers and resonance suppression multipliers.

[0027] For the algebraic structure transformation path of the operator, the parasitic parameter coupled waveform reconstruction unit loads a logarithmic limiting operator as an algebraic substitution operation for the hyperbolic tangent function. The parasitic parameter coupled waveform reconstruction unit inputs the normalized thermal exponent into the logarithmic limiting operator, which outputs the boundary numerical mapping result. Simultaneously, the parasitic parameter coupled waveform reconstruction unit loads a fractional rational function operator as an algebraic substitution operation for the natural exponential function. The mathematical denominator of the fractional rational function operator is set to the algebraic sum of the constant 1, the second weighting factor, and the square of the normalized overpressure term; the mathematical numerator of the fractional rational function operator is set to the constant 1. The parasitic parameter coupled waveform reconstruction unit inputs the normalized overpressure term into the fractional rational function operator to perform a division operation; the fractional rational function operator outputs the target attenuation scalar.

[0028] In the underlying execution chain of the electronic load device, a thermistor sensor component senses changes in ambient heat and outputs a resistance change signal. A front-end signal conditioning circuit receives the resistance change signal and converts it into an analog voltage level. An analog-to-digital converter (ADC) extracts the analog voltage level and performs clock-synchronized discrete sampling to generate thermal state data input to the parasitic parameter coupled waveform reconstruction unit. Accompanying the parasitic parameter coupled waveform reconstruction unit is the generation of a target reconstruction signal sequence, which is written to the underlying driver layer's ADC via a parallel data bus array within the main control chip. The ADC converts the digital array of the target reconstruction signal sequence into an analog level drive signal. This analog level drive signal is injected into the gate port of the power metal-oxide-semiconductor field-effect transistor (MOSFET) array, modulating the load current passing through the source and drain of the MOSFET array.

[0029] The logic structure of the discrete step feature extraction unit, parasitic parameter coupled waveform reconstruction unit, timing interrupt mapping unit, and coroutine-state closed-loop assertion unit is converted into a binary machine instruction sequence by the system compiler. This binary machine instruction sequence is then programmed into a specific sector matrix of the flash memory inside the main control chip. The central processing unit of the main control chip reads the binary machine instruction sequence from the specific sector matrix of the flash memory, triggering data register transfers and level state transitions.

[0030] The binary machine instruction sequence is encapsulated in a non-transitory computer-readable storage medium, which is specifically assembled as a solid-state drive storage array, an electrically erasable programmable read-only memory chip, or a magnetic storage disk.

[0031] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An automated testing system for electronic loads based on Lua scripts, the system comprising an electronic load device body, wherein the electronic load device body contains a main control chip, and the system, in its logical architecture from bottom to top, comprises a bottom-level driver layer, a physical perception and timing scheduling agent hub, an API encapsulation layer, a Lua engine layer, and a script application layer, characterized in that, The physical sensing and time-series scheduling agent center includes: The discrete step feature extraction unit is configured to intercept the discrete waveform instruction sequence issued by the script application layer, extract the transient rate of change matrix of the discrete waveform instruction sequence, compare the transient rate of change matrix with a preset first physical threshold set, and generate a first trigger flag bit. The parasitic parameter coupled waveform reconstruction unit is configured to acquire the parasitic parameters and thermal state data of the electronic load device body, and in response to the continuous calculation of the transient rate of change matrix, substitute the discrete waveform instruction sequence, the parasitic parameters and the thermal state data into a preset electrothermal reconstruction model for calculation. The electrothermal reconstruction model adaptively adjusts the reconstruction amplitude based on the value of the first trigger flag, generates a target reconstruction signal sequence, and sends the target reconstruction signal sequence to the underlying driver layer. The timing interrupt mapping unit is configured to intercept the asynchronous sampling interrupt signal and queue data stream generated by the underlying driver layer after executing the target reconstruction signal sequence, use the direct memory mapping mechanism to write the queue data stream into the static storage mapping area to generate the target data block, and convert the asynchronous sampling interrupt signal into a coroutine wake-up instruction vector. The coroutine-state closed-loop assertion unit is configured to use the coroutine wake-up instruction vector as the trigger source to release the suspended state of the target test coroutine in the Lua engine layer, read the target data block in the static storage mapping area through the target test coroutine, and compare the target data block based on the assertion conditions preset by the script application layer to generate a status judgment word.

2. The automated electronic load testing system based on Lua scripts according to claim 1, characterized in that, The discrete step feature extraction unit compares the transient rate of change matrix with a preset first physical threshold set to generate a first trigger flag, including: Extract the parasitic inductance parameters and the breakdown voltage threshold of the controlled device in the power circuit of the electronic load device body; The product of the parasitic inductance parameter and each element in the transient rate of change matrix is ​​defined as the expected voltage sequence; If any element in the expected voltage sequence is greater than the breakdown voltage threshold of the controlled device, the first trigger flag will be set to an active state. If none of the elements in the expected voltage sequence are greater than the breakdown voltage threshold of the controlled device, the first trigger flag is set to an invalid state.

3. The automated electronic load testing system based on Lua scripts according to claim 2, characterized in that, The parasitic parameter coupled waveform reconstruction unit substitutes the discrete waveform command sequence, the parasitic parameters, and the thermal state data into a preset electrothermal reconstruction model to generate a target reconstruction signal sequence, including: Extract thermal state parameters characterizing the degree to which the real-time junction temperature approaches the limit, and overvoltage risk parameters characterizing the degree to which the expected voltage sequence approaches the breakdown voltage threshold of the controlled device; The basic steepness of the discrete waveform command sequence is attenuated using a nonlinear easing operator to obtain the target steepness. The attenuation magnitude of the basic steepness is positively correlated with the thermal state parameter and the overpressure risk parameter. The attenuation calculation controls the mapping slope corresponding to the thermal state parameter through a preset first weighting factor and controls the attenuation rate corresponding to the overpressure risk parameter through a preset second weighting factor. The target steepness is constrained by a non-zero lower limit boundary determined by a combination of multiple preset lower limit coefficients. The discrete waveform instruction sequence is reconstructed using the target kurtosis as a first-order derivative constraint to generate the target reconstructed signal sequence.

4. The automated electronic load testing system based on Lua scripts according to claim 3, characterized in that, The thermal state parameter is the normalized heat index. The overpressure risk parameter is a normalized overpressure term. The nonlinear mitigation operator calculates the target steepness according to the following mathematical formula. : ； in, The aforementioned basic steepness, The value of the first trigger flag. The preset first lower limit coefficient is included in the non-zero lower limit boundary. The preset second lower limit coefficient is included in the non-zero lower limit boundary. The first weighting factor, is the second weighting factor, tanh is the hyperbolic tangent function, and exp is the natural exponential function.

5. The automated electronic load testing system based on Lua scripts according to claim 1, characterized in that, The static storage mapping area is an unmanaged static storage medium independent of the Lua engine layer dynamic garbage collection stack; the timing interrupt mapping unit is further configured as follows: After the direct memory mapping mechanism is triggered to write the queue data stream into the static storage mapping area, the target storage address is extracted and the target storage address is encapsulated as an external function interface pointer. The external function interface pointer is bound to the underlying clock timestamp and encapsulated as the coroutine wake-up instruction vector.

6. The automated electronic load testing system based on Lua scripts according to claim 5, characterized in that, The coroutine-state closed-loop assertion unit is further configured as follows: Parse the coroutine wake-up instruction vector and restore the execution context of the target test coroutine within a preset clock cycle threshold; In the execution context, the external function interface pointer is invoked to locate and read the target data block.

7. A method for automated testing of electronic loads based on Lua scripts, applied to an automated testing system for electronic loads based on Lua scripts as described in any one of claims 1 to 6, characterized in that, The method includes the following steps: Intercept discrete waveform command sequences, extract the transient rate of change matrix of the discrete waveform command sequences, compare the transient rate of change matrix with a preset first physical threshold set, and generate a first trigger flag bit; The parasitic parameters and thermal state data of the electronic load device body are obtained. In response to the continuous calculation of the transient rate of change matrix, the discrete waveform instruction sequence, the parasitic parameters and the thermal state data are substituted into a preset electrothermal reconstruction model for calculation. The electrothermal reconstruction model adaptively adjusts the reconstruction amplitude based on the value of the first trigger flag bit, generates a target reconstruction signal sequence, and outputs it to the underlying execution flow. Intercept the asynchronous sampling interrupt signal and queue data stream generated after executing the target reconstruction signal sequence, use the direct memory mapping mechanism to write the queue data stream into the static storage mapping area to generate the target data block, and convert the asynchronous sampling interrupt signal into a coroutine wake-up instruction vector; Using the coroutine wake-up command vector as the trigger source, the suspended state of the target test coroutine is released. The target test coroutine reads the target data block in the static storage mapping area and compares it based on preset assertion conditions to generate a status judgment word.

8. The automated electronic load testing method based on Lua scripts according to claim 7, characterized in that, The step of substituting the discrete waveform command sequence, the parasitic parameters, and the thermal state data into a preset electrothermal reconstruction model to generate a target reconstructed signal sequence further includes: Extract thermal state parameters characterizing the degree to which the real-time junction temperature approaches the limit, and overvoltage risk parameters characterizing the degree to which the expected voltage sequence approaches the breakdown voltage threshold of the controlled device; The basic steepness of the discrete waveform command sequence is attenuated using a nonlinear easing operator to obtain the target steepness. The attenuation magnitude of the basic steepness is positively correlated with the thermal state parameter and the overpressure risk parameter. The attenuation calculation controls the mapping slope corresponding to the thermal state parameter through a preset first weighting factor and controls the attenuation rate corresponding to the overpressure risk parameter through a preset second weighting factor. The target steepness is constrained by a non-zero lower limit boundary determined by a combination of multiple preset lower limit coefficients. The discrete waveform instruction sequence is reconstructed using the target kurtosis as a first-order derivative constraint to generate the target reconstructed signal sequence.

9. The automated electronic load testing method based on Lua scripts according to claim 7, characterized in that, The step of writing the queue data stream into the static storage mapping area to generate the target data block using the direct memory mapping mechanism further includes: During the time period triggered by the asynchronous sampling interrupt signal, the queue data stream is written to the static storage mapping area, which is independent of the dynamic garbage collection mechanism memory stack, using the direct memory mapping mechanism. Generate an external function interface pointer pointing to the static storage mapping area, and embed the external function interface pointer into the coroutine wake-up instruction vector.

10. The automated electronic load testing method based on Lua scripts according to claim 7, characterized in that, The step of releasing the suspended state of the target test coroutine using the coroutine wake-up command vector as the trigger source further includes: Within a preset time period after receiving the coroutine wake-up instruction vector, the execution stack is switched and the suspended target test coroutine is woken up, so that the comparison action execution node based on the assertion condition and the triggering node of the asynchronous sampling interrupt signal are aligned in time period.

Images