Concurrent transaction timeout monitoring system, computing device, and electronic device

Abstract

The present disclosure relates to a concurrent transaction timeout monitoring system, a computing device and an electronic device. The system comprises: a scheduling unit, which allocates independent monitoring channels for timeout monitoring for a plurality of concurrently transmitted transactions captured on a network-on-chip; at least one monitoring unit, which is mapped to a set type transaction initiated through the network-on-chip, each monitoring unit comprising a plurality of monitoring channels for monitoring the plurality of concurrently transmitted transactions respectively, each monitoring channel being configured to independently track a response delay time of a transaction through a respective counter, and trigger a timeout feedback task when the response delay time reaches a preset time threshold and a response signal of the monitored transaction is still not detected; and an output unit, which is configured to drive a corresponding response channel in the network-on-chip to return a timeout response signal to a host device in response to the timeout feedback task triggered by the monitoring channel. The system of the present embodiment can provide accurate timeout tracking for each transaction.

Description

Technical Field

[0001] This disclosure relates to the field of on-chip network communication technology, and more specifically, to a concurrent transaction timeout monitoring system for on-chip networks, a computing device, and an electronic device. Background Technology

[0002] Network on Chip (NOC) is a communication architecture for efficient interconnection between various hardware modules within a chip. By integrating routers, links, and communication protocols, it supports concurrent, high-bandwidth data transmission between multiple master and slave devices. In fields such as high-performance computing chips, artificial intelligence accelerators, and data center interconnects, NOC has become a core infrastructure for realizing large-scale parallel computing. The Advanced eXtensible Interface (AXI) protocol is a widely adopted high-performance bus communication protocol in NOC. It defines the transaction transmission specifications between master and slave devices, including read address channels, read data channels, write address channels, write data channels, and write response channels, supporting concurrent transmission of various transaction types.

[0003] In computing devices that support large-scale concurrent transactions, transaction timeout monitoring is a key mechanism to ensure operational reliability. When a transaction fails to complete within the expected time due to reasons such as device response delay, network congestion, or device failure, the lack of an effective timeout detection and handling mechanism may cause the master device to wait for a long time, which may lead to device deadlock or severe performance degradation. Summary of the Invention

[0004] One objective of this disclosure is to provide a technical solution for timeout monitoring of multiple transactions concurrently transmitted on an on-chip network.

[0005] According to a first aspect of this disclosure, a concurrent transaction timeout monitoring system is provided, comprising: The scheduling unit is configured to capture transactions initiated by the master device through the on-chip network and allocate independent monitoring channels for timeout monitoring of multiple transactions that are concurrently transmitted on the on-chip network. At least one monitoring unit, mapped to a specified type of transaction initiated through the on-chip network, and configured to perform timeout monitoring on the specified type of transaction initiated through the on-chip network; the monitoring unit includes multiple monitoring channels for monitoring multiple concurrently transmitted transactions respectively; each monitoring channel is equipped with an independent counter, and each monitoring channel is configured to independently track the response delay time of a transaction using its own counter, and trigger a timeout feedback task for the corresponding monitored transaction when the response delay time reaches a preset time threshold and no response signal of the monitored transaction is detected; and, An output unit is configured to, in response to the timeout feedback task triggered by the monitoring channel, drive the response channel of the transaction pointed to by the timeout feedback task in the on-chip network to return a timeout response signal corresponding to the transaction to the master device.

[0006] Optionally, the system includes two monitoring units, namely a first monitoring unit and a second monitoring unit, wherein the first monitoring unit is mapped to write transactions initiated through the on-chip network, and the second monitoring unit is mapped to read transactions initiated through the on-chip network. The monitoring channel of the first monitoring unit is configured to perform timeout monitoring with a preset first time threshold; the monitoring channel of the second monitoring unit is configured to perform timeout monitoring with a preset second time threshold.

[0007] Optionally, the at least one monitoring unit includes a first monitoring unit, which is mapped to a write transaction of a predetermined type initiated through the on-chip network; wherein, the write transaction of the predetermined type refers to a write transaction in which the master device can only initiate subsequent transactions after receiving a corresponding response signal.

[0008] Optionally, the write transaction of the specified type includes barrier transactions and atomic operation transactions with returned data; wherein, the response channel on the on-chip network corresponding to the barrier transaction is a write response channel, and the response channel on the on-chip network corresponding to the atomic operation failure is a read data channel.

[0009] Optionally, each monitoring channel of the monitoring unit is provided with a response channel identifier field to store the response channel identifier of the monitored transaction; the timeout feedback task carries the transaction identifier of the monitored transaction and the response channel identifier stored in the response channel identifier field.

[0010] Optionally, the number of monitoring channels included in the monitoring unit is the same as the maximum concurrent number of the set type of transactions mapped by the corresponding monitoring unit on the on-chip network; the monitoring channel is provided with a channel identifier field, and the channel identifier field stores a transaction identifier that uniquely corresponds to the identified monitoring channel; The monitoring and scheduling unit is configured to: determine the target monitoring unit for the corresponding transaction mapping based on the transaction initiation signal, and allocate the corresponding transaction to the monitoring channel in the target monitoring unit that matches the transaction identifier for timeout monitoring based on the transaction identifier in the transaction initiation signal.

[0011] Optionally, each monitoring channel of the monitoring unit is provided with a status identifier field, which is used to indicate whether the corresponding monitoring channel is in an effective monitoring state.

[0012] Optionally, the system further includes a first-level counter; the independent counter set in the monitoring channel is a second-level counter; The first-level counter is configured to generate a counting enable signal at a preset period, wherein the preset period is an integer multiple of the system clock period; the second-level counter is configured to perform a counting accumulation once each time the counting enable signal is received when the monitoring channel to which it belongs is in an effective monitoring state, and the current count value of the second-level counter represents the response delay time of the monitored transaction of the monitoring channel to which it belongs.

[0013] Optionally, the monitoring parameters of the system are configured through a configuration file, and the monitoring parameters include at least one of the preset period and the preset time threshold.

[0014] Optionally, the output unit includes: A first arbitrator, configured to poll and select the timeout feedback task currently prioritized from multiple concurrent timeout feedback tasks facing a write response channel; and A second arbitrator is configured to poll and arbitrate multiple concurrent timeout feedback tasks for the read data channel, and select the timeout feedback task that is currently prioritized for processing.

[0015] Optionally, the output unit is further configured to trigger an interrupt signal in response to an abnormal event; The abnormal events include at least one of response timeout events and invalid response events; the response timeout event refers to the monitoring channel triggering a timeout feedback task for the monitored transaction; the invalid response event refers to the detection of an invalid response signal that cannot be matched with a transaction in a valid monitoring state.

[0016] According to a second aspect of this disclosure, a computing device is also provided, comprising: Multiple hardware modules; On-chip network, through which the plurality of hardware modules are connected; and, According to the concurrent transaction timeout monitoring system of the first aspect of this disclosure, the system is coupled to the on-chip network and is used to monitor the timeout of transactions initiated by the hardware module as the master device through the on-chip network.

[0017] According to a third aspect of this disclosure, an electronic device is also provided, which includes the computing device described in the second aspect of this disclosure.

[0018] In this embodiment, each monitoring unit is mapped to a set type of transaction transmitted on the on-chip network, enabling the monitoring unit to perform targeted monitoring of the mapped transactions. Furthermore, each monitoring unit has multiple monitoring channels configured with independent counters, achieving independent and precise tracking of the response latency of each transaction within the mapped type. When the response latency of a monitored transaction exceeds a preset time threshold and no corresponding response signal is detected, the monitoring channel agent triggers a timeout feedback task from the slave device to return a timeout response signal to the master device through the response channel corresponding to that transaction. This prevents the master device from being blocked for an extended period due to waiting for timeout transactions, ensuring the normal operation of subsequent transactions.

[0019] The features and advantages of the embodiments of this specification will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of this specification and, together with their description, serve to explain the principles of these embodiments.

[0021] Figure 1 This is a schematic diagram of the composition structure of a computing device to which the concurrent transaction timeout monitoring system of this disclosure can be applied; Figure 2 This is a schematic diagram of the composition structure of another computing device to which the concurrent transaction timeout monitoring system of this disclosure can be applied; Figure 3 This is a schematic diagram of the microarchitecture of a concurrent transaction timeout monitoring system according to some embodiments; Figure 4 This is a schematic diagram of the microarchitecture of a concurrent transaction timeout monitoring system according to some other embodiments; Figure 5 This is a schematic diagram illustrating the workflow of a concurrent transaction timeout monitoring system according to some embodiments, which monitors the timeout of any transaction. Figure 6 These are schematic diagrams of the structure of a computing device according to some embodiments; Figure 7 This is a schematic diagram of the structure of an electronic device according to some embodiments. Detailed Implementation

[0022] Various exemplary embodiments of this specification will now be described in detail with reference to the accompanying drawings.

[0023] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the embodiments of this specification or their application or use.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0025] This disclosure relates to a scheme for timeout monitoring of concurrent transactions transmitted on an on-chip network. Figure 1 This is a schematic diagram of the structure of a computing device to which the concurrent transaction timeout monitoring scheme provided in the embodiments of this disclosure can be applied. Figure 1 As shown, the computing device 1000 includes multiple hardware modules 1100, which are connected to each other through an on-chip network 1200. The on-chip network 1200 can adopt the AXI protocol and support multiple independent channels such as read address channel, read data channel, write address channel, write data channel and write response channel to realize high-speed concurrent data transmission between hardware modules.

[0026] The computing device 1000 can be a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a neural network processor (NPU), or a tensor processor (TPU), etc. This computing device can also be referred to as a chip, processor, or artificial intelligence chip.

[0027] The role of any hardware module 1100 in a specific transaction is determined by its behavior within that transaction. When a hardware module 1100 initiates a transaction, it is a master device; when it responds to a transaction, it is a slave device.

[0028] like Figure 2 As shown, the computing device 1000 may include multiple computing units 1110, multiple memory controllers 1120, multiple peripheral controllers 1130 and other hardware modules. The computing unit 1110 can act as a master device to access the memory controller 1120 or the peripheral controller 1130 as a slave device through the on-chip network 1200.

[0029] During the operation of computing device 1000, the master device initiates various transactions to slave devices via the on-chip network, including read transactions and write transactions. After receiving the transaction request, the slave device executes the corresponding operation and returns a response signal and / or data to the master device via the on-chip network.

[0030] In large-scale concurrent scenarios, multiple transactions are transmitted concurrently on the on-chip network. Multiple master devices can independently initiate transactions, which are transmitted simultaneously on different physical links of the on-chip network or time-division interleaved on the same physical link. A single master device can also continuously initiate multiple transactions, causing transactions initiated at different times by the master device to overlap in the time interval from initiation to response completion. Therefore, it can be understood that "concurrent transmission" in this disclosure refers to multiple transactions overlapping in time, with a large number of outstanding transactions (or incomplete transactions) simultaneously existing on the on-chip network.

[0031] In large-scale concurrent scenarios, due to factors such as device response delays, network congestion, or device failures, some transactions may not receive responses for extended periods, causing the master device to continuously wait for response signals from initiated transactions, which can lead to system deadlock or performance degradation. Therefore, it is necessary to monitor timeouts for concurrent transactions transmitted on the on-chip network to ensure the operational reliability of computing devices in large-scale concurrent scenarios.

[0032] In related technologies, one possible timeout monitoring scheme is to centrally monitor various transactions using a global counter. Specifically, a global counter driven by a global clock is used, and all transactions share the counter's count value. When a transaction initiates, the current timeout value is recorded as the start timestamp. The timeout detection logic polls all incomplete transactions at fixed intervals and determines whether a transaction has timed out based on the difference between the current timeout value of the global counter and the start timestamp of each transaction. Because all transactions share the same counter resource, this scheme cannot provide independent timeout detection for different transactions, nor can it isolate timing interference between different transactions.

[0033] To address the aforementioned issues, embodiments of this disclosure integrate a concurrent transaction timeout monitoring system into a computing device. This system is coupled to an on-chip network and is used to allocate independent monitoring channels for multiple transactions concurrently transmitted on the on-chip network, so as to perform targeted, independent, and precise timeout monitoring for each transaction.

[0034] The following combination Figure 1 and Figure 2 The present disclosure describes various embodiments of a computing device.

[0035] <First Embodiment> This embodiment provides a parallel transaction timeout monitoring system. For example... Figure 3 As shown, the system 1300 includes a scheduling unit 1310, at least one monitoring unit, and an output unit 1350. Figure 3 Two monitoring units are schematically shown, namely the first monitoring unit 1321 and the second monitoring unit 1322.

[0036] The scheduling unit 1310 is configured to capture transaction initiation signals on the on-chip network and, based on the captured signals, allocate independent monitoring channels for timeout monitoring of multiple concurrently transmitted transactions. The transaction initiation signal includes a transaction identifier (transaction ID) and control signals. The transaction ID is used to identify and track a specific transaction, while the transaction type is reflected by the address channel initiating the transaction and a set of control signals thereon. The transaction ID identifies a transaction to support transaction tracking and response matching. Coarse-grained transaction types can be distinguished by the address channel initiating the transaction; read transactions are initiated through the read address channel, and write transactions are initiated through the write address channel and the write data channel. For further identification of fine-grained subtypes within read or write transactions, the control signals on the address channel can be used for determination.

[0037] Each monitoring unit is mapped to a set category of transactions initiated through the on-chip network and is configured to perform timeout monitoring on the set category of transactions initiated through the on-chip network, so as to realize the targeted timeout monitoring of the set category of transactions by the monitoring unit.

[0038] The scheduling unit 1310 is coupled to the address channel of the on-chip network through the bus interface of the on-chip network in order to capture transaction initiation signals on the address channel that belong to the timeout monitoring range of the system 1300.

[0039] In a scenario where the monitoring objects of system 1300 cover both read and write transactions, scheduling unit 1310 is coupled to both the read address channel and the write address channel. Optionally, scheduling unit 1310 may include a first scheduling subunit and a second scheduling subunit. The first scheduling subunit is coupled to the write address channel and is used to capture write transaction initiation signals on the write address channel and allocate monitoring channels for multiple concurrently transmitted write transactions; the second scheduling subunit is correspondingly coupled to the read address channel and is used to capture multiple concurrently transmitted read transactions and allocate monitoring channels. By having two scheduling subunits independently execute the scheduling of read and write transactions, scheduling efficiency can be improved.

[0040] In scenarios where the monitoring transactions of system 1300 only cover read transactions or write transactions, the scheduling unit 1310 can be coupled to the corresponding address channel.

[0041] In this embodiment, any monitoring unit is configured to monitor timeouts for a defined type of transaction. In scenarios where the system 1300 has two or more monitoring units, such as a first monitoring unit 1321 and a second monitoring unit 1322, different monitoring units are configured to monitor different types of transactions. Each monitoring unit is independent and can be configured independently, for example, its own time threshold for timeout determination can be configured independently.

[0042] The granularity of transaction type division can be flexibly set according to monitoring needs, and can adopt coarse-grained division, fine-grained division, or a combination of both.

[0043] In a coarse-grained classification, one monitoring unit can be used to monitor timeouts for all read transactions or all write transactions. For example, system 1300 includes a first monitoring unit 1321 mapped to write transactions initiated by the on-chip network, and a second monitoring unit 1322 mapped to read transactions initiated by the on-chip network.

[0044] At a finer-grained level, a monitoring unit can be used to monitor timeouts for one or more specific subtypes of read or write transactions. For example, a monitoring unit might map to a specific type of write transaction, rather than all write transactions. This specific type of write transaction might be one where the master device can only initiate subsequent transactions after receiving a corresponding response signal. Timeout monitoring for this type of write transaction can effectively prevent system deadlocks caused by the master device waiting for extended periods.

[0045] For regular write transactions, once the slave device receives the address and all write data from the master device and completes the WLAST handshake, it can quickly return a write response signal BRESP to the master device. Therefore, in some examples, the System 1300 can be configured to monitor timeouts only for specified types of write transactions, and not for regular write transactions, thereby reducing the monitoring burden without affecting the performance of the computing device.

[0046] In a coarse-grained and fine-grained approach, one monitoring unit can be used to monitor timeouts for all read transactions, while another monitoring unit can be used to monitor timeouts for write transactions of a specified type.

[0047] Each monitoring unit includes multiple monitoring channels. The multiple monitoring channels of the same monitoring unit are used to monitor multiple transactions belonging to the phase mapping setting category that are transmitted concurrently on the on-chip network.

[0048] In this embodiment, each monitoring channel independently tracks the response latency of a transaction using its own counter. The start time of this response latency is the moment when the monitoring channel is initiated by the scheduling unit 1310 to monitor the timeout of the transaction; the monitoring channel begins timing immediately upon initiation. Compared to a shared counter scheme, this system 1300 can provide independent and accurate timeout detection for each transaction, avoiding the accuracy loss problem caused by multiple transactions or different types of transactions sharing the same counter resource.

[0049] In this embodiment, each monitoring channel is further configured to trigger a timeout feedback task for the corresponding monitored transaction when the response delay time of the monitored transaction reaches a preset time threshold and no response signal of the monitored transaction is detected. This timeout feedback task is used to return the timeout response signal of the monitored transaction to the master device through the response channel of the corresponding monitored transaction in the on-chip network. The monitoring channel writes the key fields required to return the timeout response signal of the monitored transaction into the timeout feedback task, whereby the key fields include a transaction ID field, a burst transmission length (AXLEN / AWLEN) field, etc. For this purpose, each monitoring channel also sets an extended storage field to store auxiliary information of the transaction, the auxiliary information including at least the burst transmission length (AXLEN / AWLEN).

[0050] In this embodiment, the output unit 1350 is configured to respond to the timeout feedback task triggered by the monitoring channel, drive the response channel of the transaction pointed to by the timeout feedback task in the on-chip network, and return the timeout response signal of the corresponding transaction to the master device.

[0051] For read transactions, the corresponding response channel is the read data channel (R channel). When the monitoring channel monitoring the read transaction triggers a timeout feedback task, the output unit 1350 returns a timeout response signal (RRESP) to the master device through the read data channel. The status field of the timeout response signal is set to the corresponding timeout error indication code (e.g., SLVERR) to inform the master device that the corresponding read transaction failed to complete normally.

[0052] For write transactions, the corresponding response channel may differ depending on the specific transaction type. For example, for a write transaction without returned data, the corresponding response channel is the write response channel (B channel). When such a write transaction times out, the output unit 1350, based on a timeout feedback task triggered by the monitoring channel and directed to the write response channel, returns a timeout response signal (BRESP) to the master device through the write response channel. Its status field is set to the corresponding timeout error code to inform the master device that the corresponding write transaction failed to complete normally. As another example, for a write transaction with returned data, the corresponding response channel includes a read data channel (R channel) for transmitting the returned data. When such a write transaction times out, the output unit 1350, based on a timeout feedback task triggered by the monitoring channel and directed to the read response channel, returns a timeout response signal (RRESP) to the master device through the read response channel. Its status field is set to the corresponding timeout error code, and invalid data is returned to inform the master device that the corresponding write transaction failed to complete normally.

[0053] In some examples, the number of monitoring channels included in each monitoring unit can be set to be equal to the maximum concurrency supported by the on-chip network for the specified type of transactions monitored by that monitoring unit. For example, if the maximum concurrency for both read and write transactions supported by the on-chip network is 256, then the monitoring unit can be configured with 256 independent monitoring channels. In this way, when the scheduling unit 1310 captures a new transaction, it can allocate an idle monitoring channel in its corresponding monitoring unit, thereby avoiding queuing due to insufficient monitoring channel resources and ensuring the immediacy of monitoring startup.

[0054] In some examples, such as Figure 3 As shown, the monitoring channels are equipped with a channel identifier field, which permanently stores a transaction identifier (transaction ID) uniquely corresponding to the corresponding monitoring channel. That is, multiple monitoring channels of any monitoring unit are bound one-to-one with all transaction identifiers of the corresponding type of transaction. Accordingly, the scheduling unit is configured to: determine the target monitoring unit mapped to the corresponding transaction based on the transaction initiation signal, and allocate the corresponding transaction to the monitoring channel in the target monitoring unit that matches the transaction identifier for timeout monitoring, based on the transaction identifier in the transaction initiation signal. Taking a monitoring unit configured with 256 monitoring channels as an example, the channel identifier field can use 8-bit binary encoding.

[0055] In this example, when the master device initiates a transaction via the on-chip network, the transaction initiation signal carries a transaction identifier. After capturing the transaction initiation signal, the scheduling unit first determines whether the transaction belongs to the monitoring object of System 1300 based on the transaction type. If so, it determines the target monitoring unit mapped to the transaction based on the transaction type. For example, if the transaction is a read transaction, it is mapped to a monitoring unit used for monitoring read transactions; if the transaction is a write transaction, it is mapped to a monitoring unit used for monitoring write transactions, and so on. Subsequently, the scheduling unit extracts the transaction identifier from the transaction initiation signal and searches for a monitoring channel matching the transaction identifier in the target monitoring unit. Here, since each monitoring channel's channel identifier field stores a unique corresponding transaction identifier, the scheduling unit can accurately assign the transaction to the corresponding monitoring channel for timeout monitoring. This example simplifies the operation of matching transactions with monitoring channels and eliminates the need to write transaction IDs to monitoring channels during transaction allocation, thereby simplifying the hardware structure of the scheduling unit. Moreover, through the unique correspondence of transaction identifiers, accurate matching between transactions and monitoring channels is achieved, ensuring the accuracy and traceability of timeout detection.

[0056] In other examples, the monitoring channel may also have a transaction identifier field, which stores the transaction identifier of the current monitored transaction for the corresponding monitoring channel. Accordingly, when the scheduling unit 1310 assigns a transaction to a monitoring channel, it writes the transaction ID of the transaction to the transaction identifier field of that monitoring channel.

[0057] In some examples, such as Figure 3 Each monitoring channel of the monitoring unit shown is equipped with a status flag field, which indicates whether the corresponding monitoring channel is in an effective monitoring state. Each monitoring channel can be configured with a 1-bit status flag field to record the status of the corresponding monitoring channel. For example, when the value of the status flag field (status flag) is set to 1, it indicates that the corresponding monitoring channel has started the monitoring process and is in an effective monitoring state; when the value of the status flag field (status flag) is set to 0, it indicates that the corresponding monitoring channel has not started the monitoring process and is in an idle state. The value of the status flag field can be changed from 0 to 1 by the scheduling unit when starting the corresponding monitoring channel, or the status can be reversed by the operation of the scheduling unit to start the monitoring channel. When the monitoring channel completes the monitoring process of the currently assigned transaction, it will set the value of the status flag field from 1 to 0. The completion of the monitoring process includes two cases: one is that the response signal of the transaction is detected within a preset time threshold, and the other is that the timeout feedback task is triggered when a timeout is determined.

[0058] In these examples, the status identifier field effectively manages the lifecycle of the monitoring channel, avoiding erroneous monitoring of transactions that have not been initiated and preventing misjudgments. Simultaneously, the status identifier field can also be used to detect invalid response events. When a response signal for a transaction is received on the on-chip network, the system 1300 checks the status identifier field of the monitoring channel corresponding to that transaction identifier. If this field is 0, it indicates that the monitoring channel is not in a valid monitoring state, meaning the master device has not initiated the transaction. In this case, the response signal is invalid, and the system 1300 will discard the response signal and trigger an interrupt for reporting.

[0059] In some examples, such as Figure 3 As shown, each monitoring channel of the monitoring unit can be configured with a response channel identifier field to store the response channel identifier (response channel ID) of the monitored transaction. When a monitoring channel triggers a timeout feedback task, it retrieves the transaction identifier and response channel identifier of the monitored transaction stored within it. By setting a response channel identifier field for the monitoring channel, the output unit 1350 can determine the response channel to be driven without reverse querying the transaction type, thereby shortening the response path length for timeout feedback and reducing processing latency.

[0060] For monitoring units used to monitor read transactions, the response channel identifier field of their monitoring channels is fixed to an identifier value indicating the read data channel (e.g., 0). This identifier value can be permanently stored in the response channel identifier field of the monitoring channel, or it can be written by the scheduling unit 1310 when allocating monitoring channels. For monitoring units used to monitor write transactions, since the response channel of a write transaction depends on its specific type, the scheduling unit 1310 can write the corresponding identifier value into the response channel identifier field of the allocated monitoring channel according to the specific type of the write transaction; for example, 1 corresponds to the write response channel, and 0 corresponds to the read data channel.

[0061] In some examples, such as Figure 4 As shown, system 1300 may further include a first-level counter 1330. Each monitoring channel of the monitoring unit is equipped with an independent counter as a second-level counter, which is used to track the response latency of the monitored transaction. The first-level counter 1330 is configured to generate a counting enable signal at a preset period, the preset period being an integer multiple of the system clock period. The second-level counter is configured to perform a count accumulation once for each received counting enable signal when its monitoring channel is in an effective monitoring state, for example, when the status identifier field is 1. The current count value of the second-level counter represents the response latency of the monitored transaction of its monitoring channel.

[0062] In this example, the first-stage counter generates a counting enable signal at a preset period. This preset period can be flexibly configured through a configuration file, for example, it can be configured to be 100 times, 10 times, or other times the system clock cycle. Each preset period elapses, the first-stage counter generates a pulse signal as the counting enable signal, which is sent to the second-stage counters of all monitoring channels. When each monitoring channel's second-stage counter receives the counting enable signal, it first checks the status identifier field of its respective monitoring channel. If the status identifier field is 1, it indicates that the monitoring channel is in a valid monitoring state, and the second-stage counter performs a count increment; if the status identifier field is 0, it indicates that the monitoring channel is not in a valid monitoring state, and the second-stage counter does not perform a count increment.

[0063] In these examples, the current count value of the second-level counter represents the response latency of the monitored transaction in the corresponding monitoring channel. When the current count value of the second-level counter reaches a preset time threshold, if no response signal from the monitored transaction is detected, a timeout feedback task is triggered. The preset time threshold for each monitoring unit can be configured independently through a configuration file, meaning different monitoring units can be configured with different preset time thresholds to meet the real-time requirements of different types of transactions. In this example, the preset time threshold is stored as a count value in the register of the corresponding monitoring unit. This count value is calculated based on the actual expected time threshold, the system clock cycle, and a multiple of the preset cycle relative to the clock cycle.

[0064] In this two-stage counter architecture example, the first-stage counter generates a counting enable signal to uniformly control the counting rhythm of all second-stage counters. This eliminates the need for independent clock divider circuits or high-bit-width counters for each second-stage counter, effectively reducing circuit resource consumption. Furthermore, by configuring the preset period of the first-stage counter and the preset time threshold of the second-stage counter, the accuracy and detection range of timeout detection can be flexibly adjusted to adapt to different application scenarios ranging from low to high latency. Compared to traditional single-stage counter solutions, this example's two-stage counter architecture significantly reduces chip area and dynamic power consumption while maintaining detection accuracy and dynamic range.

[0065] In addition, the System 1300 supports configuring monitoring parameters such as the preset period of the first-level counter and / or the preset time threshold corresponding to the monitoring unit through configuration files. This allows users to set monitoring parameters through software configuration files according to the needs of actual application scenarios, and load the configuration parameters into the hardware circuit during system initialization, thereby improving the hardware's compatibility with different application scenarios.

[0066] In some examples, such as Figure 4 As shown, the output unit 1350 may include a first arbitrator 1351 and a second arbitrator 1352. The first arbitrator 1351 is configured to poll and arbitrate multiple concurrent timeout feedback tasks for the write response channel, and select the timeout feedback task that is currently prioritized; the second arbitrator 1352 is configured to poll and arbitrate multiple concurrent timeout feedback tasks for the read data channel, and select the timeout feedback task that is currently prioritized.

[0067] When multiple monitoring channels trigger timeout feedback tasks simultaneously, bus contention may occur if these timeout feedback tasks are directed to the same response channel. To address this, output unit 1350 employs a polling arbitrator to arbitrate and schedule tasks in the same direction, thus avoiding contention and ensuring fairness. The first arbitrator 1351 polls and arbitrates multiple concurrent timeout feedback tasks directed to the write response channel, authorizing each task to enter the processing flow that returns a timeout response signal in the drive response channel according to the polling order. The second arbitrator 1352 polls and arbitrates multiple timeout feedback tasks directed to the read data channel, authorizing each task to enter the processing flow that returns a timeout response signal in the drive response channel according to the polling order.

[0068] The polling arbitration mechanism ensures that multiple timeout feedback tasks are scheduled fairly, avoiding the problem of low-priority tasks being starved for extended periods, and improving the overall response efficiency and fairness of the system. The polling arbitrator uses a loop pointer to record the position of the last authorization, and the next arbitration starts polling from the position after that position, thus maintaining fairness across multiple arbitrations.

[0069] like Figure 4 As shown, the output unit 1350 may further include a response generation subunit 1353. The response generation subunit 1353 can be connected to a slave device interface to convert the timeout feedback task selected by arbitration into a timeout response signal conforming to the AXI protocol specification, and output it to the on-chip network through the corresponding response channel. For example, the response generation subunit is coupled to the slave device interface of the write response channel, used to convert the selected timeout feedback task for the write response channel into a timeout response signal (BRESP), and return it to the master device that initiated the transaction through the write response channel. As another example, the response generation subunit is coupled to the slave device interface of the read data channel, used to convert the selected timeout feedback task for the read data channel into a timeout response signal (RRESP), and return it to the master device that initiated the transaction through the read data channel. By outputting the timeout response signal through the slave device interface, the response behavior of the timeout feedback task can be kept consistent with the response behavior of a normal slave device on the bus, without the need for additional adaptation.

[0070] In another example, the output unit 1350 can also receive timeout feedback tasks triggered by each monitoring channel in parallel, and determine the timeout feedback tasks to be processed in the current clock cycle through the internal priority encoder.

[0071] In some examples, output unit 1350 may also include an interrupt subunit configured to trigger an interrupt signal in response to an abnormal event. The abnormal event may include at least one of a response timeout event and an invalid response event. A response timeout event refers to the monitoring channel triggering a timeout feedback task for the monitored transaction. An invalid response event refers to the detection of an invalid response signal that cannot be matched with a transaction in a valid monitoring state.

[0072] After detecting a response timeout event, the interrupt subunit triggers an interrupt signal and generates an error message containing the transaction identifier, which is then reported to the processor (such as the CPU) to notify the processor that the transaction has timed out, allowing the processor to perform error analysis and subsequent processing.

[0073] When a response signal for a transaction appears on the on-chip network, the system 1300 queries the status identifier field of the corresponding monitoring channel based on the transaction identifier carried by the response signal. If the value of this field is 0, it indicates that the monitoring channel is not currently in a valid monitoring state, meaning the master device has not initiated a valid transaction corresponding to that transaction identifier. In this case, the response signal is invalid, triggering an invalid response event. Upon detecting the invalid response event, the interrupt subunit triggers an interrupt signal and generates an error message containing the transaction identifier, reporting it to the processor to notify the processor that an invalid response has been received. Simultaneously, the system 1300 discards the invalid response signal to prevent it from interfering with the on-chip network.

[0074] When an interrupt signal is triggered, the interrupt subunit can simultaneously obtain auxiliary information stored in the extended storage field of the monitoring channel, such as burst transmission length (AXLEN / AWLEN), target address, etc., and report this information to assist the software in fault location and cause analysis.

[0075] In the example above, the interrupt subunit can promptly report abnormal events, providing support for debugging and fault location of the computing device, thereby improving the reliability and maintainability of the computing device. Simultaneously, by including transaction information such as transaction identifiers in the error messages, the transaction in which the abnormality occurred can be accurately located, facilitating rapid problem investigation by developers.

[0076] In some examples, such as Figure 5 As shown, the workflow of system 1300 for timeout monitoring of a transaction may include the following steps S510 to S550.

[0077] In step S510, the scheduling unit 1310 captures the transaction initiation signal on the address channel in the on-chip network, determines the target monitoring unit mapped to the transaction according to the transaction type, and assigns the transaction to the monitoring channel in the target monitoring unit that matches the transaction identifier according to the transaction identifier. The status identifier field of the monitoring channel is set to a valid state to start the monitoring channel to perform timeout monitoring on the transaction.

[0078] In step S520, after the monitoring channel is started, its second-level counter accumulates based on the counting enable signal generated by the first-level counter at a preset period to track the response delay time of the transaction. Simultaneously, the monitoring channel determines whether the response signal broadcast by the slave device through the on-chip network points to the transaction monitored by the monitoring channel.

[0079] Step S530: If a response signal for the transaction is detected on the on-chip network before the current count value of the second-level counter reaches the preset time threshold, the status identifier field of the monitoring channel is cleared, the second-level counter is cleared, the monitoring channel exits the effective monitoring state, and the timeout monitoring is completed.

[0080] Step S540: If the response signal for the transaction is not detected on the on-chip network when the current count value of the second-level counter reaches the preset time threshold, a timeout feedback task is triggered. The status identifier field of the monitoring channel is cleared, the second-level counter is cleared, the monitoring channel exits the effective monitoring state, and the timeout monitoring is completed.

[0081] In step S550, the output unit responds to the timeout feedback task triggered by the monitoring channel, drives the response channel corresponding to the transaction to return a timeout response signal to the master device that initiated the transaction, and triggers an interrupt signal containing the transaction identifier and error information.

[0082] <Second Embodiment> The parallel transaction timeout monitoring system provided in this embodiment includes two monitoring units, such as... Figure 3 and Figure 4 As shown, these are the first monitoring unit 1321 and the second monitoring unit 1322, respectively. The first monitoring unit 1321 is mapped to write transactions of a specified type initiated through the on-chip network, and the second monitoring unit 1322 is mapped to read transactions initiated through the on-chip network. The monitoring channel of the first monitoring unit 1321 is configured to perform timeout monitoring based on a preset first time threshold, and the monitoring channel of the second monitoring unit 1322 is configured to perform timeout monitoring based on a preset second time threshold. The first time threshold and the second time threshold can be the same or different.

[0083] In this embodiment, a write transaction of a defined type refers to a write transaction in which the master device can only initiate subsequent transactions after receiving a corresponding response signal. This can include at least one of barrier transactions and atomic operation transactions with returned data. The response channel for the corresponding barrier transaction on the on-chip network is a write response channel, and the response channel for the corresponding atomic operation transaction on the on-chip network is a read data channel.

[0084] A fence transaction is a special type of AXI write transaction. Its purpose is to ensure that all transactions initiated before it are visible to all observers globally or in a specified shared domain, and that subsequent transactions must wait for the fence transaction to complete before they can be initiated. Therefore, after initiating a fence transaction, the master device must wait for a corresponding write response signal to confirm the completion of the fence transaction before initiating any subsequent transactions.

[0085] An atomic operation transaction with a return value is a type of atomic operation in the AXI5 protocol. After the master device initiates this atomic operation transaction, the slave device executes the atomic operation and returns data and a response signal to the master device through the read data channel. Upon receiving the data and response signal, the master device confirms the completion of the atomic operation transaction.

[0086] This embodiment uses the first monitoring unit 1321 to monitor the timeout of write transactions of the above-defined types, and the second monitoring unit 1322 to monitor the timeout of read transactions that need to return data, which can effectively avoid system deadlock caused by long-term waiting of the master device.

[0087] In this embodiment, in a scenario where each monitoring channel of the monitoring unit is equipped with a response channel identifier field, the response channel identifier field of the monitoring channel in the second monitoring unit 1322 stores an identifier value of 0 indicating a read data channel; when the monitoring channel in the first monitoring unit 1321 monitors an atomic operation transaction, its response channel identifier field is written with an identifier value of 0 indicating a read data channel; when the monitoring channel in the first monitoring unit 1322 monitors a barrier transaction, its response channel identifier field is written with an identifier value of 1 indicating a write response channel. In this embodiment, the response channel identifier stored in the response channel identifier field of the monitoring channel in the first monitoring unit 1321 can also be used to distinguish whether the currently monitored write transaction is an atomic operation transaction or a barrier transaction.

[0088] In this embodiment, taking the example that both the first monitoring unit 1321 and the second monitoring unit 1322 have 256 monitoring channels, the maximum number of concurrent timeout feedback tasks for the write response channel of the system 1300 is 256, while the maximum number of concurrent timeout feedback tasks for the read response channel is 512.

[0089] When the scheduling unit assigns a barrier transaction or an atomic operation transaction with returned data to a monitoring channel of the first monitoring unit 1321, the status flag field corresponding to that monitoring channel is set to 1, indicating that the monitoring channel has started timeout monitoring for the write transaction. When the response signal of the write transaction arrives or a timeout event occurs, the monitoring channel completes its monitoring task, and its corresponding status flag field is cleared to zero, indicating that the monitoring channel has exited the effective monitoring state and can be assigned to a new write transaction.

[0090] When the scheduling unit assigns a read transaction to a monitoring channel of the second monitoring unit 1322, the status flag field corresponding to that monitoring channel is set to 1, indicating that the monitoring channel has started timeout monitoring of the read transaction. When the response signal of the read transaction arrives or a timeout event occurs, the monitoring channel completes its monitoring task, and its corresponding status flag field is cleared to zero, indicating that the monitoring channel has exited the effective monitoring state and can be assigned to a new read transaction.

[0091] <Third Embodiment> This embodiment also provides a computing device, such as Figure 6As shown, the computing device 1000 includes multiple hardware modules 1100, an on-chip network 1200, and a concurrent transaction timeout monitoring system 1300 according to any embodiment of this disclosure. In this embodiment, the multiple hardware modules 1100 are connected through the on-chip network 1200, wherein the hardware module 1100 is referred to as the master device when acting as the transaction initiator and as the slave device when acting as the transaction responder. The on-chip network 1200 is used to transmit transactions between the master device and the slave device. The on-chip network adopts the AXI protocol and realizes high-speed data transmission between the master device and the slave device through the read address channel, read data channel, write address channel, write data channel, and write response channel defined by the AXI protocol.

[0092] System 1300 is coupled to on-chip network 1200 and is used to monitor timeouts of transactions initiated by hardware module 1100 (as the master device) through on-chip network 1200. A parallel transaction timeout monitoring system is also coupled to on-chip network and is used to monitor timeouts of multiple transactions transmitted concurrently on the on-chip network.

[0093] <Fourth Embodiment> This embodiment provides an electronic device, such as... Figure 7 As shown, the electronic device 700 includes a computing device 1000 according to a third embodiment.

[0094] like Figure 7 As shown, the electronic device 700 may further include a control device 2000 and a storage device 3000 as memory. The computing device 1000, the control device 2000, and the storage device 3000 can be connected via a bus network or other means. The control device 2000 can be used to control the computing device 1000 to perform computing tasks.

[0095] The control device may be a central processing unit (CPU). The computing device may be a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a neural network processor (NPU), or a tensor processor (TPU), etc. The storage device may be a static random access memory (SRAM), a read-only memory (ROM), or an erasable programmable read-only memory (EPROM), used to store instructions and / or data, which can be retrieved and used by the control device or the computing device.

[0096] The electronic device can have any product form, such as any type of chip, terminal device, workstation or server, etc., without any limitation.

[0097] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and apparatuses according to various embodiments of this specification. In this regard, each block in a flowchart or block diagram may represent a module, unit, or part of a circuit. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using hardware that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. Unless otherwise specified, implementation in hardware, implementation in software, and implementation using a combination of software and hardware can be equivalent.

[0099] Various embodiments of this specification have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A concurrent transaction timeout monitoring system, characterized in that, include: The scheduling unit is configured to capture transactions initiated by the master device through the on-chip network and allocate independent monitoring channels for timeout monitoring of multiple transactions that are concurrently transmitted on the on-chip network. At least one monitoring unit is mapped to a specified type of transaction initiated through the on-chip network and configured to perform timeout monitoring on the specified type of transaction initiated through the on-chip network; the monitoring unit includes multiple monitoring channels for monitoring multiple transactions transmitted concurrently. Each monitoring channel is equipped with an independent counter. Each monitoring channel is configured to independently track the response delay time of a transaction through its own counter, and when the response delay time reaches a preset time threshold and no response signal of the monitored transaction is detected, the timeout feedback task of the corresponding monitored transaction is triggered. as well as, An output unit is configured to respond to the timeout feedback task triggered by the monitoring channel, drive the response channel of the transaction pointed to by the timeout feedback task in the on-chip network to return a timeout response signal corresponding to the transaction to the master device.

2. The system according to claim 1, characterized in that, The system includes two monitoring units, namely a first monitoring unit and a second monitoring unit. The first monitoring unit is mapped to write transactions initiated through the on-chip network, and the second monitoring unit is mapped to read transactions initiated through the on-chip network. The monitoring channel of the first monitoring unit is configured to perform timeout monitoring based on a preset first time threshold; The monitoring channel of the second monitoring unit is configured to perform timeout monitoring based on a preset second time threshold.

3. The system according to claim 1, characterized in that, The at least one monitoring unit includes a first monitoring unit, which is mapped to a write transaction of a specified type initiated through the on-chip network; wherein, the write transaction of the specified type refers to a write transaction in which the master device can only initiate subsequent transactions after receiving a corresponding response signal.

4. The system according to claim 3, characterized in that, The specified type of write transaction includes barrier transactions and atomic operation transactions with returned data; wherein, the response channel on the on-chip network corresponding to the barrier transaction is a write response channel, and the response channel on the on-chip network corresponding to the atomic operation failure is a read data channel.

5. The system according to any one of claims 1 to 4, characterized in that, The system also includes a first-level counter; the independent counter set in the monitoring channel is a second-level counter. The first-level counter is configured to generate a counting enable signal at a preset period, wherein the preset period is an integer multiple of the system clock period; the second-level counter is configured to perform a counting accumulation once each time the counting enable signal is received when the monitoring channel to which it belongs is in an effective monitoring state, and the current count value of the second-level counter represents the response delay time of the monitored transaction of the monitoring channel to which it belongs.

6. The system according to claim 5, characterized in that, The monitoring parameters of the system are configured through a configuration file, and the monitoring parameters include at least one of the preset period and the preset time threshold.

7. The system according to any one of claims 1 to 4, characterized in that, Each monitoring channel of the monitoring unit is provided with a response channel identifier field, which is used to store the response channel identifier of the monitored transaction; the timeout feedback task carries the transaction identifier of the monitored transaction and the response channel identifier stored in the response channel identifier field.

8. The system according to any one of claims 1 to 4, characterized in that, The number of monitoring channels included in the monitoring unit is the same as the maximum concurrent number of the set type of transactions mapped by the corresponding monitoring unit on the on-chip network; the monitoring channel is provided with a channel identifier field, and the channel identifier field stores a transaction identifier that uniquely corresponds to the identified monitoring channel; The monitoring and scheduling unit is configured to: determine the target monitoring unit for the corresponding transaction mapping based on the transaction initiation signal, and allocate the corresponding transaction to the monitoring channel in the target monitoring unit that matches the transaction identifier for timeout monitoring based on the transaction identifier in the transaction initiation signal.

9. The system according to any one of claims 1 to 4, characterized in that, Each monitoring channel of the monitoring unit is equipped with a status identifier field, which is used to indicate whether the corresponding monitoring channel is in an effective monitoring state.

10. The system according to any one of claims 1 to 4, characterized in that, The output unit includes: A first arbitrator, configured to poll and select the timeout feedback task currently prioritized from multiple concurrent timeout feedback tasks facing a write response channel; and A second arbitrator is configured to poll and arbitrate multiple concurrent timeout feedback tasks for the read data channel, and select the timeout feedback task that is currently prioritized for processing.

11. The system according to any one of claims 1 to 4, characterized in that, The output unit is also configured to trigger an interrupt signal in response to an abnormal event; The abnormal events include at least one of response timeout events and invalid response events; the response timeout event refers to the monitoring channel triggering a timeout feedback task for the monitored transaction; the invalid response event refers to the detection of an invalid response signal that cannot be matched with a transaction in a valid monitoring state.

12. A computing device, characterized in that, include: Multiple hardware modules; The multiple hardware modules are connected via the on-chip network. as well as, The concurrent transaction timeout monitoring system according to any one of claims 1 to 11, wherein the system is coupled to the on-chip network and is used to monitor the timeout of transactions initiated by the hardware module as the master device through the on-chip network.

13. An electronic device, characterized in that, Includes the computing device as described in claim 12.

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