Debugging method of software code, debugging device, radar chip and storage medium

Abstract

The application discloses a debugging method and device of software code, a radar chip and a storage medium, and belongs to the computer field.The debugging method is applied to a radar system comprising a processor and a hardware accelerator.The hardware accelerator comprises a hardware scheduler and a plurality of operators.The processor loads software code to be debugged to a cache of the hardware scheduler.In response to a running command issued by a debugging device, the hardware scheduler starts to execute from a current instruction.When an instruction timeout function is enabled, the execution time of each instruction is determined when the instruction is executed.When the execution time exceeds a preset time threshold, an error is reported to the debugging device.Based on the embodiment of the application, the performance bottleneck in the code can be quickly and accurately located by a developer, and the development efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of computers, and more specifically, to a method for debugging software code, a debugging apparatus, a radar chip, and a storage medium. Background Technology

[0002] To achieve application flexibility, the industry commonly uses general-purpose processors such as Digital Signal Processors (DSPs) for data processing in radar signal processing. With the development of radar technology, radar signal processing algorithms have become increasingly complex, and radar signal processor operators have become increasingly diverse. Multi-channel, high-precision radar applications have created a demand for high-performance, low-power processing of echo signals. Mainstream DSP solutions have accelerated the shift towards radar hardware accelerators. However, the processing flow of each operator in a hardware accelerator is simple, lacks flexibility, and fails to fully realize its performance advantages. Summary of the Invention

[0003] One embodiment of this disclosure provides a software code debugging method applied to a radar system including a processor and a hardware accelerator, wherein the hardware accelerator includes a hardware scheduler and multiple operators, and the debugging method includes:

[0004] The processor loads the software code to be debugged into the cache of the hardware scheduler. The software code includes multiple instructions executed by the hardware scheduler to control the plurality of operators to perform radar signal processing.

[0005] In response to the run command issued by the debugging device, the hardware scheduler starts execution from the current instruction. When the instruction timeout function is enabled, it determines the execution time of each instruction when executing it, and reports an error to the debugging device when the execution time exceeds a preset time threshold.

[0006] One embodiment of this disclosure also provides a radar chip, including a radio frequency module, an analog signal processing module, and a digital signal processing module connected in sequence.

[0007] The radio frequency module is configured to generate and transmit electromagnetic wave signals, and to receive electromagnetic wave signals.

[0008] The analog signal processing module is configured to down-frequency the received electromagnetic wave signal to obtain an intermediate frequency signal.

[0009] The digital signal processing module is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; wherein, the digital signal processing module includes the processor and hardware accelerator in the debugging method described in any embodiment of this disclosure.

[0010] An embodiment of this disclosure also provides a debugging apparatus, including a processor and a memory storing a computer program, characterized in that, when the processor executes the computer program, it is able to implement the processing performed by the debugging apparatus in any embodiment of the debugging method described in this disclosure.

[0011] An embodiment of this disclosure also provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, can implement the debugging method described in any embodiment of this disclosure.

[0012] In the embodiments described above, after the processor loads the software code to be debugged into the hardware scheduler's cache, in response to a run command issued by the debugging device, the hardware scheduler can start execution from the current instruction. Furthermore, with the instruction timeout function enabled, the scheduler determines the execution time of each instruction during execution and reports an error to the debugging device if the execution time exceeds a preset time threshold. This embodiment's timeout monitoring for each instruction helps developers quickly and accurately locate performance bottlenecks in the code, optimize execution efficiency, and improve development efficiency.

[0013] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the embodiments described in the description, claims, and drawings. Attached Figure Description

[0014] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0015] Figure 1 This is a schematic diagram of an exemplary radar system according to one embodiment;

[0016] Figure 2 This is a structural diagram of an exemplary radar system according to one embodiment;

[0017] Figure 3 This is a schematic diagram of electromagnetic waves emitted by a radar system in one embodiment;

[0018] Figure 4 This is a schematic diagram of the digital signal processing flow in an embodiment of a radar system;

[0019] Figure 5 This is a schematic diagram of a hardware accelerator in an embodiment of a radar system. It supports multiple operators with hard-connected interfaces.

[0020] Figure 6A and Figure 6B These are schematic diagrams of the radar system hardware accelerators in two other embodiments, supporting a single operator;

[0021] Figure 7 This is a schematic diagram of the structure of a computing system according to an embodiment of the present disclosure, including a hardware accelerator;

[0022] Figure 8A , Figure 8B , Figure 8C and Figure 8D This is a schematic diagram of multiple operators and a shared cache pool specified in the four hardware accelerators of this disclosure embodiment;

[0023] Figure 9A yes Figure 8B A diagram illustrating the cache used by multiple operators;

[0024] Figure 9B This is a schematic diagram of data flow loopback according to an embodiment of this disclosure;

[0025] Figure 10 This is a flowchart of a multi-operator control method according to an embodiment of the present disclosure;

[0026] Figure 11A and Figure 11B This is a schematic diagram of two startup and synchronization control methods for a hardware accelerator including three operators in a multiple loop process according to an embodiment of the present disclosure;

[0027] Figure 12 This is a schematic diagram of a hardware accelerator according to an embodiment of the present disclosure;

[0028] Figure 13 This is a schematic diagram of an integrated circuit according to an embodiment of the present disclosure;

[0029] Figure 14 This is an embodiment of the present disclosure. Figure 13 A schematic diagram of a device for integrated circuits;

[0030] Figure 15 This is a schematic diagram of the data flow between multiple operators and the time-step switching buffer according to an embodiment of this disclosure;

[0031] Figure 16 This is a schematic diagram of a control device according to an embodiment of the present disclosure;

[0032] Figure 17 This is a schematic diagram of a hardware scheduler according to an embodiment of the present disclosure;

[0033] Figure 18 This is a schematic diagram of the structure of an operator according to an embodiment of this disclosure;

[0034] Figure 19This is a flowchart of a multi-operator control method according to another embodiment of this disclosure;

[0035] Figure 20 This is a flowchart of a software code debugging method according to an embodiment of the present disclosure;

[0036] Figure 21 This is a schematic diagram of a debugging system including a debugging device and a radar chip according to an embodiment of the present disclosure;

[0037] Figure 22 This is a schematic diagram of a radar chip module according to an embodiment of the present disclosure;

[0038] Figure 23 This is a schematic diagram of a debugging apparatus according to an embodiment of the present disclosure. Detailed Implementation

[0039] This disclosure describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that more embodiments and implementations are possible within the scope of the embodiments described herein.

[0040] In the description of this disclosure, words such as "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments. The word "and / or" in this document describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this disclosure, the terms "first" and "second" are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that "first" and "second" do not necessarily imply differences.

[0041] In describing representative exemplary embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, as other sequences of steps are possible, to the extent that the method or process does not depend on the specific order of steps described herein. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the scope of protection. Furthermore, the scope of protection for the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied while still remaining within the spirit and scope of the embodiments disclosed herein.

[0042] The main function of radar digital signal processing is to perform fast Fourier transform on millimeter-wave echo signals, convert the time-domain signal into a frequency-domain signal, obtain the energy distribution of the spectrum, and then remove and suppress noise according to the algorithm to complete the target identification and obtain information such as the target's distance, speed and angle.

[0043] Figure 1 A radar system is illustrated, taking a frequency-modulated continuous wave (FMCW) millimeter-wave radar as an example. This radar system includes an RF chip 110, a transmitting antenna 120, a receiving antenna 130, and a main processing chip 140. The RF chip 110 is configured to generate a detection signal and transmit it through the transmitting antenna array 120. The transmitting antenna 120 is connected to the RF chip 110, forming a transmitting antenna array to transmit the detection signal, such as an FMCW electromagnetic wave signal. Multiple receiving antennas 130 are configured to receive the echo signal formed by the detection signal reflected from the detected object (also called the target object, or simply the target). The main processing chip 140 is connected to the receiving antenna array 130 and the RF chip 110, and is configured to process the echo signal obtained by the receiving antenna array 130 to obtain information such as the target's distance, velocity, and angle. In one example, the transmitting antenna 121 and the receiving antenna 131 can be integrated with the RF chip 110 to form an RF transceiver chip, which, together with the main processing chip 140, constitutes a radar signal transceiver processing system (referred to as a radar system). In another example, the RF chip 110 and the main processing chip 140 are integrated into a single system-on-a-chip (SoC), enabling the transmission, reception, and processing of RF signals with a single chip. The transmitting antenna 120 and the receiving antenna 130 can also be integrated with this SoC chip to form a structure similar to an antenna-in-package (AiP) chip.

[0044] The radio frequency chip 110, which can be integrated as one unit or set separately, and the main processing chip 140 can constitute an integrated circuit in a radar system. The integrated circuit, transmitting antenna, and receiving antenna can be set on a carrier, together with the carrier, to form an electromagnetic wave device. The electromagnetic wave device can be installed on equipment such as a car.

[0045] Figure 2The radar system shown includes a transmitting antenna 11, a power amplifier 21, a signal generator 23, a receiving antenna 13, a low-noise amplifier 31, a mixer 33, an analog-to-digital converter (ADC) 41, and a digital signal processing module 51. The signal generator 23 can be a millimeter-wave generator implemented with an oscillator. The detection signal generated by the signal generator 23 is amplified by the power amplifier 21 and then transmitted through one or more transmitting antennas 11. The radar system typically transmits a series of chirps in frames. The detection signal transmitted by an FMCW-based radar system can use... Figure 3 The sawtooth waveform shown has multiple chirps in each frame. Each chirp includes an up-modulation band, a down-modulation band, and a frequency hold band. The period of each chirp is Tc.

[0046] The detection signal is reflected and / or refracted by the target to form an echo signal. The echo signal received by the receiving antenna 13 is amplified by the low-noise amplifier 31, and then mixed with the corresponding local oscillator signal in the mixer 33 to obtain the intermediate frequency signal. The intermediate frequency signal is sent to the ADC 41 for sampling, and the resulting digital signal is further processed in the digital signal processing module 51. There are usually multiple receiving antennas 13, and the radar system can have multiple receiving channels. Unless otherwise specified, "channel" in this text refers to a receiving channel.

[0047] Figure 4 The diagram illustrates an example of a digital signal processing flow. After sampling by the ADC, the digital signals from one or more channels undergo 1D-FFT processing, such as DC removal (DC), windowing (Win), one-dimensional fast Fourier transform (1D-FFT), and spatially variable apodization (SVA), among other data processing in the range dimension. The resulting 1D-FFT data is buffered and accumulated to a predetermined number of frames, such as 128 frames. Then, 2D-FFT processing is performed, including windowing, clutter suppression, and two-dimensional fast Fourier transform (2D-FFT), among other data processing in the Doppler dimension (velocity dimension), yielding the range-Doppler two-dimensional spectrum, or RD (Range-Doppler) spectrum, of the digital signal. Target detection can be performed based on the RD spectrum, such as through constant false alarm rate (CFAR). Rate detection determines the target's spectral peaks in the range and Doppler dimensions, followed by range, velocity, and direction of arrival (D) measurements. O A: DirectionOfArrival) estimation, etc.

[0048] Radar digital signal processing can be based on Figure 1 The main processing chip shown is an implementation example. Depending on the application requirements for performance, cost, and application flexibility, different engineering implementations exist. Running these processes via software on the CPU cannot meet the high real-time requirements of some applications. In these scenarios, hardware accelerators can be placed on the chip to perform these processes and improve computational efficiency. These chips can be further divided into two types:

[0049] One type of hardware acceleration solution is to provide customized acceleration for a specific application, such as... Figure 5 As shown, the hardware accelerator includes multiple operators to perform the following processes: DC removal, primarily used to remove the DC component of the signal; windowing, using window functions to window the signal, reducing spectral leakage caused by signal truncation; FFT: used to perform a Fast Fourier Transform on the intermediate frequency signal data after analog-to-digital conversion, converting the time-domain signal into a frequency-domain representation; SVA: used to apply different weighting methods to pixels at different spatial locations, effectively suppressing sidelobes. These operators are connected serially, processing the data to be processed from the Radar Cube in sequence, and the processing results are stored back to the Radar Cube. The operators can be controlled through configuration registers. This scheme uses dedicated ASIC circuits, which have strong processing capabilities and maximize chip area utilization for specific applications. However, the operators are hard-connected, and the interaction direction and processing order between the operators are singular. Firmware development methods are limited, and it is impossible to optimize through software development or firmware iteration to adapt to new application requirements. If complex application designs are to be supported, they need to be determined in the early stages of chip design. After the chip design is completed, it can only support relatively fixed data processing flows and is difficult to support new application requirements.

[0050] These solutions all present a trade-off between application flexibility and high performance and low power consumption, and a solution is needed to resolve this conflict.

[0051] Another hardware acceleration solution, to adapt to different applications, uses software instructions to achieve data interaction between hardware accelerators, such as... Figure 6A and Figure 6B As shown, the input data to be processed by the hardware accelerator is loaded from the RadarCube via a Direct Memory Access (DMA) controller, represented as DMAI in the diagram. The processing result, i.e., the output data, of the hardware accelerator is stored in the RadarCube via another DMA controller (represented as DMAO in the diagram). The internal cache capacity of the hardware accelerator is small, consisting of a single operator (such as...). Figure 6A DC, Figure 6BThe input data is processed using the FFT (Functional Fourier Transform). The hardware accelerator of this scheme can be implemented based on a digital signal processor (DSP) and algorithm logic. Different processing flows required by different applications can be achieved by changing the data interaction between multiple hardware accelerators. The data of each operator can interact with the CPU or upper-layer applications, which is flexible. However, it requires the DSP / CPU to have strong computing power, and there needs to be a high-speed data communication interface between the upper-layer application and the DSP. The cost is high, and the data needs to be frequently moved between the hardware accelerator and the Radar Cube, resulting in low utilization efficiency of the hardware accelerator, high power consumption, long development cycle, and difficulty in meeting the processing requirements of high performance and real-time.

[0052] Although the above example uses a radar system, other applications that require hardware acceleration also need to effectively resolve the conflict between the application flexibility of hardware accelerators and high performance and low power consumption.

[0053] To address this, this disclosure proposes a novel hardware-software interaction method based on software code (such as radar-specific microinstructions). Users can develop different software code for different applications according to their needs, customizing the connection relationships and data flows between multiple operators in the hardware accelerator. During actual operation, both the software code and data flow can be processed by hardware circuits such as Application-Specific Integrated Circuits (ASICs). This solves the problem of limited development flexibility while also offering high performance.

[0054] To this end, one embodiment of this disclosure provides a hardware accelerator, including a hardware scheduler, a plurality of designated operators, a shared cache pool providing cache space for the plurality of operators, and a register set, such as Figure 7 As shown, where:

[0055] The hardware scheduler is configured to allocate caches from the shared cache pool to the plurality of operators based on a set connection order to form a data interaction channel between the plurality of operators, save the information of the allocated caches to the register group; and control the plurality of operators to start sequentially according to the set connection order, complete the processing of the loaded data to be processed in a pipeline manner, and store the processed data in external memory.

[0056] The register group is configured to store configuration information for the plurality of operators, the configuration information including information on the cache allocated to the operators;

[0057] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; if an output cache is allocated, write the processed data into the output cache.

[0058] The multiple operators in this embodiment are specified by software code as the operators that need to process the data to be processed. They can be all or some of the operators set in the hardware accelerator. The operators in this article can also be referred to as computing engines, computing units, etc.

[0059] Based on the hardware accelerator of this disclosure, users can flexibly specify multiple operators to implement computing tasks according to different usage scenarios. Not only can parameters be set for the specified multiple operators, but the connection relationships between multiple operators and the data flow direction during operation can also be configured to adapt to the requirements of different application scenarios for the required operators and processing flows. Furthermore, multiple operators can be controlled to process in parallel in a pipelined manner, maximizing the processing power per unit chip area. This enables systems equipped with this hardware accelerator, such as radar signal processors, to achieve optimal performance in different scenarios.

[0060] The shared cache pool (also written as memory pool) in this embodiment can use storage media such as Static Random-Access Memory (SRAM), Dynamic Random-Access Memory (DRAM), and Phase-Change Memory (PCM). This shared cache pool can be implemented using a memory with multiple independently accessible memory regions, which can be accessed simultaneously by different operators, such as a physical memory comprising multiple banks.

[0061] In one example of this embodiment, multiple register groups can be set up, with each register group corresponding to a specific operator. However, in other examples, the register group can be a set of registers shared by multiple operators, or it can include multiple register groups, with at least some of these register groups being shared by multiple operators.

[0062] The connection between the multiple operators specified in this embodiment is a "soft" connection. Users can generate software code according to the needs of the computing task, and select some or all of the operators set by the hardware accelerator through the software code to execute the computing task (the selected multiple operators are the specified multiple operators). The connection order of the specified multiple operators can be defined by the positional relationship between the caches allocated to the multiple operators in the software code, as well as the order of scheduling instructions sent to the operators. Data interaction between multiple operators is carried out through a shared cache pool, and the start time and synchronization method of different operators can also be defined by the software code.

[0063] Figure 7 This illustration shows some operators used in this embodiment when applied to a radar system, such as FFT, SVA, CFAR, DoA, etc., which are merely exemplary. These operators can be implemented in multiple hardware accelerators. The DMA controller shown in the figure can also be used as an operator, namely a DMA operator. The DMA operator can load data under the control of the hardware scheduler, and can also store processed data in memory. This embodiment can support a variety of operators, including but not limited to dedicated hardware operators defined by chip manufacturers, such as FFT operators, CMB operators, etc. Dedicated hardware operators include logic circuits that implement certain calculations (such as complex number multiplication and addition operations), and may also include other auxiliary circuits such as multiplexers, internal lookup tables, internal memory, filters, etc. In other embodiments, it can also be extended to general-purpose operators, and the hardware scheduler can schedule processors such as DSPs, CPUs, DPUs, APUs, etc., as operators.

[0064] This embodiment describes how operator buffer allocation and scheduling methods are related to the characteristics of the operators. Some operators, such as FFT and SVA, process the input data, resulting in processed data that differs from the input data. These operators can be allocated both input and output buffers. However, some operators, such as Digital Front End (DFE) operators, perform statistical analysis on the input data while transmitting it directly. These operators can be allocated only an output buffer. Other operators are used for data movement, such as the DMAO operator, which moves processed input data to memory. These operators can be allocated only an input or output buffer. The operators in this embodiment are not limited to the methods listed here.

[0065] The hardware scheduler in this embodiment can also be represented as SEQ (sequencer), and can be implemented using ASIC, Field Programmable Gate Array (FPGA), microprocessor (MCU), etc. This hardware scheduler can internally set up a cache to load software code generated for the current computing task. By executing instructions in the software code, it performs operations such as allocating caches for operators and scheduling operators. Operator scheduling can be implemented based on scheduling instructions. However, this does not mean that the hardware scheduler must send scheduling instructions to every operator. For example, it may not send scheduling instructions to the DFE operator that transmits data. When the DFE operator detects data input, it can automatically transmit the input data to the output cache and perform statistics. The sequential startup of multiple operators described in this paper does not mean that only one operator can be started at a time step, but rather covers the case where a DFE operator and another operator start at the same time step.

[0066] Radar signal processing can be divided into multiple stages, such as 1D-FFT, 2D-FFT, and CFAR, each of which can be accelerated by its corresponding hardware accelerator. Each stage's hardware accelerator can be pre-configured with the operators required for that stage. The function of an operator is determined by the division of the processing flow within that stage; however, operator configuration is not simply based on size, but also on possible combinations. If further subdivision is not possible to accommodate multiple combinations, even a large operator (e.g., high computational load, numerous processing steps, large circuit size) does not need further subdivision. Conversely, if an operator's components require multiple possible combinations, it can be further subdivided into more operators. The hardware accelerator can be configured with operators required for various applications. When executing a computational task for a specific application, some operators are enabled via software code, while others can be disabled.

[0067] In an exemplary embodiment of this disclosure, the specified plurality of operators are operators in the 1D-FFT processing stage, including, in sequence, the DFE operator, the Chirp Quality Monitor Detection (CQMD) operator, the Fast Fourier Transform (FFT) operator, and the Spatial Vector Analysis (SVA) operator, such as Figure 8A As shown, the DFE operator is optional.

[0068] In another embodiment, the specified plurality of operators are operators in the 2D-FFT processing stage, including, in sequence, the DC removal (DC: Direct Current) operator, the FFT operator, and the SVA operator. Figure 8BThe figure shows an example of this embodiment, which includes two SVA operators, denoted as SVA1 and SVA2, but other examples may only include one SVA operator. In addition to the above operators, it also includes a DMA operator (denoted as DMAI operator) for loading external data to be processed into the hardware accelerator and a DMA operator (denoted as DMAO operator) for storing data processed by the hardware accelerator into external memory.

[0069] In another embodiment, the specified multiple operators are operators processed in the CFAR stage, which include, in sequence, the Controller of Combination (CMB) operator, the Statistic (STAS) operator, the Histogram (HIST) operator, the CFAR operator, and the STAS operator. Figure 8C The figure shows an example of this embodiment. In addition to the above-mentioned operators, the figure also includes two DMA operators, which are denoted as DMAI operator and DMAO operator respectively.

[0070] The processing performed by the hardware accelerator is not necessarily divided according to the above-described 1D-FFT, 2D-FFT, and CFAR stages. In another example of this embodiment, the specified plurality of operators sequentially include the DC operator, FFT operator, SVA operator, and CMB operator, as shown below. Figure 8D As shown.

[0071] Depending on the application requirements, other operators can be inserted between the multiple operators in the above example.

[0072] In the exemplary hardware accelerator described above, the cache for each operator can be allocated independently. This can be achieved through cache allocation instructions in the software code. The hardware scheduler parses the cache allocation instruction for an operator and writes the allocated cache information into the register group corresponding to that operator. The operator can read data from the input cache based on the information read from the corresponding register group, such as the location and size of the input and output caches, process the data, and write it to the output cache.

[0073] by Figure 8B Taking an example, we will further explain the data interaction between the various operators. In the diagram, the DC operator, FFT operator, SVA1 operator, and SVA2 operator are connected sequentially. Each of these operators reads input data from its own input buffer, processes it, and saves the processed data to its own output buffer, which then serves as the input data for the next operator. The detailed data flow is as follows: Figure 9AAs shown, taking the processing and flow of a data block in the data to be processed as an example, the DMAI operator loads the data block from external (such as memory) into Cache0 or Cache1 in the shared cache pool. Cache0 and Cache1 are two output caches allocated for the DMAI operator and two input caches allocated for the DC operator. The operator switches the cache used in adjacent time steps. The DC operator reads the data block from Cache0 or Cache1 for processing, and the processed data block is written to Cache2 or Cache3. Cache2 and Cache3 are two output caches allocated for the DC operator and two input caches allocated for the FFT operator. The FFT operator reads data blocks from Cache2 or Cache3 for processing, and writes the processed data blocks to Cache4 or Cache5. Cache5 and Cache6 are two output caches allocated for the FFT operator and two input caches allocated for the SVA1 operator. The subsequent processing of the SVA1 and SVA2 operators is similar. After the SVA2 operator writes the processed data block to Cache8 or Cache9, the DMAO operator stores the processed data block externally (e.g., in memory), thus completing the processing of the data block by the hardware accelerator. Cache0 to Cache1 are caches allocated from the shared cache pool. During operation, data blocks to be processed are continuously loaded into the hardware accelerator, which processes multiple data blocks in parallel in a pipelined manner until the processing of the data is complete. In this embodiment, a data block can be the data of a chirp or the data of multiple chirs on a distance gate.

[0074] In another embodiment, the hardware accelerator may not include a DMA operator. Instead, the processor performs the operations of loading the data to be processed into a shared cache pool and storing the data processed by all operators in the shared cache pool to the external storage. Figure 8D As shown. For example, after the hardware scheduler completes processing a batch of data blocks, it can notify the processor to retrieve the data from the output cache (e.g., Cache9) of the last operator. Upon receiving the notification, the processor configures the DMA controller to move the data from Cache9 to memory. At this time, the DMA controller is not an operator controlled by the hardware scheduler. It is easy to understand that in other embodiments, the hardware accelerator may only have DMAI or DMAO operators, such as... Figure 8A As shown. Figure 8A In this process, external data to be processed can be directly loaded into the input of the DFE operator and passed through to the output buffer of the DEF operator, so there is no need to allocate an input buffer for the DEF operator.

[0075] In addition to the sequential connection of multiple operators, the hardware accelerator of this disclosure also supports various connection methods, such as... Figure 9BAs shown, after operator B processes the input data multiple times, operator C reads the data processed by operator B. This means the data stream can loop. When an operator needs to perform multiple processing operations on a data block, such as when operator B needs to process the data block output by operator A twice consecutively, the hardware scheduler can be designed through software code to schedule operators and reallocate buffers for operators in the following way, achieving data stream looping: At time step N, after operator B completes its first processing of the data block, the output buffer of operator B at time step N is reallocated to operator B. At time step N+1, the input buffer of operator B at time step N is reallocated to the output buffer of operator B at time step N+1. At time step N+1, operator B processes the data block again. Before the start of time step N+2, the output buffer of operator B at time step N+1 is allocated to the input buffer of operator C at time step N+2. In this way, at time step N+2, operator C can read the data block from the allocated input buffer for subsequent processing, realizing one loop of the data stream at operator B, where N is a positive integer.

[0076] By designing the software code, the operators to be looped and the number of loops can be specified, enabling the data stream to loop back at the specified operators a specified number of times. The looping in this embodiment can be between the input and output of a single operator, or between the input and output of a computational unit composed of multiple operators. When multiple operators of the same type exist, such as... Figure 9B When there are two operators B, the software code connects the four operators in the order of operator A, operator B, operator B, and operator C, which has the same effect as looping back once at operator B (performing the process twice).

[0077] Besides changing the connection relationships of operators, different operators can be specified to implement different applications by generating corresponding software code. For example, if the current application's computation task does not require the participation of operator A, operator A can be omitted, and only operators B and C can be specified to participate in the computation task. During operation, only operators B and C are cached and scheduled. In this case, the data flow of the hardware accelerator is as follows: Figure 9B As shown by the dashed line.

[0078] The hardware accelerator solution of this disclosure can decompose the radar signal processing flow into multiple computational operations, each implemented by multiple operators. All operators are connected to a shared memory pool, and data interaction between operators is achieved through the memory pool. Furthermore, the memory pool's space allocation and operator scheduling are exposed and defined by software instructions, thus being relatively decoupled from the hardware design. Therefore, the hardware acceleration solution of this disclosure has high performance and application flexibility.

[0079] This disclosure also provides a computing system, including a processor, memory, and a hardware accelerator, see [link to relevant documentation]. Figure 7 As shown, where:

[0080] The processor is configured to load the data to be processed stored in the memory into the hardware accelerator;

[0081] The memory is configured to store data to be processed, and to store data obtained by the hardware accelerator after processing the data to be processed.

[0082] The hardware accelerator is configured to allocate caches to multiple operators based on a set connection order to form a data interaction channel between the multiple operators; and to control the multiple operators to start sequentially according to the set connection order, to complete the processing of the loaded data to be processed in a pipeline manner, and to store the processed data in the memory.

[0083] The computing system of this disclosure can be integrated on a SoC chip. The hardware accelerator can allocate caches to multiple operators based on a set connection order to form data interaction channels between the operators; and control the multiple operators to start sequentially according to the set connection order, completing the processing of the loaded data in a pipeline manner. Therefore, users can generate software code according to computing tasks in different usage scenarios. The hardware scheduler runs the software code, flexibly selecting multiple operators required for the computing task and setting the connection relationships between the multiple operators and the data flow direction when the multiple operators are working, to adapt to the processing flow requirements of the computing task.

[0084] As mentioned above, the radar signal processing flow includes multiple stages, each of which can be accelerated by its respective hardware accelerator. Therefore, the computing system in this embodiment can have multiple hardware accelerators. For example, a first hardware accelerator can be set to accelerate the 1D-FFT stage, a second hardware accelerator to accelerate the 2D-FFT stage, and a third hardware accelerator to accelerate the CFAR stage. More accelerators can also be set to perform other processing such as target recognition and target tracking. During software code development, the parallel use of multiple hardware accelerators can be fully considered to utilize the maximum data processing capacity per unit chip area.

[0085] In a hardware accelerator, one or more operators of the same type can be configured. Multiple hardware accelerators can be started sequentially. For example, after the first hardware accelerator, which is used to accelerate the 1D-FFT stage processing, processes the data output by the ADC, it stores the processed 1D-FFT data in memory, loads it into the second hardware accelerator, which is used to accelerate the 2D-FFT stage processing, and starts the second hardware accelerator. After the second hardware accelerator processes the 1D-FFT data, it stores the obtained data (such as the RD map) in memory, loads it into the third hardware accelerator, which is used to accelerate the CFAR stage processing, and so on, until the final processing result is obtained.

[0086] Figure 7 The processors mentioned include CPUs and DSPs, which are merely exemplary. The processor in this embodiment can be a general-purpose processor, such as any one or a combination of a central processing unit (CPU), DSP, data processing unit (DPU), and accelerated processing unit (APU), or other conventional processors; the processor can also be an integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), discrete logic or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above devices. That is, the processor in the above embodiments can be any processing device or combination of devices that implements the methods, steps, and logic block diagrams disclosed in the embodiments of this invention.

[0087] In this embodiment, the memory can use storage media such as SRAM, DRAM, NAND Flash, or a combination of multiple storage media. The DRAM can be a Double Data Rate (DDR) chip, a High-Bandwidth Memory (HBM), or the like.

[0088] In this embodiment, the hardware accelerator includes multiple operators connected in a set connection order. If an input buffer is allocated for the first operator from a shared buffer pool, the processor can load the data block to be processed in memory into the input buffer of the first operator. However, if the first operator is an operator that passes through the input data (such as a DFE operator), the processor can directly load the data block to be processed in memory into the input of the operator.

[0089] In an exemplary embodiment of this disclosure, the hardware accelerator in the computing system employs the hardware accelerator described in any embodiment of this disclosure. The computing system can be a system-on-a-chip (SoC), which integrates the hardware accelerator, processor, and memory into a single SoC. In one example of this embodiment, the SoC is a millimeter-wave chip or sensor chip in a radar system, but this disclosure is not limited to this. Although the computing system in this embodiment adopts an SoC architecture, in other embodiments, a separate hardware accelerator can also be used. For example, the hardware accelerator can be implemented using the control chip of a CXL device, and the processor can access the hardware accelerator through the CXL interface. The memory can be a DDR chip on the CXL device connected to the control chip.

[0090] One embodiment of this disclosure also provides a multi-operator control method, applied to a hardware accelerator including multiple operators and a hardware scheduler, such as... Figure 10 As shown, this includes: scheduling the multiple operators sequentially according to a set connection order through time-step scheduling to complete the processing of the data to be processed, wherein the scheduling of each time step includes:

[0091] Step 100: Send a start signal to the activation operator to trigger the activation operator to start a process once; wherein, the activation operator is the operator among the plurality of operators that needs to be controlled to start a process once in this time step;

[0092] Step 101: In response to the fact that all the activation operators have completed the current processing, the scheduling of this time step ends. If the processing of the data to be processed has not been completed, the scheduling of the next time step continues.

[0093] The method in this embodiment can be implemented by executing software code generated for the application using a hardware scheduler. The hardware scheduler can decode the startup instruction in the software code, send a startup signal to the activation operator by executing the decoded startup instruction; and decode the synchronization instruction, determine whether all the activation operators have completed the current processing by executing the decoded synchronization instruction, and end the scheduling of the current time step if all the activation operators have completed the current processing. A scheduling operation can be completed by the cooperation of the startup instruction and the synchronization instruction. In this embodiment, a combination of a startup instruction and a synchronization instruction is also referred to as a set of scheduling instructions. As mentioned above, some operators, such as the DFE operator, also perform corresponding calculations, but do not require a control signal to start the processing and have a small computational load. These operators may not be scheduled as activation operators.

[0094] The embodiments of the present disclosure take a time step as the time unit for scheduling, trigger the activation operator to start one processing by sending a start signal (such as a pulse signal) to the activation operator, and end the scheduling of the current time step after all activation operators have completed the current processing. Synchronous processing of activation operators in units of time steps is realized, making the processing of multiple operators orderly, with a simple control mode, which can avoid conflicts such as the subsequent operator reading data when the preceding operator has not yet output the data required by the subsequent operator.

[0095] In an exemplary embodiment of the present disclosure, the scheduling by time steps causes the multiple operators to start sequentially according to a set connection order to complete the processing of the data to be processed, including: performing multiple cycles of control, and in each cycle, through scheduling of multiple time steps, controlling the multiple operators to complete the processing of multiple data blocks in the data to be processed in a pipeline manner; wherein each activation operator completes the processing of one data block in one time step, and sends a current processing end signal after completing the processing of one data block to notify the hardware scheduler. In this embodiment, all data to be processed is processed through multiple cycles of control, and each cycle can make multiple operators process concurrently in a pipeline manner through scheduling, so the efficiency is very high.

[0096] For a hardware accelerator, different computing tasks have different processing flows, and the cyclic processing process defined in the embodiments of the present disclosure does not mean that all computing tasks of the hardware accelerator must use such a flow.

[0097] In an example of this embodiment, each cycle process includes M time steps, M=m1+m2-1, where m1 is the number of the multiple operators, m2 is the number of data blocks processed in each cycle, m1≥2, m2≥2;

[0098] When m<m1, the activation operators at the m-th time step are the 1st to the m-th operators, m=1,2,…,M;

[0099] When m1≤m≤m2, the activation operators at the m-th time step are all of the multiple operators;

[0100] When m2<m≤M, the activation operators at the m-th time step are the (m-m2+1)-th to the m1-th operators.

[0101] Description is given by taking an example of a radar system hardware accelerator including 3 operators, such as Figure 11AAs shown, the operators of the hardware accelerator include a bandwidth extension (BWE: Bandwidth Extension) operator, an FFT operator, and an SVA operator connected in sequence. The processing of the data to be processed is completed through multiple cycles. The radar system includes 4 receiving channels, and the data to be processed includes data on the 4 receiving channels. It is assumed that the data on each channel includes 128 data blocks. Then the processing of the data to be processed can be completed through 128 cycles, and each cycle completes the processing of 4 data blocks on the 4 channels, where the 4 data blocks may be data corresponding to the same chirp signal.

[0102] Figure 11A shows the assembly line of the 3 operators, and only the processing of each operator in each time step in the first two cycles is shown. In the figure, each row represents an operator, each column represents a time step, and the channel number in the small square at the intersection of the row and the column is the serial number of the channel where a data block processed by the operator represented by the row at the time step represented by the column is located. As shown in the figure, only the BWE operator starts at the first time step of the first cycle, the BWE operator and the FFT operator start at the second time step, the BWE operator, the FFT operator and the SVA operator all start at the third time step and the fourth time step, the FFT operator and the SVA operator start at the fifth time step, and the SVA operator starts at the sixth time step, thereby completing one cycle. The start sequence of each operator in each cycle and the activated operators in each time step are the same. For a single operator, there are 2 idle time steps between each cycle. But in Figure 11B in another embodiment shown, there is no idle time step for the operators between two cycles, and the situation that some operators are inactive (not started or have exited the processing) only occurs in the first two time steps at the beginning of the first cycle and the last two time steps of the last cycle.

[0103] still take Figure 11A as an example, corresponding to this embodiment, m1 is the number of the plurality of operators, that is, equal to 3, m2 is the number of data blocks processed in each cycle, equal to the number of receiving channels 4, then M=m1+m2-1=6, that is, each cycle has 6 time steps, and in each cycle:

[0104] When m<m1, the activated operators at the m-th time step are the 1st to m-th operators; corresponding to this example, that is, when m<3, the activated operators at the first time step are the first operator, i.e., the BWE operator, and the activated operators at the second time step are the first operator and the second operator, i.e., the BWE operator and the FFT operator;

[0105] In the case where m1≤m≤m2, the activation operators at the m-th time step are all of the plurality of operators, which corresponds to this example where 3≤m≤4, all operators at the 3rd time step and the 4th time step, namely the BWE operator, FFT operator and SVA operator, are activation operators;

[0106] In the case where m2<m≤M, the activation operators at the m-th time step are the (m-m2+1)-th to the m1-th operators; which corresponds to this example where 4<m≤6, the activation operators at the 5th time step are the 2nd operator and the 3rd operator, namely the FFT operator and the SVA operator, and the activation operator at the 6th time step is the 3rd operator, namely the SVA operator.

[0107] It can be understood that when m1 and m2 are other values, the rule for determining the activation operators in this embodiment is still satisfied.

[0108] In this example, 4 pairs of caches can be allocated to each operator, and each pair of caches includes an input cache and an output cache. In each loop, each operator performs 4 processes in 4 time steps, and the 4 processes are respectively for data blocks of 4 channels, and each process uses one of the 4 allocated pairs of caches, so that the data of the 4 channels are independent of each other. That is, for an operator that needs to process data of each channel independently, the number of cache pairs allocated to it may be equal to the number of channels of the radar system. For other operators that do not have such a requirement, more than 2 pairs of caches can be allocated. Whether an operator processes the data of each channel independently can be determined according to the requirements of the current application.

[0109] In an exemplary embodiment of the present disclosure, the control method further includes: respectively allocating caches used for accessing data to the plurality of operators, where the allocated caches include input caches and / or output caches; wherein the caches allocated to the plurality of operators are all from a shared cache pool, the plurality of caches allocated to the plurality of operators for use in the same time step are located in different and independently accessible areas in the shared cache pool, and for adjacent operators, the output cache allocated to the preceding operator for use in the current time step is the input cache allocated to the subsequent operator for use in the next time step, so as to form a data interaction channel between adjacent operators. In the present application, adjacent operators among the plurality of operators can be determined according to the set connection sequence of the plurality of operators. From the perspective of data interaction, when the output data of one operator is the input data of another operator, the two operators are adjacent operators, wherein the operator that outputs the data is the preceding operator, and the operator that takes the output data of the preceding operator as input data is the subsequent operator.

[0110] In one example of this embodiment, allocating caches for data access to the plurality of operators includes: before performing the multiple loop control operations, allocating caches for the first processing of each of the plurality of operators, wherein, for adjacent operators among the plurality of operators, the output cache allocated to the preceding operator is the input cache allocated to the following operator. In this example, caches are allocated to specified operators before the start of loop control. The information of the allocated caches may include row information and column information, which can be represented by offset, size, block information, etc. Here, the caches allocated are for the first processing of each operator, not for use in the same time step; therefore, the output cache allocated to the preceding operator can be the input cache allocated to the following operator.

[0111] In one example of this embodiment, after allocating caches for the multiple operators to be used during the loop before the loop, the allocation of caches for the multiple operators to access data further includes: reallocating caches for operators that are active in both the previous and next time steps between two adjacent time steps; wherein, for adjacent operators among the multiple operators, the output cache allocated (including reallocation) for the preceding operator in the next time step is different from the input cache allocated for the following operator in the next time step. This example achieves the switching of caches used by operators between multiple or multiple pairs of allocated caches by reallocating caches (the multiple or multiple pairs of allocated caches can be a collection of caches allocated multiple times during the loop, and do not necessarily need to be allocated simultaneously), and the output cache allocated for the preceding operator in the next time step is different from the input cache allocated for the following operator in the next time step, which can ensure that two operators will not access the same cache simultaneously and cause a conflict. It should be noted that the cache used by the operator switches between multiple or multiple pairs of caches allocated. It is not necessary to allocate multiple or multiple pairs of caches at once. This can be achieved by the hardware scheduler performing the cache reallocation operation, or by the operator's hardware logic combined with configuration information (such as the total number of allocated caches or the total number of pairs).

[0112] In one example of this embodiment, for each of the plurality of operators, there are K groups of buffers allocated and reallocated for the preceding operator during the multiple loops, where K ≥ 2. Each group includes an input buffer and / or an output buffer. Starting from the first processing of the operator, with a period of K time steps, the buffer used by the operator in the kth time step of different periods is the same, and the buffer used in different time steps of the same period is different.

[0113] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system processing the received signal; the plurality of operators include operators performing 1D-FFT stage processing, and one data block in the data to be processed is the data of a chirp signal received on a channel; or, the plurality of operators include operators performing 2D-FFT stage processing, and one data block in the data to be processed is the data at the same range gate in the 1D-FFT data, wherein the 1D-FFT data is the data obtained after the 1D-FFT stage processing, including the data of multiple chirps.

[0114] One embodiment of this disclosure also provides a hardware scheduler, such as Figure 12 As shown, it includes a memory 50 and a control device 60, wherein the memory stores software code for controlling multiple operators, and the control device is configured to run the software code to execute the multi-operator control method described in any embodiment of this disclosure (including...). Figure 10 The control method of the corresponding multi-operator implementation, Figure 19 (A control method for multiple operators in a corresponding embodiment). The control device can be any device capable of implementing control functions according to software code.

[0115] One embodiment of this disclosure also provides a hardware accelerator, which can be found in [reference 1]. Figure 7 It includes a hardware scheduler and a plurality of specified operators, wherein the hardware scheduler adopts the hardware scheduler described in any embodiment of this disclosure.

[0116] In an exemplary embodiment of this disclosure, the hardware accelerator further includes a shared cache pool and a register set that provide cache space for operators; wherein:

[0117] The hardware scheduler controls the plurality of operators by: allocating caches from the shared cache pool for the plurality of operators to use when accessing data, wherein the caches include input caches and / or output caches;

[0118] The register group is configured to store configuration information for the plurality of operators. The configuration information includes information on the cache allocated to the operators, and may also include other information such as parameters configured for the operators.

[0119] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; if an output cache is allocated, write the processed data into the output cache.

[0120] In an exemplary embodiment of this disclosure, the plurality of operators sequentially include: a CQMD operator, an FFT operator, and an SVA operator; or, the plurality of operators sequentially include: a DC operator, an FFT operator, and an SVA operator; or, the plurality of operators sequentially include: a CMB operator, a STAS operator, a HIST operator, a CFAR operator, and a STAS operator; or, the plurality of operators sequentially include: a DC operator, an FFT operator, an SVA operator, and a CMB operator.

[0121] One embodiment of this disclosure also provides an integrated circuit, such as... Figure 13 As shown, the integrated circuit includes a radio frequency module 2011, an analog signal processing module 2012, and a digital signal processing module 2013 connected in sequence, wherein:

[0122] The radio frequency module 2011 is configured to generate and transmit electromagnetic wave signals, and to receive echo signals;

[0123] The analog signal processing module 2012 is configured to down-frequency the echo signal to obtain an intermediate frequency signal; and

[0124] The digital signal processing module 2013 is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; wherein the digital signal processing module includes the hardware accelerator described in any embodiment of this disclosure.

[0125] In an exemplary embodiment of this disclosure, the integrated circuit is a millimeter-wave chip or sensor chip used in a radar system.

[0126] One embodiment of this disclosure also provides an electromagnetic wave device, such as... Figure 14 As shown, it includes: a carrier 4; an integrated circuit 5 according to any embodiment of this disclosure, disposed on the carrier 4; and an antenna 6 disposed on the carrier 4, either integrated with the integrated circuit 5 as a single device or disposed separately; wherein the integrated circuit 5 is connected to the antenna 6 and is used to transmit the electromagnetic wave signal and / or receive the echo signal.

[0127] An embodiment of this disclosure also provides an apparatus, including: an apparatus body; and an electromagnetic wave device disposed on the apparatus body as described in any embodiment of this disclosure; wherein the electromagnetic wave device is configured to perform target detection and / or communication to provide reference information to the operation of the apparatus body.

[0128] The following describes an exemplary hardware accelerator that enables a 1D-FFT stage processing flow and a corresponding multi-operator control method.

[0129] The 1D-FFT stage primarily involves performing noise compensation on the echo ADC data at the front end, followed by interference detection, Fast Discrete Fourier Transform (FFT), and Spatial Vector Analysis (SVA) to obtain frequency domain data. This data is then moved from the accelerator buffer to the external memory via DMA. Operators used in the 1D-FFT stage include: a Digital Front End (DFE) operator for noise compensation; a CQMD operator for interference detection; an FFT operator for performing FFT; an SVA operator for sidelobe suppression; and a DMA operator for storing data in memory. Data exchange between operators is sequential; for each operator, the input data is the data to be processed, and the output data is the processed data.

[0130] In this embodiment, the cache allocation and scheduling of each operator are as follows:

[0131] DFE operator: It belongs to the data pass-through module and is not controlled by the start instruction and synchronization instruction, but it needs to allocate a buffer to buffer the pass-through data. The DFE operator can pass-through the input data to the output buffer and perform statistics on the input data. The amount of statistical results is very small and can be written to the output buffer or register group for use by subsequent operators.

[0132] CQMD operator: Controlled by start command and synchronization command, and requires buffer allocation for CQMD operator to read input data and write output data;

[0133] FFT operator: Controlled by start instructions and synchronization instructions, and requires the allocation of input buffer and output buffer for FFT to read input data and write output data;

[0134] SVA operator: Controlled by start instructions and synchronization instructions, and requires the allocation of input buffer and output buffer for SVA to read input data and write output data;

[0135] DMA operator: Controlled by start and synchronization instructions, it requires an input buffer to read input data. DMA moves the input data to the chip's memory and does not require an output buffer.

[0136] In terms of cache physical space, the data flow between operators in this embodiment is sequential. The input data of CQMD is the output data of the DFE operator, the input data of FFT is the output data of CQMD, and the input data of DMA is the output data of SVA. Figure 15As shown, the caches allocated to each operator are divided into four levels. Each level includes two caches: the first level is the output cache allocated to the DFE operator and the input cache allocated to the CQMD operator; the second level is the output cache allocated to the CQMD operator and the input cache allocated to the FFT operator; the third level is the output cache allocated to the FFT operator and the input cache allocated to the SVA operator; and the fourth level is the output cache allocated to the SVA operator and the input cache allocated to the DMA operator.

[0137] In the time dimension, in this embodiment, when a later operator accesses data in the input buffer, it must be ensured that the data processed by the previous operator has been completely written to the output buffer to avoid access conflicts. To this end, this embodiment divides the time dimension into two alternating time steps (also called time slices or time units). In odd-numbered time steps (time steps 1, 3, 5, ...), the DFE operator processes the ADC data of chirps with odd indices, and writes the output data to DFE Cache0 (DFE output cache 0 / CQMD input cache 0 in the diagram). The CQMD operator processes the data in DFE Cache1 (DFE output cache 1 / CQMD input cache 1 in the diagram), and writes the output data to CQMD Cache1 (CQMD output cache 1 / FFT input cache 1 in the diagram). The FFT operator processes the data in CQMD Cache0 (CQMD output cache 0 / FFT input cache 0 in the diagram), and writes the output data to FFT Cache0 (FFT output cache 0 / SVA input cache 0 in the diagram). The SVA operator processes the data in FFT Cache1 (FFT output cache 1 / SVA input cache 1 in the diagram), and writes the output data to SVACache1 (SVA output cache 1 / DMA input cache 1 in the diagram). The DMA operator processes the SVA... Data in Cache0 (SVA output cache 0 / DMA input cache 0 in the diagram) is moved to external memory. The above odd-numbered time steps process data for chirps with odd indices such as 1, 3, 5, ... based on the case where chirp indices start from 1. If chirp indices start from 0, then odd-numbered time steps are used to process data for chirps with even indices such as 0, 2, 4, ...

[0138] The data flow for the odd-numbered time steps is shown by the solid arrows in the figure. Similarly, in the even-numbered time steps (the 2nd, 4th, 6th, ... time steps), each operator processes the data of other chirps. The dashed arrows in the figure represent the data flow direction for each operator to read and write data, which will not be elaborated here.

[0139] Although this embodiment allocates two input buffers and / or two output buffers (dynamically allocated) to each operator, switching between the two input buffers and / or two output buffers at a period of two time steps (odd time steps and even time steps), it is easy to understand that it is also feasible to allocate more than three input buffers and / or output buffers to each operator, switching between more than three input buffers and / or output buffers at a period of more than three time steps. For example, when the radar system has four receiving channels, four input buffers and / or four output buffers can be allocated to each operator, switching between the four input buffers and / or four output buffers at a period of four time steps, processing the data of one receiving channel at each time step. This allows for independent processing of the data from each channel. This embodiment avoids access conflicts between operators, such as access conflicts caused by simultaneous reading and writing to the same cache, by allocating different caches for operators at odd and even time steps, and for adjacent operators, the output cache allocated for the preceding operator in the next time step is different from the input cache allocated for the following operator in the next time step.

[0140] In a time step where multiple operators are started, the processing bandwidth and processing time of each operator differ. Upper-level instruction control must ensure synchronization of operators within the time step. In this embodiment, the hardware scheduler uses a set of scheduling instructions to synchronize operators. Each set of instructions includes a start instruction and a synchronization instruction. The start instruction controls the operator to begin processing, and the synchronization instruction determines whether the operator has completed its processing. The execution of the synchronization instruction ends when all operators have completed their processing. The time step proposed in this application begins with the execution of the start instruction in a set of scheduling instructions and ends when the execution of the synchronization instruction in that set of scheduling instructions is completed.

[0141] The table below shows the scheduling process for each operator in the hardware accelerator at each time step, where L1, L2, ... L... n This represents the 1st, 2nd, and up to the nth time step. Each time step can be divided into a start area (starting the operator) and a sync area (synchronization between operators) to ensure the synchronization of different operators. As mentioned earlier, the DFE operator does not need to be controlled by scheduling instructions, so it is not shown in the table.

[0142]

[0143]

[0144] As shown in the table above, the start and synchronization instructions for the first time step L1 are sent to the CQMD operator to start it, and the synchronization for this time step ends after the CQMD operator finishes processing (completes processing of all data in the input buffer and writes the processed data to the output buffer). The start and synchronization instructions for the second time step L2 are sent to both the CQMD and FFT operators to start them simultaneously, and the synchronization for this time step ends after both the CQMD and FFT operators have finished processing. The start and synchronization instructions for the third time step L3 are sent to the CQMD, FFT, and SVA operators to start them simultaneously, and the synchronization for this time step ends after all three operators have finished processing. From the fourth time step L4 to the (n-3)th time step L... n-3 The start and synchronization instructions for each time step are sent to the CQMD, FFT, SVA, and DMA operators to simultaneously start them. Synchronization for the current time step ends after all three operators have finished processing. The (n-2)th time step L... n-2 The start and synchronization instructions are sent to the FFT operator, SVA operator, and DMA operator to start them simultaneously, and the synchronization of this time step ends after all three operators have finished processing; the (n-1)th time step L n-1 The start and synchronization instructions are sent to both the SVA and DMA operators to start them simultaneously, and the synchronization ends at the current time step after both the SVA and DMA operators have finished processing; in the nth time step L n Both the start command and the synchronization command are sent to the DMA operator to start the DMA operator, and the synchronization of the current time step ends after the DMA operator has finished processing. One cycle of processing is completed in n time steps.

[0145] In this embodiment, the aforementioned n time steps are the time steps taken to obtain the processing result of the input dataset (such as a frame of ADC data) through multiple loop processing. It can be seen that, except for the first three time steps where each operator starts processing sequentially and the last three time steps where each operator exits sequentially, all operators in other time steps process synchronously. Each loop can process one data block at the corresponding position of all channels, and the next loop can begin before the processing of one loop is completely finished. The entire process is carried out in a pipeline manner. Taking its application in a radar system as an example, considering the characteristics of radar data processing, an application typically has thousands of data blocks to process. For over 99% of the entire processing time, all operators and buffers are 100% utilized, thus maximizing the processing capacity of the chip per unit area.

[0146] In the design of hardware accelerators, it is possible to make the processing time of multiple operators consistent as much as possible in order to maximize resource utilization. In this embodiment, the CQMD operator, FFT operator, and SVA operator process roughly the same amount of data per run, and their processing time within a time step is consistent. Even with a simple scheduling method, they still achieve high efficiency.

[0147] In another embodiment, the n time steps in the table above can be processed in a single loop. For example, when the radar system includes 8 receiving channels, the data from the 8 chirps received by the 8 receiving channels can be processed in 11 time steps. In this loop, all operators are executing processing in time steps 4 to 8. Starting from time step 9, the CQMD operator, FFT operator, and SVA operator exit the processing of this loop one by one. In time step 11, only the DMA operator works. After time step 11 ends, the next round of loop processing begins. In this embodiment, multiple operators still work in a pipeline manner during each loop processing, and this application still refers to it as a pipeline operation mode.

[0148] As described above, the multiple operators specified in this embodiment can be soft-connected through software code. Based on the same hardware accelerator, different software codes can be generated when facing different computing tasks. Through cache allocation instructions in the software code, caches are allocated to the specified multiple operators based on the set connection order to form a data interaction channel between operators. Simultaneously, data processing in this embodiment is executed through hardware-accelerated operators. Scheduling instructions can control multiple operators to start sequentially and process in parallel in a pipeline manner. Therefore, the hardware accelerator in this embodiment has application flexibility, does not require frequent data transfer, and also has good performance and low power consumption, effectively resolving the contradiction between application flexibility and high performance / low power consumption in hardware accelerators. The hardware accelerator in this embodiment can be applied not only to radar systems but also to other systems that require hardware accelerators.

[0149] This disclosure also provides a control device (referred to as a first control device when it needs to be distinguished from the control devices of other embodiments), for controlling a plurality of operators configured to process data to be processed according to a set connection order, the control device comprising:

[0150] The instruction decoding circuit is configured to decode software code, which includes multiple sets of scheduling instructions. Each set of scheduling instructions includes a start instruction and a synchronization instruction. The start instruction includes operands for indicating which operator needs to be started, and the synchronization instruction includes operands for indicating which operator needs to be synchronized.

[0151] The instruction execution circuit, coupled to the instruction decoding circuit, is configured to, in response to a start instruction in a set of decoded scheduling instructions, control the operator indicated by the operand to start a processing operation; and, in response to a synchronization instruction in the set of decoded scheduling instructions, determine that all operators indicated by the operands have completed the current processing operation, and then terminate the execution of the synchronization instruction.

[0152] The control device in this embodiment can be the logic control circuit in the aforementioned hardware scheduler. For example... Figure 16 As shown, the instruction decoding circuit 10 reads the instructions in the software code and decodes them. The decoded instructions are executed by the instruction execution circuit 20 and converted into corresponding operations, such as sending a start signal, reading or writing registers, etc.

[0153] The following is a set of pseudocode examples of scheduling instructions:

[0154] start_eng_q0 BWE+FFT

[0155] sync_q0 BWE+FFT

[0156] The pseudocode for the start instruction is "start_eng_q0 BWE+FFT". "start_eng_q0" indicates that this instruction is a start instruction, and "BWE+FFT" indicates that the operators to be started are the BWE and FFT operators. The pseudocode for the synchronization instruction is "sync_q0 BWE+FFT". "sync_q0" indicates that this instruction is a synchronization instruction, and "BWE+FFT" indicates that the operators to be synchronized are the BWE and FFT operators. During the execution of the synchronization instruction, the instruction execution circuit can monitor the status of the BWE and FFT operators. When it determines that both operators have completed processing (e.g., when it receives a completion signal from either operator), the execution of the synchronization instruction ends, and subsequent instructions can then be executed.

[0157] This embodiment decodes multiple sets of scheduling instructions through an instruction decoding circuit and then executes them through an instruction execution circuit. One scheduling can start one or more operators and end after all the started operators have completed processing. Therefore, it can control the operators to complete the processing of the data to be processed step by step in a time step manner, ensuring that the operators connected according to the set connection order process the data blocks in the correct time order, avoiding conflicts such as when the previous operator has not yet outputted the data required by the subsequent operator while the subsequent operator is reading data.

[0158] In an exemplary embodiment of this disclosure, the start instruction includes an opcode and operands represented by a bitmap. Each of the plurality of operators corresponds to one bit in the bitmap, and the value of this bit indicates whether the operator needs to be started. The synchronization instruction includes an opcode and operands represented by a bitmap. Each of the plurality of operators corresponds to one bit in the bitmap, and the value of this bit indicates whether the operator needs to be synchronized. After the start instruction is decoded and executed, a start signal can be generated for each operator that needs to be started. This signal is sent to the operator through a dedicated interface such as a signal line to trigger the operator to begin a processing cycle. The pseudocode mentioned above is not the actual executed instruction; the format of the actual instruction is described here.

[0159] In an exemplary embodiment of the present disclosure, a single instruction in the software code is a 16-bit, 32-bit or 64-bit short instruction. In some scenarios, 128-bit instructions are adopted, which have a relatively wide bit width and are not friendly to instruction encoding and parsing. Moreover, for some instructions, 128 bits cannot be fully utilized. For example, a STOP instruction only uses the high 6 bits, resulting in a waste of instruction set storage space. The embodiments of the present disclosure adopt short instructions of less than 128 bits, such as 32-bit short instructions, which facilitate encoding and parsing and help improve the efficiency of instruction execution. The embodiments have, but are not limited to, the following advantages: 32 bits can be effectively utilized to avoid a large amount of bit waste, which is beneficial to saving the storage space of the instruction set; the instruction combination is more flexible, which facilitates users to implement various functions; the hardware implementation of the scheduler is simpler, reducing the possibility of errors; and the transmission efficiency of short instructions is higher, which reduces the power consumption and running time of the radar signal processor.

[0160] In an exemplary embodiment of the present disclosure, the software code decoded by the instruction decoding circuit further includes a loop start instruction and a loop end instruction, where the loop start instruction includes an operand indicating the number of loops; the multiple sets of scheduling instructions are located between the loop start instruction and the loop end instruction; correspondingly, the instruction execution circuit executes multiple loop processes in response to the decoded software code, and controls the multiple operators to complete the processing of the to-be-processed data in a pipeline manner according to a set connection sequence; wherein each loop process includes a plurality of time steps, each time step starts with executing a start instruction in a set of scheduling instructions and ends when the execution of a synchronization instruction in the set of scheduling instructions is completed, and each operator started at each time step completes the processing of one data block in the to-be-processed data at that time step.

[0161] An example of loop-related instructions is shown below in pseudo-code:

[0162]

[0163]

[0164] Instructions for reallocating a cache may also be inserted between the above set of scheduling instructions, as described below.

[0165] In an exemplary embodiment of the present disclosure, M sets of scheduling instructions are included between the loop start instruction and the loop end instruction, each loop process includes M time steps, M = m1 + m2 - 1, m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each loop, and m1 ≥ 2, m2 ≥ 2;

[0166] In the case where m < m1, the activated operators at the m-th time step are the 1st to the m-th operators, m = 1, 2, ..., M;

[0167] In the case of m1≤m≤m2, the activation operators at the m-th time step are all operators among the plurality of operators;

[0168] In the case of m2<m≤M, the activation operators at the m-th time step are the (m-m2+1)-th to the m1-th operators;

[0169] Wherein, the operators to be started indicated by the start instruction in the m-th set of scheduling instructions are the activation operators at the m-th time step.

[0170] For the activation operators (i.e., the operators that need to be started) at each of the above time steps, reference may be made to the foregoing description of Figure 11A the example shown, which may be specifically implemented by generating software code.

[0171] In an exemplary embodiment of the present disclosure, the software code decoded by the instruction decoding circuit further includes a plurality of cache allocation instructions; in response to the plurality of cache allocation instructions, the instruction execution circuit respectively allocates caches used for accessing data for the plurality of operators;

[0172] Wherein, the caches allocated for the plurality of operators are all from a shared cache pool, and the multiple caches allocated for the plurality of operators to be used at the same time step are located in different and independently accessible areas in the shared cache pool, so as to avoid access conflicts caused by two operators accessing one cache at the same time;

[0173] Wherein, the allocated caches include input caches and / or output caches, and for adjacent operators among the plurality of operators, the output cache allocated for the preceding operator to be used at the current time step is the input cache allocated for the subsequent operator to be used at the next time step, so as to form a data interaction channel between adjacent operators.

[0174] In an exemplary embodiment of the present disclosure, the plurality of cache allocation instructions decoded by the instruction decoding circuit include a plurality of first cache allocation instructions located before the loop start instruction, and the first cache allocation instructions include: a first operand, configured to indicate the position and size of the cache initially allocated for the operator; a second operand, configured to indicate the storage space to which the first operand is to be written;

[0175] The instruction execution circuit is further configured to, in response to the decoded plurality of first cache allocation instructions, write the first operand in each first cache allocation instruction into the storage space indicated by the second operand in the cache allocation instruction, so as to respectively allocate caches to be used in the first processing for the plurality of operators.

[0176] The cache space of the shared cache pool can be a storage array, including multiple rows and columns. The aforementioned first cache allocation instruction can be a single instruction or multiple related instructions. In one example of this embodiment, where a single instruction in the software code uses a short instruction, the first cache allocation instruction includes multiple short instructions.

[0177] The first operand, used to indicate the location and size of the cache, can include multiple immediate values ​​representing the position of the first row, the number of rows, and the position and number of the first column. The position of the first row and the position of the first column can be represented by the index of the first row and the index of the first column, respectively. The number of rows and columns can be represented in various ways. For example, the number of rows can be represented directly by the value of the number of rows, or by the combination of the index of the first row and the index of the last row, or by the size and number of banks (areas, which can be understood as a set of rows) in the row direction. That is, one or more numbers can be used to represent them directly or indirectly. The second operand, used to indicate the memory space to be written to by the first operand, can be a register address. However, not every immediate value needs to be written to this register address; it is sufficient that the register address to which each immediate value needs to be written can be obtained based on this register address.

[0178] Here is an example of a first cache allocation instruction represented in pseudocode:

[0179]

[0180] In the pseudocode above, each line represents an instruction. The first line, wr_que0, indicates writing to a register. 0xb00 is the register address, and 29 indicates that 30 numbers are to be written. The first number is written to address 0xb00, the second to address 0xb04, the third to address 0xb08, and so on, jumping sequentially.

[0181] In each line, Wdat represents the written data. The immediate value in line 2 is defined as the position of the first column in the SVA input buffer, with a configured value of 16, indicating that the index of the first column is 16. The immediate value in line 3 is defined as the position of the first row in the SVA input buffer, with a configured value of 0, indicating that the index of the first row is 0. The immediate value in line 4 is defined as the size of the BANK (set of columns) in the column direction of the SVA input buffer, with a configured value of 3, indicating that a BANK in the column direction has 4 columns. The immediate value in line 5 is defined as the size of the BANK in the row direction of the SVA input buffer, with a configured value of 11, indicating that a BANK in the row direction has 12 rows. The immediate value in line 6 is defined as the number of BANKs included in the column direction of the SVA input buffer, with a configured value of 3, indicating that there are 4 BANKs. The immediate value in line 7 is defined as the number of BANKs included in the row direction of the SVA input buffer, with a configured value of 2, indicating that there are 3 BANKs. By combining multiple instructions, the input buffer allocated to the SVA operator has a first column index of 16, a total of 4×4 columns, a first row index of 0, and a total of 12×3 rows. The information for the output buffer allocated to the SVA operator can be configured in the same way.

[0182] In the example above, the multiple instructions used to configure the registers can also be called a parameter set, where each line can be 32 bits, but a single instruction cannot independently implement a specific function.

[0183] In an exemplary embodiment of this disclosure, the multiple cache allocation instructions decoded by the instruction decoding circuit further include a second cache allocation instruction located between two adjacent sets of scheduling instructions. The second cache allocation instruction includes: a first operand, used to indicate the location of the cache to be reallocated for the operator in the next time step; and a second operand, used to indicate the storage space to be written to by the first operand.

[0184] The instruction execution circuit is further configured to, in response to each decoded second cache allocation instruction, write the first operand therein to the storage space indicated by the second operand therein, to allocate a cache for use in the next time step for an operator using the storage space; wherein, for adjacent operators among the plurality of operators, the output cache allocated for use in the next time step for the preceding operator is different from the input cache allocated for use in the next time step for the following operator.

[0185] This embodiment uses a second buffer allocation instruction between two sets of scheduling instructions to reallocate buffers for operators. This allows operators to switch between multiple buffers, staggering the output buffer used by the operator at the same time step with the input buffer used by the operator at the next time step. This enables two operators to process data in parallel (including reading and writing data), thus working in a pipelined manner to improve efficiency. The two sets of scheduling instructions in this embodiment can be located in different loop processes.

[0186] The second cache allocation instruction can reallocate caches by changing a few parameters based on the cache allocated by the first cache allocation instruction. An example is as follows:

[0187] Wr_que0 [0xb00],0

[0188] Wdat 32 / / CFG_SVA_INP_BBUF_COL_OFFSET

[0189] In the pseudocode above, line 1 `wr_que0` indicates writing to the register, where 0xb00 is the register address and 0 indicates that the number of data to be written is 1. Line 2 `Wdat` indicates writing data; the immediate value to be written is defined as the index of the first column in the SVA operator's input buffer, configured to a value of 32. The information for the other buffers is the same as that allocated by the first buffer instruction and does not need to be reconfigured. Therefore, when reallocating the buffer, simply updating the index of the first column from 16 to 32 is sufficient to determine the location and size of the input buffer reallocated for the SVA operator. The same applies to the reallocation of the output buffer. Setting the reallocation instruction within a loop reduces the number of instructions required.

[0190] In one example of this embodiment, among the multiple sets of scheduling instructions, the second cache allocation instruction between two adjacent sets of scheduling instructions is used to reallocate the cache position for each operator that performed processing in the previous time step and still needs to perform processing in the next time step; for each of the multiple operators, starting from the time step when the operator is first started, with a period of K time steps, the cache allocated by the instruction execution circuit for the operator in the K time steps of the same period is different, and the cache allocated for the operator in the k-th time step of different periods is the same, k = 0, 1, ..., K-1, K ≥ 2.

[0191] Switching the cache used by an operator during a loop does not necessarily require instructions; it can also be achieved through the operator's hardware logic in conjunction with the configured number of caches. In another exemplary embodiment of this disclosure, the first operand in the first cache allocation instruction is further used to indicate the number K of cache groups used by the operator in the multiple loop processes. This instructs the operator to update the row or column position of the allocated cache step by step, with a period of K time steps, so that the operator uses different caches in the K time steps of the same period and uses the same cache in the k-th time step of different periods, where k = 0, 1, ..., K-1, K ≥ 2. The "number K of cache groups" here is equal to the K in "K cache groups are allocated and reallocated for the operator" mentioned above. When only an input buffer is allocated to an operator, the number K in this group represents the number of input buffers; when only an output buffer is allocated to an operator, the number K in this group represents the number of output buffers; when both input and output buffers are allocated to an operator (i.e., allocated in pairs), the number K in this group represents the number of pairs of input and output buffers, i.e., 4 input buffers and 4 output buffers are allocated in this case.

[0192] For example, in the example of the first cache allocation instruction mentioned above, another instruction could be added after the last instruction:

[0193] Wdat 3 / / CFG_SVA_BBUF_PPG_NUM

[0194] The immediate value in this pseudocode is defined as the number of caches allocated by the SVA operator. A configured value of 3 indicates an allocation of 4 caches. This means that when only the input cache is allocated, the number is 4; when only the output cache is allocated, the number is 4; in this example, when both input and output caches are allocated, the number is 4 for both. However, the input and output caches can also be allocated separately. The number of caches allocated here equals the number of time steps in a cache allocation cycle. Based on this configuration, the SVA operator operates in a cycle of 4 time steps. In each cycle, the caches used by the 4 time steps will cycle sequentially between 4 pairs of caches. These 4 pairs of caches can be defined as having the same size and being sequentially connected in the column direction. The operator updates the position of the cache used in each time step based on the position and size of the first pair of caches and the number of received start signals (which can be counted cyclically using a counter), while keeping the cache size unchanged, thus reallocating the cache on the operator side. This method eliminates the need for a second cache allocation instruction, simplifying the software code.

[0195] In an exemplary embodiment of this disclosure, the instruction execution circuit responds to a start instruction in a decoded set of scheduling instructions by sending a start signal to the operator indicated by the operand to control the operator to start a processing operation; the operator receiving the scheduling instruction among the plurality of operators is configured to: upon receiving the start signal, read the input data block from the input buffer and process it, and save the processing result to the output buffer; and, in response to the data block obtained after processing (i.e. the processing result) being saved to the output buffer, generate a signal indicating that the current processing is complete to notify the instruction execution circuit.

[0196] In this embodiment, the start signal is transmitted through a dedicated interface (such as the line between the hardware scheduler and the operator). In other embodiments, it can also be implemented through a configuration register, such as by setting a register corresponding to an operator to 1 and 0 to generate a pulse signal, and using this pulse signal as a start signal to trigger the operator's start process.

[0197] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system from processing received radar signals; the plurality of operators are operators performing 1D-FFT stage processing, and one data block in the data to be processed is the data of a chirp signal received on a channel; or, the plurality of operators are operators performing 2D-FFT stage processing, and one data block in the data to be processed is the data at the same range gate in the 1D-FFT data. In application fields outside of radar, and in different processing stages within a radar system, the data blocks to be processed by the operators and the amount of data contained in the data to be processed, as well as the physical meaning of the data to be processed, can be different.

[0198] One embodiment of this disclosure provides a hardware scheduler, such as Figure 17 As shown, it includes a control device and an internal memory. The control device includes the control device described in any embodiment of this disclosure (such as a first control device or a second control device). The internal memory is configured to store the software code (also referred to as an instruction queue or instruction set) to be decoded and executed by the control device.

[0199] The hardware scheduler may include one or more memories and one or more control devices. Figure 17 The example shown includes two memories and two control units, capable of simultaneously controlling multiple hardware accelerators. The internal memories can use high-speed storage media such as SRAM to cache software code. The software code in the internal memories can be loaded in several ways: first, it can be written to the internal memories via a bus, which can then be executed by the processor; the bus used could be an Advanced Peripheral Bus (APB); second, it can be initially stored in memory (see...). Figure 7The first method involves moving the data from main memory to internal memory via DMA; the second method involves the hardware scheduler actively reading the software code from a designated address. A multiplexer can be configured to select the data path for each of these three methods. As shown in the diagram, the hardware scheduler connects to the register bank and the shared buffer pool, allowing it to read and write to both. The hardware scheduler can also send start signals to operators and receive completion signals (represented as "done" in the diagram) to indicate that the operator has completed its current processing. The control device can determine whether to terminate the synchronization instruction based on the validity of the "done" signals for all active operators at the current time step.

[0200] One embodiment of this disclosure provides an operator, such as Figure 18 As shown, it includes a data reading unit, a processing unit, and a data writing unit, wherein:

[0201] The data reading unit is configured to acquire information about the input buffer allocated to the operator, and based on the information about the input buffer, read out the data block in the input buffer and input it into the processing unit;

[0202] The processing unit is configured to process the data block to obtain a processed data block;

[0203] The write data unit is configured to obtain information about the output cache allocated to the operator, and write the processed data block into the output cache based on the information about the output cache.

[0204] The operator in this embodiment can be applied to the hardware accelerator described in any embodiment of this disclosure, enabling data to be passed between operators through a cache and allowing information of the allocated cache to be read from the outside. This achieves soft connections (configurable connections) and fast data interaction between operators. While ensuring processing efficiency, the connection relationship between operators and the design of data flow can be changed according to application needs, improving the application flexibility of the hardware accelerator using the operator.

[0205] In an exemplary embodiment of this disclosure, the operator further includes any one or more of the following interfaces:

[0206] The scheduling interface receives a start signal, which is used as a trigger signal for this operator to begin processing.

[0207] The synchronization interface is used to write the processed data block into the output buffer and then send a signal indicating that the processing is complete.

[0208] like Figure 18As shown, the operator can initiate a processing step (which includes reading, processing, and writing data) based on a start signal, such as a pulse signal, sent by the hardware scheduler through the scheduling interface. After processing, the operator returns a "done" signal to the hardware scheduler through the synchronization interface to indicate that the processing is complete. The scheduling interface and synchronization interface can be dedicated interfaces between the hardware scheduler and the operator, such as dedicated lines, or they can be implemented through register configuration.

[0209] In an exemplary embodiment of this disclosure, the read data unit obtains information about the input buffer allocated to the operator from the register set, and the write data unit obtains information about the output buffer allocated to the operator from the register set; the register set can be a register set used by one operator or a register set shared by multiple operators. The hardware scheduler can also write operator parameters, statistical data generated during processing, or other configuration information into the corresponding register set, and is not limited to allocating buffers for operators.

[0210] In an exemplary embodiment of this disclosure, the operator further includes a cache update unit;

[0211] The cache update unit is configured to: read from the register group the location and size of the cache initially allocated to the operator, and the number of cache groups K allocated to the operator, K≥2; and cyclically count the number of times the scheduling interface receives the start signal, with the count value ranging from 0 to K-1; when the cumulative number of cycles is k, calculate the location of the cache used by the operator in the next time step based on the location and size of the initially allocated cache and the value of k, and update the cache location in the register group to the calculated cache location; where k=0,1,…,K-1, and the calculated cache location is different when the value of k is different.

[0212] exist Figure 11A In the example shown, each operator uses 4 caches during the loop. When updating the cache position on the operator side, taking the input cache of the SVA operator as an example, assume that the first column index of the input cache initially allocated to the SVA operator in the register set is 16, and the total number of columns in the cache is 16. The SVA operator's cache update unit monitors the number of times the start signal is received by the scheduling interface. The initial value of k is 0. In the first loop:

[0213] The SVA operator receives the start signal for the first time in the third time step, uses the initially allocated input buffer with the first column index of 16, adds 1 to the value of k to equal 1, and updates the first column index stored in the register group to the new position 16+16=32.

[0214] The SVA operator receives the start signal for the second time in the fourth time step, uses the input buffer with the first column index of 32, adds 1 to the value of k to equal 2, and updates the first column index stored in the register group to 16 + 16 × 2 = 48;

[0215] The SVA operator receives the start signal for the third time in the 5th time step, uses the input buffer with the first column index of 48, adds 1 to the value of k to equal 3, and updates the first column index stored in the register group to 16 + 16 × 3 = 64;

[0216] The SVA operator receives the start signal for the fourth time at the 6th time step, uses the input buffer with the first column index of 64, and sets the value of k to 0 because it exceeds the maximum value. The first column index stored in the register group is updated to 16 + 16 × 0 = 16.

[0217] The updates to the input buffer are the same in subsequent loops, and the updates to the output buffer are similar, so I will not repeat them here.

[0218] This embodiment updates the cache on the operator side. When the number of caches allocated to the operator is large, it is not necessary to update the cache through many instructions, which can simplify instruction design and speed up the operation.

[0219] Another embodiment of this disclosure provides a control device (when it is necessary to distinguish it from the control device of other embodiments, the control device of this embodiment is referred to as a second control device). The control device of this embodiment is used to control a plurality of specified operators, the plurality of operators being configured to process data to be processed according to a set connection order, the control device comprising:

[0220] An instruction decoding circuit is configured to decode software code, the software code including a plurality of first cache allocation instructions, each first cache allocation instruction including: a first operand, used to indicate the location and size of the cache allocated for the operator; and a second operand, used to indicate the storage space to be written to the first operand;

[0221] The instruction execution circuit, coupled to the instruction decoding circuit, is configured to, in response to a plurality of decoded first cache allocation instructions, write a first operand in each first cache allocation instruction into the storage space indicated by a second operand in the cache allocation instruction, so as to allocate caches for the plurality of operators to use when accessing data.

[0222] The caches allocated to the multiple operators are all from a shared cache pool.

[0223] The control device in this embodiment can be the logic control circuit in the aforementioned hardware scheduler. It can employ... Figure 16As shown in the structure, the instruction decoding circuit 10 reads the instructions in the software code and decodes them. The decoded instructions are then converted into corresponding operations by the instruction execution circuit 20, such as reading or writing registers, sending start signals, etc.

[0224] This embodiment decodes multiple first cache allocation instructions through an instruction decoding circuit and then executes them through an instruction execution circuit. It allocates caches to multiple operators from a shared cache pool, enabling data to be passed between operators through the cache. This achieves soft connections (configurable connections) and fast data interaction between operators. While ensuring processing efficiency, the connection relationship between operators can be changed according to application needs, improving the application flexibility of hardware accelerators using multiple operators.

[0225] In an exemplary embodiment of this disclosure, the first operand in the first cache allocation instruction is used to indicate the location and size of the cache initially allocated to the operator. The cache initially allocated to the operator is the cache used when the operator performs its first processing. The cache includes an input cache and / or an output cache.

[0226] The multiple operators are started sequentially according to a set connection order. For adjacent operators, the output buffer initially allocated to the preceding operator is the same as the input buffer initially allocated to the following operator. In this embodiment, the first buffer allocation instruction indicates the location and size of the buffer initially allocated to the operator. When the subsequent operator performs subsequent processing, the buffer can be reallocated using instructions, but this disclosure is not limited to this. In another embodiment, the initially allocated buffer can be used throughout the entire computation task. In this case, for adjacent operators, when the preceding operator writes the processed data to its output buffer, the following operator can pause processing. After the preceding operator completes writing the data, it notifies the hardware scheduler or the following operator, which then reads the data from the preceding operator's output buffer (i.e., the following operator's input buffer) for processing. Although parallel processing between operators is not possible, soft connections between operators can still be achieved, improving application flexibility. Furthermore, the buffer space occupied is small, making it suitable for situations with limited buffer space. This embodiment can schedule operators without using start and synchronization instructions.

[0227] In an exemplary embodiment of this disclosure, a single instruction in the software code is a short instruction of 16 bits, 32 bits, or 64 bits. The aforementioned first cache allocation instruction may include multiple short instructions to implement the cache allocation function.

[0228] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes multiple sets of scheduling instructions; the instruction execution circuit is further configured to schedule one or more operators in response to each set of decoded scheduling instructions, so that the scheduled operators start and complete one processing of a data block in a time step; wherein each time step starts when a set of scheduling instructions is executed and ends when the execution of the set of scheduling instructions ends.

[0229] This embodiment can be implemented using start and synchronization instructions, similar to the previous embodiments. However, other scheduling methods can also be used. For example, during the design phase, the processing time of multiple operators can be balanced. When generating the software code, a set time margin can be added to the maximum processing time of multiple operators each time, serving as the set time for each time step. Each time step begins when the start instruction is executed and ends after the set time (a delay instruction can be designed to implement this function). This control method is slightly less efficient, but it simplifies control and the corresponding hardware circuitry.

[0230] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes a loop start instruction and a loop end instruction. The loop start instruction includes an operand representing the number of loop iterations. The first cache allocation instruction is located before the loop start instruction, and the multiple sets of scheduling instructions are located between the loop start instruction and the loop end instruction.

[0231] The instruction execution circuit responds to the decoded software code by performing multiple loop processes, controlling the multiple operators to complete the processing of the data to be processed in a pipeline manner according to a set connection order; each loop process includes multiple time steps, and each operator completes one processing of a data block in the data to be processed in one time step.

[0232] The instructions for looping and scheduling in this embodiment can adopt the loop-related instructions shown in the pseudocode above. They can also be modified. For example, the loop start instruction (Lp_start_q0), loop end instruction (lp_end_q0), and start instruction (Start_eng_q0) remain unchanged, but the synchronization instruction (sync_q0) is updated to a delay instruction (delay_q0). The operand of the delay instruction can be set to the delay time, which can be configured to be the maximum processing time of multiple operators plus a set time margin.

[0233] In an exemplary embodiment of the present disclosure, M sets of scheduling instructions are included between the loop start instruction and the loop end instruction, each loop process includes M time steps, M=m1+m2-1, m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each loop, and m1≥2, m2≥2;

[0234] In the case of m<m1, the active operators at the m-th time step are the 1st to m-th operators, m=1,2,…,M;

[0235] In the case of m1≤m≤m2, the active operators at the m-th time step are all of the plurality of operators;

[0236] In the case of m2<m≤M, the active operators at the m-th time step are the (m-m2+1)-th to m1-th operators;

[0237] Herein, the operators to be started indicated by the start instruction in the m-th set of scheduling instructions are exactly the active operators at the m-th time step.

[0238] For this embodiment, reference may be made to the detailed description above.

[0239] In an exemplary embodiment of the present disclosure, the first cache allocation instruction includes one write register instruction and N' write data instructions associated with the write register instruction, and the write register instruction is associated with a total of N write data instructions, where:

[0240] The write register instruction includes: an opcode, the second operand indicating the register address Add, and an operand indicating the number of immediate numbers N, where N≥N'≥2;

[0241] The write data instruction includes an opcode and an immediate number, the first operand includes N' immediate numbers in the N' write data instructions, and the N' immediate numbers in the N' write data instructions include information of the row position, the number of rows, the column position and the number of columns of the cache allocated for the operator;

[0242] The instruction execution circuit writes the first operand in each first cache allocation instruction into the storage space indicated by the second operand in the cache allocation instruction, which includes: for each of the N' write data instructions, writing the immediate number therein into the register with the address Add+n-1 for the operator to read, where n is the serial number of the instruction in the N write data instructions, indicating that the instruction is the n-th instruction under the write register instruction, and 1≤n≤N.

[0243] This embodiment may also adopt an example of the first cache allocation instruction represented by pseudo code above:

[0244]

[0245] For detailed explanation, please refer to the aforementioned embodiments, where Wr_que0[0xb00],29 is a write register instruction, and the other instructions are write data instructions. It should be noted that an operator usually needs to configure other parameters besides the cache, and the configuration of these other parameters can also be accomplished through write data instructions. Therefore, the write data instructions for implementing cache allocation mentioned above do not necessarily follow the write register instruction immediately; they can also be separated from the write register instruction by one or more other write data instructions.

[0246] In one example of this embodiment, the N' immediate values ​​in the N' write data instructions also include the number K of cache groups used by the operator in multiple loops, to instruct the operator to update the row or column position of the allocated cache step by step with a period of K time steps, so that the operator uses different caches in the K time steps of the same period and the same cache in the k-th time step of different periods, k = 0, 1, ..., K-1, K ≥ 2.

[0247] An example of this embodiment is as follows:

[0248] Wdat 3 / / CFG_SVA_BBUF_PPG_NUM

[0249] The instruction has been explained in detail above using the SVA operator as an example, so it will not be repeated here.

[0250] In an exemplary embodiment of this disclosure, the software code decoded by the instruction decoding circuit further includes a second cache allocation instruction located between two adjacent sets of scheduling instructions. The second cache allocation instruction includes: a first operand for indicating the location of the cache to be reallocated for the operator in the next time step; and a second operand for indicating the storage space to be written to by the first operand.

[0251] The instruction execution circuit is further configured to, in response to each decoded second cache allocation instruction, write the first operand therein to the storage space indicated by the second operand therein, so as to allocate a cache for the operator using the storage space to use in the next time step; wherein the caches allocated for the plurality of operators to use in the same time step are located in different and independently accessible regions in the shared cache pool, and for adjacent operators among the plurality of operators, the output cache allocated for the preceding operator to use in the current time step is the input cache allocated for the following operator to use in the next time step.

[0252] This embodiment uses a second buffer allocation instruction between two sets of scheduling instructions to reallocate buffers for operators. This allows operators to switch between multiple buffers, staggering the output buffer used by the operator at the same time step with the input buffer used by the operator at the next time step. This enables two operators to process data in parallel (including reading and writing data), thus working in a pipelined manner to improve efficiency. The two sets of scheduling instructions in this embodiment can be located in different loop processes.

[0253] In one example of this embodiment, among the multiple sets of scheduling instructions, the second cache allocation instruction between two adjacent sets of scheduling instructions is used to reallocate the cache position for each operator that performed processing in the previous time step and still needs to perform processing in the next time step; for each of the multiple operators, starting from the time step when the operator is first started, with a period of K time steps, the cache allocated by the instruction execution circuit for the operator in the K time steps of the same period is different, and the cache allocated for the operator in the k-th time step of different periods is the same, k = 0, 1, ..., K-1, K ≥ 2.

[0254] In an exemplary embodiment of this disclosure, the second cache allocation instruction includes a write register instruction and M write data instructions associated with the write register instruction, where M ≥ 1, wherein:

[0255] The write register instruction includes: an opcode, a second operand representing the register address Add', and an operand representing the number of immediate values ​​M;

[0256] The write data instruction includes an opcode and an immediate value. The first operand includes M immediate values ​​from the M write data instructions. The M immediate values ​​from the M write data instructions include information about the row or column position of the cache reallocated for the operator.

[0257] The instruction execution circuit responds to each second cache allocation instruction by writing the first operand therein into the storage space indicated by the second operand, including: for each of the M write data instructions, writing the immediate value therein into a register at address Add'+m-1 for the operator to read, where m is the sequence number of the instruction in the M write data instructions, indicating that the instruction is the m-th instruction under the write register instruction, 1≤m≤M.

[0258] An example of a second cache allocation instruction (M=1) is as follows:

[0259] Wr_que0 [0xb00],0

[0260] Wdat 32 / / CFG_SVA_INP_BBUF_COL_OFFSET

[0261] The example has been explained in detail above, so it will not be repeated here.

[0262] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system from processing received radar signals; the plurality of operators are operators performing 1D-FFT stage processing, and one data block in the data to be processed is data of a chirp signal received on a channel; or, the plurality of operators are operators performing 2D-FFT stage processing, and one data block in the data to be processed is data at the same range gate in the 1D-FFT data. Similar to the foregoing embodiments, when the control device of this disclosure is applied to a radar system, it can use a frame of data as the dataset to be processed in a set of multiple loops.

[0263] This disclosure also provides an embodiment of a multi-operator control method applied to a hardware accelerator, the hardware accelerator including a hardware scheduler, a specified number of operators, and a shared cache pool, such as... Figure 19 As shown, the control method includes:

[0264] Step 200: Allocate caches from the shared cache pool for the multiple operators to use when accessing data, so as to form a data channel between the multiple operators. The allocated caches include input caches and / or output caches.

[0265] Step 201: By scheduling time steps, the multiple operators are started sequentially according to the set connection order to complete the processing of the data to be processed.

[0266] Among the plurality of operators, the output buffer used by the preceding operator at the current time step is the input buffer used by the following operator at the next time step.

[0267] This embodiment allocates caches to multiple operators from a shared cache pool, enabling data transfer between operators via the cache. This achieves soft connections and rapid data interaction between operators, and through time-step scheduling, the multiple operators can be started sequentially according to a set connection order to process the data to be processed. While ensuring processing efficiency, the connection relationship between operators can be changed according to application needs, improving the application flexibility of hardware accelerators using multiple operators. The term "adjacent operator" in this paper refers to two operators whose output data is the input data of another operator, from the perspective of data interaction.

[0268] In an exemplary embodiment of the present disclosure, the allocating, from the shared cache pool, caches respectively used by the plurality of operators for accessing data includes: allocating, from the shared cache pool, caches respectively used by the plurality of operators for performing the first processing; wherein for adjacent operators among the plurality of operators, the output cache allocated for the preceding operator to use in the first processing is exactly the input cache allocated for the subsequent operator to use in the first processing (since they are started sequentially, reading and writing operations thereon will not be performed at the same time step). In another embodiment, the initially allocated cache can be used by the operator throughout the execution of the entire computing task. As described above, details will not be repeated here.

[0269] In an exemplary embodiment of the present disclosure, the enabling, by step-by-step scheduling, the plurality of operators to start sequentially according to a set connection sequence to complete processing of to-be-processed data includes: performing multiple cycle control to control the plurality of operators to complete processing of a plurality of data blocks in the to-be-processed data in a pipeline manner according to the set connection sequence; each cycle process includes a plurality of time steps, and each operator completes one processing of one data block in the to-be-processed data in one time step. The caches allocated for the plurality of operators to use at the same time step are located in different and independently accessible areas in the shared cache pool; and for adjacent operators among the plurality of operators, the output cache allocated for the preceding operator to use at the current time step is exactly the input cache allocated for the subsequent operator to use at the next time step. Through multiple cycle control in combination with cache allocation, this embodiment can avoid access conflicts among the plurality of operators.

[0270] In an exemplary embodiment of the present disclosure, each cycle process includes M time steps, where M = m1 + m2 - 1, m1 is the number of the plurality of operators, m2 is the number of data blocks processed in each cycle, m1 ≥ 2, and m2 ≥ 2;

[0271] In each cycle process:

[0272] When m < m1, the activated operators at the m-th time step are the 1st to the m-th operators, where m = 1, 2, ..., M;

[0273] When m1 ≤ m ≤ m2, the activated operators at the m-th time step are all of the plurality of operators;

[0274] When m2 < m ≤ M, the activated operators at the m-th time step are the (m - m2 + 1)-th to the m1-th operators.

[0275] For this embodiment, reference may be made to the related embodiments above.

[0276] In an exemplary embodiment of this disclosure, the method further includes: allocating a number K of buffer groups for each of the plurality of operators to be used in the multiple loops, to instruct the operators to update the position of the allocated buffers step by step over a period of K time steps, so that the operators use different buffers in the K time steps of the same period, and use the same buffer in the k-th time step of different periods, where k = 0, 1, ..., K-1, K ≥ 2. This embodiment configures the number K of buffer groups for the operators, enabling switching between K pairs of buffers (or K buffers) on the operator side to avoid conflicts. In one example, the number K can be the number of receiving channels of the radar system.

[0277] In an exemplary embodiment of this disclosure, the allocation of caches from the shared cache pool for the plurality of operators to access data includes: reallocating caches for operators that process data in both the previous and next time steps between two adjacent time steps; wherein, for each of the plurality of operators, there are K groups of caches allocated and reallocated for that operator during the multiple loops, where K ≥ 2, and each group includes an input cache and / or an output cache; starting from the first processing of the operator, with a period of K time steps, the operator uses the same cache in the k-th time step of different periods, and uses different caches in different time steps of the same period, k = 0, 1, ..., K-1. This embodiment reallocates caches through instructions, eliminating the need for operators to design circuits to update cache information, thus simplifying hardware design.

[0278] In an exemplary embodiment of this disclosure, the data to be processed is a frame of data obtained by the radar system from processing the received radar signal; the plurality of operators are operators that perform 1D-FFT stage processing, and one data block in the data to be processed is the data of a chirp signal received on a channel; or, the plurality of operators are operators that perform 2D-FFT stage processing, and one data block in the data to be processed is the data at the same range gate in the 1D-FFT data.

[0279] One embodiment of this disclosure provides a hardware scheduler, including a control device and an internal memory. The control device includes any of the control devices described in any embodiment of this disclosure (such as a first control device or a second control device). The internal memory is configured to store software code to be decoded and executed by the control device. See also... Figure 17 .

[0280] This disclosure also provides a hardware accelerator, including a hardware scheduler, a specified plurality of operators, a shared cache pool providing cache space for the operators, and a register set, wherein:

[0281] The hardware scheduler adopts the second hardware scheduler described in any embodiment of this disclosure, wherein the cache information allocated to each operator is saved in the register group, and the processed data is stored in external memory;

[0282] The register group is configured to store configuration information for the plurality of operators, the configuration information including information on the cache allocated to the operators;

[0283] The plurality of operators are configured to, upon startup, obtain information about the cache allocated to the operator from the register group; if an input cache is allocated, read the data block to be processed from the input cache and process it; if an output cache is allocated, write the processed data into the output cache.

[0284] The structure of the hardware accelerator in this embodiment can be found in [reference]. Figure 7 .

[0285] In an exemplary embodiment of this disclosure, the operator includes:

[0286] The data reading unit is configured to acquire information about the input buffer allocated to the operator, and based on the information about the input buffer, sequentially read out the data blocks in the input buffer and input them into the processing unit;

[0287] The processing unit is configured to process the data block to obtain a processed data block;

[0288] The write data unit is configured to obtain information about the output buffer allocated to the operator, and write the processed data block into the output buffer based on the information about the output buffer.

[0289] The scheduling interface is configured to receive a start signal and use it as a trigger signal to begin processing this operator.

[0290] The synchronization interface is configured to send a signal indicating that the processing is complete after the write data unit writes the processed data block into the output buffer.

[0291] The structure of the operator in this embodiment can be found in [reference needed]. Figure 18 .

[0292] In one example of this embodiment: the read data unit obtains information about the input buffer allocated to the operator from the register group, and the write data unit obtains information about the output buffer allocated to the operator from the register group;

[0293] The operator also includes a cache update unit;

[0294] The cache update unit is configured to: read from the register group the location and size of the cache initially allocated to the operator, and the number of cache groups K allocated to the operator, where K ≥ 2; and cyclically count the number of times the scheduling interface receives the start signal, starting a new cycle after the accumulated count reaches K times in each cycle, and when the accumulated count in each cycle is k times, calculate the location of the cache used by the operator in the next time step based on the location and size of the initially allocated cache and the value of k, and update the cache location in the register group to the calculated cache location; where k = 0, 1, ..., K-1, and the calculated cache location is different when the value of k is different.

[0295] In an exemplary embodiment of this disclosure, the plurality of operators sequentially include: a CQMD operator, an FFT operator, and an SVA operator; or the plurality of operators sequentially include: a DC operator, an FFT operator, and an SVA operator; or the plurality of operators sequentially include: a CMB operator, a STAS operator, a HIST operator, a CFAR operator, and a STAS operator; or the plurality of operators sequentially include: a DC operator, an FFT operator, an SVA operator, and a CMB operator.

[0296] One embodiment of this disclosure also provides a computing system, including a processor, memory, and a hardware accelerator, wherein:

[0297] The processor is configured to load the data to be processed stored in the memory into the hardware accelerator;

[0298] The memory is configured to store data to be processed, and to store data obtained by the hardware accelerator after processing the data to be processed.

[0299] The hardware accelerator employs the hardware accelerator described in any of the disclosed embodiments.

[0300] In an exemplary embodiment of this disclosure, the computing system is a system-on-a-chip, which may be a millimeter-wave chip or a sensor chip in a radar system.

[0301] One embodiment of this disclosure also provides an automated method for generating operating instructions based on a Radar digital signal processing hardware accelerator.

[0302] The following explains the format of the exemplary start command (start_engine command) and synchronization command (sync command):

[0303] The `start_engine` directive is used to start one or more operators, and its exemplary format is shown in the table below:

[0304] Bit 31～28 27 26～20 19～0 Field start_engine que_num reserved engine_bit

[0305] Bits [31:28] represent the op_code of the instruction; the hardware scheduler has two instruction queues, and bit

[27] is used to distinguish whether the instruction is executed in the different instruction queues; bits [26:20] are not currently used, but can be used to expand the number of operators if the number of operators increases; bits [19:0] are a total of 20 bits, corresponding to a maximum of 20 operators, such as FFT, CFA, etc. The pseudocode example corresponding to this instruction is as follows:

[0306] start_eng_qn fft

[0307] start_eng_qn fft+cfar.

[0308] The `start_engine` instruction can start a single operator, as in the first pseudocode, or multiple operators simultaneously, as in the second pseudocode. After the pseudocode is written, a script will convert it into binary code instructions that the hardware scheduler can parse. When the hardware scheduler executes this instruction, it sends a start signal to the corresponding operator based on bits [19:0]. This start signal is high for only one clock cycle. When the operator receives the start signal, it will begin working according to the configured register information. This register information includes the range of values ​​the operator can access, such as col offset, colsize, row offset, row_size, etc. These registers can be configured before the `start_engine` instruction using the `reg_write` instruction, as shown in the following figure:

[0309] The `sync` instruction is used by the instruction scheduler to check whether the corresponding operator has completed its task. If it has, the hardware scheduler continues executing subsequent instructions; otherwise, it waits for the corresponding operator to complete its task. An example format is as follows:

[0310] Bit 31～28 27 26～20 19～0 Field sync que_num reserved engine_bit

[0311] In the table above, bits [31:28] represent the op_code of the sync instruction, bit

[27] is used to distinguish whether the instruction is executed in different instruction queues, bits [26:20] are temporarily reserved like the start_eng instruction and can be used for subsequent expansion, and bits [19:0] correspond to a maximum of 20 operators like the start_eng instruction. The pseudocode example for this instruction is as follows:

[0312] sync_qn fft

[0313] sync_qn fft+cfar

[0314] The `sync` instruction can check whether a single operator has completed its work, as shown in the first pseudocode, or it can check whether multiple operators have completed their work, as shown in the second pseudocode. When an operator completes its work, it sends a `clockcycle high-level done` signal to the hardware scheduler. After receiving the `done` signal, `seq` considers that the operator has entered the idle state. When all operators corresponding to bits [19:0] have entered the idle state, the `sync` instruction ends, and the hardware scheduler continues to execute subsequent instructions.

[0315] In an exemplary embodiment of this disclosure, the hardware accelerator further includes general-purpose registers and dedicated registers for each operator, and the software code further includes one or more of the following instructions:

[0316] The register read instruction (reg_read instruction) reads the value of the special register corresponding to the specified address when executed;

[0317] The Reg_load instruction writes data to a general-purpose register when executed.

[0318] The arithmetic instructions (rf op instructions) perform operations between data in general-purpose registers when executed, including addition, subtraction, AND, OR, NOT, shift, etc.

[0319] The register store instruction (reg_store instruction) is used to write the value of a general-purpose register to the special-purpose register corresponding to a specified address.

[0320] In this embodiment, one or more dedicated registers corresponding to each operator are called the register group corresponding to that operator.

[0321] The aforementioned instructions enable data exchange between operators, excluding the data to be processed. For example, statistical data obtained by one operator during processing can be written to a designated dedicated register. The hardware scheduler retrieves this statistical data from the dedicated register using a register read instruction; it can then perform calculations on it and write it to a general-purpose register using a write instruction; arithmetic instructions can perform operations on data in multiple general-purpose registers, and the results can be written to another operator's dedicated register using a register save instruction. This establishes a channel for information transfer between operators. These instructions in the software code can be generated according to specific application requirements.

[0322] In addition to these instructions, software code may also include the following instructions, such as: wait instructions, used to stop the execution of instructions until the processor configures the corresponding event bit, which can be used for debugging; delay instructions, used to delay for a preset time period; break instructions, used to jump out of the current loop or branch; and clear instructions (pc_clear instructions), used to clear the value of the program counter.

[0323] In one example, the Reg_load directive has the following exemplary format:

[0324] Bit 31～28 27 26-25 24 23～20 19～0 Field reg_load que_num load_mode hi_lo_sel rf_idx addr / im_dat[15:0] / rf_idx[3:0]

[0325] The table above shows the bit allocation corresponding to the reg_load instruction. Bits [31:28] represent the instruction ID; bit

[27] is used to distinguish the instruction from the different instruction queues for execution; bits [26:25] are used to select the source of the general-purpose register value. 0 indicates that the value corresponding to address bit [19:0] is written to the general-purpose register; 1 indicates that the immediate value is written to the general-purpose register; 2 indicates that the address exists in another general-purpose register, and the data at the corresponding address is read according to the value of the other general-purpose register, and then the read data is written to the current general-purpose register; bit

[24] is used to select whether the immediate value is written to the high or low 16 bits of the general-purpose register; bits [23:20] represent the index of the current general-purpose register; bits [19:0] represent the address, the immediate value, or the index of another general-purpose register.

[0326] The cache allocation instruction in the aforementioned embodiment is implemented through the register write instruction (reg_write instruction), which writes a value to the register corresponding to a certain address; the reg_load instruction here writes a value or the value of the register corresponding to a certain address to a general-purpose register.

[0327] The `reg_read` instruction reads the value of the register corresponding to the specified address. The results of operator processing can be of several types: one is data obtained from calculations on the input data, which can be stored in the output buffer; another is statistical results of the input data, which are smaller in size, such as the count of valid targets. This statistical result can be stored in a result register, typically 32 bits, and the application can obtain these statistical results by reading the register.

[0328] The `reg_store` instruction writes the value of a general-purpose register to the register corresponding to a specified address. General-purpose registers can be used to cache intermediate results or perform simple mathematical operations, and the resulting value can be assigned to the register at a specific address. The `reg_store` instruction can be used to achieve this.

[0329] The operand event_idx in the wait instruction can be configured from 0 to 7. When the wait instruction is executed, seq will stop and will not continue to execute subsequent instructions. Only when the CPU configuration ctl_seq_event_set and event_idx are consistent will seq continue to execute subsequent instructions.

[0330] An example of the delay instruction is delay 0x3, which means that the execution of the next instruction will continue after a delay of 3 cycles.

[0331] The pc_clear instruction is used when the program counter (PC) value needs to be incremented from 0.

[0332] The rf_op instruction can perform simple calculations on intermediate results during instruction execution and then allocate them to a register.

[0333] The software code (short instruction set) generated in the above embodiments can be considered as firmware stored in the chip. Configuration data has been written into the radar signal processing registers, and the configuration data required for each engine's operation has been configured in the engine's internal registers. This means that the hardware acceleration chip implementing the customized functions has been customized and can begin operation. During chip startup, the CPU and hardware scheduler (SEQ) on the chip start independently. The software code is written into the internal memory (instruction queue 0 or 1) of the hardware scheduler. The controllers in the hardware scheduler retrieve the software code (such as 32-bit short instructions) from their respective queues, decode it, determine its instruction function, and then execute the corresponding instruction function.

[0334] As mentioned above, to effectively resolve the contradiction between application flexibility and high performance / low power consumption in hardware accelerators, this disclosure proposes a novel hardware-software interaction scheme based on software code implementation. Users can develop different software codes for different applications according to their needs, customizing the connection relationships and data flows between multiple operators in the hardware accelerator. During actual operation, both the software code and the data flow can be processed by hardware circuits. This solves the problem of limited development flexibility while also possessing high performance. The hardware accelerator that runs this software code to perform corresponding processing and the software code it executes have been described in detail above. However, during development, an effective method for debugging the software code is also needed.

[0335] Taking a hardware accelerator used in a radar system as an example, before writing software code, it is necessary to first design the hardware accelerator that runs the software code and determine the operators to be designed in the hardware accelerator. To this end, the hardware required for radar signal processing can be broken down into multiple subdivided operators. Each operator, as an independent radar signal processing unit, can implement a basic computational function and can be controlled and scheduled by a hardware scheduler. For example, the hardware scheduler can perform operations such as register configuration, register reading, startup, and synchronization related to the operators through instructions in the software code. When designing operators, the smallest computational units can be identified based on the computational characteristics required by the radar application, such as FFT, complex multiplication, complex addition, complex subtraction, and real number comparators, as candidates for operators in the hardware accelerator to meet possible combination requirements.

[0336] The foregoing embodiments of this disclosure have proposed solutions for operator cache allocation and scheduling, including corresponding control devices, hardware schedulers, hardware accelerators, computing systems, and multi-operator control methods. After developing corresponding software code for different applications, the debugging methods of the software code in the embodiments of this disclosure can be used to debug the software code. With the expansion and increasing complexity of radar signal processor functions, a complete signal acceleration processing flow requires more and more operators to cooperate. The reasons for abnormal software code operation are also diverse, such as an engine malfunction or an instruction execution error. Some debugging methods for similar software code can pinpoint errors to specific parts of operators, such as DMA address overflow or FIFO overflow, which are relatively fixed, singular, and lack versatility. In particular, the foregoing embodiments of this disclosure employ new cache allocation and scheduling methods. The cache allocation and operator scheduling implemented by the software code may also be abnormal, making it difficult to locate the problem based solely on register data read during debugging.

[0337] Therefore, one embodiment of this disclosure provides a software code debugging method applied to a radar system including a processor and a hardware accelerator, wherein the hardware accelerator includes a hardware scheduler and multiple operators, such as... Figure 20 As shown, the debugging method includes:

[0338] Step 400: The processor loads the software code to be debugged into the cache of the hardware scheduler; the software code includes multiple instructions executed by the hardware scheduler for controlling the multiple operators to perform radar signal processing;

[0339] Step 401: In response to the run command issued by the debugging device, the hardware scheduler starts execution from the current instruction. When the instruction timeout function is enabled, the scheduler determines the execution time of each instruction and reports an error to the debugging device when the execution time exceeds a preset time threshold.

[0340] In this embodiment, the software code is used for radar digital signal processing. The instructions in the software code are dedicated micro-instructions for radar digital signal processing, with an instruction length of 16 bits, 32 bits, or 64 bits. The plurality of operators sequentially include: CQMD operator, FFT operator, SVA operator; or sequentially include DC operator, FFT operator, SVA operator; or sequentially include CMB operator, STAS operator, HIST operator, CFAR operator, STAS operator; or sequentially include DC operator, FFT operator, SVA operator, and CMB operator.

[0341] In this embodiment, the processor can load the software code to be debugged into the hardware scheduler's cache using any of the following methods, see [link to relevant documentation]. Figure 17 The first method is to write the code to the hardware scheduler's cache (such as the internal memory shown in the diagram) via a bus, such as the Advanced Peripheral Bus (APB). The second method is to first store the code in memory outside the hardware accelerator and then move it from memory to the hardware scheduler's cache using DMA. The third method is for the hardware scheduler to actively read the software code from a set address into its local cache.

[0342] Some debugging schemes only monitor and report timeouts for functions or code blocks, and deciding which functions and code blocks to monitor and report relies on experience. This may lead to the omission of some timeout-exceeding instructions, resulting in performance bottlenecks in the debugged software code. In this embodiment, after the processor loads the software code to be debugged into the hardware scheduler's cache, in response to the run command issued by the debugging device, the hardware scheduler can start execution from the current instruction. With the instruction timeout function enabled, the scheduler determines the execution time of each instruction and reports an error to the debugging device when the execution time exceeds a preset time threshold. This embodiment can monitor timeouts for every instruction in the software code, helping developers to more quickly and accurately locate performance bottlenecks, optimize execution efficiency, and improve development efficiency. Furthermore, this embodiment allows the instruction timeout function to be enabled or disabled. Timeout monitoring is only performed on each instruction when the instruction timeout function is enabled. This function can be disabled (i.e., turned off) at any time during debugging to avoid the additional overhead of timeout monitoring.

[0343] In an exemplary embodiment of this disclosure, the radar system is a radar chip, which is connected to the debugging device via a debugging interface; wherein the processor is configured to read and write the register specified by the command in response to an access register command issued by the debugging device, and is configured to send a run command issued by the debugging device to the hardware scheduler, which then responds to the run command.

[0344] An example of the debugging system consisting of the debugging device and the radar system in this embodiment is as follows: Figure 21 As shown, the radar system in this example is a radar chip, but is not limited to this. As illustrated, the processor (such as a CPU) in the radar chip of this embodiment can communicate directly with the hardware scheduler in the hardware accelerator. The processor can also directly access various registers in the hardware accelerator (such as the instruction timeout enable register, PC value register, operator status register, etc., as described below) and the register groups corresponding to the operators. Other parts of this figure can be connected to... Figure 7 The same applies, so I won't repeat it here. In this embodiment, the debugging device can be a debugger, connected to the chip via an interface such as USB or JTAG / SWD. The debugging device can also be a development board integrating the target chip and debugging interfaces, allowing developers to directly load and debug code on the development board. Alternatively, the debugging device can be an emulator simulating the chip's operating environment, allowing developers to debug when the actual hardware is unavailable.

[0345] Based on the above architecture, the debugging device can send debugging commands to the radar chip via an interface, which can then be received by the processor. If the debugging command relates to register read / write operations, the processor can execute it directly, reading and writing the corresponding registers. Figure 21 As shown, the processor can directly access the register group corresponding to the operator and some registers with different functions. The processor in this embodiment can access various registers in the hardware accelerator. If it is to execute a debugging command (such as a single-step execution command or a multi-step execution command) in the software code, the processor can send the debugging command to the hardware scheduler, and the hardware scheduler can execute the corresponding debugging action according to the debugging command, such as executing the instruction.

[0346] In an exemplary embodiment of this disclosure, the hardware accelerator further includes an instruction timeout enable register and an instruction timeout timer; the debugging method further includes: in response to an instruction timeout enable command issued by the debugging device, the processor sets the value of the instruction timeout enable register to a value indicating instruction timeout enable; the hardware scheduler, when the value of the instruction timeout enable register indicates instruction timeout enable, starts the instruction timeout timer to count when each instruction begins execution, stops counting when the instruction is completed, and determines the execution time of the instruction based on the count value when the instruction timeout timer stops counting.

[0347] In this embodiment, the debugging device can issue debugging commands to assign values ​​to registers, thereby enabling or disabling the instruction timeout function. During debugging, developers can change the enabled state of the instruction timeout function at any time as needed. This ensures accurate instruction timeout occurrence while avoiding unnecessary burden on the hardware scheduler caused by timeout monitoring for every instruction. In other embodiments, the instruction timeout function can be controlled together with other functions, such as setting multiple debugging modes, and enabling or disabling the instruction timeout function when entering certain debugging modes.

[0348] In an exemplary embodiment of this disclosure, the software code includes a wait instruction as a breakpoint;

[0349] When the response execution command is a multi-step execution command and carries information about a specified breakpoint, the hardware scheduler executes the instructions sequentially from the current instruction. If an error occurs before reaching the specified breakpoint, the instruction execution stops and an error is reported; if no error occurs when reaching the specified breakpoint, the instruction execution stops after reaching the specified breakpoint.

[0350] When the response execution command is a single-step execution command, the hardware scheduler starts execution from the current instruction. If the current instruction is executed successfully, the execution of the instruction is stopped and the next instruction is taken as the new current instruction. If the current instruction is executed incorrectly, the execution of the instruction is stopped, the next instruction is taken as the new current instruction, and an error is reported.

[0351] The single-step execution command in this embodiment can also be called a single-step debugging command. Using the single-step execution command is beneficial for flexibly controlling the execution of instructions and accurately locating the erroneous instruction. The multi-step execution command in this embodiment can also be called a multi-step debugging command or a breakpoint debugging command. It can roughly locate the instruction range where the problem is located. During debugging, the multi-step execution command can be used first to locate the instruction range where the problem is located, and then the single-step execution command can be used to locate the instruction where the problem is located, thereby improving debugging efficiency. Both single-step execution commands and multi-step execution commands can be generated and issued by the developer by selecting the icon on the debugging interface provided by the debugging device. In this embodiment, an interrupt reporting method can be used when an error is reported. By reporting errors through interrupts, the legality of the instruction can be ensured. The error reason can be displayed in code or text during the report. In addition to interrupt reporting, the error information can also be written to the corresponding register and then the debugging device can be notified to read it.

[0352] In one example of this embodiment, different wait instructions in the software code contain different index values; the multi-step execution command carries a target index value, and the hardware scheduler identifies the wait instruction containing the target index value as the specified breakpoint. In this embodiment, breakpoints can be specified during breakpoint-based debugging. For example, if three breakpoints with index values ​​of 0, 1, and 2 are set in the software code, and the current instruction is before these three breakpoints, the developer can issue a multi-step execution command carrying the breakpoint index value 2. When the hardware scheduler executes this multi-step execution command, it will continue execution until the breakpoint with index value 2, provided there are no errors. This makes debugging more flexible for developers when there are many breakpoints, improving debugging efficiency.

[0353] In one example of this embodiment, single-step execution of instructions can be controlled via two registers: a single-step enable register and a single-step set register. When the value of the single-step enable register indicates that single-step execution is enabled, each time the value of the single-step set register is configured to indicate that one instruction can be executed (e.g., "1"), the hardware scheduler executes one instruction. After each instruction is executed, instruction execution stops, and the value of the single-step set register is set to its initial value (e.g., "0") (indicating that instruction execution is paused). Afterward, configuring the value of the single-step set register to 1 again allows for the execution of another instruction, and so on. When instruction execution is stopped, developers can check whether the instruction execution meets expectations and read the register data to pinpoint problems. For developers, simply selecting the single-step or multi-step execution icon allows the debugging device to issue single-step or multi-step execution instructions.

[0354] In an exemplary embodiment of this disclosure, the hardware accelerator further includes a PC value register; the debugging method further includes: in response to an instruction jump command issued by the debugging device, the processor updates the PC value in the PC value register to a target PC value carried in the instruction jump command, so that the current instruction to be executed by the hardware scheduler jumps to the target instruction pointed to by the target PC value.

[0355] Based on this embodiment, when a developer needs to perform an instruction jump, they can specify the target instruction to jump to based on the debugging interface (which displays the software code being debugged and its execution progress). For example, the developer can move the cursor to the target instruction and then click the instruction jump icon on the interface. The debugging device can determine the PC value (the PC value of each instruction in the software code changes sequentially with the instruction order) corresponding to the instruction to jump to based on the position of the target instruction where the cursor is located in the software code. Then, it generates an instruction jump command carrying the target PC value. After receiving the instruction jump command, the processor updates the PC value in the PC value register to the target PC value, thus realizing the instruction jump.

[0356] In an exemplary embodiment of this disclosure, the hardware accelerator further includes a shared cache pool and a register set;

[0357] The software code includes multiple cache allocation instructions. When the multiple cache allocation instructions are executed, caches used for accessing data are allocated from the shared cache pool for the multiple operators respectively, and the cache information allocated for the multiple operators is written into the register group to form a data channel through the multiple operators for the data flow.

[0358] The debugging method further includes: after the hardware scheduler executes the cache allocation instruction and stops the execution of the instruction, in response to the cache information read command issued by the debugging device, the processor reads the cache information allocated to the plurality of operators for two consecutive time steps from the register group, and reports the read information to the debugging device.

[0359] The cache information reading command in this embodiment is not necessarily dedicated to retrieving cache information; it can read both cache information and other information. During instruction execution, the hardware scheduler outputs status register information, including the currently executing instruction, the currently operating engine, general-purpose register values, loop counts, and state machine information. The processor can read this information based on commands from the debugging device to diagnose and resolve problems. For ease of operation, the information to be read can be grouped, and one or more groups can be read at a time. Developers can select the information to query based on the debugging interface, and the debugging device automatically generates the corresponding command and sends it to the processor in the radar system.

[0360] This embodiment reads the allocated cache information based on the cache allocation method first proposed in the embodiments of this disclosure. In order to form the data stream through the data channels of the multiple operators, the cache allocated to the multiple operators participating in radar signal processing needs to meet certain conditions. If the cache allocated by the cache allocation instruction does not meet these conditions, the path of the data stream will be abnormal. These abnormalities are unique problems of the embodiments of this disclosure. After reading the cache information allocated to the multiple operators to the debugging device, the developer can check this information to determine whether there are any errors.

[0361] In an exemplary embodiment of this disclosure, the software code further includes multiple sets of scheduling instructions. When the multiple sets of scheduling instructions are executed, the multiple operators are scheduled step by step, so that the multiple operators are started sequentially according to the order in which the data stream passes through the operators, and the processing of the data to be processed is completed in a pipeline manner; wherein, each time step starts when a set of scheduling instructions is executed and ends when the execution of that set of scheduling instructions ends.

[0362] The software code also includes a loop start instruction preceding the multiple sets of scheduling instructions and a loop end instruction following the multiple sets of scheduling instructions, enabling the multiple operators to complete radar signal processing through multiple loops;

[0363] The multiple cache allocation instructions are all located before the loop start instruction; or, some of the multiple cache allocation instructions are located before the loop start instruction and some are located between the loop start instruction and the loop end instruction.

[0364] The loop start instruction, loop end instruction, and the scheduling and cache allocation instructions in between in the software code have been described in detail above and will not be repeated here. As mentioned above, cache information can include information about the buffered cache and / or the output cache, such as the size and location of the cache. Before the loop starts, a first cache allocation instruction can be set to allocate the initial cache for the operator. Then, during the loop, a second cache allocation instruction can be used to reallocate the cache for the operator. Developers can read the cache information after executing the first cache allocation instruction or after executing the second cache allocation instruction.

[0365] In one example, the plurality of operators are operators that perform 1D-FFT stage processing, with each operator processing the data of a chirp signal on a channel in one time step; in another example, the plurality of operators are operators that perform 2D-FFT stage processing, with each operator processing the data at the same range gate in the 1D-FFT data in one time step; in other examples, the plurality of operators can also perform other radar digital signal processing functions.

[0366] In one example of this embodiment, after the processor reports the read information to the debugging device, the debugging method further includes: the debugging device determining whether the cache currently allocated to the plurality of operators meets the following conditions: among adjacent operators, the output cache used by the preceding operator in the previous time step is the input cache used by the following operator in the next time step, and the caches used by the plurality of operators in the same time step are located in different independently accessible regions of the shared cache pool; and if the conditions are not met, the debugging device reports an error to the user, indicating that the error type is a cache allocation error; wherein, the preceding time step and the following time step are the two consecutive time steps.

[0367] After reading the information about the caches allocated to multiple operators, the debugging device in this embodiment can automatically determine whether the caches allocated to multiple operators meet certain conditions. The first condition is that, among adjacent operators, the output cache used by the preceding operator in the previous time step (equivalent to the current time step mentioned above) is the input cache used by the following operator in the next time step. This condition is required for normal data flow between adjacent operators. If this condition is not met, the following operator will not be able to correctly read the data output by the preceding operator, resulting in processing abnormalities. If this condition is left to the developer to determine manually, it requires sufficient experience and takes a lot of time. The debugging device in this embodiment can automatically determine whether the allocated caches meet this condition, which can improve debugging efficiency.

[0368] For ease of identification, the registers corresponding to the operators and used to store buffer information can be numbered sequentially and the input buffer and output buffer can be distinguished. See [link to relevant documentation] Figure 15For operators that require cache allocation, the register used to store the output cache information of the first operator (DFE operator) is named 1outCache_reg, the registers used to store the input cache information and output cache information of the second operator (CQMD operator) are named 2inCache_reg and 2outCache_reg respectively, the registers used to store the input cache information and output cache information of the third operator (FFT operator) are named 3inCache_reg and 3outCache_reg respectively, and so on. Therefore, to determine whether the first condition is met, it is only necessary to compare the output buffer information read from the register corresponding to the preceding operator in the previous time step with the input buffer information read from the register corresponding to the following operator in the next time step (for example, comparing the value read from 1outCache_reg in the previous time step with the value read from 2inCache_reg in the next time step, the value read from 2outCache_reg in the previous time step with the value read from 3inCache_reg in the next time step, and so on). If the comparison result is the same, it is determined that the output buffer used by the preceding operator in the previous time step is the input buffer used by the following operator in the next time step. In this way, regardless of the number or type of operators, this method can be used for determination.

[0369] The second condition for determining whether the cache allocated to multiple operators satisfies the criteria is that the caches used by the multiple operators at the same time step are located in different independently accessible regions of the shared cache pool. In one example, the debugging device can determine the address range of the BANK where the cache is located based on the read cache location (i.e., address) information, and then determine whether the addresses of these caches read at the same time step are located in the address ranges of different BANKs. If so, the second condition is satisfied. Here, BANK refers to an independently accessible region in DDR memory; when the storage medium is different, the independently accessible region can have other names.

[0370] In one example of this embodiment, the software code includes M sets of scheduling instructions between the loop start instruction and the loop end instruction. Each set of scheduling instructions includes a start instruction and a synchronization instruction. The operand of the start instruction in the m-th set of scheduling instructions is used to indicate the activation operator of the m-th time step, where m = 1, 2, ..., M, and M ≥ 2.

[0371] The hardware scheduler also includes an operator status register corresponding to each of the plurality of operators. The operator status register is used to store the status information of the operator, and the status information indicates whether the operator is an active operator.

[0372] The debugging method further comprises: after the hardware scheduler executes the m-th group of scheduling instructions and stops executing the instructions, in response to an operator status read command issued by the debugging apparatus, the processor reads the status information of the plurality of operators from the operator status register, and reports the read status information to the debugging apparatus.

[0373] As described above, in order to implement pipelined operation of multiple operators, at different time steps of one cycle, part or all of the operators need to be activated to start corresponding processing, and the operators that need to be started at each time step may be determined according to the operators that the data flow passes through sequentially. This requires that in the software code, the operators started by the scheduling instructions at each time step shall meet the requirements of the data flow, and details may be referred to the above description. In this example, the status information of the operators is read from the operator status registers corresponding to the respective operators, so as to verify whether the activated operators indicated in the scheduling instructions meet this requirement. The operator status read command in this embodiment may not be a command dedicated to reading the operator status, and may also read other data besides the operator status, for example, read the information of the instruction execution status from the instruction execution status register, and so on.

[0374] In this example, after the processor reports the read status information to the debugging apparatus, the debugging method may further comprise:

[0375] The debugging apparatus judges, according to the serial number m of the time step and the status information of the plurality of operators, whether the activated operators at the m-th time step indicated by the start instruction in the m-th group of scheduling instructions conform to a rule: if the rule is not met, the debugging apparatus reports an error to a user, indicating that the error type is an activated operator error; wherein,

[0376] The rule is: in each cycle, when m<m1, the activated operators at the m-th time step are the 1st to the m-th operators; when m1≤m≤m2, the activated operators at the m-th time step are the plurality of operators; when m2<m≤M, the activated operators at the m-th time step are the (m-m2+1)-th to the m1-th operators; wherein M=m1+m2-1, m1 and m2 are preset values, m1 is the number of operators to be scheduled among the plurality of operators, and m2 is the number of data blocks processed in each cycle.

[0377] The period from the start to the end of the m-th group of scheduling instructions described above defines exactly the m-th time step, since the activated operators indicated by the m-th group of scheduling instructions are exactly the activated operators at the m-th time step. As for which operators are activated at each time step, a detailed description has been given above, which will not be repeated here. The rule given in this example is only exemplary, and the pipeline processing manner implemented thereby may be referred to Figure 11A the example shown in the accompanying drawings. In another example, if what is to be implemented is Figure 11Bthe pipeline shown, the rules to be satisfied are as follows:

[0378] In the first cycle, when m ≤ m1, the activation operators at the m-th time step are the 1st to m-th operators; when m1 < m ≤ M, the activation operators at the m-th time step are all the plurality of operators;

[0379] From the second cycle to the penultimate cycle, the activation operators at all time steps are all the plurality of operators;

[0380] In the last cycle, the activation operators at the m'-th time step are the (m'+1)-th to m1-th operators;

[0381] where M is equal to the number of receiving channels, m1 is the number of operators to be scheduled among the plurality of operators; M ≥ m1, and m' = 1, 2, ..., m1-1. The scheduling manner of this example can implement Figure 11B the pipeline shown.

[0382] It can be seen from Figure 11B that in this example, in multiple cycles, at the first several time steps starting from the first cycle, the plurality of operators are activated in sequence, and after an operator is activated, it remains an activation operator at each subsequent time step until the plurality of operators sequentially exit the processing in the last cycle. In this manner, the number M of time steps included in each cycle may be equal to the number of receiving channels. When M is greater than the number m1 of operators to be scheduled, the number of cycles is 1 more than that of the example corresponding to Figure 11A , for example, when one frame of data includes 128 chirp data, the number of cycles of the example corresponding to Figure 11A is 128, while the number of cycles of this example corresponding to Figure 11B is 129. However, in this example, there is no idle time for an operator from activation to exit, and the total number of time steps required to complete the entire processing is less than that of the example corresponding to Figure 11A , which has higher efficiency.

[0383] Because the rules for determining the activation operator differ between the first and last loops in this example, the activation operator can be determined through a judgment instruction in each loop. Specifically, the judgment instruction determines whether the current loop is the first, middle, or last loop. If it's the first loop, the first branch is entered, and the operands indicating the activation operator in the startup instruction are generated according to the method used for determining the activation operator in the first loop. If it's a middle loop (i.e., the second to the penultimate loop process), the second branch is entered, and the operands indicating the activation operator in the startup instruction are generated according to the method used for determining the activation operator in the middle loop (the activation operators for all time steps are the aforementioned multiple operators). If it's the last loop, the third branch is entered, and the operands indicating the activation operator in the startup instruction are generated according to the method used for determining the activation operator in the last loop. If the first two branches are entered, a jump instruction can be used to jump to the subsequent processing flow.

[0384] This embodiment provides a convenient method for verifying the activation operator indicated by the operand in the scheduling instruction. This method replaces the verification performed by the developer with the debugging device, which can improve the accuracy of the verification and the efficiency of the debugging.

[0385] In an exemplary embodiment of this disclosure, the debugging method further includes: during the process of loading the software code to be debugged into the cache of the hardware scheduler, the hardware scheduler determines whether each instruction is valid based on the instruction ID, generates an original checksum for each valid instruction and writes it into the cache together with the instruction, and if there is an invalid instruction, it reports an error to the debugging device and indicates the reason for the error; and when the hardware scheduler executes each instruction, it generates a checksum for the instruction and compares it with the original checksum of the instruction, and if it determines that the instruction is wrong based on the comparison result, it reports an error to the debugging device and indicates the reason for the error.

[0386] Hardware accelerators rely on instruction scheduling to complete their work, so ensuring instruction correctness is paramount. Instruction errors can occur for two reasons: errors during instruction encoding or errors during transmission. For the first reason, the hardware scheduler will report an interrupt when it detects that the instruction's identifier (ID) does not belong to a valid instruction. For the second reason, a 4-bit parity check can be added during instruction transmission. Parity checking is performed during instruction execution, and if an error occurs, an interrupt will be reported.

[0387] This embodiment generates checksums on a per-instruction basis when loading software code. Each instruction is then checked against these checksums before execution, allowing for the detection of any invalid instructions during saving and thus more accurately pinpointing the cause of the error. Without checksums, errors during instruction execution are less likely to be found due to the limited number of possible causes. If an instruction is found to be invalid during saving during debugging, it can be reloaded, or the cached media containing the software code can be repaired or replaced with a new one.

[0388] The debugging methods described in the above embodiments of this disclosure offer various debugging techniques, enabling users to locate problems more quickly and accurately, thereby improving development efficiency. In particular, the debugging device can automatically verify the correctness of the cache allocated by the cache allocation instructions and the operators activated by the scheduling instructions in the software code based on the data stream passing through the operators. This allows for faster and more accurate discovery of related instruction problems in cache allocation and scheduling, further improving debugging efficiency.

[0389] One embodiment of this disclosure also provides a radar chip, such as Figure 22 As shown, it includes a radio frequency module 500, an analog signal processing module 501, and a digital signal processing module 502 connected in sequence;

[0390] The radio frequency module is configured to generate and transmit electromagnetic wave signals, and to receive electromagnetic wave signals.

[0391] The analog signal processing module is configured to down-frequency the received electromagnetic wave signal to obtain an intermediate frequency signal.

[0392] The digital signal processing module is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; wherein, the digital signal processing module includes the processor and hardware accelerator in the debugging method described in any embodiment of this disclosure, that is, the processor and hardware accelerator in the digital signal processing module can complete the debugging operations performed by the processor and hardware accelerator in the above-mentioned debugging method, such as the processor can load software code, the hardware accelerator includes a hardware scheduler and multiple operators, and the hardware scheduler in the hardware accelerator can perform instruction timeout monitoring when executing each instruction.

[0393] One embodiment of this disclosure also provides a debugging device, such as... Figure 23 As shown, it includes a processor 60' and a memory 50' storing a computer program. When the processor executes the computer program, it can perform the processing performed by the debugging device in the debugging method described in any embodiment of this disclosure.

[0394] An embodiment of this disclosure also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the debugging method described in any embodiment of this disclosure.

[0395] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A method for debugging software code, applied to a radar system including a processor and a hardware accelerator, wherein the hardware accelerator includes a hardware scheduler and multiple operators, the debugging method comprising: The processor loads the software code to be debugged into the cache of the hardware scheduler. The software code includes multiple instructions executed by the hardware scheduler for controlling the multiple operators to perform radar signal processing. In response to the run command issued by the debugging device, the hardware scheduler starts execution from the current instruction. When the instruction timeout function is enabled, it determines the execution time of each instruction when executing it, and reports an error to the debugging device when the execution time exceeds a preset time threshold.

2. The debugging method as described in claim 1, characterized in that: The hardware accelerator also includes an instruction timeout enable register and an instruction timeout timer; The debugging method further includes: in response to an instruction timeout enable command issued by the debugging device, the processor sets the value of the instruction timeout enable register to a value indicating instruction timeout enable; The hardware scheduler starts the instruction timeout timer to count when the instruction timeout enable register indicates that instruction timeout is enabled, and stops counting when the instruction is completed. The execution time of the instruction is determined based on the count value when the instruction timeout timer stops counting.

3. The debugging method as described in claim 1, characterized in that: The software code includes wait instructions as breakpoints; When the response execution command is a multi-step execution command and carries information about a specified breakpoint, the hardware scheduler executes the instructions sequentially from the current instruction. If an error occurs before reaching the specified breakpoint, the instruction execution stops and an error is reported; if no error occurs when reaching the specified breakpoint, the instruction execution stops after reaching the specified breakpoint. When the response execution command is a single-step execution command, the hardware scheduler starts execution from the current instruction. If the current instruction is executed successfully, the execution of the instruction is stopped and the next instruction is taken as the new current instruction. If the current instruction is executed incorrectly, the execution of the instruction is stopped, the next instruction is taken as the new current instruction, and an error is reported.

4. The debugging method as described in claim 3, characterized in that: Different waiting instructions in the software code contain different index values; The multi-step execution command carries a target index value, and the hardware scheduler identifies the wait instruction containing the target index value as the specified breakpoint.

5. The debugging method as described in claim 1, characterized in that: The hardware accelerator also includes a PC value register; The debugging method further includes: in response to an instruction jump command issued by the debugging device, the processor updates the PC value in the PC value register to the target PC value carried in the instruction jump command, so that the current instruction to be executed by the hardware scheduler jumps to the target instruction pointed to by the target PC value.

6. The debugging method as described in claim 1, characterized in that: The hardware accelerator also includes a shared cache pool and register set; The software code includes multiple cache allocation instructions. When the multiple cache allocation instructions are executed, caches used for accessing data are allocated from the shared cache pool for the multiple operators respectively, and the cache information allocated for the multiple operators is written into the register group to form a data channel through the multiple operators for the data flow. The debugging method further includes: after the hardware scheduler executes the cache allocation instruction and stops the execution of the instruction, in response to the cache information read command issued by the debugging device, the processor reads the cache information allocated to the plurality of operators for two consecutive time steps from the register group, and reports the read information to the debugging device.

7. The debugging method as described in claim 6, characterized in that: The software code also includes multiple sets of scheduling instructions. When the multiple sets of scheduling instructions are executed, the multiple operators are scheduled step by step, so that the multiple operators are started sequentially according to the order in which the data stream passes through the operators, and the data to be processed is processed in a pipeline manner. Each time step starts when a set of scheduling instructions is executed and ends when the execution of that set of scheduling instructions is completed. The software code also includes a loop start instruction preceding the multiple sets of scheduling instructions and a loop end instruction following the multiple sets of scheduling instructions, enabling the multiple operators to complete radar signal processing through multiple loops; The multiple cache allocation instructions are all located before the loop start instruction; or, some of the multiple cache allocation instructions are located before the loop start instruction and some are located between the loop start instruction and the loop end instruction.

8. The debugging method as described in claim 7, characterized in that: After the processor reports the read information to the debugging device, the debugging method further includes: The debugging device determines whether the cache currently allocated to the multiple operators meets the following conditions: among adjacent operators, the output cache used by the preceding operator in the previous time step is the same as the input cache used by the subsequent operator in the next time step, and the caches used by the multiple operators in the same time step are located in different independently accessible regions of the shared cache pool; and If the conditions are not met, the debugging device reports an error to the user, indicating that the error type is a cache allocation error; The preceding time step and the following time step are two consecutive time steps.

9. The debugging method as described in claim 7, characterized in that: In the software code, there are M sets of scheduling instructions between the loop start instruction and the loop end instruction. Each set of scheduling instructions includes a start instruction and a synchronization instruction. The operand of the start instruction in the m-th set of scheduling instructions is used to indicate the activation operator of the m-th time step, where m = 1, 2, ..., M, and M ≥ 2. The hardware scheduler also includes an operator status register corresponding to each of the plurality of operators. The operator status register is used to store the status information of the operator, and the status information indicates whether the operator is an active operator. The debugging method further comprises: after the hardware scheduler executes the m-th group of scheduling instructions and stops executing instructions, in response to an operator status read command issued by the debugging apparatus, the processor reads the status information of the plurality of operators from the operator status register, and reports the read status information to the debugging apparatus.

10. The code generation method as claimed in claim 9, wherein: After the processor reports the read status information to the debugging apparatus, the debugging method further comprises: the debugging apparatus determines, according to the serial number m of the time step and the status information of the plurality of operators, whether the activation operator of the m-th time step indicated by the activation instruction in the m-th group of scheduling instructions conforms to a rule: if the rule is not conformed to, the debugging apparatus reports an error to a user, indicating that the error type is an activation operator error; wherein The rule is as follows: in each cycle process, when m<m1, the activation operators of the m-th time step are the 1st to m-th operators; when m1≤m≤m2, the activation operators of the m-th time step are the plurality of operators; when m2<m≤M, the activation operators of the m-th time step are the (m-m2+1)-th to m1-th operators; wherein M=m1+m2-1, m1 and m2 are preset values, m1 is the number of operators to be scheduled among the plurality of operators, and m2 is the number of data blocks processed in each cycle; or The rule is as follows: in the first cycle process, when m≤m1, the activation operators of the m-th time step are the 1st to m-th operators, and when m1<m≤M, the activation operators of the m-th time step are all the plurality of operators; in the processes from the second cycle to the second-to-last cycle, the activation operators of all time steps are all the plurality of operators; in the last cycle process, the activation operators of the m'-th time step are the (m'+1)-th to m1-th operators; wherein M is equal to the number of receiving channels, m1 is the number of operators to be scheduled among the plurality of operators, M≥m1, and m'=1,2,…,m1-1.

11. The debugging method as claimed in claim 1, wherein: The debugging method further comprises: In the process of loading the software code to be debugged into the cache of the hardware scheduler, the hardware scheduler judges whether each instruction is valid according to the ID of the instruction, generates an original check code for each valid instruction and writes the original check code into the cache together with the instruction, and if any invalid instruction exists, reports an error to the debugging apparatus and specifies the error cause; and When the hardware scheduler executes each instruction, it generates a check code for the instruction and compares the check code with the original check code of the instruction, and when it is determined that the instruction is erroneous according to the comparison result, it reports an error to the debugging apparatus and specifies the error cause.

12. The debugging method as claimed in claim 1, wherein: The radar system is a radar chip, and the radar chip is connected with the debugging apparatus through a debugging interface; The processor is configured to read and write the register specified by the command in response to the access register command issued by the debugging device, and is configured to send the run command issued by the debugging device to the hardware scheduler, which then responds to the run command.

13. A radar chip, characterized in that, It includes a radio frequency module, an analog signal processing module, and a digital signal processing module connected in sequence; The radio frequency module is configured to generate and transmit electromagnetic wave signals, and to receive electromagnetic wave signals. The analog signal processing module is configured to down-frequency the received electromagnetic wave signal to obtain an intermediate frequency signal. The digital signal processing module is configured to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; wherein the digital signal processing module includes a processor and a hardware accelerator as described in any one of claims 1 to 12.

14. A debugging apparatus, comprising a processor and a memory storing a computer program, characterized in that, When the processor executes the computer program, it can perform the processing performed by the debugging device in any of the debugging methods described in claims 1 to 12.

15. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the debugging method as described in any one of claims 1 to 12.

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