Method of operating a mixed-mode NAND flash memory cell, computer readable storage medium and apparatus

Abstract

The present application relates to a method for operating a hybrid NAND flash memory cell, a computer readable storage medium and an apparatus. The method is performed by a processing unit of a flash controller and comprises connecting a flash module comprising a first NAND flash memory cell, a second NAND flash memory cell, a third NAND flash memory cell and a fourth NAND flash memory cell, and writing user data obtained from a host into the flash module. A first partition of a single-layer cell local of the first to fourth NAND flash memory cells provides a cache space of a three-layer cell local of the first and third NAND flash memory cells, and a second partition of the single-layer cell local of the first to fourth NAND flash memory cells provides a cache space of a four-layer cell local of the second and fourth NAND flash memory cells.

Description

Technical Field

[0001] This invention relates to storage devices, and more particularly to a method for operating hybrid NAND flash memory cells, a computer-readable storage medium, and an apparatus. Background Technology

[0002] Flash memory is generally divided into NOR flash memory and NAND flash memory. NOR flash memory is a random access device. The host side can provide any address to access the NOR flash memory on the address pins and obtain the data stored at that address from the data pins of the NOR flash memory in real time. In contrast, NAND flash memory is not random access, but serial access. Unlike NOR flash memory, NAND flash memory cannot access any random address. Instead, the host side needs to write serial bytes of values ​​into the NAND flash memory to define the type of request command (e.g., read, write, erase, etc.) and the address used for this command. The address can point to a page (the smallest data block in flash memory for a write operation) or a block (the smallest data block in flash memory for an erase operation). Summary of the Invention

[0003] In view of this, how to mitigate or eliminate the deficiencies in the aforementioned related fields is a problem that needs to be solved.

[0004] The present invention relates to a method for operating hybrid NAND flash memory cells, executed by a processing unit of a flash memory controller, comprising: connecting a flash memory module comprising a first NAND flash memory cell, a second NAND flash memory cell, a third NAND flash memory cell, and a fourth NAND flash memory cell; and writing user data acquired from a host device into the flash memory module.

[0005] The present invention also relates to a computer-readable storage medium for storing program code that can be loaded and executed by a processing unit, and the program code, when executed by the processing unit of the flash memory controller, implements the method of operating the hybrid NAND flash memory cell as described above.

[0006] The present invention also relates to an apparatus for operating hybrid NAND flash memory cells, comprising: a flash memory interface coupled to a flash memory module including a first NAND flash memory cell, a second NAND flash memory cell, a third NAND flash memory cell, and a fourth NAND flash memory cell; and a processing unit coupled to the flash memory interface. The processing unit is configured to: connect to the flash memory module; and write user data acquired from a host device to the flash memory module.

[0007] In the flash memory module, the first partitions of the single-layer cell locality of the first to fourth NAND flash memory cells are combined to provide cache space for the three-layer cell locality of the first and third NAND flash memory cells, and the second partitions of the single-layer cell locality of the first to fourth NAND flash memory cells are combined to provide cache space for the four-layer cell locality of the second and fourth NAND flash memory cells.

[0008] One of the advantages of the above embodiments is that, through the configuration of the hybrid architecture of the flash memory module as described above, the data transfer capacity of the flash memory module is increased, and the read / write latency of the flash memory module is reduced.

[0009] Other advantages of the present invention will be explained in more detail below with reference to the accompanying drawings. Attached Figure Description

[0010] The accompanying drawings, which are provided to further illustrate this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application.

[0011] Figure 1 This is a system architecture diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2 This is a schematic diagram of a flash memory module according to an embodiment of the present invention.

[0013] Figure 3 This is a partial hardware architecture diagram of a NAND flash memory cell according to an embodiment of the present invention.

[0014] Figure 4 This is a hybrid architecture built in a flash memory module according to an embodiment of the present invention.

[0015] Figure 5 This is a schematic diagram illustrating data access operations of a hybrid architecture of a flash memory module according to some implementation methods.

[0016] Figure 6 and Figure 7 This is a schematic diagram illustrating data access operations of a hybrid architecture flash memory module according to an embodiment of the present invention.

[0017] Figure 8 This is a flowchart of a rapid programming method for data access operations of a hybrid architecture of a flash memory module, executed by the processing unit of a flash memory controller according to an embodiment of the present invention.

[0018] Explanation of reference numerals in the attached figures: 10 electronic devices 110 host terminal 130 Flash Controller 131 host interface 132 bus architecture 134 processing units 136 Random Access Memory 139 flash memory interface 150 flash memory modules 151 interface 153#0~153#3 NAND flash memory cells Channels CH#0~CH#1 CE#0~CE#1 start signals 300 storage blocks 310 floating gate transistor BL1~BL3 bit lines WL0~WL5 letter lines 400, 410, 420, 430 SLC local 405, 425TLC local 415, 435QLC local 400-1, 410-1, 420-1, 430-1 TLC Buffer 400-2, 410-2, 420-2, 430-2 QLC Buffer 500, 510 superblocks / data blocks 505, 507, 515 Current Block 600 superblocks / data blocks 605, 607 Current Block 700 superblocks / data blocks 705 Current Block S805~S860 Method Steps Detailed Implementation The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals denote the same or similar components or method flows.

[0019] The following provides various aspects and embodiments of this specification. Some embodiments can be implemented independently, while others can be combined and implemented by those skilled in the art where readily apparent. The following description is for illustrative purposes only, and specific details are provided to enable a complete understanding of various aspects of the present invention. However, it will be apparent that these embodiments are not necessarily to be carried out in such a detailed and complete manner. The accompanying drawings and description are not intended to limit the scope of the invention.

[0020] The following description is merely illustrative and is not intended to limit the scope, application, or setting of this specification. Rather, the examples provided are intended to offer implementations that can be carried out by those skilled in the art. It should be understood that the function and arrangement of the elements may be changed without departing from the scope and spirit of the claims.

[0021] refer to Figure 1Electronic device 10 includes a host side 110, a flash memory controller 130, and a flash memory module 150, which can be collectively referred to as the device side. Electronic device 10 can be implemented in peripheral storage devices, personal computers, laptop PCs, tablets, mobile phones, digital cameras, digital camcorders, smart TVs, smart refrigerators, automotive electronic systems, and other electronic products. The host interface 131 of the host side 110 and the flash memory controller 130 can communicate with each other using communication protocols such as Universal Serial Bus (USB), Advanced Technology Attachment (ATA), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCI-E), Universal Flash Storage (UFS), and Embedded Multi-Media Card (eMMC). The flash interface 139 of the flash controller 130 and the flash module 150 can communicate with each other using a Double Data Rate (DDR) communication protocol, such as Open NAND Flash Interface (ONFI), DDR Toggle, or other communication protocols. The flash controller 130 includes a processing unit 134, which can be implemented in various ways, such as using general-purpose hardware (e.g., a microcontroller unit, a single processor, a multiprocessor with parallel processing capabilities, a graphics processor, or other processors with computing power), and provides the functionality described later when executing software and / or firmware instructions. The processing unit 134 receives host commands, such as read commands, write commands, discard commands, and erase commands, through the host interface 131, and schedules and executes these commands.The flash controller 130 also includes random access memory (RAM) 136, which can be implemented as dynamic random access memory (DRAM), static random access memory (SRAM), or a combination of the two. This RAM is used to configure space as a data buffer, storing user data (also referred to as host data) read from the host 110 and about to be written to the flash module 150, as well as user data read from the flash module 150 and about to be output to the host 110. The RAM 136 can also store data required during execution, such as variables, data tables, data structures, host-to-flash / H2F tables, flash-to-host / F2H tables, queues, etc. The flash interface 139 includes a NAND flash controller (NFC) that provides the functions required to access the flash module 150, such as a command sequencer and low-density parity check (LDPC).

[0022] The flash memory controller 130 includes a configurable bus architecture 132 for coupling components to each other to transmit data, addresses, control signals, etc. These components include, but are not limited to, the host interface 131, the processing unit 134, RAM 136, and the flash memory interface 139. Direct Memory Access (DMA) circuitry within the components can migrate data between components via the bus architecture 132 according to instructions or control signals. For example, the DMA circuitry in the host interface 131 or the flash memory interface 139 can move data from a specific data buffer to a specific address in RAM 136, or move data from a specific address in RAM 136 to a specific data buffer.

[0023] Flash module 150 provides a large storage space, typically hundreds of gigabytes (GB) or even multiple terabytes (TB), for storing large amounts of user data, such as high-resolution images and videos. Flash module 150 includes control circuitry and a memory array. The memory cells in the memory array can be configured as single-level cells (SLCs), multiple-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), or any combination thereof. Processing unit 134 writes user data to a specified address (destination address) in flash module 150 and reads user data from a specified address (source address) in flash module 150 via flash interface 139. Flash interface 139 uses multiple electronic signals to coordinate data and command transmission between flash controller 130 and flash module 150, including data lines, clock signals, and control signals. Data lines can be used to transmit commands, addresses, read data, and write data; control signal lines can be used to transmit control signals such as Chip Enable (CE), Address Latch Enable (ALE), Command Latch Enable (CLE), and Write Enable (WE).

[0024] refer to Figure 2The interface 151 in the flash memory module 150 may include two input / output channels (I / O channels) CH#0 to CH#1. Each channel connects two NAND flash memory cells. For example, channel CH#0 connects NAND flash memory cells 153#0 and 153#1, and channel CH#1 connects NAND flash memory cells 153#2 and 153#3. Each NAND flash memory cell may be packaged as an independent die, and each die may be distinguished by a Logical Unit Number (LUN) or a similar but different identifier. Each die contains one or more data planes, and each data plane contains hundreds or more physical blocks. The flash memory interface 139 can start NAND flash memory cells 153#0 and 153#2 by issuing a start signal CE#0 through interface 151, or start NAND flash memory cells 153#1 and 153#3 by issuing a start signal CE#1 through interface 151. Then, user data is read from the started NAND flash memory cells or written to the started NAND flash memory cells in an interleaved parallel manner. The flash memory interface 139 can transmit write commands, specified physical addresses, and data via the data bus in channel CH#0 or CH#1, for writing data to the specified physical address of the corresponding NAND flash memory cell (or the corresponding chip). The flash memory interface 139 can also transmit read commands and specified physical addresses via the data bus in channel CH#0 or CH#1, and read data from the specified physical address of the corresponding NAND flash memory cell (or the corresponding chip) via the data bus in the same channel. Figure 2 The arrangement of the flash memory module 150 shown is for illustrative purposes only. Those skilled in the art can modify the flash memory module 150 to include more channels and / or provide more NAND flash memory cells in one channel according to different system requirements.

[0025] refer to Figure 3 The local hardware architecture of a NAND flash memory cell. Each NAND flash memory cell may contain memory blocks 300, and memory blocks 300 contain multiple memory cells, such as floating gate transistors 310 or other charge trap devices. The structure of memory blocks 300 includes multiple bit lines and multiple word lines. For simplicity, Figure 3 Only bit lines BL1 to BL3 and word lines WL0 to WL5 are labeled. For example, the floating gate transistors on any of the word lines WL0 to WL2 and WL3 to WL5 can store one or more pages of data.

[0026] Each NAND flash memory cell can contain multiple data planes, and each data plane can contain multiple physical blocks. To improve data write and read efficiency, specific physical pages in multiple data planes of multiple NAND flash memory cells can be organized into a super page (SP). For example, in Figure 2 In the example setup shown, each flash cell contains four data planes, and each data plane contains a 4-kilobyte (KB) physical page. A superpage can store 32KB of user data (= four channels × (multiplied by) two CEs × two data planes × 4KB). Specific superpages across multiple data planes of multiple NAND flash cells can be organized into a superblock (SB). In some embodiments, any superblock can be configured as a SingleLevel Cell (SLC) superblock, where each word line (WL) in the SLC SB can be configured as an SLC WL, and each superpage in the SLC WL is an SLC SP. In other embodiments, any superblock can be configured as a MultipleLevel Cell (MLC) superblock, where each WL in the MLC SB can be configured as an SLC WL or an MLC WL. Each superpage in each SLC WL can be called an SLC SP, while each superpage in an MLC SB can be either a Most Significant Bit (MSB SP) or a Least Significant Bit (LSB SP). In other embodiments, any superblock can be configured as a Triple Level Cell (TLC SB), where each WL in the TLC SB can be configured as an SLC WL or a TLC WL. Each superpage in each SLC WL can be called an SLC SP, while each superpage in the TLC SB can be either an MSB SP, a Center Significant Bit (CSB SP), or an LSB SP. In other embodiments, any superblock can be configured as a Quad-Level Cell (QLC SB), where each WL in the QLC SB can be configured as an SLC WL or a QLC WL. Each superpage in each SLC WL can be called an SLC SP, while each superpage in a QLC SB can be a Top Significant Bit (TSB Page), MSB SP, CSB SP, or LSB SP.

[0027] In some embodiments, a Logical Block Address (LBA) managed by host 110 may represent 512 bytes (B) of user data, and each physical page is divided into eight 64-byte sections. The LBA number can be referred to as the logical address managed by host 110. Superblocks, superpages, physical pages, and sections can be identified using Super-block Number, Super-page Number, Physical Block Number, Physical Page Number, and Section Number, respectively, and the combination of these numbers can be referred to as the physical address of flash memory module 150. In other embodiments, an LBA managed by host 110 may represent 4KB of user data, and each physical page is divided into eight 512-byte sections. The LBA number can be referred to as the logical address managed by host 110. Superblocks, superpages, physical blocks, physical pages, and segments can be identified using superblock numbers, superpage numbers, physical block numbers, physical page numbers, and segment numbers, respectively. The combination of these numbers can be referred to as the physical address of the flash memory module 150. In some other embodiments, a host page number managed by the host 110 can represent 4KB of user data, and each physical page does not need to be further subdivided into segments. The host page number can be referred to as the logical address managed by the host 110. Superblocks, superpages, physical blocks, and physical pages can be identified using superblock numbers, superpage numbers, physical block numbers, and physical page numbers, respectively. The combination of these numbers can be referred to as the physical address of the flash memory module 150.

[0028] Each physical block can be divided into a data block or a current block according to its function. The processing unit 134 can select an empty superblock in the data plane as the current block to prepare for writing user data received from the host 110. To improve the efficiency of data writing, the user data provided by the host 110 can be written in parallel to empty pages in the current block that spans multiple NAND flash memory cells (or chips). The processing unit 134 can maintain an F2H table for each current block in RAM 136, containing multiple records that store information about which logical address each physical page in the current block is associated with (or mapped to) according to the page number of the physical page in the current block. The logical address can be represented using a logical block address (LBA), host page number, or other methods and is managed by the host 110. After all physical pages in a current block are filled with user data, or after the remaining pages in a current block are filled with dummy values, processing unit 134 can drive flash interface 139 to write the corresponding F2H table in RAM 136 to the data portion of a specified physical page (e.g., the last physical page) of the current block. Once the corresponding F2H table has been written to flash module 150, this current block becomes a data block, and the user data stored in the data block will no longer change. Then, processing unit 134 can select another empty superblock as the new current block.

[0029] In addition to writing the F2H table to the specified physical page in the current block, the processing unit 134 also needs to update the H2F table based on the contents of the F2H table in the current block. This is so that when a host read command is executed in the future, the information on which physical address the user data associated with a specific logical address is actually stored can be quickly found from the H2F table. The H2F table contains multiple records, storing information on which logical address the user data of each logical address is actually stored in order of logical address. However, since RAM 136 cannot provide enough space to store the entire H2F table for the processing unit 134 to quickly look up during data read operations, the H2F table can be divided into multiple H2F sub-tables and stored in the flash memory module 150, so that the corresponding H2F sub-table can be read from the flash memory module 150 to RAM 136 during data read operations.

[0030] As storage capacity demands increase, the NAND module 150 can be configured with more QLC SBs to replace TLC SBs. While each QLC SB offers approximately 33% higher storage density than each TLC SB, the access performance (read / write speed) of QLC SPs is slower than that of TLC SPs because more voltage levels need to be managed per cell, especially during intensive write operations. The flash controller 130 needs to gather more data in preparation for the two-stage programming of QLC SPs, for example, four times the amount required for TLC SPs. That is, the flash controller 130 needs to allocate more space in RAM 136 to temporarily store the data to be written to the QLC SPs. The narrower voltage margin of QLCs increases the error rate during frequent reads. Compared to TLCs, QLCs have higher voltage stress and use more programming steps per cell, thus increasing the probability of disturbance-related errors. Due to the poor voltage state stability of QLCs, the data retention time of QLCs is typically shorter than that of TLCs (QLCs last less than a year under power-off conditions, while TLCs can last 1 to 3 years). Each QLC physical block supports only 100 to 1000 program / erase (P / E) cycles, while each TLC physical block supports approximately 1000 to 3000 P / E cycles. Furthermore, due to the higher error rate, QLC requires more advanced error correction, wear averaging, and caching mechanisms, making the flash controller 130 more complex.

[0031] To overcome the limitations of QLC, this invention proposes a hybrid architecture configured in a flash memory module 150, and a method for writing data to the storage space of this hybrid architecture. The hybrid architecture serves as a leveraging mechanism for SLC cache, TLC cache with folding mechanisms, and QLC storage space. (Reference) Figure 4The diagram illustrates a hybrid architecture built into flash memory module 150. Flash memory module 150 provides at least two channels CH#0 and CH#1, and each channel connects to at least two NAND flash memory cells. For example, channel CH#0 connects NAND flash memory cells 153#0 and 153#1, and channel CH#1 connects NAND flash memory cells 153#2 and 153#3. NAND flash memory cells 153#0 and 153#2 are provided as TLC NAND flash memory cells and are enabled by the CE signal CE#0. A portion of each of the TLC NAND flash memory cells 153#0 and 153#2 is configured as a static SLC cache, where this portion is referred to as an SLC portion, for example, SLC portion 400 or 420. Other portions of each of the TLC NAND flash memory cells 153#0 and 153#2 are configured as TLC buffers, where this portion is referred to as a TLC portion, for example, TLC portion 405 or 425. NAND flash memory cells 153#1 and 153#3 are provided as QLC NAND flash memory cells and are enabled by the CE signal CE#1. A portion of each of the QLC NAND flash memory cells 153#1 and 153#3 is configured as a static SLC cache, wherein this portion is referred to as an SLC portion, for example, SLC portion 410 or 430. Other portions of each of the QLC NAND flash memory cells 153#1 and 153#3 are configured as QLC storage spaces, wherein this portion is referred to as a QLC portion, for example, QLC portion 415 or 435. The physical block of each SLC portion is configured as an SLC block, and each write level (WL) of the SLC block is configured as an SLC write level (WL). The physical block of each TLC portion is configured as a TLC block, and each write level (WL) of the TLC block is configured as a TLC write level (WL). The physical block of each QLC portion is configured as a QLC block, and each write level (WL) of the QLC block is configured as a QLC write level (WL).

[0032] In some embodiments, for reliability and durability reasons, each physical block of SLC locales 400, 410, 420, and 430 is configured as an SLC block only. In other words, each physical block of SLC locales 400, 410, 420, and 430 cannot be selectively configured as an SLC block or a TLC / QLC block (referred to as dynamic SLC configuration).

[0033] In some implementations, see reference Figure 5 The diagram shows a hybrid architecture of the flash module 150 in several cases, in which SLC locales 400 and 420 are used as SLC cache spaces for TLC locales 405 and 425, and SLC locales 410 and 430 are used as SLC cache spaces for QLC locales 415 and 435.

[0034] Regarding the hybrid architecture of flash module 150, an exemplary data access operation is provided as follows: For user data to be stored in TLC regions 405 and 425, this user data is interleaved and written to empty pages in physical blocks (e.g., SB 500) associated with spanning SLC regions 400 and 420, until the total number of empty SBs (or empty physical blocks) in SLC regions 400 and 420 is lower than the default SLC empty-block threshold. Once the total number of empty SBs (or empty physical blocks) in SLC regions 400 and 420 is lower than the default SLC empty-block threshold, an SLC-to-TLC folding process is performed to collect user data from physical blocks (e.g., data block 500) in SLC regions 400 and 420, and the collected user data is interleaved and written to empty pages in physical blocks (e.g., current block 505) associated with SBs spanning TLC regions 405 and 425. Those skilled in the art will understand that data from three SPs in SLC regions 400 and 420 can be collected and written to one SP in TLC regions 405 and 425. After the total number of empty SBs (or empty physical blocks) in TLC regions 405 and 425 falls below the default TLC-empty-block threshold, TLC write-through processing is performed to continuously collect user data from at least three SPs from host 110 and interleave the collected user data to empty pages in physical blocks (such as current block 507) associated with SBs spanning TLC regions 405 and 425. Those skilled in the art will understand that data from three SPs can be collected from host 110 and written to one SP in regions 405 and 425. After the total number of empty SBs (or empty physical blocks) in TLC regions 405 and 425 falls below the default TLC Garbage Collection (TLC-GC) threshold, background garbage collection and / or foreground garbage collection are performed to collect valid user data from data blocks in TLC regions 405 and 425. The collected user data is then interleaved and written to empty pages in the current block associated with the SBs spanning TLC regions 405 and 425. The default TLC garbage collection threshold is lower than the default TLC empty block threshold. Interleaved writing (or programming) involves distributing data across TLC NAND flash cells 153#0 and 153#2.

[0035] For user data to be stored in QLC regions 415 and 435, this user data is interleaved and written to empty pages in physical blocks (e.g., SB 510) associated with spanning SLC regions 410 and 430, until the total number of empty SBs (or empty physical blocks) in SLC regions 410 and 430 falls below the default SLC empty block threshold. Once the total number of empty SBs (or empty physical blocks) in SLC regions 410 and 430 falls below the default SLC empty block threshold, an SLC-to-QLC folding process is performed to collect user data from physical blocks (e.g., data block 510) in SLC regions 410 and 430, and the collected user data is interleaved and written to empty pages in physical blocks (e.g., current block 515) associated with SBs spanning QLC regions 415 and 435. Those skilled in the art will understand that data can be collected from four SPs in SLC regions 410 and 430 and written to one SP in QLC regions 415 and 435. After the total number of empty SBs (or empty physical blocks) in QLC regions 415 and 435 falls below the default QLC Garbage Collection Threshold (QLC-GCThreshold), background garbage collection and / or foreground garbage collection are performed to collect valid user data from the data blocks in QLC regions 415 and 435, and the collected user data is interleaved and written to empty pages in the current block associated with the SBs spanning QLC regions 415 and 435. Interleaved writing (or programming) involves distributing data across QLCNAND flash cells 153#1 and 153#3.

[0036] In order to improve, Figure 5 The data transfer volume of the data access operation shown, and the reduction of its read / write latency, are as follows: Figure 4 The hybrid architecture shown includes TLC locales 405 and 425 and QLC locales 415 and 435. This embodiment of the invention proposes a new sharing policy for SLC cache space. (See reference...) Figure 6 and Figure 7The diagram illustrates new data access operations with a novel sharing strategy under several scenarios. Any memory cell in SLC sections 400, 410, 420, and 430 stores one of two states, representing one bit of information. Any memory cell in TLC sections 405 and 425 stores one of eight states, representing three bits of information, including the MSB, CSB, and LSB. Any memory cell in QLC sections 415 and 435 stores one of sixteen states, representing four bits of information, including the TSB, MSB, CSB, and LSB. Each of SLC sections 400, 410, 420, and 430 is further divided into two areas: a TLC cache and a QLC cache. The TLC cache areas 400-1 of SLC locale 400, 410-1 of SLC locale 410, 420-1 of SLC locale 420, and 430-1 of SLC locale 430 are merged to provide SLC cache space for TLC locales 405 and 425. The QLC cache areas 400-2 of SLC locale 400, 410-2 of SLC locale 410, 420-2 of SLC locale 420, and 430-2 of SLC locale 430 are merged to provide QLC cache space for QLC locales 415 and 435. For example, the storage space of two SBs is configured as TLC cache space (e.g., the storage space containing TLC cache area 400-1 of SLC locality 400, TLC cache area 420-1 of SLC locality 420, TLC cache area 410-1 of SLC locality 410, and TLC cache area 430-1 of SLC locality 430), and the storage space of two SBs is configured as QLC cache space (e.g., the storage space containing QLC cache area 400-2 of SLC locality 400, QLC cache area 420-2 of SLC locality 420, QLC cache area 410-2 of SLC locality 410, and QLC cache area 430-2 of SLC locality 430).

[0037] The storage partition information, as described above, can be stored in one or more tables. These tables are stored in specific pages of the system block within the flash module 150 before the device (including the flash controller 130 and flash module 150) leaves the factory. After the device leaves the factory, these tables are read from specific pages of the system block in the flash module 150 to obtain the storage partition information, and stored in RAM 136 for reference in general operation.

[0038] In some embodiments, a Super-block Management Table is provided to store basic profile information for each SB. An example of the Super-block Management Table's data structure is shown in Table 1: Table 1

[0039] The field "SB_No" records the superblock number of a specific SB, and the field "Type" records information about whether a specific SB is used as a TLC cache, a QLC cache, a TLC locality, or a QLC locality. For example, the superblock management table initialization contains two records: {0,0} and {1,0}, indicating that superblocks SB#0 and SB#1 are used as TLC cache spaces for SLC localities. The superblock management table initialization also stores two records: {2,1} and {3,1}, indicating that superblocks SB#2 and SB#3 are used as QLC cache spaces for SLC localities. The superblock management table initialization also stores ten records: {4,2}, {5,2}, to {13,2}, indicating that superblocks SB#4, SB#5 to SB#13 are used as TLC localities. During superblock management table initialization, ten records are stored: {14,3}; {15,3}; to {23,3}, indicating that superblocks SB#14, SB#15 to SB#23 are used as QLC locales. After initialization, the records of the superblock management table are stored in the system block and cannot be modified. Those skilled in the art can implement the information stored in the superblock management table using different data structures, such as linked lists.

[0040] The physical block management table provides basic information for each physical block. Each record in the physical block management table stores at least the information of which physical block is associated with. An example of the physical block management table's data structure is shown in Table 2. Table 2

[0041] The "LUN" field records the logical cell number of a specific chip within a specific NAND flash memory cell where a specific physical block is located (e.g., "0", "1", "2", "3", "4", "5", "6", "7" represent the 0th and 1st chips of NAND flash memory cell 153#0, the 0th and 1st chips of NAND flash memory cell 153#1, the 0th and 1st chips of NAND flash memory cell 153#2, and the 0th and 1st chips of NAND flash memory cell 153#3, respectively). The "Plane_No" field records the data plane number of a specific data plane where the specific physical block is located (e.g., "0" and "1" represent the 0th and 1st planes, respectively). The "Block_No" field records the physical block number of the specific physical block. The "SB_No" field records the superblock number to which the specific physical block is contained. The "Empty_Page_Start" field records the page number of the starting empty page in the specific physical block of the specific data plane of the specific chip within the specific NAND flash memory cell. If any record stores a null value (NULL) in the "Empty_Page_Start" field, it means that a particular physical block has been filled with data and has become a data block. Before the device leaves the factory, the physical block management table is initialized to an empty table. After the device leaves the factory, new records are added to the physical block management table during normal operation. When specific conditions are met, such as when it is determined that the device needs to be powered off, the latest physical block management table is written to the empty page of the current block (i.e., the candidate system block) of the flash memory module 150.

[0042] For example, before writing user data of one or more SPs to the TLC cache space of flash module 150 (at which no user data has been stored yet), processing unit 134 selects an empty physical block (e.g., the first physical block) in each data plane of each chip of each NAND flash cell as the current block. Processing unit 134 creates sixteen records: {0,0,1,0,0}; {0,1,1,0,0}; {1,0,1,0,0}; {1,1,1,0,0}; {2,0,1,0,0}; {2,1,1,0,0}; {3,0,1,0,0}; {3,1,1,0,0}; {4,0,1,0,0}; {4,1,1,0,0}; {5,0,1,0,0}; {5,1,1,0,0}; {6,0,1,0,0}; {6,1,1,0,0}; {7,0,1,0,0}; and {7,1,1,0,0}, and adds them to the physical block management table of RAM 136. Based on the example records in Table 1, these sixteen records show that the first physical block in the 0th and 1st data planes of the 0th and 1st chips of NAND flash memory cells 153#0, 153#1, 153#2 and 153#3 is merged to form an SB, and its superblock number is "0" (i.e. SB#0). The superblock SB#0 is used as the TLC cache space of the SLC local area.

[0043] For another example, after the physical block in superblock number "2" (i.e., SB#2) is full of user data, superblock SB#2 is designated as the QLC cache space for SLC locality, and the processing unit 134 selects an empty physical block (e.g., the 4th physical block) in each data plane of each chip of each NAND flash memory cell as the current block. Processing unit 134 creates sixteen records: {0,0,4,3,0}; {0,1,4,3,0}; {1,0,4,3,0}; {1,1,4,3,0}; {2,0,4,3,0}; {2,1,4,3,0}; {3,0,4,3,0}; {3,1,4,3,0}; {4,0,4,3,0}; {4,1,4,3,0}; {5,0,4,3,0}; {5,1,4,3,0}; {6,0,4,3,0}; {6,1,4,3,0}; {7,0,4,3,0}; and {7,1,4,3,0}, and adds them to the physical block management table of RAM 136. Referring to the example records in Table 1, these sixteen records show that the fourth physical block in the 0th and 1st data planes of the 0th and 1st chips of NAND flash memory cells 153#0, 153#1, 153#2 and 153#3 is merged to form an SB, and its superblock number is "3" (i.e. SB#3). Superblock SB#3 is used as the QLC cache space of the SLC local area.

[0044] Regarding the hybrid architecture of flash module 150, an exemplary data access operation with the new sharing policy is provided as follows: (Refer to...) Figure 6 Initially, for user data that is about to be stored in TLC locales 405 and 425, a fast programming process is performed to write this user data in an interleaved manner to empty pages in physical blocks (such as SB 600) associated with TLC caches 400-1, 420-1, 410-1, and 430-1, until the total number of empty SBs (or empty physical blocks) in TLC caches 400-1, 420-1, 410-1, and 430-1 is lower than the default SLC empty-block threshold. Figure 6 The storage capacity shown for each SB spanning TLC cache areas 400-1, 420-1, 410-1, and 430-1 is approximately... Figure 5 This represents twice the storage capacity of each SB across SLC sections 400 and 420, as shown. Compared to... Figure 5 The implementation method shown, Figure 6 The interleaved programming illustrated involves distributing data across more NAND flash cells (e.g., not only TLC NAND flash cells 153#0 and 153#2, but also QLC NAND flash cells 153#1 and 153#3), which can increase the data transfer rate between flash interface 139 and interface 151, and / or reduce the write latency of data programming operations. Once the total number of empty SBs (or empty physical blocks) in TLC caches 400-1, 420-1, 410-1, and 430-1 falls below the default SLC empty block threshold, an SLC-to-TLC folding process is performed to collect user data from physical blocks (such as data block 600) in TLC caches 400-1, 420-1, 410-1, and 430-1, and the collected user data is interleaved and written to empty pages in physical blocks (such as current block 605) associated with SBs spanning TLC locales 405 and 425. Those skilled in the art will understand that data from three SPs in TLC buffers 400-1, 420-1, 410-1, and 430-1 can be collected and written to two SPs in TLC local areas 405 and 425. Compared to... Figure 5 The implementation method shown, Figure 6The interleaved reads illustrated involve reading data from more NAND flash cells (e.g., not only TLC NAND flash cells 153#0 and 153#2, but also QLC NAND flash cells 153#1 and 153#3), which can increase the data transfer rate between flash interface 139 and interface 151, and / or reduce the read latency of data read operations in SLC-to-TLC folding processing. After the total number of empty SBs (or empty physical blocks) in TLC regions 405 and 425 falls below the default TLC-empty-block Threshold, a TLC write-through process is performed to continuously collect user data from at least three SPs from host 110, and the collected user data is written in an interleaved manner to empty pages in physical blocks (such as current block 607) associated with SBs spanning TLC regions 405 and 425. Those skilled in the art will understand that data from three SPs can be collected from host 110 and written to one SP in regions 405 and 425. After the total number of empty SBs (or empty physical blocks) in TLC regions 405 and 425 falls below the default TLC Garbage Collection (TLC-GC) threshold, background garbage collection and / or foreground garbage collection are performed to collect valid user data from the data blocks in TLC regions 405 and 425. The collected user data is then interleaved and written to empty pages in the current block associated with the SBs spanning TLC regions 405 and 425. The default TLC garbage collection threshold is lower than the default TLC empty block threshold.

[0045] refer to Figure 7 For user data that is about to be stored in QLC locales 415 and 435, a fast programming process is initially performed to write this user data in an interleaved manner to empty pages in physical blocks (such as SB 700) associated with SBs spanning QLC caches 400-2, 420-2, 410-2, and 430-2, until the total number of empty SBs (or empty physical blocks) in QLC caches 400-2, 420-2, 410-2, and 430-2 is lower than the default SLC empty block threshold. Figure 7 The storage capacity shown for each SB spanning QLC caches 400-2, 420-2, 410-2, and 430-2 is approximately... Figure 5 The storage capacity of each SB across SLC sections 410 and 430 is twice that shown. Compared to, Figure 5 The implementation method shown, Figure 7The interleaved programming illustrated involves distributing data across more NAND flash cells (e.g., not only QLC NAND flash cells 153#1 and 153#3, but also TLC NAND flash cells 153#0 and 153#2), which can increase data transfer rates between flash interface 139 and interface 151, and / or reduce write latency for data programming operations. Once the total number of empty SBs (or empty physical blocks) in QLC caches 400-2, 420-2, 410-2, and 430-2 falls below the default SLC empty block threshold, an SLC-to-QLC folding process is performed to collect user data from physical blocks (such as data block 700) in QLC caches 400-2, 420-2, 410-2, and 430-2, and the collected user data is interleaved and written to empty pages in physical blocks (such as current block 705) associated with SBs spanning QLC locales 415 and 435. Those skilled in the art will understand that it is possible to collect data from two SPs in QLC buffers 400-2, 420-2, 410-2, and 430-2, and write it to one SP in QLC local areas 415 and 435. Compared to... Figure 5 The implementation method shown, Figure 7 The interleaved reads illustrated involve reading data from more NAND flash cells (e.g., not only QLC NAND flash cells 153#1 and 153#3, but also TLC NAND flash cells 153#0 and 153#2), which can increase the data transfer rate between flash interface 139 and interface 151, and / or reduce the read latency of data read operations in SLC-to-QLC folding processing. After the total number of empty SBs (or empty physical blocks) in QLC regions 415 and 435 falls below the default QLC Garbage Collection Threshold (QLC-GCThreshold), background garbage collection and / or foreground garbage collection are performed to collect valid user data from data blocks in QLC regions 415 and 435, and the collected user data is written in an interleaved manner to empty pages in the current block associated with SBs spanning QLC regions 415 and 435.

[0046] With the new sharing policy of the hybrid architecture of the flash memory module 150, the flash memory controller 130 (specifically, processing unit 134) performs a rapid programming method. (See reference) Figure 8 The method shown is a rapid programming process for data access operations in a hybrid architecture, executed by the processing unit 134. Detailed explanation follows: Step S805: Connect the flash memory module 150, whose storage partitioning is as follows: Figure 6 and Figure 7As shown. After completing the system boot process, the processing unit 134 is connected to the flash memory module 150. The system boot process includes various hardware tests on the flash memory module 150, reading the program code and necessary system information of the Flash Translation Layer (FTL) from the system block of the flash memory module 150, storing the program code and necessary system information of the Flash Translation Layer into RAM 136, and other similar operations. The system information includes at least a superblock management table, which is used to implement new sharing policies. The superblock management table contains multiple records, each storing information indicating that a specific superblock is provided across TLC caches 400-1, 420-1, 410-1, and 430-1, QLC caches 400-2, 420-2, 410-2, and 430-2, TLC locales 405 and 425, or QLC locales 415 and 435.

[0047] Next, when the processing unit 134 loads and executes the FTL program code, it repeatedly executes a loop containing steps S810 to S860 to write the user data obtained from the host 110 through the host interface 131 to the flash memory module 150.

[0048] Step S810: Receive a host write command from the host 110 via the host interface 131. For example, the host 110 transmits a command UFS Protocol Information Unit (UPIU) to the flash controller 130, instructing the flash controller 130 to write user data in a specific logical address range to the flash module 150.

[0049] Step S820: Based on the parameters of the host write command, store the user data associated with the host write command into one of the TLC data buffer and the QLC data buffer. Specific space in RAM 136 is allocated as the TLC data buffer and the QLC data buffer. The TLC data buffer is used to temporarily store user data acquired from the host 110 and about to be written to TLC locales 405 and 425. The QLC data buffer is used to temporarily store user data acquired from the host 110 and about to be written to QLC locales 415 and 435.

[0050] In some embodiments, the data type of the user data associated with the host write command is first determined based on the parameters carried in the host write command. For example, the Group Number Field of the command UPIU carries information about the data type of the user data. The Group Number Field is located in bits 0 to 4 of the 22nd byte of the command UPIU. The host 110 sets the data type value to "0h", representing that the user data is infrequently updated data (also known as cold data); otherwise, it sets it to "1h", representing that the user data is frequently updated data (also known as hot data). When the user data data type is detected as cold data, the processing unit 134 stores the user data into the QLC data buffer. Conversely, when the user data data type is detected as hot data, the processing unit 134 stores the user data into the TLC data buffer.

[0051] In other embodiments, the LBA or LBA segment in the host write command is first determined. For example, host 110 reserves a first LBA segment (such as LBA#0 to LBA#1023) for system data and a second LBA segment (such as LBA#1024 and larger LBAs) for application data. It is important to note that the first and second LBA segments do not overlap. When an LBA or LBA segment carried by a host write command is detected to enter the first LBA segment, processing unit 134 stores user data in the TLC data buffer. Conversely, when an LBA or LBA segment carried by a host write command is detected to enter the second LBA segment, processing unit 134 stores user data in the TLC or QLC data buffer.

[0052] In other embodiments, the length of the user data carried in the host write command is first determined. When the length of the user data is detected to be shorter than a threshold, the processing unit 134 determines that the host write command is a random write command and stores the user data in the TLC data buffer. Conversely, when the length of the user data is detected to be equal to or longer than the threshold, the processing unit 134 determines that the host write command is a sequential write command and stores the user data in the QLC data buffer. The threshold can be set to 4K, 16K, or 32K bytes.

[0053] Step S830: Determine whether the data buffer used to store user data in step S820 is full of user data for one SP. If yes, the process continues to step S840. Otherwise, the process continues to step S810 to collect more data into the buffer.

[0054] Step S840: Determine whether the data buffer used to store user data in step S820 is a TLC data buffer or a QLC data buffer. If the data buffer is a TLC data buffer, the process continues to step S850. If the data buffer is a QLC data buffer, the process continues to step S860.

[0055] Step S850: User data in the TLC data buffer is written in an interleaved manner to the empty page of the current block spanning TLC cache area 400-1 of TLC NAND flash cell 153#0, TLC cache area 420-1 of TLC NAND flash cell 153#2, TLC cache area 410-1 of QLC NAND flash cell 153#1, and TLC cache area 430-1 of QLC NAND flash cell 153#3. After programming the current block, the page becomes a superpage. Search the superblock management table and physical block management table to obtain information about a specific empty page of a specific current block that the user data of the TLC data buffer has written to, spanning TLC cache 400-1 of TLC NAND flash cell 153#0, TLC cache 420-1 of TLC NAND flash cell 153#2, TLC cache 410-1 of QLC NAND flash cell 153#1, and TLC cache 430-1 of QLC NAND flash cell 153#3.

[0056] Step S860: User data in the QLC data buffer is written in an interleaved manner to the empty page of the current block spanning QLC cache 400-2 of TLC NAND flash cell 153#0, QLC cache 420-2 of TLC NAND flash cell 153#2, QLC cache 410-2 of QLC NAND flash cell 153#1, and QLC cache 430-2 of QLC NAND flash cell 153#3. After programming the current block, the page becomes a superpage. Search the superblock management table and physical block management table to obtain information about a specific empty page of a specific current block across QLC cache 400-2 of TLC NAND flash cell 153#0, QLC cache 420-2 of TLC NAND flash cell 153#2, QLC cache 410-2 of QLC NAND flash cell 153#1, and QLC cache 430-2 of QLC NAND flash cell 153#3, where user data in the QLC data buffer is written.

[0057] Although the present invention has been described and illustrated herein with reference to specific embodiments, it is not intended to be limited to the details shown. Rather, various modifications to the details may be made within the scope and equivalents of the claims without departing from the invention. It should be understood that the above description is illustrative and should not be construed as limiting the invention. Various modifications, applications, and / or combinations of the embodiments will be apparent to those skilled in the art without departing from the scope of the invention as defined by the claims.

[0058] It will be readily understood by those skilled in the art that the invention discussed above can be implemented using different configurations of hardware elements than those disclosed. Therefore, although the invention has been described based on these preferred embodiments, certain modifications, variations, and alternative constructions will be apparent to those skilled in the art, and are also within the scope of the invention.

[0059] It must be understood that the terms "comprising" and "including" used in this specification are used to indicate the presence of specific technical features, values, method steps, operation processes, parts and / or components, but do not preclude the addition of more technical features, values, method steps, operation processes, components, parts, or any combination thereof.

[0060] In this invention, terms such as "first," "second," and "third" are used to modify components in the claims and are not used to indicate a priority order, a prior relationship, or that one component precedes another, or the chronological order of the execution of method steps. They are only used to distinguish components with the same name.

[0061] It's important to understand that when a component is described as "connected" or "coupled" to another component, it can be a direct connection or coupling to other components, potentially involving intermediate components. Conversely, when a component is described as "directly connected" or "directly coupled" to another component, there are no intermediate components. Other terms used to describe relationships between components can be interpreted similarly, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," and so on.

[0062] The terms "device" or "module" are not limited to one or a specific number of physical objects (e.g., a smartphone, a controller, a processing system, etc.). As used herein, a device can be any electronic device having one or more components that performs at least some of the functions of the invention disclosed herein. While the description and examples use the terms "device" or "module" to describe various aspects of the invention, the terms "device" or "module" are not limited to a particular configuration, type, or number of objects. Furthermore, the terms "system" or "module" are not limited to multiple components or a particular orientation. For example, a system may be implemented on one or more printed circuit boards or other substrates and may have movable or static components. While the description and examples use the term "system" to describe various aspects of the invention disclosed herein, the term "system" is not limited to a particular configuration, type, or number of objects.

[0063] Specific details are provided in the above description to aid in a thorough understanding of various aspects of the invention. However, those skilled in the art will understand that these aspects can be implemented without these specific details. For clarity of explanation, in some instances, the technology may be presented as comprising individual functional blocks, including devices, device components, steps or subroutines embodied in software methods, or combinations of hardware and software. Other additional components, different from those shown in the figures and / or described herein, may also be used. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form to avoid obscuring these aspects with unnecessary detail. In other instances, to avoid obscuring these aspects with unnecessary detail, known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail.

[0064] Some aspects can be described as processes or methods in the text, and can be shown as flowcharts, data flow diagrams, structure diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, multiple operations can be executed in parallel or simultaneously. Furthermore, the order of these operations can be rearranged. The process terminates when an operation is completed, but there may be other steps not included in the diagram. A process can correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0065] All or part of the steps in the method described in this invention can be implemented by a computer program, such as a Flash Translation Layer (FTL) in the device or a driver for specific hardware. Furthermore, it can also be implemented in other types of programs as described above. Those skilled in the art can write the methods of the embodiments of this invention into program code, which will not be described further for the sake of brevity. The computer program implementing the method according to the embodiments of this invention can be stored on a suitable computer-readable storage medium or placed on a network server accessible via a network (e.g., the Internet, or other suitable media).

[0066] Computer-readable storage media include volatile and non-volatile, removable and non-removable media that store information, such as computer-readable instructions, data structures, program modules, or other data, using any method or technology. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory, CD-ROM, DVD, Blu-ray disc or other optical storage media, magnetic cards, magnetic tape, hard disks or other magnetic storage media, or other carriers that can be used to store information required and accessed by an instruction execution system. It should be noted that computer-readable storage media can be paper or other suitable media used to print program code, enabling the program code to be accessed electrically, such as by optical scanning of the paper or other media, and then, if necessary, compiled, interpreted, or otherwise processed, and then stored in the memory of an electronic device.

[0067] The program code can be executed by a processor, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such a processor can be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor; however, in alternative instances, the processor may be any conventional processor, controller, microprocessor, or state machine. The processor may be implemented as a combination of multiple computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors paired with a DSP core, or any other similar arrangement. Accordingly, the term "processing unit" as used herein may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or device suitable for implementing the counts described herein.

[0068] The various illustrative logic blocks, modules, engines, circuits, and algorithm steps described in conjunction with the inventive aspects disclosed herein can be implemented as electronic hardware, computer software, firmware, or any combination thereof. To clearly illustrate the interchangeability of hardware and software, the various illustrative components, blocks, modules, engines, circuits, and steps have been generally described above in terms of their functionality. Whether these functions are implemented in hardware or software depends on the specific application scenario and the design constraints imposed on the overall system. Those skilled in the art can implement the described functions in different ways for each specific application scenario, but such implementation decisions should not be construed as departing from the scope of this application.

[0069] Although Figures 1 to 3 It includes the components described above, but does not preclude the use of other additional components to achieve better technical results without violating the spirit of the invention. Furthermore, although... Figure 8 The flowchart describes the steps in a specified order. However, those skilled in the art can modify the order of these steps to achieve the same effect without departing from the spirit of the invention. Therefore, the present invention is not limited to using only the order described above. Furthermore, those skilled in the art can integrate several steps into one step, or perform more steps sequentially or in parallel in addition to these steps, and the present invention should not be limited thereto.

[0070] The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Those skilled in the art can make further improvements and changes on this basis without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the content defined in the claims of this application.

Claims

1. A method for operating a hybrid NAND flash memory cell, executed by a processing unit of a flash memory controller, characterized in that, The method for operating hybrid NAND flash memory cells includes: A flash memory module is connected, wherein the flash memory module includes a first NAND flash memory cell, a second NAND flash memory cell, a third NAND flash memory cell, and a fourth NAND flash memory cell; and User data obtained from the host is written into the flash memory module; The first channel connects the first NAND flash memory cell and the second NAND flash memory cell, and the second channel connects the third NAND flash memory cell and the fourth NAND flash memory cell. The first NAND flash memory cell and the third NAND flash memory cell are powered on by a first chip power-on signal, and the second NAND flash memory cell and the fourth NAND flash memory cell are powered on by a second chip power-on signal. The storage space of the first NAND flash memory cell includes a first portion and a second portion; the storage space of the second NAND flash memory cell includes a third portion and a fourth portion; the storage space of the third NAND flash memory cell includes a fifth portion and a sixth portion; and the storage space of the fourth NAND flash memory cell includes a seventh portion and an eighth portion. The storage space in the first part includes a first partition and a second partition; the storage space in the third part includes a third partition and a fourth partition; the storage space in the fifth part includes a fifth partition and a sixth partition; and the storage space in the seventh part includes a seventh partition and an eighth partition. Specifically, the first partition, the third partition, the fifth partition, and the seventh partition are combined to provide cache space for the second local area and the sixth local area, and the second partition, the fourth partition, the sixth partition, and the eighth partition are combined to provide cache space for the fourth local area and the eighth local area.

2. The method for operating a hybrid NAND flash memory cell as described in claim 1, characterized in that, The first part, the third part, the fifth part and the seventh part are single-layer unit parts, the second part and the sixth part are three-layer unit parts, and the fourth part and the eighth part are four-layer unit parts.

3. The method for operating a hybrid NAND flash memory cell as described in claim 1, characterized in that, include: The superblock management table, which contains multiple records, is read from the system block of the flash memory module. Each record stores information indicating that a particular superblock is provided across the first partition, the fifth partition, the third partition, and the seventh partition; across the second partition, the sixth partition, the fourth partition, and the eighth partition; across the second part and the sixth part; or across the fourth part and the eighth part.

4. The method for operating a hybrid NAND flash memory cell as described in claim 1, characterized in that, include: The hot data associated with the first host write command sent by the host is written in an interleaved manner to the empty pages of the current block across the first partition, the fifth partition, the third partition, and the seventh partition; as well as The cold data associated with the second host write command sent by the host is written in the interleaved manner to the empty pages of the current block across the second partition, the sixth partition, the fourth partition, and the eighth partition.

5. The method of operating a hybrid NAND flash memory cell as described in claim 4, characterized in that, The group number field of the first command UFS protocol information unit corresponding to the first host write command carries an indication of the hot data, and the group number field of the second command UFS protocol information unit corresponding to the second host write command carries an indication of the cold data.

6. The method of operating a hybrid NAND flash memory cell as described in claim 1, characterized in that, include: The user data associated with the first logical address falling within the first or second logical address range, as indicated by the first host write command sent by the host, is written in an interleaved manner to the empty pages of the current block across the first partition, the fifth partition, the third partition, and the seventh partition: and The user data associated with the second logical address that falls within the second logical address range, as indicated by the second host write command sent by the host, is written in an interleaved manner to the empty pages of the current block across the second partition, the sixth partition, the fourth partition, and the eighth partition. The first logical address range and the second logical address range do not overlap.

7. The method of operating a hybrid NAND flash memory cell as described in claim 1, characterized in that, include: The user data of a first length shorter than a threshold, as indicated by the first host write command sent by the host, is written in an interleaved manner to the empty pages of the current block across the first partition, the fifth partition, the third partition, and the seventh partition; as well as The user data of a second length, equal to or longer than the threshold, as indicated by the second host write command sent by the host, is written in the interleaved manner to empty pages of the current block across the second partition, the sixth partition, the fourth partition, and the eighth partition. The threshold is set to 4K, 16K, or 32K bytes.

8. A computer-readable storage medium for storing program code executable by a processing unit, characterized in that, When the program code is executed by the processing unit of the flash memory controller, it implements the method of operating a hybrid NAND flash memory cell as described in any one of claims 1 to 7.

9. An apparatus for operating a hybrid NAND flash memory cell, characterized in that, include: A flash memory interface, coupled to a flash memory module, includes a first NAND flash memory cell, a second NAND flash memory cell, a third NAND flash memory cell, and a fourth NAND flash memory cell. A first channel connects the first NAND flash memory cell and the second NAND flash memory cell, and a second channel connects the third NAND flash memory cell and the fourth NAND flash memory cell. The first and third NAND flash memory cells are powered on by a first chip power-on signal, and the second and fourth NAND flash memory cells are powered on by a second chip power-on signal. The storage space of the first NAND flash memory cell includes a first portion and a second portion, and the storage space of the second NAND flash memory cell includes a third portion and a fourth portion. The storage space of the NAND flash memory cell includes a fifth portion and a sixth portion, and the storage space of the fourth NAND flash memory cell includes a seventh portion and an eighth portion. The first portion includes a first partition and a second partition; the third portion includes a third partition and a fourth partition; the fifth portion includes a fifth partition and a sixth partition; and the seventh portion includes a seventh partition and an eighth partition. The first, third, fifth, and seventh partitions are combined to provide cache space for the second and sixth portions, and the second, fourth, sixth, and eighth partitions are combined to provide cache space for the fourth and eighth portions. The processing unit, coupled to the flash interface, is configured to: connect to the flash module; and write user data obtained from the host to the flash module.

10. The apparatus for operating a hybrid NAND flash memory cell as claimed in claim 9, characterized in that, The first part, the third part, the fifth part and the seventh part are single-layer unit parts, the second part and the sixth part are three-layer unit parts, and the fourth part and the eighth part are four-layer unit parts.

11. The apparatus for operating a hybrid NAND flash memory cell as claimed in claim 9, characterized in that, The processing unit is configured to: read a superblock management table from the system block of the flash memory module via the flash memory interface, which contains multiple records, wherein each record stores information indicating that a specific superblock is provided across the first partition, the fifth partition, the third partition and the seventh partition, across the second partition, the sixth partition, the fourth partition and the eighth partition, across the second part and the sixth part, or across the fourth part and the eighth part.

12. The apparatus for operating a hybrid NAND flash memory cell as claimed in claim 9, characterized in that, The processing unit is configured to: write the hot data associated with the first host write command sent by the host to the empty pages of the current block across the first partition, the fifth partition, the third partition, and the seventh partition in an interleaved manner through the flash memory interface; And write the cold data associated with the second host write command sent by the host to the empty pages of the current block across the second partition, the sixth partition, the fourth partition and the eighth partition in the interleaved manner through the flash interface.

13. The apparatus for operating a hybrid NAND flash memory cell as claimed in claim 12, characterized in that, The group number field of the first command UFS protocol information unit corresponding to the first host write command carries an indication of the hot data, and the group number field of the second command UFS protocol information unit corresponding to the second host write command carries an indication of the cold data.

14. The apparatus for operating a hybrid NAND flash memory cell as claimed in claim 9, characterized in that, The processing unit is configured to: write user data associated with a first logical address falling within a first or second logical address range, as indicated by a first host write command sent by the host, to empty pages of the current block spanning the first partition, the fifth partition, the third partition, and the seventh partition via the flash memory interface in an interleaved manner; and write user data associated with a second logical address falling within a second logical address range, as indicated by a second host write command sent by the host, to empty pages of the current block spanning the second partition, the sixth partition, the fourth partition, and the eighth partition via the flash memory interface in the interleaved manner, wherein the first logical address range and the second logical address range do not overlap.

15. The apparatus for operating a hybrid NAND flash memory cell as claimed in claim 9, characterized in that, The processing unit is configured to: write user data of a first length, shorter than a threshold, as indicated by a first host write command sent by the host to empty pages of the current block spanning the first partition, the fifth partition, the third partition, and the seventh partition via the flash memory interface in an interleaved manner; and write user data of a second length, equal to or longer than the threshold, as indicated by a second host write command sent by the host to empty pages of the current block spanning the second partition, the sixth partition, the fourth partition, and the eighth partition via the flash memory interface in the interleaved manner, wherein the threshold is set to 4K, 16K, or 32K bytes.

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