Memory access method, device, cluster, system, storage medium and program product

Abstract

The application discloses a memory access method, device, cluster, system, storage medium and program product. The method is applied to a first device, the first device reads data of a first memory space shared by a second device using a first virtual address, the first virtual address has a mapping relationship with a first physical address, and the first physical address has a mapping relationship with a remote address. The method comprises the following steps: receiving a first message from the second device; in response to receiving the first message, modifying the mapping relationship between the first virtual address and the first physical address into a mapping relationship between the first virtual address and a second physical address, the second physical address cannot be hit by cache, and modifying the mapping relationship between the first physical address and the remote address into a mapping relationship between the second physical address and the remote address. By modifying the mapping relationship, the first device can load the latest data from the first memory space to the cache, thereby ensuring the cache consistency between the first device and the second device.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a memory access method, device, cluster, system, storage medium, and computer program product. Background Technology

[0002] In the digital age, cluster technology has become a core architecture supporting large-scale computing. A cluster is a system composed of multiple interconnected servers or computers (called compute nodes) that provide high-performance, highly available, and scalable services through resource integration and collaborative work. For example, e-commerce platforms rely on clusters to distribute request pressure and ensure service stability in high-concurrency scenarios. Within a cluster, each compute node has its own processor, memory, and cache. To achieve efficient collaboration, compute nodes within a cluster can overcome the memory size limitations of a single compute node through shared memory mechanisms. Multiple compute nodes can access the same memory space through shared memory, thereby enabling rapid data exchange between compute nodes and improving the overall performance of the cluster.

[0003] In shared memory scenarios, when multiple compute nodes in a cluster simultaneously access or modify data in the same memory space, cache coherence issues may arise between different compute nodes. This is because the local caches of multiple compute nodes may store the same data in the shared memory space. When this data is modified by any one of these compute nodes, the modified data may not be synchronized to the caches of other compute nodes within that cluster. Thus, when other compute nodes read this data, they will read the incorrect, unmodified data from their respective local caches. In existing technologies, before modifying data in the shared memory space, a compute node can notify all other compute nodes that have stored the data in their caches to invalidate the data in their caches. The compute node can then modify the data in the shared memory space after the invalidation operation is complete. However, the compute nodes need a considerable amount of time to wait for the invalidation operation to complete, which can lead to a decrease in the overall performance of the cluster. Summary of the Invention

[0004] This application provides a memory access method to address the problem of inconsistent cached data between different computing nodes when multiple computing nodes in a cluster simultaneously access or modify data in the same memory space in a shared memory scenario. It also reduces the latency for computing nodes to read shared memory. Furthermore, this application provides corresponding devices, clusters, systems, storage media, and computer program products.

[0005] Firstly, this application provides a memory access method applicable to a first device. The first device uses a first virtual address to read data from a first memory space shared by a second device. The first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When the first device's local cache already stores data from the shared first memory space, the first physical address mapped by the first virtual address can be hit by the first device's local cache. Thus, the first device can read data from its local cache using the first physical address. In this case, the mapping between the first physical address and the remote address is not used in this memory access. When the first device's local cache does not store data from the shared first memory space, the first physical address cannot be hit by the first device's local cache. The first device obtains the remote address through the mapping between the first virtual address and the first physical address, and the mapping between the first physical address and the remote address, and reads data from the shared memory space of the second device using the remote address. The first device also receives a first message from the second device, instructing the first device to stop reading data from the first memory space. In response to receiving a first message from the second device, the first device modifies the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the second physical address, which cannot be hit by the local cache of the first device, and modifies the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address.

[0006] By modifying the mapping relationship twice, the second physical address mapped by the first virtual address of the first device cannot hit the corresponding data in the local cache of the first device. Instead, the latest data is loaded into the local cache from the first memory space in the shared memory of the second device through the remote address mapped by the second physical address. This ensures cache consistency between the first device and the second device. Furthermore, the first device does not need an invalid local cache of the first physical address before reading data from the first memory space, thereby reducing the latency of the first device reading data from the first memory space.

[0007] In one possible embodiment, the first message specifically includes the first virtual address, which is used to instruct the first device to stop reading data from the first memory space. The first virtual address may be a virtual address generated based on the physical address of the first device.

[0008] Because there is a mapping relationship between the first virtual address and the first physical address, and a mapping relationship between the first physical address and the remote address, the first device can obtain the remote address through the above mapping relationship. This address can be used to indicate the physical address of the first memory space shared by the second device. After receiving the first message from the second device, the first device can temporarily stop reading data from the first memory space through the first virtual address according to the first message, so as to avoid the problem of reading old data in the first memory space.

[0009] In one possible embodiment, the first message specifically includes the second virtual address, which is used to be mapped to the first virtual address to instruct the first device to stop reading data from the first memory space. The second virtual address may be a virtual address generated based on the physical address of the second device.

[0010] Since the second virtual address can be mapped to the first virtual address, the first device can first obtain the first virtual address through the second virtual address, and then obtain the remote address through the mapping relationship between the first virtual address and the first physical address, and the mapping relationship between the first physical address and the remote address. This address can be used to indicate the physical address of the first memory space shared by the second device. After receiving the first message from the second device, the first device can temporarily stop reading data from the first memory space through the first virtual address according to the first message to avoid the problem of reading old data from the first memory space.

[0011] In one possible embodiment, the method further includes: the first device sending a second message to the second device, the second message indicating that the first device has stopped reading data from the first memory space.

[0012] After receiving a first message from the second device, the first device will temporarily stop reading data from the shared first memory space of the second device. At this time, the first device can send a second message to the second device to indicate that it has stopped reading data from the first memory space. The second device can then write new data to the first memory space based on this second message. Since the first device does not read data from the first memory space when the second device writes new data, the problem of the first device reading old data from the first memory space will not occur.

[0013] In one possible embodiment, the method further includes: the first device receiving a third message from the second device, the third message instructing the first device to begin reading data from the first memory space.

[0014] After the second device writes new data to the first memory space, it can send a third message to the first device, instructing the first device to read the data from the first memory space. Since the second device has already written the new data to the first memory space, the first device can read the latest data from the first memory space and store it in its local cache, thus ensuring cache consistency between the first and second devices.

[0015] In one possible embodiment, the method further includes: in response to receiving a third message from the second device, the first device maps the first virtual address to the second physical address, and maps the second physical address to the remote address, and reads data from the first memory space through the remote address.

[0016] After receiving the first message from the second device, the first device modifies the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the second physical address, and also modifies the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address. Therefore, after receiving the third message from the second device, the first device can map the first virtual address to the second physical address. Furthermore, since the second physical address cannot be hit by the first device's local cache, the first device can map the second address to the remote address and load the latest data from the first memory space in the shared memory of the second device into its local cache through the remote address, thereby ensuring cache consistency between the first and second devices. In addition, the first device does not need an invalid local cache of the first physical address before reading data from the first memory space, thereby reducing the latency of the first device reading data from the first memory space.

[0017] Secondly, this application provides an apparatus that has the functionality to implement the memory access method described in the first aspect above. The apparatus includes one or more modules for implementing the memory access method provided in the first aspect.

[0018] Specifically, the device uses a first virtual address to read data from a first memory space shared by the second device. The first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When the device's local cache already stores data from the first memory space, the first physical address can be hit by the device's local cache, and the device reads data from its local cache using the first physical address. When the device's local cache does not store data from the first memory space, the first physical address cannot be hit by the device's local cache, and the device reads data from the first memory space shared by the second device using the remote address. The device includes: a receiver for receiving a first message from the second device, the first message instructing the device to stop reading data from the first memory space; and a processor for, in response to receiving the first message from the second device, modifying the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the first physical address, preventing the second physical address from being hit by the cache, and modifying the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address.

[0019] In one possible embodiment, the device further includes a transmitter for sending a second message to the second device, the second message indicating that the device has stopped reading data from the first memory space.

[0020] In one possible embodiment, the receiver can also be used to receive a third message from the second device, the third message instructing the device to begin reading data from the first memory space.

[0021] In one possible embodiment, the device further includes a memory management unit, configured to map the first virtual address to the second physical address in response to receiving a third message from the second device.

[0022] In one possible embodiment, the device further includes a decoder for mapping the second physical address to the remote address in response to receiving a third message from the second device.

[0023] In one possible embodiment, the processor is further configured to read data from the first memory space via the remote address in response to receiving a third message from the second device.

[0024] In one possible embodiment, the device has read-only access to the first memory space.

[0025] Thirdly, this application provides a cluster comprising at least one first device and one second device. The first device uses a first virtual address to read data from a first memory space shared by the second device. The first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When the cache stores data from the first memory space, the first physical address can be hit by the cache, and the first device reads the data from the cache through the first physical address. When the cache does not store data from the first memory space, the first physical address cannot be hit by the cache, and the first device reads the data from the first memory space shared by the second device through the remote address. Furthermore, the second device is configured to send a first message to the first device, the first message instructing the first device to stop reading data from the first memory space. The first device is configured to receive the first message, and in response to receiving the first message, modify the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the first physical address, making the second physical address unhappen by the cache, and modify the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address.

[0026] In one possible embodiment, the first device is further configured to send a second message to the second device, the second message indicating that the device has stopped reading data from the first memory space.

[0027] In one possible embodiment, the second device is further configured to receive the second message and, in response to receiving the second message, write data to the first memory space.

[0028] In one possible embodiment, the second device is further configured to send a third message to the first device, the third message instructing the device to begin reading data from the first memory space.

[0029] In one possible embodiment, the first device is further configured to receive the third message, and in response to receiving the third message, map the first virtual address to the second physical address, and map the second physical address to the remote address, and read data from the first memory space through the remote address.

[0030] In one possible embodiment, the first device has read-only access to the first memory space.

[0031] In one possible embodiment, the second device has read or write access to the first memory space.

[0032] Fourthly, this application provides a computing device including a processing unit and a memory, the memory containing instructions, the processing unit executing the steps of the method described in any implementation of the first aspect above through the instructions in the memory.

[0033] Fifthly, this application provides a computing system including at least one first computing device and a second computing device. The first computing device can execute the steps of the method described in any implementation of the first aspect by means of instructions. The second computing device is used to write data to a first memory space shared by the second computing device.

[0034] In a sixth aspect, this application provides a computer-readable storage medium including instructions that, when executed on at least one computing device, cause the computing device to perform the steps of the method described in any implementation of the first aspect above.

[0035] In a seventh aspect, this application provides a computer program product comprising instructions that, when the computer program product is run on at least one computing device, cause the computing device to perform the steps of the method described in any implementation of the first aspect.

[0036] The technical effects achieved by the second, third, fourth, fifth, sixth, and seventh aspects mentioned above are similar to the technical effects achieved by the corresponding technical means in the first aspect, and will not be repeated here. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the structure of an exemplary cluster provided in this application;

[0038] Figure 2 This application provides another exemplary cluster structure diagram;

[0039] Figure 3 A schematic diagram of the structure of yet another exemplary cluster provided in this application;

[0040] Figure 4 A flowchart illustrating a memory access method provided in this application;

[0041] Figure 5 A schematic diagram illustrating the process of compute node 101 accessing the shared memory space of compute node 102;

[0042] Figure 6 A schematic diagram illustrating the process of modifying the first and second mapping tables for compute node 101;

[0043] Figure 7A schematic diagram illustrating the process of writing new data to the local memory space of compute node 102;

[0044] Figure 8 A schematic diagram illustrating the process of compute node 101 accessing the shared memory space of compute node 102 again;

[0045] Figure 9 A schematic diagram of the structure of a computing device provided in this application;

[0046] Figure 10 A schematic diagram of another computing device provided in this application. Detailed Implementation

[0047] A cluster is a system composed of multiple interconnected computing nodes that provide high-performance, high-availability, and scalable services through resource integration and collaborative work. In shared memory scenarios, multiple computing nodes within a cluster may simultaneously access or modify data in the same memory space. Without proper management, this can lead to inconsistencies in the cached data across different computing nodes. To ensure cache consistency across multiple computing nodes in a cluster and reduce latency when reading shared memory, this application provides a memory access method, particularly a shared memory access method, applied between multiple computing nodes. In this method, a second computing node provides its own memory as shared memory, which the first computing node can access. Specifically, the first compute node can use a first virtual address to read data from the first memory space shared by the second compute node. This first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When the first compute node's local cache already stores the data from the first memory space shared by the second compute node, the first physical address mapped by the first virtual address can be hit by the first compute node's local cache. Thus, the first compute node can read the data from its local cache using the first physical address. In this case, the mapping between the first physical address and the remote address is not used in this memory access. When the first compute node's local cache does not store the data from the first memory space shared by the second compute node, the first physical address cannot hit the first compute node's local cache. The first compute node obtains the remote address through the mapping between the first virtual address and the first physical address, and the mapping between the first physical address and the remote address, and reads the data from the shared memory space of the second compute node using the remote address. The first compute node also receives a first message from the second compute node, which instructs the first compute node to stop reading data from the first memory space. In response to receiving the first message, the first compute node modifies the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the second physical address, which cannot be hit by the first compute node's local cache. It also modifies the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address. Through these two modifications, the second physical address mapped by the first virtual address cannot be hit by the corresponding data in the first compute node's local cache. Instead, the latest data is loaded into the local cache from the first memory space in the shared memory of the second compute node via the remote address mapped by the second physical address. This ensures cache consistency between the first and second compute nodes. Furthermore, the first compute node does not need an invalid local cache of the first physical address before reading data from the first memory space, thereby reducing the latency of the first compute node reading data from the first memory space.

[0048] To facilitate understanding of the technical solution of this application, the relevant technical terms involved in this application will be explained below.

[0049] The memory management unit (MMU) is used to process memory access requests generated by the processor, specifically including the translation of virtual addresses to physical addresses.

[0050] A decoder is used to translate memory access requests into bus-based memory access requests, specifically including the translation of physical addresses into virtual addresses for bus-based memory access.

[0051] A bus memory management unit (MMU) is an MMU adapted to a bus that can process bus-based memory access requests, including translating the virtual address (VA) in the request into the physical address (PA) of memory. The bus can be a unified bus (UB or UBUS) or other types of bus; there is no limitation on this.

[0052] A supernode is a collection of multiple compute nodes. A single supernode can include multiple compute nodes of different types. Each supernode's compute nodes can be further divided into multiple work frames, with each compute node belonging to one work frame. In practical applications, each work frame can correspond to a server rack, allowing multiple compute nodes within each work frame to be deployed within the same rack.

[0053] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0054] Figure 1 This is a schematic diagram of the structure of an exemplary cluster provided in this application. Figure 1 As shown, cluster 10 may include multiple compute nodes. Figure 1 The following explanation uses computing nodes 101 to 104 as an example.

[0055] The computing nodes in cluster 10 can be implemented using computing devices that include processors, such as servers. For example, the processor can be a central processing unit (CPU) or an accelerator, such as a deep-learning processing unit (DPU), a data processing unit (DPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), or a tensor processing unit (TPU), or other types of processors. Alternatively, the processor can be any type of processor or any combination thereof, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), or a generic array logic (GAL).

[0056] like Figure 1 As shown, the computing nodes in cluster 10 may include not only processors, but also memory and cache. The memory is used to store data to be processed by the processor. For example, the memory may be implemented using storage media such as dynamic random access memory (DRAM) or static random access memory (SRAM).

[0057] Caching is used to temporarily store data in memory to improve processor access speed. Typically, cache capacity is much smaller than memory, but access speed can approach the processor's frequency. When the data accessed by the processor exists in the cache, a cache hit occurs. The processor can then directly access the data in the cache without needing to access memory, thus significantly improving access speed.

[0058] Multiple compute nodes in cluster 10 can share some or all of their memory. For example... Figure 1As shown, a portion of the memory space in compute node 101 is accessible to compute nodes 102 through 104, and compute node 101 can also access the memory in compute nodes 102 through 104. The memory spaces accessible to other compute nodes from different compute nodes can be the same or different. In practical applications, the memory in compute nodes 101 through 104 can form a memory pool, allowing each compute node to access the memory space within this pool.

[0059] The compute nodes in cluster 10 can be directly connected via the bus, so that memory access requests sent by compute node 101 can be directly transmitted to compute node 102 (or other compute nodes) via the bus.

[0060] The above Figure 1 The cluster 10 shown is merely an example. In other possible implementations, cluster 10 may include a greater number of compute nodes, or may include other types of nodes, such as management nodes (for managing the individual compute nodes).

[0061] or, Figure 1 In the cluster 10 shown, compute nodes 101 to 104 all share a portion of their memory space with other compute nodes. In other possible implementations, some compute nodes in the cluster may share all of their memory space with other compute nodes, or some compute nodes in the cluster may not share their memory space but may access the memory space of other compute nodes, etc.

[0062] Or perhaps, in Figure 1 In the cluster 10 shown, multiple computing nodes are directly connected via a bus to achieve high-speed communication over short distances. And... Figure 2 In the cluster 20 shown, multiple compute nodes can be interconnected through hierarchical switching nodes (e.g., Figure 2 The layer 1 switching nodes 201 and 202, and the layer 2 switching node 203 shown are used to achieve flexible networking among computing nodes.

[0063] Or perhaps, in Figure 3 The cluster 30 shown may include multiple supernodes, and each supernode includes multiple compute nodes, such as... Figure 3 As shown, supernode 1 includes compute nodes 101 to 104, and supernode 2 includes compute nodes 105 to 108. Furthermore, the multiple compute nodes within each supernode can be divided into multiple working frames, such as... Figure 3As shown, compute nodes 101 and 102 in supernode 1 are assigned to work frame 1, and compute nodes 103 and 104 are assigned to work frame 2. Different compute nodes within the same work frame can communicate through switching nodes (such as network interface cards or switching chips) deployed within that work frame, or through an interconnect bus; there is no limitation on this. Figure 3 This example illustrates how multiple compute nodes within the same workframe communicate via a built-in switching node. Alternatively, in... Figure 3 The cluster 30 shown can itself be called a supernode.

[0064] This application does not limit the specific implementation method of the cluster.

[0065] When multiple compute nodes in a cluster access the same memory space, data in that memory space is temporarily stored in the caches of multiple compute nodes. When this data in the memory space is modified, inconsistencies may occur in the caches of the multiple compute nodes. For example, in Figure 1 In the process, compute node 101 reads data from the first memory space shared by compute node 102. This data is temporarily stored in the cache of compute node 101. When compute node 102 modifies the data in the first memory space, the cache of compute node 102 temporarily stores the modified data, while the cache of compute node 101 temporarily stores the data before modification. Therefore, the data in the cache of compute node 101 and the data in the cache of compute node 102 are inconsistent.

[0066] One solution to the above problem is that after compute node 102 modifies the data in the first memory space, compute node 101 invalidates the unmodified data temporarily stored in its cache, then rereads the modified data from compute node 102 and temporarily stores the read data in its cache. At this point, both compute node 101's cache and compute node 102's cache temporarily store the modified data in the first memory space, ensuring data consistency. However, invalidating the data in the cache requires significant time overhead, resulting in substantial latency for compute nodes reading shared memory.

[0067] The embodiments of the memory access method provided in this application are described below.

[0068] Figure 4 This is a flowchart illustrating a memory access method provided in this application. This method can be applied to... Figure 1 Cluster 10 or shown Figure 2 or Figure 3The cluster shown can be applied to other suitable clusters. For ease of explanation, this embodiment uses an example of an application... Figure 1 The following example illustrates how cluster 10 and compute node 101 access the shared memory space of compute node 102.

[0069] in, Figure 4 The memory access method shown may specifically include the following steps:

[0070] S401: Compute node 101 uses the first virtual address to read data from the target memory space shared by compute node 102, and temporarily stores the read data in the cache of compute node 101.

[0071] In this embodiment, during the operation of services, compute node 101 may need to access the shared memory of compute node 102 in cluster 10, such as reading data from the shared memory of compute node 102. In one possible implementation, before accessing the shared memory of compute node 102 across nodes, compute node 101 can first determine the local physical addresses of all memory space it can access (including compute node 101's local memory space and the memory space shared by the other compute nodes). The local physical address is the physical address generated during addressing within the compute node. Thus, compute node 101 can subsequently access its local memory or memory shared by other compute nodes using this local physical address, based on the method of accessing local memory. For example, assuming compute nodes 101 to 104 each provide 1GB of memory space for other compute nodes to access, this memory space available to other compute nodes can constitute a 4GB shared memory pool. Furthermore, compute node 101 also has 2GB of local memory that cannot be accessed by other compute nodes. In this configuration, compute node 101 can access a total of 6GB of memory space and generates a 6GB local physical address within it. Compute node 101 can then access this 6GB of memory space in a manner similar to accessing local memory. Specifically, when the local physical address corresponding to the memory space accessed by compute node 101 is in the range of 0 to 2GB, compute node 101 can directly access its local memory space (i.e., memory space that cannot be accessed by other compute nodes); when the local physical address corresponding to the memory space accessed by compute node 101 is in the range of 2GB to 6GB, compute node 101 can access the memory space in the shared memory pool (i.e., the shared memory space constituted by compute nodes 101 to 104) across compute nodes. Thus, applications running on compute node 101 can access memory as if it were local memory without needing to distinguish between the two.

[0072] In practical applications, the processor in compute node 101 can access memory based on virtual addresses. Therefore, after determining the local physical addresses of all accessible memory spaces, compute node 101 can generate corresponding virtual addresses based on these local physical addresses and provide the generated virtual addresses to the processor. Compute node 101 also contains a first mapping table corresponding to virtual addresses, used to record the mapping relationship between virtual addresses and local physical addresses. When compute node 101 accesses memory based on virtual addresses, it can convert the accessed virtual address to a local physical address through the first mapping table and then access the memory space indicated by the local physical address.

[0073] Meanwhile, since some local physical addresses indicate memory spaces in other computing nodes (not this computing node), computing node 101 also includes a second mapping table corresponding to the local physical address. This table records the mapping relationship between the local physical address and the remote address. The remote address can be used to indicate the physical address of memory space in other computing nodes. The remote address can be the physical address of memory in other computing nodes. Alternatively, the remote address can be the virtual address corresponding to the physical address of memory in other computing nodes. For example, the remote address can be a unified bus address (UBA), etc. This embodiment uses a unified bus address as the remote address for explanation.

[0074] Both remote addresses and the aforementioned local physical addresses can indicate memory spaces shared by multiple computing nodes. Specifically, the local physical address within computing node 101 is the addressing of the memory space accessible to computing node 101 within computing node 101; the remote address is the addressing of the memory space in other computing nodes accessible to computing node 101 outside of computing node 101.

[0075] Through the first mapping table, compute node 101 can translate virtual addresses into local physical addresses, thereby accessing the local memory space of compute node 101. Through the second mapping table, compute node 101 can further translate local physical addresses into remote addresses, thereby accessing the memory space shared by other compute nodes.

[0076] It should be noted that the above example illustrates that the compute node 101 contains two different mapping tables. In other implementations, the compute node 101 may also contain a mapping table to simultaneously record the mapping relationship between the local physical address and the remote address and the mapping relationship between the virtual address and the local physical address.

[0077] Figure 5This is a diagram illustrating how compute node 101 accesses the shared target memory space of compute node 102. (See diagram below.) Figure 5 As shown, during the operation of services, the processor of compute node 101 sends a virtual address N1.VA1 to the MMU. This virtual address can be the starting address within the virtual address range corresponding to the target memory space shared by compute node 102. The MMU converts the virtual address N1.VA1 to the local physical address N1.PA1 through the first mapping table. The local physical address N1.PA1 is the local physical address of the target memory space shared by compute node 102 in compute node 101.

[0078] Then, compute node 101 sends the local physical address N1.PA1 obtained from the above conversion to the decoder, so that the decoder can convert the local physical address N1.PA1 to the remote address UB.VA through the second mapping table. The remote address UB.VA can be used to indicate the physical address of the target memory space shared by compute node 102 in compute node 102.

[0079] It should be noted that in this embodiment, compute node 101 accesses the target memory space shared by compute node 102. Therefore, compute node 101 uses the MMU and decoder to convert the virtual address N1.VA1 to the local physical address N1.PA1 and the local physical address N1.PA1 to the remote address UB.VA, respectively. When compute node 101 accesses local memory, since data in local memory can be directly accessed through the local physical address N1.PA1, compute node 101 can simply use the MMU to convert the virtual address N1.VA1 to the local physical address N1.PA1 and then directly access the corresponding memory space in local memory based on the local physical address N1.PA1, without needing to use the decoder to convert the local physical address N1.PA1 to the remote address UB.VA.

[0080] Furthermore, compute node 101 can generate a memory access request containing the remote address UB.VA and transmit this memory access request to compute node 102 via the bus connecting compute node 101 and compute node 102. In practical applications, the memory access request generated by compute node 101 can also include other types of information, such as an opcode, data length, and a token. The opcode indicates the access operation to the target memory space, such as a read operation or a write operation. The data length indicates the length of data to be read from the target memory space or the length of data to be written to the target memory space. The token is used for security authentication when accessing the target memory space. In addition, when the opcode indicates reading data from the target memory space, the memory access request can also carry the identifier of compute node 101 so that compute node 102 can subsequently return the data read from the target memory space to compute node 101. For example, the identifier of the compute node can be the network address of the compute node, or other information that can be used to identify the compute node. For example, the network address of a compute node can be a Clan network address (CNA) or other types of network addresses; there is no limitation on this. If the identifier of a compute node is represented by a CNA, then a memory access request can carry a source CNA (SCNA) and a destination CNA (DCNA), where the SCNA is the identifier of compute node 101 and the DCNA is the identifier of compute node 102.

[0081] Compute node 102 receives a memory access request from compute node 101. In one possible implementation, compute node 102 can parse the memory access request to obtain information such as the opcode, remote address (and the identifiers of compute node 102, compute node 101, and token). Then, compute node 102 accesses the target memory space in memory based on the remote address.

[0082] like Figure 5As shown, compute node 102 parses the remote address UB.VA from the memory access request and sends this remote address UB.VA to the bus memory management unit, enabling the bus memory management unit to convert the remote address UB.VA into the physical address N2.PA1 of compute node 102. In practical applications, compute node 102 may also contain a third mapping table corresponding to the remote address, used to record the mapping relationship between the remote address and the physical address of compute node 102. The bus memory management unit can use this mapping relationship to convert the remote address UB.VA into the physical address N2.PA1 of compute node 102. Then, compute node 102 accesses the shared target memory space of compute node 102 according to the converted physical address N2.PA1.

[0083] After accessing the target memory space, compute node 102 can return a request response to compute node 101. Specifically, when compute node 101 reads data from the target memory space shared by compute node 102, compute node 102 can generate a request response that includes the data read from the target memory space and may also include the identifier of compute node 101. Compute node 102 can then return the request response to compute node 101 via the bus connecting compute node 101 and compute node 102.

[0084] Compute node 101 receives the request response from compute node 102, parses the data from the target memory space read by compute node 102, and temporarily stores the data in the cache of compute node 101. Thus, when compute node 101 needs to access the same data in the target memory space of compute node 102 later, its cache is hit. Compute node 101 can then directly retrieve the data from its cache without accessing compute node 102, significantly improving its access speed.

[0085] S402: Compute node 102 sends a first message to compute node 101, which instructs compute node 101 to stop reading data in the target memory space shared by compute node 102.

[0086] In this embodiment, during the operation of services, computing node 102 may need to access the target memory space shared by computing node 102, such as writing new data to the target memory space. When computing node 102 writes new data to the target memory space, the data in the target memory space shared by computing node 102 will be modified, and the modified data will be temporarily stored in the cache of computing node 102. At this time, since the cache of computing node 101 temporarily stores the data before modification, the data in the cache of computing node 101 and the data in the cache of computing node 102 are inconsistent. According to the method described in S401, if computing node 101 does not stop reading the data in the target memory space shared by computing node 102, then computing node 101 will directly read the data before modification from its local cache due to a cache hit, resulting in reading incorrect data. Therefore, it is beneficial for computing node 102 to send a message to computing node 101 to instruct computing node 101 to stop reading the data in the target memory space before writing the data to be written.

[0087] It should be noted that the above example is based on computing node 101 reading data from the target memory space shared by computing node 102. In other possible implementations, some or all of the other computing nodes in cluster 10 may also read data from the target memory space shared by computing node 102. In this case, computing node 102 sends a first message to these computing nodes respectively to instruct these nodes to stop reading data from the target memory space shared by computing node 102.

[0088] In one possible implementation, the first message sent by compute node 102 to compute node 101 contains a first virtual address. According to the method described in S401, compute node 101 can use the first virtual address to read data from the cache of compute node 101 in the target memory space. The first message may also include a control field to indicate a stop read operation. In addition, the first message may also include an identifier of compute node 101 to send the first message to compute node 101 via the bus connecting compute node 101 and compute node 102.

[0089] In another possible implementation, the first message sent by compute node 102 to compute node 101 includes a second virtual address, which is a virtual address generated based on the physical address of compute node 102, while the first virtual address is a virtual address generated based on the physical address of compute node 101. Compute node 101 can convert the second virtual address to the first virtual address, thereby instructing compute node 101 to stop using the first virtual address to read data from the target memory space in compute node 101's cache.

[0090] S403: Compute node 101 receives a first message from compute node 102 and obtains a first virtual address through the first message. Compute node 101 can use this first virtual address to read data from its cache in the target memory space. Furthermore, compute node 101 contains a first mapping table recording the mapping relationship between the first virtual address and the first physical address, and a second mapping table recording the mapping relationship between the first physical address and a remote address. In response to receiving the first message, compute node 101 modifies the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and a second physical address, wherein the second physical address cannot be hit by compute node 101's cache, and modifies the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address.

[0091] According to the description in S402, to prevent compute node 101 from reading unmodified data due to a cache hit, compute node 101 temporarily stops reading data in the target memory space shared by compute node 102 after receiving the first message from compute node 102. Compute node 101 can place memory access requests containing the first virtual address into a waiting queue. When compute node 101 can read data in the target memory space shared by compute node 102 again, it can retrieve these memory access requests from the waiting queue and then read the data in the target memory space.

[0092] In one possible implementation, after receiving the first message from computing node 102, computing node 101 also invalidates the data temporarily stored in the target memory space in its cache to resolve the inconsistency between the cached data of computing node 101 and computing node 102. Specifically, the processor of computing node 101 can convert the first virtual address to a first physical address using a second mapping table, and then find the corresponding cache line in the cache of computing node 101 based on the first physical address. These cache lines temporarily store the data in the target memory space. The processor of computing node 101 invalidates these cache lines. Thus, when computing node 101 reads the data in the target memory space shared by computing node 102 again using the first virtual address, the first physical address converted from the first virtual address will not be cache-hit. At this time, computing node 101 rereads the data in the target memory space from computing node 102 according to the method described in S401, and temporarily stores the data in the cache of computing node 101. This data is the data modified by computing node 102. Therefore, both the cache of compute node 101 and the cache of compute node 102 temporarily store the data modified by compute node 102, and the data in their caches is consistent. However, since compute node 101 requires a large time overhead to invalidate the data in its cache, compute node 101 requires a large latency to read the data in the target memory space shared by compute node 102.

[0093] In this embodiment, after receiving the first message from the computing node 102, the computing node 101 modifies the mapping relationship between the first virtual address and the first physical address, as well as the mapping relationship between the first physical address and the remote address, to achieve the same effect as invalidating the cached data, thereby solving the problem of inconsistency between the cached data of the computing node 101 and the cached data of the computing node 102.

[0094] Specifically, compute node 101 selects a second physical address from its local physical address range. The memory space indicated by this second physical address can be free memory space in other compute nodes accessible to compute node 101, or it can be a physical address reserved by compute node 101 for specific scenarios (such as modifying address mappings), or other unused physical addresses. This application does not limit this. Since the cache of compute node 101 temporarily stores data in the memory space based on historical memory access records, and the second physical address is not used for memory access, the cache of compute node 101 will not temporarily store data in the memory space indicated by the second physical address. Therefore, the second physical address is not cache-hung.

[0095] Then, compute node 101 modifies the first mapping table according to the second physical address, changing the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the second physical address. Simultaneously, it modifies the second mapping table according to the second physical address, changing the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address. Thus, when compute node 101 uses the first virtual address to read data from the target memory space shared by compute node 102 again, the second physical address obtained from the first virtual address will not be cached. Furthermore, compute node 101 can also obtain the remote address from the second physical address, thereby reading data from the target memory space from compute node 102 according to the method described in S401. This data is the modified data from compute node 102. It can be seen that in this embodiment, compute node 101 solves the problem of inconsistency between the cached data of compute node 101 and compute node 102. At the same time, compute node 101 avoids directly performing invalid operations on the cached data by modifying the address mapping relationship, reducing the latency of compute node 101 reading the target memory space shared by compute node 102.

[0096] Figure 6 This is a diagram illustrating the modification of the first and second mapping tables for compute node 101. (See diagram below.) Figure 6 As shown, in response to receiving a first message from computing node 102, the processor in computing node 101 modifies the mapping relationship between virtual address N1.VA and physical address N1.PA1 in the first mapping table to a mapping relationship between virtual address N1.VA and physical address N1.PA2, and modifies the mapping relationship between physical address N1.PA1 and remote address UB.VA in the second mapping table to a mapping relationship between physical address N1.PA2 and remote address UB.VA. Thus, when the processor sends virtual address N1.VA to the MMU, the MMU can convert virtual address N1.VA to local physical address N1.PA2 through the first mapping table. Furthermore, the processor can send local physical address N1.PA2 to the decoder, and the decoder can convert local physical address N1.PA2 to remote address UB.VA through the second mapping table. This remote address can be used to read data from the target memory space from computing node 102 according to the method described in S401.

[0097] S404: Compute node 101 sends a second message to compute node 102, the second message indicating that compute node 101 has stopped reading data in the target memory space shared by compute node 102.

[0098] After ceasing to read data from the target memory space shared by compute node 102 and modifying the first and second mapping tables, compute node 101 can send a message to compute node 102, enabling compute node 102 to write new data to the target memory space shared by compute node 102 according to the needs of running services. The second message sent by compute node 101 to compute node 102 includes the identifier of compute node 102, which can be used to send the second message to compute node 102 via the bus connecting compute node 101 and compute node 102. The second message may also include the identifier of compute node 101; in one possible implementation, this second message may be a response message from compute node 101 receiving the first message from compute node 102.

[0099] S405: Compute node 102 receives the second message from compute node 101 and then writes new data to the target memory space shared by compute node 102.

[0100] It should be noted that this embodiment is illustrated by taking the example of computing node 101 reading data from the target memory space shared by computing node 102. In other possible implementations, some or all of the other computing nodes in cluster 10 may also read data from the target memory space shared by computing node 102. In this case, computing node 102 receives a second message from these computing nodes to indicate that these computing nodes have stopped reading data from the target memory space, and then writes new data into the target memory space.

[0101] In one possible implementation, compute node 102 can use a third virtual address to write new data to a target memory space shared by compute node 102. Compute node 102 may include a fourth mapping table to record the mapping relationship between the virtual address and the physical address of compute node 102. Compute node 102 uses the fourth mapping table to convert the third virtual address into a third physical address, which indicates the target memory space in compute node 102. Then, compute node 102 writes new data to the target memory space in its local memory according to the third physical address. After compute node 102 completes the write, the data in the target memory space is modified to the new data.

[0102] Furthermore, compute node 102 can adopt a write-through cache writing strategy, under which compute node 102 also temporarily stores new data in the cache. In one possible implementation, compute node 102 finds the corresponding cache line in its cache based on the third physical address and modifies the data in that cache line to the new data.

[0103] Figure 7 This is a diagram illustrating the writing of new data from compute node 102 to the target memory space. Figure 7 As shown, the processor of compute node 102 sends the virtual address N2.VA1 to the MMU. The MMU converts the virtual address N2.VA1 to the physical address N2.PA1 through the fourth relational mapping table. Then, the processor modifies the data in the memory space indicated by the physical address N2.PA1 to the new data. At the same time, the processor finds the corresponding cache line in the cache according to the physical address N2.PA1 and modifies the data in the cache line to the new data.

[0104] S406: Compute node 102 sends a third message to compute node 101, which instructs compute node 101 to start reading data in the target memory space shared by compute node 102.

[0105] After writing new data to the target memory space, compute node 102 can send a third message to compute node 101, enabling compute node 101 to read the data in the target memory space shared by compute node 102 again according to the needs of running services. In other possible implementations, some or all of the other compute nodes in cluster 10 can also read the data in the target memory space shared by compute node 102 again. In this case, compute node 102 sends a third message to these compute nodes respectively, instructing these nodes to start reading the data in the target memory space shared by compute node 102.

[0106] In one possible implementation, the third message sent by compute node 102 to compute node 101 contains a first virtual address, which compute node 101 can use to read data in the target memory space shared by compute node 102. The third message may also include a control field to indicate the start of the read operation. In addition, the third message may also include an identifier of compute node 101 to send the first message to compute node 101 via the bus connecting compute node 101 and compute node 102.

[0107] In another possible implementation, the third message sent by compute node 102 to compute node 101 contains a second virtual address, which compute node 101 can convert into a first virtual address, thereby instructing compute node 101 to start reading data in the target memory space shared by compute node 102 using the first virtual address.

[0108] S407: Compute node 101 receives a third message from compute node 102, obtains a first virtual address through the third message, and then uses the first virtual address to read the data in the target memory space shared by compute node 102 again. This data is the data modified by compute node 102.

[0109] In response to receiving the third message, compute node 101 reads the data in the target memory space shared by compute node 102 again according to the method described in S401. Since in S403, compute node 101 modified the mapping relationship between the first virtual address and the first physical address in the first mapping table to a mapping relationship between the first virtual address and the second physical address, and modified the mapping relationship between the first physical address and the remote address in the second mapping table to a mapping relationship between the second physical address and the remote address, compute node 101 will not convert the first virtual address to the first physical address, and therefore will not read the data from the target memory space before modification by compute node 102 from the cache. Further, compute node 101 converts the first virtual address to the second physical address through the first mapping table. Since the second physical address cannot be cached, compute node 101 further converts the second physical address to the remote address through the second mapping table, and then reads the modified data from the target memory space of compute node 102 according to the remote address, and temporarily stores the modified data in the cache of compute node 101.

[0110] Figure 8 This diagram illustrates how compute node 101 accesses the shared target memory space of compute node 102 again. It can be seen that compute node 101 avoids the data inconsistency problem caused by cache hits on physical address N1.PA1 by modifying the mapping relationship between virtual address N1.VA1 and physical address N1.PA1 to that between virtual address N1.VA1 and physical address N1.PA2, and modifying the mapping relationship between physical address N1.VA1 and remote address UB.VA to that between physical address N1.VA2 and remote address UB.VA. The data modified by compute node 102 in the target memory space is stored in the cache corresponding to physical address N1.PA2, which is consistent with the cache data corresponding to physical address N2.PA1 in compute node 102.

[0111] In one possible implementation, the cache of compute node 101 can simultaneously store the data in the target memory space before and after the modification by compute node 102. Compute node 101 can check the invalid data in the cache when certain conditions are met (e.g., the processor is idle or a fixed time interval has elapsed) and perform invalidation operations on the data.

[0112] It is worth noting that other reasonable combinations of steps that can be conceived by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0113] This application also provides a computing device. This computing device can achieve the above-described... Figures 1 to 8 The steps implemented by computing node 101 in the memory access method of the illustrated embodiment are as follows: The computing device can access the shared memory of the second device. Specifically, the computing device can use a first virtual address to read data in the first memory space shared by the second device. The first virtual address has a mapping relationship with a first physical address, and the first physical address has a mapping relationship with a remote address. When the local cache of the computing device already stores the data in the first memory space shared by the second device, the first physical address mapped by the first virtual address can be hit by the local cache of the computing device. In this case, the computing device can read the data in the local cache of the computing device through the first physical address. At this time, the mapping relationship between the first physical address and the remote address is not used in this memory access. When the local cache of the computing device does not store the data in the first memory space shared by the second device, the local cache of the computing device cannot be hit by the first physical address. The computing device obtains the remote address through the mapping relationship between the first virtual address and the first physical address and the mapping relationship between the first physical address and the remote address, and reads the data in the first memory space shared by the second device from the shared memory of the second device through the remote address.

[0114] Figure 9 This is a schematic diagram of the structure of a computing device provided in this application. Figure 9 As shown, the computing device includes a receiver 901 for receiving a first message from a second device, the first message instructing the computing device to stop reading data from a first memory space. The computing device also includes a processor 902 for, in response to receiving the first message, modifying the mapping relationship between a first virtual address and a first physical address to a mapping relationship between a first virtual address and a second physical address, wherein the second physical address cannot be hit by the local cache of the first computing node, and modifying the mapping relationship between a first physical address and a remote address to a mapping relationship between a second physical address and a remote address.

[0115] Furthermore, the computing device also includes a transmitter 903 for sending a second message to the second device, the second message indicating that the computing device has stopped reading data from the first memory space. The receiver 901 of the computing device is also used to receive a third message from the second device, the third message indicating that the computing device has begun reading data from the first memory space.

[0116] Furthermore, the computing device also includes a memory management unit 904 and a decoder 905. The memory management unit is used to map a first virtual address to a second physical address in response to receiving a third message, and the decoder 905 is used to map the second virtual address to a remote address in response to receiving a third message. The processor 902 of the computing device is also used to read data from the first memory space via the remote address in response to receiving the third message.

[0117] Figure 10 A schematic diagram of another computing device provided in this application. The computing device includes a processor 1001 and a memory 1002, wherein the memory 1002 is used to store instructions, and the processor 1001 is used to execute the instructions in the memory 1002 to implement the above-described [specification / feature]. Figures 1 to 8 The steps implemented by computing node 101 in the memory access method of the illustrated embodiment.

[0118] This application also provides a cluster system. The cluster includes at least one first device and one second device, wherein the first device can implement the above-described... Figures 1 to 8 The steps implemented by computing node 101 in the memory access method of the illustrated embodiment; the second device can implement the above. Figures 1 to 8 The steps implemented by computing node 102 in the memory access method of the illustrated embodiment. That is, the first device can read data in the memory space shared by the second device.

[0119] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to perform any of the above-described memory access methods.

[0120] This application also provides a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computing device, all or part of the processes or functions described in this application are generated.

[0121] The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, or data center to another website, computer, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means.

[0122] The computer program product can be a software installation package. When any of the aforementioned memory access methods is required, the computer program product can be downloaded and executed on a computing device.

[0123] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive.

[0124] The terminology used in the above embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the embodiments of this application, “one or more” refers to one, two, or more; the character “ / ” generally indicates that the preceding and following objects are in an “or” relationship. In the embodiments of this application, “simultaneously” means within the same time period, including situations where they are at the same moment. The terms “first,” “second,” etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate, and this is merely a way of distinguishing objects with the same attributes in the embodiments of this application.

[0125] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0126] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory access method, characterized in that, The method is applied to a first device, which uses a first virtual address to read data from a first memory space shared by a second device. The first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When a cache stores data from the first memory space, the first physical address can be hit by the cache, and the first device reads data from the cache using the first physical address. When the cache does not store data from the first memory space, the first physical address cannot be hit by the cache, and the first device reads data from the first memory space shared by the second device using the remote address. The method includes: Receive a first message from the second device, the first message instructing the first device to stop reading data from the first memory space; In response to receiving the first message from the second device, the mapping relationship between the first virtual address and the first physical address is modified to the mapping relationship between the first virtual address and the second physical address, the second physical address cannot be hit by the cache, and the mapping relationship between the first physical address and the remote address is modified to the mapping relationship between the second physical address and the remote address.

2. The method according to claim 1, characterized in that, The first message specifically includes the first virtual address, which is used to instruct the first device to stop reading data from the first memory space.

3. The method according to claim 1, characterized in that, The first message specifically includes a second virtual address, which is used to be mapped to the first virtual address to instruct the first device to stop reading data from the first memory space.

4. The method according to any one of claims 1 to 3, characterized in that, The method further includes: A second message is sent to the second device, indicating that the first device has stopped reading data from the first memory space.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: A third message is received from the second device, the third message instructing the first device to begin reading data from the first memory space.

6. The method according to claim 5, characterized in that, The method further includes: In response to receiving a third message from the second device, the first virtual address is mapped to the second physical address, and the second physical address is mapped to the remote address, and data in the first memory space is read through the remote address.

7. A device, characterized in that, The device uses a first virtual address to read data from a first memory space shared by the second device. The first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When the cache stores data from the first memory space, the first physical address can be hit by the cache, and the device reads data from the cache using the first physical address. When the cache does not store data from the first memory space, the first physical address cannot be hit by the cache, and the device reads data from the first memory space shared by the second device using the remote address. The device includes: A receiver is configured to receive a first message from the second device, the first message instructing the device to stop reading data from the first memory space; The processor is configured to, in response to receiving a first message from the second device, modify the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the second physical address, such that the second physical address cannot be cached, and modify the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address.

8. The device according to claim 7, characterized in that, The device also includes: A transmitter is used to send a second message to the second device, the second message indicating that the device has stopped reading data from the first memory space.

9. The device according to claim 7 or 8, characterized in that, The receiver is also used for: A third message is received from the second device, the third message instructing the device to begin reading data from the first memory space.

10. The device according to claim 9, characterized in that, The device also includes: A memory management unit is configured to, in response to receiving a third message from the second device, map the first virtual address to the second physical address.

11. The device according to claim 10, characterized in that, The device also includes: A decoder, configured to map the second physical address to the remote address in response to receiving a third message from the second device.

12. The device according to claim 11, characterized in that, The processor is also used for: In response to receiving a third message from the second device, data in the first memory space is read via the remote address.

13. The device according to any one of claims 7 to 12, characterized in that, The device has read-only access rights to the first memory space.

14. A cluster, characterized in that, The device includes at least one first device and one second device. The first device uses a first virtual address to read data in a first memory space shared by the second device. The first virtual address is mapped to a first physical address, and the first physical address is mapped to a remote address. When the cache stores data in the first memory space, the first physical address can be hit by the cache, and the first device reads the data in the cache through the first physical address. When the cache does not store data in the first memory space, the first physical address cannot be hit by the cache, and the first device reads the data in the first memory space shared by the second device through the remote address. The second device is configured to send a first message to the first device, the first message instructing the first device to stop reading data from the first memory space; The first device is configured to receive the first message, and in response to receiving the first message, modify the mapping relationship between the first virtual address and the first physical address to a mapping relationship between the first virtual address and the second physical address, wherein the second physical address cannot be hit by the cache, and modify the mapping relationship between the first physical address and the remote address to a mapping relationship between the second physical address and the remote address.

15. The cluster according to claim 14, characterized in that, The first device is further used for: A second message is sent to the second device, indicating that the first device has stopped reading data from the first memory space.

16. The cluster according to claim 15, characterized in that, The second device is also used for: Upon receiving the second message, in response to receiving the second message, data is written to the first memory space.

17. The cluster according to claim 16, characterized in that, The second device is also used for: A third message is sent to the first device, the third message instructing the first device to begin reading data from the first memory space.

18. The cluster according to claim 17, characterized in that, The first device is further used for: Upon receiving the third message, in response to receiving the third message, the first virtual address is mapped to the second physical address, and the second physical address is mapped to the remote address, and data in the first memory space is read through the remote address.

19. The cluster according to any one of claims 14 to 18, characterized in that, The first device has read-only access rights to the first memory space.

20. The cluster according to any one of claims 14 to 19, characterized in that, The second device has read or write access to the first memory space.

21. A device, characterized in that, It includes a processor and a memory, the memory containing instructions, the processor executing the steps of the method as described in any one of claims 1 to 6 via the instructions in the memory.

22. A computing system, characterized in that, It includes at least one first computing device and one second computing device, wherein the first computing device can execute the steps of the method as described in any one of claims 1 to 6 by means of instructions; and the second computing device is used to write data to a first memory space shared by the second computing device.

23. A computer-readable storage medium, characterized in that, Includes instructions that, when executed on at least one computing device, cause the computing device to perform the steps of the method as described in any one of claims 1 to 6.

24. A computer program product containing instructions, characterized in that, When it is run on at least one computing device, the computing device performs the steps of the method as described in any one of claims 1 to 6.

Images