Data processing apparatus, method, storage medium and electronic device

Abstract

Embodiments of the present disclosure disclose a data processing apparatus, method, storage medium and electronic device. The data processing apparatus comprises: a cache circuit configured to store a plurality of data elements of an input array; an interpolation operation circuit configured to perform an interpolation operation on two adjacent data elements stored in the cache circuit to obtain interpolation data; the interpolation operation circuit comprises an addition calculation sub-circuit and a halving calculation sub-circuit; the addition calculation sub-circuit is configured to perform an addition operation on the two adjacent data elements stored in the cache circuit to obtain first sum data; the halving calculation sub-circuit is configured to perform a halving operation on the first sum data to obtain the interpolation data; the cache circuit is further configured to store the interpolation data corresponding to the adjacent data element pair in a free storage position in the cache circuit; and an output array is determined based on the interpolation data. The data processing apparatus can reduce the consumption of computing resources.

Description

Technical Field

[0001] This disclosure relates to the field of data processing, and more particularly to a data processing apparatus, method, storage medium, and electronic device. Background Technology

[0002] In related technologies, array resizing operations are usually implemented using interpolation algorithms. Resizing a large array once requires millions or even tens of millions of operations, which consumes a lot of computing resources. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a data processing apparatus, method, storage medium, and electronic device to reduce the consumption of computing resources.

[0004] A first aspect of this disclosure provides a data processing apparatus, comprising: A buffer circuit is configured to store multiple data elements of the input array; The interpolation circuit is configured to perform interpolation operations on two adjacent data elements stored in the cache circuit to obtain interpolated data; The interpolation circuit includes an addition sub-circuit and a subtraction sub-circuit; The addition subcircuit is configured to perform an addition operation on two adjacent data elements stored in the cache circuit to obtain the first sum data; The halving calculation subcircuit is configured to perform a halving operation on the first summed data to obtain interpolated data; The cache circuit is also configured to store interpolated data corresponding to adjacent data elements in free storage locations within the cache circuit; the output array is determined based on the interpolated data.

[0005] A second aspect of this disclosure provides a data processing method, comprising: The buffer circuit stores multiple data elements of the input array; Perform an addition operation on two adjacent data elements stored in the cache circuit to obtain the first sum data; Perform a halving operation on the first summed data to obtain the interpolated data; The interpolated data corresponding to adjacent data elements is stored in the free storage location of the cache circuit; The output array is determined based on the interpolated data.

[0006] A third aspect of this disclosure provides a computer-readable storage medium storing a computer program that is executed by a processor to perform the data processing method proposed in the second aspect of this disclosure.

[0007] A fourth aspect of this disclosure provides an electronic device comprising: processor; Memory used to store processor-executable instructions; A processor is configured to read executable instructions from memory and execute the instructions to implement the data processing method proposed in the second aspect of this disclosure.

[0008] The fifth aspect of the disclosure provides a computer program product that, when executed by an instruction processor in the computer program product, performs the data processing method proposed in the second aspect of the disclosure.

[0009] The data processing apparatus provided in this disclosure includes a cache circuit and an interpolation circuit. The interpolation circuit includes an addition subcircuit and a halving subcircuit. The addition subcircuit performs an addition operation on two adjacent data elements stored in the cache circuit to obtain a first sum data. The halving subcircuit performs a halving operation on the first sum data to obtain interpolated data. This "addition + halving" operation replaces the multiplication operation in related technologies, thereby reducing the computational overhead of a single interpolation operation. Furthermore, storing the interpolated data in an idle storage location within the cache circuit allows the interpolated data and the original data to be stored in the same cache circuit, eliminating the need to allocate separate cache space for the interpolated data and reducing the requirement for cache capacity. Therefore, the data processing apparatus provided in this disclosure reduces the consumption of corresponding computing resources from both computational and storage perspectives. Attached Figure Description

[0010] Figure 1 This is a first structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 2 This is a second structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 3 This is a third structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 4 This is a fourth structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 5 This is a schematic diagram illustrating the principle of a cache circuit storing input arrays and interpolation data according to an embodiment of this disclosure; Figure 6 This is a fifth structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 7 This is a sixth structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 8 This is a seventh structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 9 This is an eighth structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 10 This is a ninth structural schematic diagram of a data processing apparatus provided in one embodiment of the present disclosure; Figure 11 This is a schematic diagram illustrating the principle of a cache circuit storing an input array according to an embodiment of this disclosure; Figure 12 This is a schematic diagram illustrating the principle of an interpolation circuit for calculating row interpolation data according to an embodiment of this disclosure; Figure 13 This is a schematic diagram illustrating the principle of an interpolation circuit for calculating column interpolation data according to an embodiment of this disclosure; Figure 14 This is a schematic flowchart of a data processing method provided in one embodiment of the present disclosure; Figure 15 This is a schematic diagram of the structure of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0011] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0012] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0013] Application Overview In related technologies, array resizing operations are typically implemented using interpolation algorithms. Taking bilinear interpolation as an example, a weighted average of the four known data elements surrounding the interpolation position is needed to calculate the new pixel value. The specific calculation process is as follows: Vertical interpolation: interp_y0=Q 00 ×(1-u)+Q 10 ×u; interp_y1=Q 01 ×(1-u)+Q 11 ×u; Horizontal interpolation: P=interp_y0×(1-v)+interp_y1×v; Among them, Q 00 Q 01 Q 10 and Q 11Given four known data elements, u is the weight in the vertical direction, V is the weight in the horizontal direction, interp_y0 and interp_y1 are the edge interpolation data, and P is the center interpolation data.

[0014] As can be seen from the above calculation process of the central interpolation data P, each calculation of an interpolation data requires 6 multiplication operations and 5 addition operations.

[0015] Taking a 64×64×256 array enlarged to 128×128×256 as an example, the output array contains 128×128×256 data elements. If the bilinear interpolation algorithm is used, the number of multiplication operations required for a single adjustment is approximately 63×63×256×6, or about 6 million multiplication operations, and the number of addition operations is approximately 63×63×256×5, or about 5 million addition operations, which consumes a large amount of computing resources.

[0016] To address the aforementioned technical problems, the data processing apparatus provided in this disclosure includes a cache circuit and an interpolation circuit. The hardware structure of the interpolation circuit is improved, comprising an addition subcircuit and a halving subcircuit. The addition subcircuit performs an addition operation on two adjacent data elements stored in the cache circuit to obtain a first summed data. The halving subcircuit performs a halving operation on the first summed data to obtain interpolated data. This "addition + halving" operation replaces the multiplication operation in related technologies, thereby reducing the computational overhead of a single interpolation operation. Furthermore, the interpolated data is stored in an idle storage location within the cache circuit, allowing the interpolated data and the original data to be stored in the same cache circuit, eliminating the need to allocate separate cache space for the interpolated data and reducing the requirement for cache capacity. Thus, the data processing apparatus provided in this disclosure reduces the consumption of corresponding computing resources from both computational and storage perspectives.

[0017] Exemplary device Figure 1 This is a schematic diagram of the structure of a data processing apparatus provided in an exemplary embodiment of this disclosure. The data processing apparatus 100 provided in this embodiment includes, but is not limited to, hardware on an electronic device, hardware on a system-on-a-chip (SoC), or hardware on a neural network processor, and may also include an SoC or a neural network processor. The electronic device includes, but is not limited to, in-vehicle computing platforms (or in-vehicle terminals), embody intelligent agents, mobile phones, tablets, wearable devices, etc., and the SoC includes, but is not limited to, intelligent driving SoCs, intelligent cockpit SoCs, cockpit-driver integrated SoCs, and SoCs in other electronic devices. Figure 1 As shown, the data processing device 100 includes a cache circuit 10 and an interpolation operation circuit 20.

[0018] The cache circuit 10 is configured to store multiple data elements of the input array.

[0019] The interpolation circuit 20 is configured to perform interpolation operations on two adjacent data elements stored in the cache circuit 10 to obtain interpolated data.

[0020] The interpolation operation circuit 20 includes an addition calculation sub-circuit 21 and a halving calculation sub-circuit 22.

[0021] The addition calculation sub-circuit 21 is configured to perform an addition operation on two adjacent data elements stored in the cache circuit 10 to obtain the first sum data.

[0022] The halving calculation sub-circuit 22 is configured to perform a halving operation on the first summed data to obtain interpolated data.

[0023] The cache circuit 10 is also configured to store interpolated data corresponding to adjacent data elements in free storage locations within the cache circuit 10; and to determine the output array based on the interpolated data.

[0024] In this embodiment, the buffer circuit 10 is electrically connected to the interpolation circuit 20. After the buffer circuit 10 stores multiple data elements of the input array, the interpolation circuit 20 obtains at least a portion of the data elements from the input array from the buffer circuit 10, performs interpolation operations on two adjacent data elements in the buffer circuit 10 to obtain interpolated data, and outputs the interpolated data to the buffer circuit 10. The buffer circuit 10 stores the interpolated data in a free storage location within the buffer circuit 10.

[0025] The interpolation circuit 20 includes an addition subcircuit 21 and a halving subcircuit 22. The buffer circuit 10 is electrically connected to both the addition subcircuit 21 and the halving subcircuit 22. The addition subcircuit 21 is electrically connected to the halving subcircuit 22. The addition subcircuit 21 obtains at least a portion of the data elements from the input array in the buffer circuit 10, performs an addition operation on two adjacent data elements in the buffer circuit 10 to obtain a first sum, and outputs the first sum to the halving subcircuit 22. The halving subcircuit 22 performs a halving operation on the first sum to obtain interpolated data, which is the average of two adjacent data elements. The halving subcircuit 22 outputs the interpolated data to the buffer circuit 10, and the buffer circuit 10 stores the interpolated data in a free storage location within the buffer circuit 10.

[0026] The addition calculation subcircuit 21 includes devices with addition functionality known to those skilled in the art. For example, the addition calculation subcircuit 21 includes multiple parallel adders.

[0027] The halving calculation subcircuit 22 performs a halving operation on the first sum of data output by the addition calculation subcircuit, that is, reduces the value of the first sum of data to half of its original value. The halving operation performed by the halving calculation subcircuit 22 is implemented, for example, but not limited to, through wire shifting or exponent adjustment, and does not rely on multipliers or dividers at the hardware level, thus incurring a small computational overhead when performing the halving operation.

[0028] The cache circuit 10 has a free storage location, also known as a free storage unit, for storing interpolation data. The cache circuit 10 stores the free storage location and the data elements in the input array in the same storage device. After receiving the interpolation data output by the halving calculation sub-circuit 22, the interpolation data is stored in the free storage location. There is no need to allocate a separate cache space for the interpolation data, which helps to reduce the requirement for cache capacity.

[0029] The data processing apparatus provided in this disclosure improves the hardware structure of the interpolation circuit 20. The improved interpolation circuit 20 includes an addition subcircuit 21 and a halving subcircuit 22. The addition subcircuit 21 performs an addition operation on two adjacent data elements stored in the cache circuit 10 to obtain a first sum data. The halving subcircuit 22 performs a halving operation on the first sum data to obtain interpolated data. The multiplication operation in related technologies is replaced by "addition operation + halving operation", thereby reducing the computational overhead of a single interpolation operation. In addition, the interpolated data is stored in an idle storage location in the cache circuit 10, so that the interpolated data and the original data elements are stored in the same cache circuit, eliminating the need to allocate separate cache space for the interpolated data and reducing the requirement for cache capacity. Thus, the data processing apparatus provided in this disclosure reduces the consumption of corresponding computing resources from both computation and storage perspectives.

[0030] As one implementation method, such as Figure 2 As shown, the halving calculation sub-circuit 22 includes an integer data halving sub-circuit 221, which is configured to: when the data element is integer data, perform a right shift operation on the first summed data by one bit to obtain the second summed data; and determine the interpolation data based on the second summed data.

[0031] In this embodiment, for integer data, the integer data halving sub-circuit 221 performs a right shift operation on the first summed data by one bit. Since the integer data is represented in binary, the data obtained after right shifting by one bit is half of the first summed data, thus halving the first summed data. This disclosure obtains interpolated data by performing a shift operation on the first summed data using the integer data halving sub-circuit. The computational overhead of the shift operation is less than that of the multiplication operation, which helps reduce the computational overhead of a single interpolation operation.

[0032] The operation data output by the addition calculation subcircuit 21 and the subtraction calculation subcircuit 22 does not change the data type of the data elements. The data elements in the input array are integer data. The first sum data output by the addition calculation subcircuit 21 and the interpolation data output by the integer data subtraction subcircuit 221 are also integer data.

[0033] If the first sum is even, the second sum will be an integer, and the second sum can be used as interpolation data.

[0034] If the first sum is odd, the resulting second sum is not an integer. In this case, the rounded second sum can be used as the interpolated data. The rounding methods for the second sum in this disclosure include, but are not limited to, rounding to the nearest even number, rounding down, rounding up, and rounding towards zero.

[0035] As an example, one implementation of the integer data halving sub-circuit 221 is a shifter. The shifter performs a right shift operation on the first summed data by one bit, which can still achieve the halving effect without using a multiplier. Moreover, the shifter has a smaller computational overhead compared to a multiplier.

[0036] As an example, another implementation of the integer data halving subcircuit 221 is a hardware connection, where the j-th bit of the input is connected to the (j-1)-th bit of the output. The right shift operation is completed solely through metal layer traces, without the need for logic gate circuits. Compared to a multiplier, the hardware-connected integer data halving subcircuit 221 has lower computational and hardware area overhead.

[0037] As one implementation method, such as Figure 3 As shown, the integer data halving sub-circuit 221 is specifically configured to: determine the second summed data as interpolated data when the least significant bit of the first summed data is 0; or, perform an increment operation on the second summed data to obtain interpolated data when the least significant bit of the first summed data is 1.

[0038] In this embodiment, the least significant bit of the first sum is 0, indicating that the first sum is an even number. The second sum obtained by halving it is also an integer. There is no need to perform a rounding operation on the second sum. The second sum can be directly determined as the interpolation data.

[0039] As an example, the first sum of data output by the addition calculation sub-circuit 21 is the Arabic numeral "6", which is represented as "110" in binary. After performing a right shift operation, the second sum of data is "11", which corresponds to the Arabic numeral "3". That is, the second sum of data is half of the first sum of data, thus halving the first sum of data. The second sum of data is an integer, and the second sum of data is determined as interpolation data.

[0040] The least significant bit of the first sum is 1, indicating that the first sum is an odd number. The data obtained by halving it contains a decimal. The addition calculation sub-circuit 21 truncates it and outputs the integer part as the second sum. By performing an increment operation on the second sum, it is equivalent to performing a rounding operation on the halved first sum, thereby compensating for the truncation error of the right shift operation and balancing the requirements of processing accuracy and low power consumption.

[0041] As an example, the first summation data output by the addition calculation sub-circuit 21 is the Arabic numeral "5", half of which is "2.5", and its round-up is "3"; "5" is represented as "101" in binary. After performing a right shift operation on it, the second summation data is "10", and the corresponding Arabic numeral is "2". The data after adding 1 to the second summation data is determined as the interpolation data.

[0042] As one implementation method, such as Figure 4 As shown, the halving calculation sub-circuit 22 includes a floating-point data halving sub-circuit 222; the floating-point data halving sub-circuit 222 is configured to perform a decrement operation on the exponent field of the first summed data when the data element is of floating-point data and the value of the exponent field of the first summed data is greater than 1, to obtain the third summed data; and based on the third summed data, determine the interpolation data.

[0043] As one implementation method, such as Figure 4 As shown, the floating-point data halving sub-circuit 222 is configured to: when the data type of the data element is floating-point data and the value of the exponent field of the data element is less than or equal to 1, perform a right shift operation on the mantissa field of the first summed data by one bit to obtain the fourth summed data; and determine the interpolation data based on the fourth summed data.

[0044] As one implementation method, such as Figure 4 As shown, the floating-point data halving sub-circuit 222 is configured as follows: If the data element is of floating-point type and the exponent field of the first sum is greater than 1, the exponent field of the first sum is decremented by 1 to obtain the third sum; based on the third sum, the interpolation data is determined; and if the data element is of floating-point type and the exponent field of the data element is less than or equal to 1, the mantissa field of the first sum is shifted right by one bit to obtain the fourth sum; based on the fourth sum, the interpolation data is determined.

[0045] In this embodiment, the floating-point data includes a sign field, an exponent field, and a mantissa field. The first summation data (floating-point data) is expressed as: (±1)×2 E-Bias ×(1.M). The sign field is not affected by the numerical value of the exponent field and is directly preserved.

[0046] This disclosure involves subtracting 1 from the exponent field E of the first summed data when the value is greater than 1, resulting in the expression for the third summed data as: (±1)×2 E-1-Bias ×(1.M), by performing a subtraction operation to halve the first sum of data, helps to reduce the computational overhead of a single interpolation operation and preserves the precision of the mantissa of the data elements.

[0047] As an example, with an exponent field E=1 and a bias value Bias=127, the first summation data is represented as: (±1)×2 1-127 ×(1.M)=2 -126 If we continue to subtract 1 from the value of the exponent E, the result becomes (±1)×2. -127 ×(1.M), which corresponds to a value of 0 in the exponent field, represents a denormalized number in IEEE 754, causing a sudden change in the representation format of data from normalized to denormalized numbers.

[0048] As an example, with the exponent field E=0 and the bias value Bias=127, the first summation data is represented as: (±1)×2 0-127 ×(1.M)=2 -127 If the value of the exponent field E is decremented by 1 if ×(1.M), an exponent underflow will occur, and the calculation result will be an error.

[0049] This disclosure performs a right shift operation on the mantissa field of the first summed data by one bit when the value of the exponent field E is less than or equal to 1, and no longer performs a decrement operation on the value of the exponent field E, thereby reducing the risk of data loss due to exponent field underflow.

[0050] The data processing apparatus provided in this disclosure does not require calling a complex division operation unit, which helps to reduce hardware area and computational overhead. It also covers the halving scenario of unconventional formatted numbers, reducing the risk of data loss due to exponent field underflow.

[0051] It should be noted that the floating-point data halving subcircuit 222 performs a right shift operation on the mantissa field of the first summed data by one bit. Its hardware implementation is the same as the right shift operation in the aforementioned integer data halving subcircuit 221, for example, through a shifter or hardware connection remapping. The floating-point data halving subcircuit 222 and the integer data halving subcircuit 221 can share some hardware connections, and path selection is only performed through data type identifiers, further reducing the overall circuit area.

[0052] As one implementation, the cache circuit is specifically configured to store multiple data elements of the input array in multiple storage rows and multiple storage columns of the cache circuit according to the method of interleaved storage rows and interleaved storage columns, so that at least one free storage location is formed between adjacent data elements.

[0053] The addition calculation sub-circuit is configured to: perform an addition operation on at least one pair of adjacent data elements stored in the cache circuit in the row direction to obtain the first row sum data corresponding to the row direction; and perform an addition operation on at least one pair of adjacent data elements stored in the cache circuit in the column direction to obtain the first column sum data corresponding to the column direction; the first row sum data includes at least one first sum data; the first column sum data includes at least one first sum data.

[0054] The halving calculation sub-circuit is configured to: perform a halving operation on each of the first sums in the first row to obtain row interpolated data; and perform a halving operation on each of the first sums in the first column to obtain column interpolated data.

[0055] The cache circuit is also configured to: store row interpolation data corresponding to at least one pair of adjacent data elements in a free storage location between at least one pair of adjacent data elements in the row direction of the cache circuit; and store column interpolation data corresponding to at least one pair of adjacent data elements in a free storage location between at least one pair of adjacent data elements in the column direction of the cache circuit; and determine the output array based on the row interpolation data and the column interpolation data.

[0056] In this embodiment, before being stored in the cache circuit, the data elements in the input array are arranged row by row and column by column in the storage circuit. There may be no free storage space between adjacent data elements in the row direction and between adjacent data elements in the column direction. When storing multiple data elements in the input array, the cache circuit stores them in a way that alternating rows and columns, so that at least one free storage space is formed between adjacent data elements in the input array in the row direction and between adjacent elements in the column direction.

[0057] The cache circuit includes multiple storage rows and multiple storage columns. Each storage row extends horizontally, and each storage column extends vertically. The intersection of a storage row and a storage column corresponds to a storage location (also called a "storage cell"). Multiple storage locations are arranged horizontally to form storage rows and vertically to form storage columns. The multiple storage rows and multiple storage columns together form the storage array in the cache circuit.

[0058] The storage circuit includes data storage devices located outside the data processing device, used to store the complete input and output arrays. During data processing, data elements in the input array are first loaded from the storage circuit to the buffer circuit; after interpolation operations are completed, the buffer circuit writes the output array back to the storage circuit.

[0059] like Figure 5 As shown in the first operation, the buffer circuit stores multiple data elements (represented by solid white circles) from the input array in multiple storage rows and columns of the buffer circuit according to the method of storing rows and columns at intervals. Adjacent data elements form a free storage location (represented by dashed white circles) between the row direction H and the column direction W. These free storage locations are used to store row interpolation data and column interpolation data. Taking a 2×4 dimension input array as an example, it includes 2×4 data elements, that is, the input array includes two rows, each with four data elements. The buffer circuit stores the four data elements of the first row of the input array in columns W0, W2, W4, and W6 of row H0, and the four data elements of the second row of the input array in columns W0, W2, W4, and W6 of row H2, respectively. Multiple free storage locations are set in rows H1, columns W1, W3, and W5, so that originally adjacent data elements in the input array form a free storage location.

[0060] The addition subcircuit performs an addition operation on at least one pair of adjacent data elements stored in the buffer circuit in the row direction H to obtain the first row sum data corresponding to row direction H, and outputs the first row sum data to the halving subcircuit. The halving subcircuit performs a halving operation on each first sum data in the first row sum data to obtain row interpolation data, and outputs the row interpolation data to the buffer circuit.

[0061] like Figure 5 As shown in the second operation, the caching circuit stores the row interpolation data (represented by gray solid circles) in the free storage locations between adjacent data elements in the row. Continuing the previous example, the interpolation operation circuit performs the above addition and halving operations on the four data elements in row H0 and the four data elements in row H2 respectively, to obtain four row interpolation data; the caching circuit stores these four row interpolation data in the four free storage locations in columns W0, W2, W4 and W6 of row H1 respectively, realizing row interpolation between adjacent data elements.

[0062] The addition subcircuit performs an addition operation on at least one pair of adjacent data elements stored in the column direction W in the cache circuit to obtain the first column sum data corresponding to column direction W, and outputs the first column sum data to the halving subcircuit. The halving subcircuit performs a halving operation on each first sum data in the first column sum data to obtain column interpolation data, and outputs the column interpolation data to the cache circuit.

[0063] like Figure 5 As shown in the third operation, the caching circuit stores the column interpolation data (still represented by gray solid circles) in the free storage locations between adjacent data elements in the column. Continuing the previous example, the interpolation circuit performs the above addition and halving operations on the three data elements of column W0 (including the row interpolation data calculated in the previous step) and the three data elements of column W2, respectively, to obtain three column interpolation data. Similarly, the above addition and halving operations are performed on the three data elements of column W2 and the three data elements of column W4, and the three data elements of column W4 and the three data elements of column W6, respectively, to obtain column interpolation data. The caching circuit stores these column interpolation data in the free storage locations of columns W1, W3, and W5, respectively, to achieve column interpolation between adjacent data elements.

[0064] It should be noted that, Figure 5 This illustration merely demonstrates that the data processing apparatus performs row interpolation operations on data elements first, followed by column interpolation operations, but does not constitute a limitation on the data processing apparatus provided in the embodiments of this disclosure. In other embodiments, column interpolation operations may be performed on data elements first, followed by row interpolation operations, or column interpolation operations and row interpolation operations may be performed simultaneously on different groups of data elements; this disclosure does not limit this.

[0065] This disclosure uses a cache circuit to store the input array by storing rows and columns at intervals, and stores row interpolation data and column interpolation data in the free storage positions between adjacent data elements. This achieves the fusion storage of the original data elements and the interpolation data, eliminating the need to allocate separate storage space for intermediate calculation results (i.e., interpolation data) and reducing address mapping overhead. At the same time, the cache circuit can directly determine the output array based on the interpolation data without additional data moving operations to reorganize the data to output the array, further reducing computational overhead and consumption of hardware resources.

[0066] As one implementation method, such as Figure 6 As shown, the data processing device also includes a controller 30, which is configured to: The system receives and parses data processing configuration instructions to obtain configuration instruction information. The configuration instruction information includes at least one of the following: the starting address of the input array in the storage circuit 200, the dimension information of the input array, and the data bit width information of the data elements. Based on the starting address, dimension information, and data bit width information, a read / write access request is sent to the storage circuit 200 to read multiple data elements from the input array.

[0067] In this embodiment, the data processing configuration instructions come from the upper-level control system of the data processing device.

[0068] The input array can be stored, for example, in a storage circuit 200 located outside the data processing device. The starting address of the input array in the storage circuit 200 includes the input base address of the input array, which is used to locate the starting position of the input array in the storage circuit 200 so that the source of the read data elements is correct.

[0069] The dimension information of the input array refers to the number of rows, columns, and channels of the input array, which gives us the data size of the input array, that is, the number of data elements in the input array and the arrangement of the data elements.

[0070] The bit width information of a data element refers to the number of bytes occupied by each data element, used to accurately calculate the read and write addresses. Combined with the number of columns in the input array, the number of bytes occupied by a row of data can be obtained, which is called the "row stride". For example, integer data elements occupy 2 bytes, and floating-point data elements occupy 4 bytes.

[0071] The controller 30 is electrically connected to the storage circuit 200 and the cache circuit 10 respectively. The cache circuit 10 reads the input array in the storage circuit 200 through the controller 30 and writes the output array back to the storage circuit 200 through the controller 30.

[0072] The controller 30 calculates the read / write access address of the input array based on the starting address, dimension information, and bit width information of the data elements, and generates corresponding read / write access requests based on the read / write access address. This enables the controller 30 to accurately retrieve data elements from the storage circuit 200 and store the retrieved data elements in the cache circuit 10, thereby providing an effective data source for the interpolation circuit 20.

[0073] In other implementations, the instruction configuration information also includes the data type of the data element and the target scaling parameters, which include the target magnification factor and the dimension information of the magnified target.

[0074] As one implementation method, such as Figure 7 As shown, the controller includes a control signal sending unit 31, which is configured to: Send a first write enable signal to the cache circuit 10 to control the cache circuit 10 to write multiple data elements from the input array into the cache circuit 10; Send an operation enable signal and a data selection signal to the interpolation operation circuit 20 to control the addition operation sub-circuit 21 to perform an addition operation on two adjacent data elements stored in the cache circuit 10 to obtain the first sum data; and control the halving operation sub-circuit 22 to perform a halving operation on the first sum data to obtain the interpolated data; A second write enable signal is sent to the cache circuit 10 to store the interpolated data corresponding to two adjacent data elements in a free storage location in the cache circuit; the output array is determined based on the interpolated data.

[0075] In this embodiment, the first enable signal is used to control the buffer circuit 10 to write multiple data elements of the input array into the buffer circuit 10. The second enable signal is used to control the buffer circuit to write interpolated data into the buffer circuit 10. The operation enable signal is used to control the interpolation operation circuit 20 to perform data operations, and the data selection signal is used to control the interpolation operation circuit 20 to switch the data source between the row direction and the column direction as needed, thereby realizing the switching between row interpolation operation and column interpolation operation.

[0076] The control signal sending unit 31 is electrically connected to the buffer circuit 10 and the interpolation operation circuit 20, respectively.

[0077] The controller 30 sends a first write enable signal to the cache circuit 10 through the control signal sending unit 31 to control the cache circuit 10 to perform a data write operation and store multiple data elements read by the controller 30 from the storage circuit 200 into the cache circuit 10.

[0078] The control signal sending unit 31 also sends an operation enable signal and a data selection signal to the interpolation operation circuit 20 to control the interpolation operation circuit 20 to perform addition and halving operations on two adjacent data elements stored in the buffer circuit 10 to obtain interpolated data.

[0079] The control signal sending unit 31 also sends a second write enable signal to the cache circuit 10 to control the cache circuit 10 to perform a data write operation and store the interpolation data output by the halving calculation sub-circuit 22 into the corresponding free storage location in the cache circuit 10.

[0080] As an example, in response to a first write enable signal, cache circuit 10 writes multiple data elements from the input array into the cache circuit in an alternating row and column manner, reserving multiple free storage locations for interpolated data. In response to a second write enable signal, cache circuit 10 stores row interpolated data into free storage locations in the corresponding storage rows and stores column interpolated data into free storage locations in the corresponding storage columns.

[0081] This disclosure achieves complete data flow control from data loading and interpolation calculation to interpolation data storage by coordinating the timing of the aforementioned control signals. This enables each circuit module to work together efficiently, reducing computational and storage overhead while improving the correctness and consistency of the data processing flow, thereby completing data processing operations with lower hardware overhead.

[0082] As one implementation method, such as Figure 8 As shown, the control signal sending unit 31 is specifically configured as follows: Send a first write enable signal to the cache circuit 10 to control the cache circuit 10 to write multiple data elements in the input array into multiple storage rows and multiple storage columns of the cache circuit 10 in an alternating storage row and alternating storage column manner; When the number of data elements stored in the cache circuit 10 reaches the first preset threshold, a read enable signal is sent to the cache circuit 10 to control the cache circuit 10 to output data elements to the interpolation circuit 20. An operation enable signal and a data selection signal are sent to the interpolation operation circuit 20 to control the addition calculation subcircuit 21 to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit 10 in the row direction to obtain the first row sum data corresponding to the row direction; and to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit 10 in the column direction to obtain the first column sum data corresponding to the column direction; and to control the halving calculation subcircuit 22 to perform halving operations on each first sum data in the first row sum data to obtain row interpolation data, and to perform halving operations on each first sum data in the first column sum data to obtain column interpolation data; A second write enable signal is sent to the cache circuit 10 to store row interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the row direction of the cache circuit 10, and to store column interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the column direction of the cache circuit 10; and to determine the output array based on the row interpolation data and the column interpolation data.

[0083] In this embodiment, the control signal sending unit 31 sends a first write enable signal to the cache circuit 10, and writes the data elements of the input array into multiple storage rows and columns of the cache circuit 10 in an alternating storage row and alternating storage column manner, reserving multiple free storage locations for interpolation data.

[0084] The first preset threshold is determined based on the data processing capability of the interpolation circuit 20 within one clock cycle. The first preset threshold is greater than or equal to the data processing volume of the interpolation circuit 20 within one clock cycle. For example, if the interpolation circuit 20 can perform 8 addition operations within one clock cycle, and each row of the input array includes 8 data elements, when it detects that the number of data elements stored in the buffer circuit 10 has reached two rows, an operation enable signal is sent to the interpolation circuit 20, and the addition calculation sub-circuit 21 in the interpolation circuit 20 performs addition operations on the data elements already stored in the buffer circuit 10. This disclosure only starts controlling the buffer circuit 10 to output data to the interpolation circuit 20 when it detects that the number of data elements stored in the buffer circuit 10 has reached the first preset threshold, that is, when the buffer circuit 10 has stored data elements that meet the preset threshold for reading.

[0085] As an example, the first preset threshold is equal to the storage capacity of the cache circuit 10, that is, the first preset threshold is equal to the maximum number of data elements that can be stored in the cache circuit 10, and the read enable signal is triggered only when the number of data elements stored in the cache circuit 10 reaches the full state.

[0086] As an example, the first preset threshold is less than the storage capacity of the cache circuit 10, allowing the cache circuit 10 to trigger a read enable signal even before the number of data elements reaches its full capacity. This means that while outputting stored data elements to the interpolation circuit 20, the cache circuit 10 continues to store data elements loaded from the storage circuit 200. Consequently, the data write and read operations of the cache circuit 10 at least partially overlap in time, and the interpolation operation does not need to wait for the cache circuit 10 to reach its full capacity before starting, which helps improve the throughput of data processing.

[0087] While or after the control signal sending unit 31 sends a read enable signal to the buffer circuit 10, it can also send an operation enable signal to the interpolation operation circuit 20 to control the interpolation operation circuit 20 to perform the above-mentioned row interpolation operation and column interpolation operation, and output row interpolation data and column interpolation data.

[0088] During row interpolation, the addition subcircuit 21, in response to the operation enable signal, performs addition operations on at least one pair of adjacent data elements stored in the row direction to obtain the first row sum data. The halving subcircuit 22, in response to the operation enable signal, performs halving operations on each first sum data in the first row sum data to obtain the row interpolation data.

[0089] During column interpolation, the addition subcircuit 21, in response to the operation enable signal, performs addition operations on at least one pair of adjacent data elements stored in the column direction to obtain the first column sum data. The halving subcircuit 22, in response to the operation enable signal, performs halving operations on the first column sum data in the column direction to obtain the column interpolation data.

[0090] Row interpolation and column interpolation are not performed synchronously. Row interpolation can be performed first and then column interpolation, or vice versa. By sending a data selection signal to the interpolation circuit 20, the interpolation circuit 20 can switch the data source between the row and column directions as needed, thereby switching between row interpolation and column interpolation. This eliminates the need to configure separate operation circuits for different directions, which helps to reduce the area of ​​the interpolation circuit.

[0091] The control signal sending unit 31 also sends a second write enable signal to the cache circuit 10, storing the row interpolation data and column interpolation data into the corresponding free storage locations in the cache circuit. Since the cache circuit 10 has reserved free storage locations according to the method of storing rows and columns at intervals during the initial write, the interpolation data can be stored without additional cache space. The cache circuit 10 can determine the output array based on the stored row interpolation data and column interpolation data, further reducing the overhead of data reassembly.

[0092] As one implementation method, such as Figure 9 As shown, the interpolation circuit 20 also includes a first row register 23, a second row register 24, and a data selector 25.

[0093] The first row register 23 is configured to store the i-th row of data elements read from the cache circuit 10, where i is an integer greater than or equal to 0; The second row register 24 is configured to store the (i+2)th row of data elements read from the cache circuit 10; The first row register 23 is electrically connected to the first input terminal of the addition calculation sub-circuit 21, the first row register 23 and the second row register 24 are electrically connected to the input terminal of the data selector 25 respectively, and the output terminal of the data selector 25 is electrically connected to the second input terminal of the addition calculation sub-circuit 21. Data selector 25 is configured as follows: In row interpolation mode, in response to the first data selection signal sent by the control signal sending unit, the bus between the second row register 24 and the second input terminal of the addition calculation sub-circuit 21 is turned on, so that the addition calculation sub-circuit 21 performs addition operation on at least one pair of data elements located in the same column in the first row register 23 and the second row register 24 respectively to obtain the first row sum data corresponding to the row direction, and makes the halving calculation sub-circuit 22 perform halving operation on each first sum data in the first row sum data to obtain row interpolation data; In column interpolation mode, in response to the second data selection signal sent by the control signal sending unit, the bus between the first row register 23 and the second input terminal of the addition calculation sub-circuit 21 is turned on, so that the addition calculation sub-circuit 21 performs addition operation on at least one pair of adjacent data elements in the first row register 23 respectively to obtain the first column sum data corresponding to the column direction, and the halving calculation sub-circuit performs halving operation on each first sum data in the first column sum data to obtain column interpolation data.

[0094] In this embodiment, the data selection signal includes a first data selection signal and a second data selection signal.

[0095] The first data selection signal controls the data selector 25 to select the data element in the second row register 24 to the addition calculation subcircuit 21. The first row register 23 is connected to the addition calculation subcircuit 21. The addition calculation subcircuit 21 performs addition operations on at least one pair of data elements in the first row register 23 and the second row register 24 located in the same column, respectively, to obtain the first row sum data corresponding to the row direction; the halving calculation subcircuit 22 performs a halving operation on each first sum data in the first row sum data to obtain the row interpolation data.

[0096] The second data selection signal is used to control the data selector 25 to select the data elements in the first row register 23 to the addition calculation subcircuit 21. The first row register 23 is also connected to the addition calculation subcircuit 21. The addition calculation subcircuit 21 performs addition operations on at least one pair of adjacent data elements in the first row register 23 to obtain the first column sum data corresponding to the column direction; the halving calculation subcircuit performs halving operations on each first sum data in the first column sum data to obtain column interpolation data.

[0097] This disclosure achieves the reuse of interpolation circuits by changing the data source of the addition sub-circuit 21 through channel switching of the data selector 25. Row interpolation and column interpolation operations share the same set of operation circuits in a time-division multiplexing manner, eliminating the need to configure independent addition and halving sub-circuits for each direction, thereby reducing the number of interpolation circuits and further reducing hardware area overhead.

[0098] In addition, the first row register 23 and the second row register 24 store the data elements of the i-th row and the (i+2)-th row, respectively, so that the data elements required for the row direction interpolation operation remain stable in the registers and do not need to be read repeatedly from the cache circuit 10, thereby reducing the number of reads and data moving overhead of the cache circuit 10.

[0099] As one implementation method, such as Figure 9 As shown, the interpolation circuit 20 also includes a data distributor 26, which is located between the output of the buffer circuit 10 and the inputs of the two row registers. The data distributor 26 is configured to sequentially distribute the row data read from the buffer circuit to the first row register 23 and the second row register 24.

[0100] As one implementation, the data loading of the first row register 23 and the second row register 24 adopts a sliding window method. During the initial loading, the cache circuit 10 reads the i-th row of data in the first clock cycle and writes it to the first row register 23 via the data distributor 26; in the second clock cycle, it reads the (i+1)-th row of data and writes it to the second row register 24 via the data distributor 26. In subsequent processing, when it is necessary to slide to the next set of data elements, the cache circuit 10 only needs to read a new row of data elements in a single clock cycle. The original (i+1)-th row of data elements stored in the second row register 24 is moved into the first row register 23, and the newly read data element is written to the second row register 24, thus realizing the sliding update of the data content in the row registers. Therefore, the data element reuse of the data distributor 26 helps reduce the number of accesses by the cache circuit 10 and improves the execution efficiency of row-direction interpolation.

[0101] As one implementation method, such as Figure 10 As shown, the controller 30 also includes: Instruction parsing unit 32 is configured to receive and parse data processing configuration instructions to obtain configuration instruction information; The data dimension counter 33 is configured to initialize the count values ​​corresponding to different dimensions in response to receiving a data processing configuration instruction; or, in response to the controller reading data elements from the storage circuit, update the count values ​​corresponding to different dimensions. The segmentation counter 34 is configured to initialize the count value of the segmentation counter in the data block dimension in response to receiving a data processing configuration instruction; or, in response to a first overflow signal generated by the data dimension counter, update the count value of the segmentation counter in the data block dimension; wherein the input array includes at least one data block; the first overflow signal is generated when the count value of the data dimension counter in different dimensions reaches the boundary value of the dimension corresponding to the currently read data block; Address generation unit 35 is configured to generate read / write access addresses based on the count values ​​of data dimension counters in different dimensions, the count value of split counters in the data block dimension, the starting address, dimension information, and data bit width information. The read / write unit 36 ​​is configured to send a read / write access request to the storage circuit according to the read / write access address in order to read multiple data elements from the input array in the storage circuit.

[0102] In this embodiment, the instruction parsing unit parses the received data processing configuration instructions to obtain configuration instruction information, and sends the configuration instruction information to the corresponding component unit in the controller 30. For example, it sends the starting address of the input array in the storage circuit 200, the dimension information of the input array, and the data bit width information of the data elements to the address generation unit 35, so that the address generation unit 35 can generate read / write access addresses based on the above configuration instruction information. It also sends the dimension information of the input array to the data dimension counter 33, so that the data dimension counter can determine the boundary values ​​of different dimensions based on the dimension information of the input array. Furthermore, it sends the total number of data blocks to the segmentation counter 34, so that the segmentation counter 34 can determine the boundary values ​​of the data block dimensions based on the total number of data blocks. The total number of data blocks is determined based on the dimension information of the input array to be processed and the storage capacity of the cache circuit.

[0103] Upon receiving the data processing configuration command, the data dimension counter 33 resets the count values ​​corresponding to different dimensions to zero. When the controller 30 reads data elements from the input array from the storage circuit 200, the data dimension counter 33 updates the count values ​​for each dimension, accurately recording the position of the currently read data element in the input array. For example, each time the controller 30 reads a data element from the storage circuit 200, the count value of the corresponding dimension of the data dimension counter 33 increments by 1. When the count values ​​of the data dimension counter 33 in different dimensions reach the boundary value of the dimension corresponding to the currently read data block, the data dimension counter 33 generates a first overflow signal, indicating that all data elements in the currently read data block have been read and it is necessary to switch to the next data block.

[0104] Upon receiving the data processing configuration command, the segment counter 34 resets the count value of the data block dimension to zero. When the data dimension counter 33 generates the first overflow signal, the segment counter 34 updates the count value of the data block dimension to track the number of the currently read data block. For example, if the total number of data blocks corresponding to the input array is M, and the count value of the data block dimension ranges from 0 to M-1, if the count value of the data block dimension by the segment counter 34 is less than M-1, the segment counter 34 increments the count value of the data block dimension by 1 when the first overflow signal is generated. If the count value of the data block dimension by the segment counter 34 is equal to M-1, the first overflow signal indicates that the currently read data block is the last data block of the input array, the batch dimension count value of the data dimension counter 33 is incremented by 1, and the segment counter 34 is initialized to the count value of the data block dimension.

[0105] As an example, consider an 8×8 input array, consisting of 8 rows and 8 columns, containing 64 data elements. The data block size is 32 data elements (4 rows). The input array needs to be divided into two data blocks: the first block contains data elements from rows 0 to 3, and the second block contains data elements from rows 4 to 7. The splitting counter's count value ranges from 0 to 1 in the data block dimension. The data dimension counter tracks the current data element position, with a count value range of 0 to 3 in the row dimension and 0 to 7 in the column dimension. When the data dimension counter's count value in the row dimension equals 3 and its count value in the column dimension equals 7, it indicates that the current data block has been read up to row 3, column 7, meaning all data elements in the current data block have been read. When the data dimension counter attempts to jump from 7 to the next column in the column dimension, the column dimension count value should theoretically be 8, exceeding the column boundary of the data block and generating the first overflow signal. If the count value of the segment counter in the data block dimension is 0, the segment counter responds to the first overflow signal, increments the count value of the data block dimension by 1, and switches to the next data block; if the count value of the segment counter in the data block dimension is 1, it indicates that the currently read data block is the last data block, the segment counter responds to the first overflow signal, controls the count value of the batch dimension of the data dimension counter 33 to be incremented by 1, and controls the segment counter 34 to initialize the count value of the data block dimension.

[0106] This disclosure divides a large input array into multiple data blocks, and only one data block needs to be loaded into the cache circuit 10 at a time. The number of the currently read data block is determined by the count value of the data block dimension of the segmentation counter 34, so as to support input arrays of various sizes under the condition of limited capacity of the cache circuit 10.

[0107] Address generation unit 35 generates read / write access addresses based on the count values ​​of data dimension counter 33 in different dimensions, the count value of segmentation counter 34 in the data block dimension, and the starting address, dimension information, and bit width information of the input array. Read / write unit 36 ​​sends read / write access requests to storage circuit 200 based on these read / write access addresses, enabling read / write unit 36 ​​to continuously read data elements from storage circuit 200.

[0108] In addition, the first overflow signal triggers the segmentation counter 34 to update the count value of the data block dimension, which indicates a data block switch. The address generation unit 35 then switches the base address of the read / write address from the starting address corresponding to the current data block to the starting address corresponding to the next data block, thereby achieving seamless connection between data blocks, which is beneficial to improving the continuity of data reading and the throughput of data processing.

[0109] As one implementation method, such as Figure 10 As shown, the address generation unit 35 is also configured to: generate a read / write address based on the row dimension count value and column dimension count value of the data dimension counter 33 during the process of the read / write unit 36 ​​reading multiple data elements from the input array in the storage circuit 200, and send the read / write address to the cache circuit 10 to locate the data element in the storage array of the cache circuit.

[0110] The read / write addresses generated by address generation unit 35 are internal read / write addresses, used to locate data elements in cache circuit 10. The read / write access addresses generated by address generation unit 35 are external read / write addresses, used to locate data elements in storage circuit 200.

[0111] As one implementation method, the data dimension counter is also configured such that after reading data elements from the storage circuit, the count of the data dimension counter increments sequentially according to the preset data dimension order. The preset data dimensions are ordered as follows: channel dimension, column dimension, row dimension, and batch dimension. The data dimension counters are specifically configured as follows: When the channel dimension count overflows, the column dimension count is incremented by 1, and the channel dimension count is initialized. When the column dimension count overflows, the row dimension count is incremented by 1, and the channel dimension and column dimension counts are initialized. When the row dimension count overflows, the batch dimension count is incremented by 1, and the channel dimension, column dimension, and row dimension counts are initialized. or, The preset data dimension order includes channel dimension, row dimension, column dimension, and batch dimension, and the data dimension counter is specifically configured as follows: When the channel dimension count overflows, the row dimension count is incremented by 1, and the channel dimension count is initialized. When the row dimension count overflows, the column dimension count is incremented by 1, and the channel dimension and row dimension counts are initialized. When the column dimension count overflows, the batch dimension count is incremented by 1, and the channel, row, and column dimension counts are initialized.

[0112] In this embodiment, the data dimension counter includes channel dimension (C), row dimension (H), column dimension (W), and batch dimension (B).

[0113] Channel dimension refers to the number of channels in the input array. For example, if the input array is RGB color image data with 3 channels, the channel dimension corresponding to the data dimension counter can range from 0 to 2.

[0114] Row dimension refers to the vertical dimension of the input array, expressed in the number of rows. For example, a 224×224 input array has a total of H=224 rows, and the row dimension corresponding to the data dimension counter ranges from 0 to 223.

[0115] Column dimension refers to the horizontal dimension of the input array, expressed as the number of columns. For example, a 224×224 input array has a total of W=224 columns, and the column dimension corresponding to the data dimension counter ranges from 0 to 223.

[0116] Batch dimension refers to the number of data samples processed at one time, such as the number of input arrays. The count value for batch dimension is represented by "N".

[0117] The count value of the data dimension counter can be incremented sequentially according to the channel dimension, column dimension, row dimension, and batch dimension. Specifically, when the count value of the previous dimension overflows, that is, when the count value of the previous dimension reaches the boundary value corresponding to that dimension and can no longer be increased, the count value of the next dimension is incremented by 1, and the count value of the previous dimension is cleared to zero.

[0118] As an example, taking an input array with dimensions 1×4×4×3 (N×H×W×C), when the channel dimension count equals 2, the channel dimension overflows, the column dimension count is incremented by 1, and the channel dimension count is reset to zero. When the column dimension count equals 3, the column dimension overflows, the row dimension count is incremented by 1, and both the channel and column dimension counts are reset to zero. When the row dimension count reaches 3, the row dimension overflows, the batch dimension count is incremented by 1, and the channel, column, and row dimension counts are reset to zero.

[0119] The count value of the data dimension counter can be incremented sequentially according to the channel dimension, row dimension, column dimension, and batch dimension. Specifically, when the count value of the previous dimension overflows, that is, when the count value of the previous dimension reaches the boundary value corresponding to that dimension and can no longer be increased, the count value of the next dimension is incremented by 1, and the count value of the previous dimension is cleared to zero.

[0120] As an example, taking an input array with dimensions 1×4×4×3 (N×H×W×C), when the channel dimension count equals 2, the channel dimension overflows, the row dimension count is incremented by 1, and the channel dimension count is reset to zero. When the row dimension count equals 3, the row dimension overflows, the column dimension count is incremented by 1, and both the channel and row dimension counts are reset to zero. When the column dimension count reaches 3, the column dimension overflows, the batch dimension count is incremented by 1, and the channel, row, and column dimension counts are reset to zero.

[0121] This disclosed data dimension counter triggers the increment of the column or row dimension count by 1 when the channel dimension count overflows, and then triggers the increment of the count in a higher dimension, until the batch dimension finishes counting, thus enabling hierarchical traversal of data elements in the row, column, and channel directions. This data dimension counter supports counting order of channel, column, row, and batch dimensions, as well as technical order of these dimensions, which can meet the data formats of different storage layouts and improve the flexibility of data processing.

[0122] It should be noted that, for the preset data dimension order of channel, column, row, and batch dimensions, row dimension overflow is only determined when the count value of the row dimension reaches the boundary value of the corresponding row dimension in the input array. Similarly, for the preset data dimension order of channel, row, column, and batch dimensions, column dimension overflow is only determined when the count value of the column dimension reaches the boundary value of the corresponding row dimension in the input array.

[0123] As one implementation, the data dimension counter is also configured to generate a first overflow signal when the row dimension count reaches the row boundary value corresponding to the currently read data block and the column dimension count exceeds the column boundary value corresponding to the currently read data block. The segmentation counter is also configured to, in response to a first overflow signal generated by the data dimension counter, increment the data block dimension count by 1 and send the updated data block dimension count to the address generation unit when the count value of the data block dimension is less than a second preset threshold; the second preset threshold is determined based on the dimension information of the input array and the dimension information of the data block. The address generation unit is also configured to switch the starting address of the current data block to the starting address of the next data block in response to the updated count value of the data block dimension. The data dimension counter is also configured to initialize the column dimension and row dimension counts in the data dimension counter after the split counter increments the count value of the current data block by 1, while keeping the channel dimension and batch dimension counts unchanged.

[0124] In this embodiment, when the data dimension counter reaches the row boundary value corresponding to the currently read data block and the column dimension counter exceeds the column boundary value corresponding to the currently read data block, it indicates that the controller has read all the data in the currently read data block and generates a first overflow signal to trigger the split counter to update the data block dimension counter value.

[0125] The second preset threshold is determined based on the dimensional information of the input array and the dimensional information of the data blocks. For example, if the input array has 100 rows and 100 columns, and the data blocks have 10 rows and 100 columns, the input array can be divided into 10 data blocks, each numbered from 0 to 9, and the second preset threshold is set to 9.

[0126] If the count value of the data block dimension of the segment counter is less than the second preset threshold, it indicates that the currently read data block is not the last data block in the input array. In response to the first overflow signal generated by the data dimension counter, the segment counter increments the count value of the data block dimension by 1 and sends the updated count value of the data block dimension to the address generation unit to trigger the reading of the next data block.

[0127] The address generation unit automatically switches the starting address of the read / write address based on the updated count value of the data block dimension, enabling the read / write unit to start reading data from the beginning of the next data block.

[0128] After the split counter increments the count value of the current data block by 1, the data dimension counter resets the count values ​​of the row dimension and column dimension to zero, while keeping the count values ​​of the channel dimension and batch dimension unchanged, in preparation for reading the first data element of the next data block.

[0129] This disclosure enables automatic switching from the current data block to the next data block without external control intervention, achieving block-based continuous reading of large input arrays. This helps reduce waiting time during data processing and improves data processing throughput.

[0130] As one implementation, the split counter is also configured to generate a second overflow signal in response to a first overflow signal generated by the data dimension counter when the count value in the data block dimension reaches a second preset threshold. The control signal sending unit is also configured to, in response to the second overflow signal, stop sending the first write enable signal to the cache circuit to control the cache circuit to stop storing data elements in the input array; and to stop sending the read enable signal to the cache circuit when it is detected that all data elements stored in the cache circuit have been sent to the interpolation circuit; the read enable signal is sent to the cache circuit by the control signal sending unit when it is detected that the number of data elements stored in the cache circuit has reached a first preset threshold, so as to control the cache circuit to output data elements to the interpolation circuit.

[0131] In this embodiment, when the count value of the data block dimension of the segment counter reaches the second preset threshold, it indicates that the currently read data block is the last data block in the input array. The segment counter responds to the first overflow signal generated by the data dimension counter and generates a second overflow signal to prompt the control signal sending unit that the data reading of the last data block in the input array has been completed. This triggers the control signal sending unit to stop sending the first write enable signal to the cache circuit, thereby controlling the cache circuit to stop storing data elements in the input array.

[0132] Since the data operation of the interpolation circuit lags behind the data reading operation, after the buffer circuit stops storing data elements in the input array, the control signal sending unit continues to send read enable signals to the buffer circuit until all data elements stored in the buffer circuit have been sent to the interpolation circuit. This ensures that all data elements loaded in the buffer circuit can be sent to the interpolation circuit for processing before stopping, which helps reduce the risk of data loss.

[0133] As one implementation method, the configuration instruction information also includes the target magnification factor of the input array, where the target magnification factor is a power of 2, and N is a positive integer; The controller is also configured as follows: After each output array is determined, increment the number of iterations completed by 1; If the number of iterations has not reached N, the output array of the current output is determined as the input array of the next iteration. The buffer circuit is controlled to store the newly determined input array, and the interpolation circuit is controlled to perform interpolation operation based on the newly determined input array, until the number of iterations has reached N. If the number of iterations has reached N, stop the iteration and determine the output array obtained in this iteration as the final output array.

[0134] In this embodiment, after determining the output array each time, the controller increments the number of completed iterations by 1 and compares the number of completed iterations with the number of iterations N corresponding to the target magnification. If the number of completed iterations has not reached N, the current output array is determined as the input array for the next iteration. The controller then controls the buffer circuit to store the newly determined input array and controls the interpolation circuit to perform interpolation operations based on the newly determined input array to obtain a new output array. This process is repeated until the number of completed iterations reaches N. Once the number of completed iterations reaches N, the iteration stops, and the output array obtained in this iteration is determined as the final output array.

[0135] The data processing device performs the interpolation operation provided in the above embodiment on the input array. Each time the output data is determined, one iteration is completed, and a single iteration magnifies the input array by a factor of 2. By performing N iterations on the input array, the input array is magnified by a power of 2.

[0136] The data processing device provided in this disclosure supports size adjustment operations of 2 to the power of N, and the hardware resources do not need to increase with the increase of magnification, which helps to reduce resource consumption.

[0137] For example, such as Figure 11 As shown, for a 3x8 input array (in[0][0]~in[2][7]), the bandwidth of the cache circuit allows it to write 4 data elements per clock cycle. In cycle 0, in[0][0]~in[0][3] of the first row of the input array are stored in the cache circuit at the corresponding storage locations of out[0][0], out[0][2], out[0][4] and out[0][6], respectively, and adjacent data elements in the same row are stored in an alternating column manner. In cycle 1, in[0][4]~in[0][7] of the first row of the input array are stored in the cache circuit at the corresponding storage locations of out[0][8], out[0]

[10] , out[0]

[12] and out[0]

[14] , respectively, and adjacent data elements in the same row are stored in an alternating column manner. In cycle 2 and cycle 3, the in[1][0]~in[1][7] of the second row of the input array are stored in the storage positions corresponding to the out[2][0]~out[2]

[14] row in the buffer circuit, respectively; in cycle 4 and cycle 5, the in[2][0]~in[2][7] of the third row of the input array are stored in the storage positions corresponding to the out[4][0]~out[4]

[14] row in the buffer circuit, and adjacent data elements in different rows are stored in a way that is separated by rows.

[0138] For example, such as Figure 12As shown, the interpolation circuit includes four sets of parallel interpolation circuits to perform row interpolation on the data elements stored in the cache circuit. Specifically, during cycle 0, the data elements in the same column of the first four data elements in[0][0]~in[0][3] of the first row of the input array and the first four data elements in[1][0]~in[1][3] of the second row are input into the same interpolation circuit to obtain the row interpolation data corresponding to the two rows of data elements. The row interpolation data is stored in the free storage locations corresponding to out[1][0], out[1][2], out[1][4] and out[1][6] in the cache circuit. In cycle 1, the first four data elements of the second row of the input array, in[1][0]~in[1][3], and the first four data elements of the third row, in[2][0]~in[2][3], are input into the same interpolation circuit to obtain the row interpolation data corresponding to the two rows of data elements. The row interpolation data is stored in the free storage locations corresponding to out[3][0], out[3][2], out[3][4], and out[3][6] in the buffer circuit. In cycle 2, the last four data elements of the first row of the input array, in[0][4]~in[0][7], and the last four data elements of the second row, in[1][4]~in[1][7], are input into the same interpolation circuit to obtain the row interpolation data corresponding to the two rows of data elements. The row interpolation data is stored in the free storage locations corresponding to out[1][8], out[1]

[10] , out[1]

[12] , and out[1]

[14] in the buffer circuit. In cycle 3, the data elements in the same column of the last four data elements in[1][4]~in[1][7] of the second row and the last four data elements in[2][4]~in[2][7] of the third row of the input array are input into the same interpolation circuit to obtain the row interpolation data corresponding to the two rows of data elements. The row interpolation data is stored in the free storage locations corresponding to out[3][8], out[3]

[10] , out[3]

[12] and out[3]

[14] in the cache circuit.

[0139] It should be noted that, Figure 12 This illustration merely demonstrates the process of calculating the row interpolation data for the first half of the data elements in adjacent rows, and then calculating the row interpolation data for the second half of the data elements in adjacent rows, but it does not constitute a limitation on the data processing apparatus provided in this disclosure. In other embodiments, the row interpolation data for the operations on two adjacent rows can be calculated before reading the data of the next adjacent row and calculating the corresponding row interpolation data, which is not limited here.

[0140] For example, such as Figure 13As shown, after calculating the row interpolation data, column interpolation is performed on the data elements in the cache circuit. Specifically, in cycle 0, the first four data elements of the first row of the input array, out[0][0], out[0][2], out[0][4], out[0][6], and out[0][8], are input into the interpolation circuit to calculate the column interpolation data of two adjacent data elements in the column direction. The resulting column interpolation data is stored in the free storage locations corresponding to out[0][1], out[0][3], out[0][5], and out[0][7] in the first row of the cache circuit. In cycle 1, the first four data elements of the first row of the input array, out[0]

[10] , out[0]

[12] , and out[0]

[14] , are input into the interpolation circuit to calculate the column interpolation data of two adjacent data elements in the column direction. The resulting column interpolation data is stored in the free storage locations corresponding to out[0][9], out[0]

[11] , and out[0]

[13] in the first row of the cache circuit. In cycle 2 and cycle 3, calculate the interpolation data of two adjacent elements in the column direction in out[1][0]~out[1]

[14] , and store the column interpolation data in the cache circuit at the free storage location corresponding to the odd position in the row out[1][0]~out[1]

[14] . Perform column interpolation operations on out[2][0]~out[2]

[14] , out[3][0]~out[3]

[14] and out[4][0]~out[4]

[14] respectively, and store the obtained column interpolation data in the free storage location of the corresponding row.

[0141] As one implementation, when performing a target reduction operation on the input array to be processed using the data processing device provided in this disclosure, the cache circuit is further configured to store multiple data elements of the input array read from the storage circuit into the storage row and storage column of the cache circuit in a row-by-row and column-by-column manner, that is, to store the data element operations in the input array into the cache circuit in the original storage method, and there are no free storage positions between the data elements.

[0142] The cache circuit is also configured to read data from the cache circuit at intervals of rows and columns, perform operations, and determine the read data elements as the output array. For the shrinking operation, no interpolation circuit is required; it can be achieved by controlling the read and write operations of the cache circuit.

[0143] Exemplary methods Figure 14 This is a flowchart illustrating a data processing method provided in an exemplary embodiment of this disclosure. Figure 14 As shown, the data processing method includes the following steps: S1410~1450.

[0144] S1410. Store multiple data elements of the input array in the buffer circuit.

[0145] S1420. Perform an addition operation on two adjacent data elements stored in the cache circuit to obtain the first sum data.

[0146] S1430. Perform a halving operation on the first summed data to obtain the interpolated data.

[0147] S1440: Store the interpolated data corresponding to adjacent data elements in the free storage location of the cache circuit.

[0148] S1450. Determine the output array based on the interpolated data.

[0149] The data processing method provided in this disclosure stores multiple data elements of an input array through a cache circuit. An addition subcircuit performs an addition operation on two adjacent data elements stored in the cache circuit to obtain a first summed data. A halving subcircuit performs a halving operation on the first summed data to obtain interpolated data. This "addition + halving" operation replaces the multiplication operation in related technologies, thereby reducing the computational overhead of a single interpolation operation. Furthermore, the interpolated data is stored in the free storage space between adjacent data elements in the cache circuit, allowing the interpolated data and the original data (i.e., the original data elements stored in the cache circuit) to be stored in the same cache circuit. This eliminates the need to allocate separate cache space for the interpolated data, reducing the requirement for cache capacity. Therefore, the data processing apparatus provided in this disclosure reduces the consumption of corresponding computing resources from both computational and storage perspectives.

[0150] As one implementation, the halving calculation sub-circuit includes an integer data halving sub-circuit, and accordingly, S1430 follows the steps below: When the data element is an integer, the first summed data is shifted right by one bit by the integer data halving sub-circuit to obtain the second summed data. Based on the second summed data, the interpolation data is determined.

[0151] As one implementation method, "when the data element's data type is integer, the first summed data is right-shifted by one bit through the integer data halving sub-circuit to obtain the second summed data, and the interpolation data is determined based on the second summed data" includes the following steps: If the least significant bit of the first summed data is 0, the second summed data is determined as the interpolated data; or, If the least significant bit of the first summed data is 1, perform an increment operation on the second summed data to obtain the interpolated data.

[0152] As one implementation, the halving calculation subcircuit includes a floating-point data halving subcircuit, and accordingly, S1430 follows the steps below: If the data element is of floating-point data type and the exponent field value of the first summed data is greater than 1, the exponent field value of the first summed data is decremented by 1 through the floating-point data halving sub-circuit to obtain the third summed data; based on the third summed data, the interpolation data is determined; and / or, When the data element is of floating-point type and the exponent field of the first sum is less than or equal to 1, the mantissa field of the first sum is shifted right by one bit by the floating-point data halving sub-circuit to obtain the fourth sum; based on the fourth sum, the interpolation data is determined.

[0153] As one implementation, S1410 includes the following steps: storing multiple data elements of the input array in multiple storage rows and multiple storage columns of the cache circuit according to the method of interleaved storage rows and interleaved storage columns, so that at least one free storage location is formed between adjacent data elements; S1420 includes the following steps: performing an addition operation on at least one pair of adjacent data elements stored in the row direction in the cache circuit through an addition calculation sub-circuit to obtain the first row sum data corresponding to the row direction; and performing an addition operation on at least one pair of adjacent data elements stored in the column direction in the cache circuit to obtain the first column sum data corresponding to the column direction; the first row sum data includes at least one first sum data; the first column sum data includes at least one first sum data.

[0154] S1430 includes the following steps: performing a halving operation on each of the first summed data in the first row summed data through a halving calculation sub-circuit to obtain row interpolated data, and performing a halving operation on each of the first summed data in the first column summed data to obtain column interpolated data.

[0155] S1440~S1450 includes the following steps: storing row interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the row direction of the cache circuit; and storing column interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the column direction of the cache circuit; and determining the output array based on the row interpolation data and the column interpolation data.

[0156] As one implementation, prior to S1410, the method also includes the following steps: Receive and parse data processing configuration instructions to obtain configuration instruction information. The configuration instruction information includes at least one of the following: the starting address of the input array in the storage circuit, the dimension information of the input array, and the data bit width information of the data elements. Based on the starting address, dimension information, and data bit width information, a read / write access request is sent to the storage circuit to read multiple data elements from the input array.

[0157] As one implementation, S1410 includes the following steps: sending a first write enable signal to the cache circuit to control the cache circuit to write multiple data elements from the input array into the cache circuit.

[0158] S1420~S1430 includes the following steps: sending an operation enable signal and a data selection signal to the interpolation operation circuit to control the addition operation sub-circuit to perform an addition operation on two adjacent data elements stored in the cache circuit to obtain the first sum data, and controlling the halving operation sub-circuit to perform a halving operation on the first sum data to obtain the interpolated data.

[0159] S1440~S1450 includes the following steps: sending a second write enable signal to the cache circuit to store interpolated data corresponding to two adjacent data elements in a free storage location in the cache circuit; and determining the output array based on the interpolated data.

[0160] As one implementation, S1410 includes the following steps: sending a first write enable signal to the cache circuit to control the cache circuit to write multiple data elements in the input array into multiple storage rows and multiple storage columns of the cache circuit in an alternating storage row and alternating storage column manner; S1420~S1430 includes the following steps: When the number of data elements stored in the cache circuit reaches the first preset threshold, a read enable signal is sent to the cache circuit to control the cache circuit to output data elements to the interpolation circuit. Send an operation enable signal and a data selection signal to the interpolation operation circuit to control the addition operation subcircuit to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit in the row direction to obtain the first row sum data corresponding to the row direction; perform addition operations on at least one pair of adjacent data elements stored in the cache circuit in the column direction to obtain the first column sum data corresponding to the column direction; control the halving operation subcircuit to perform halving operations on each first sum data in the first row sum data to obtain row interpolation data, and perform halving operations on each first sum data in the first column sum data to obtain column interpolation data.

[0161] S1440~S1450 includes the following steps: A second write enable signal is sent to the cache circuit to store row interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the row direction of the cache circuit, and to store column interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the column direction of the cache circuit; and to determine the output array based on the row interpolation data and the column interpolation data.

[0162] As one implementation method, the approach includes the following steps: Receive and parse data processing configuration instructions to obtain configuration instruction information; In response to receiving a data processing configuration command, the data dimension counter is initialized with the corresponding count values ​​for different dimensions; or, in response to the controller reading a data element from the storage circuit, the data dimension counter is updated with the corresponding count values ​​for different dimensions. In response to receiving a data processing configuration instruction, the count value of the split counter in the data block dimension is initialized; or, in response to a first overflow signal generated by the data dimension counter, the split counter updates the count value in the data block dimension; wherein, the input array includes at least one data block; the first overflow signal is generated when the count value of the data dimension counter in different dimensions reaches the boundary value of the dimension corresponding to the currently read data block; Based on the count values ​​of the data dimension counter in different dimensions, the count value of the split counter in the data block dimension, the starting address, dimension information, and data bit width information, a read / write access address is generated. Based on the read / write access address, a read / write access request is sent to the storage circuit to read multiple data elements from the input array.

[0163] As one implementation method, "in response to the controller reading data elements from the storage circuit, the data dimension counter updates the count values ​​corresponding to different dimensions" includes the following steps: After reading data elements from the storage circuit, the data dimension counter increments sequentially according to the preset data dimension order. The preset data dimensions are ordered as follows: channel dimension, column dimension, row dimension, and batch dimension. The data dimension counters are specifically configured as follows: When the channel dimension count overflows, the column dimension count is incremented by 1, and the channel dimension count is initialized. When the column dimension count overflows, the row dimension count is incremented by 1, and the channel dimension and column dimension counts are initialized. When the row dimension count overflows, the batch dimension count is incremented by 1, and the channel dimension, column dimension, and row dimension counts are initialized. or, The preset data dimension order includes channel dimension, row dimension, column dimension, and batch dimension, and the data dimension counter is specifically configured as follows: When the channel dimension count overflows, the row dimension count is incremented by 1, and the channel dimension count is initialized. When the row dimension count overflows, the column dimension count is incremented by 1, and the channel dimension and row dimension counts are initialized. When the column dimension count overflows, the batch dimension count is incremented by 1, and the channel dimension, row dimension, and column dimension counts are initialized.

[0164] As one implementation method, the approach also includes the following steps: When the row dimension count reaches the row boundary value corresponding to the currently read data block and the column dimension count exceeds the column boundary value corresponding to the currently read data block, the data dimension counter is controlled to generate a first overflow signal. If the count value of the data block dimension is less than the second preset threshold, in response to the first overflow signal generated by the data dimension counter, the count value of the data block dimension is incremented by 1, and the updated count value of the data block dimension is sent to the address generation unit; the second preset threshold is determined based on the dimension information of the input array and the dimension information of the data block. In response to the updated count value of the data block dimension, switch the starting address of the current data block to the starting address of the next data block; After the split counter increments the count value of the current data block by 1, the count values ​​of the column dimension and row dimension in the data dimension counter are initialized respectively, while the count values ​​of the channel dimension and batch dimension remain unchanged.

[0165] As one implementation method, the approach also includes the following steps: When the count value of the data block dimension reaches the second preset threshold, the split counter generates a second overflow signal in response to the first overflow signal generated by the data dimension counter. In response to the second overflow signal, the sending of the first write enable signal to the cache circuit is stopped, thereby controlling the cache circuit to stop storing data elements in the input array; When it is detected that all data elements stored in the cache circuit have been sent to the interpolation circuit, the read enable signal is stopped being sent to the cache circuit. The read enable signal is sent to the cache circuit by the control signal sending unit when the number of data elements stored in the cache circuit reaches the first preset threshold, so as to control the cache circuit to output data elements to the interpolation circuit.

[0166] As one implementation method, the configuration instruction information also includes the target magnification factor of the input array, where the target magnification factor is a power of 2, and N is a positive integer; The method also includes the following steps: After each output array is determined, increment the number of iterations completed by 1; If the number of iterations has not reached N, the output array of the current output is determined as the input array of the next iteration. The buffer circuit is controlled to store the newly determined input array, and the interpolation circuit is controlled to perform interpolation operation based on the newly determined input array, until the number of iterations has reached N. If the number of iterations has reached N, stop the iteration and determine the output array obtained in this iteration as the final output array.

[0167] As one implementation, the interpolation circuit further includes a first row register, a second row register, and a data selector; the first row register is configured to store the i-th row of data elements read from the buffer circuit, where i is an integer greater than or equal to 0; the second row register is configured to store the (i+2)-th row of data elements read from the buffer circuit; the first row register is electrically connected to the first input terminal of the addition sub-circuit, the first row register and the second row register are respectively electrically connected to the input terminals of the data selector, and the output terminal of the data selector is electrically connected to the second input terminal of the addition sub-circuit; the data selection signals include a first data selection signal and a second data selection signal; The method also includes the following steps: In row interpolation mode, the control data selector responds to the first data selection signal sent by the control signal sending unit to select the bus between the second row register and the second input terminal of the addition calculation sub-circuit, so that the addition calculation sub-circuit performs addition operation on at least one pair of data elements in the first row register and the second row register located in the same column respectively to obtain the first row sum data corresponding to the row direction, and makes the halving calculation sub-circuit perform halving operation on each first sum data in the first row sum data to obtain row interpolation data; In column interpolation mode, the control data selector responds to the second data selection signal sent by the control signal sending unit to select the bus between the first row register and the second input terminal of the addition calculation sub-circuit, so that the addition calculation sub-circuit performs addition operations on at least one pair of adjacent data elements in the first row register to obtain the first column sum data corresponding to the column direction, and causes the halving calculation sub-circuit to perform halving operations on each first sum data in the first column sum data to obtain column interpolation data.

[0168] Exemplary electronic devices Figure 15 This is a structural diagram of an electronic device provided in an embodiment of this disclosure. Figure 15 As shown, the electronic device 1500 includes at least one processor 1501 and a memory 1502.

[0169] The processor 1501 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0170] The memory 1502 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1501 may execute one or more computer program instructions to implement the data processing methods and / or other desired functions of the various embodiments of this disclosure described above.

[0171] In one example, the electronic device 1500 may also include an input device 1503 and an output device 1504, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0172] The input device 1503 may also include, for example, a keyboard, a mouse, etc.

[0173] The output device 1504 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0174] Of course, for the sake of simplicity, Figure 15 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0175] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the data processing methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0176] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0177] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps of the data processing methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0178] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0179] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0180] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A data processing apparatus, comprising: A buffer circuit is configured to store multiple data elements of the input array; An interpolation circuit is configured to perform interpolation operations on two adjacent data elements stored in the cache circuit to obtain interpolated data; The interpolation circuit includes an addition sub-circuit and a halving sub-circuit; The addition calculation sub-circuit is configured to perform an addition operation on two adjacent data elements stored in the cache circuit to obtain a first sum data; The halving calculation sub-circuit is configured to perform a halving operation on the first summed data to obtain the interpolated data; The cache circuit is further configured to store the interpolated data corresponding to adjacent data elements in a free storage location in the cache circuit; and to determine the output array based on the interpolated data.

2. The data processing apparatus according to claim 1, wherein, The halving calculation sub-circuit includes an integer data halving sub-circuit; The integer data halving sub-circuit is configured to perform a right shift operation on the first summed data by one bit when the data element's data type is integer data, to obtain a second summed data, and to determine the interpolated data based on the second summed data.

3. The data processing apparatus according to claim 2, wherein, The integer data halving sub-circuit is specifically configured as follows: If the least significant bit of the first summed data is 0, the second summed data is determined as the interpolated data; or, If the least significant bit of the first summed data is 1, then the second summed data is incremented by 1 to obtain the interpolated data.

4. The data processing apparatus according to any one of claims 1-3, wherein, The halving calculation sub-circuit includes a floating-point data halving sub-circuit; The floating-point data halving sub-circuit is configured to, when the data element is of floating-point data and the exponent field value of the first summed data is greater than 1, perform an exponent field decrement operation on the first summed data to obtain a third summed data; determine the interpolated data based on the third summed data; and / or, The floating-point data halving sub-circuit is configured to perform a right shift operation on the mantissa field of the first summed data by one bit when the data element is of floating-point data and the value of the exponent field of the first summed data is less than or equal to 1, to obtain a fourth summed data; and to determine the interpolated data based on the fourth summed data.

5. The data processing apparatus according to any one of claims 1-4, wherein, The cache circuit is specifically configured to store multiple data elements of the input array in multiple storage rows and multiple storage columns of the cache circuit in an alternating storage row and alternating storage column manner, so that at least one free storage location is formed between adjacent data elements. The addition calculation sub-circuit is configured to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit in the row direction to obtain a first row sum data corresponding to the row direction; and to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit in the column direction to obtain a first column sum data corresponding to the column direction; the first row sum data includes at least one first sum data; the first column sum data includes at least one first sum data; The halving calculation sub-circuit is configured to perform a halving operation on each of the first summed data in the first row to obtain row interpolated data; and to perform a halving operation on each of the first summed data in the first column to obtain column interpolated data. The cache circuit is further configured to store row interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the row direction of the cache circuit; and to store column interpolation data corresponding to at least one pair of adjacent data elements in the free storage location between at least one pair of adjacent data elements in the column direction of the cache circuit; and to determine the output array based on the row interpolation data and the column interpolation data.

6. The data processing apparatus according to any one of claims 1-5, wherein, The data processing device further includes a controller, which is configured to: Receive and parse data processing configuration instructions to obtain configuration instruction information, wherein the configuration instruction information includes at least one of the following: the starting address of the input array in the storage circuit, the dimension information of the input array, and the data bit width information of the data element; Based on the starting address, the dimension information, and the data bit width information, a read / write access request is sent to the storage circuit to read multiple data elements from the input array.

7. The data processing apparatus according to claim 6, wherein, The controller includes a control signal transmitting unit, which is configured to: Send a first write enable signal to the cache circuit to control the cache circuit to write multiple data elements from the input array into the cache circuit; Send an operation enable signal and a data selection signal to the interpolation operation circuit to control the addition operation subcircuit to perform an addition operation on two adjacent data elements stored in the cache circuit to obtain a first sum data; and control the halving operation subcircuit to perform a halving operation on the first sum data to obtain the interpolated data; A second write enable signal is sent to the cache circuit to store the interpolated data corresponding to two adjacent data elements in the free storage location of the cache circuit; the output array is determined based on the interpolated data.

8. The data processing apparatus according to claim 7, wherein, The control signal transmitting unit is specifically configured as follows: Send the first write enable signal to the cache circuit to control the cache circuit to write multiple data elements in the input array into multiple storage rows and multiple storage columns of the cache circuit in an alternating storage row and alternating storage column manner; When the number of data elements stored in the cache circuit is detected to reach a first preset threshold, a read enable signal is sent to the cache circuit to control the cache circuit to output the data elements to the interpolation circuit; The interpolation circuit sends the operation enable signal and the data selection signal to control the addition subcircuit to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit in the row direction to obtain the first row sum data corresponding to the row direction; to perform addition operations on at least one pair of adjacent data elements stored in the cache circuit in the column direction to obtain the first column sum data corresponding to the column direction; to control the halving subcircuit to perform halving operations on each of the first sum data in the first row sum data to obtain row interpolation data; and to perform halving operations on each of the first sum data in the first column sum data to obtain column interpolation data. Send a second write enable signal to the cache circuit to store at least one pair of adjacent data elements corresponding to row interpolation data in the free storage location between at least one pair of adjacent data elements in the row direction of the cache circuit; and store at least one pair of adjacent data elements corresponding to column interpolation data in the free storage location between at least one pair of adjacent data elements in the column direction of the cache circuit; determine the output array based on the row interpolation data and the column interpolation data.

9. The data processing apparatus according to claim 6, wherein, The controller also includes: The instruction parsing unit is configured to receive and parse the data processing configuration instruction to obtain the configuration instruction information. The data dimension counter is configured to initialize the count values ​​corresponding to different dimensions in response to receiving the data processing configuration instruction; or, in response to the controller reading the data element from the storage circuit, the data dimension counter updates the count values ​​corresponding to different dimensions. A segmentation counter is configured to initialize its count value in the data block dimension in response to receiving the data processing configuration instruction; or, in response to a first overflow signal generated by the data dimension counter, update its count value in the data block dimension; wherein the input array includes at least one of the data blocks; the first overflow signal is generated when the count value of the data dimension counter in different dimensions reaches the boundary value of the dimension corresponding to the currently read data block; The address generation unit is configured to generate a read / write access address based on the count values ​​of the data dimension counter in different dimensions, the count value of the segmentation counter in the data block dimension, the starting address, the dimension information, and the data bit width information. The read / write unit is configured to send a read / write access request to the storage circuit according to the read / write access address, so as to read multiple data elements from the input array from the storage circuit.

10. The data processing apparatus according to claim 9, wherein the data dimension counter is further configured to: after reading the data element from the storage circuit, the count of the data dimension counter increments sequentially according to a preset data dimension order; in, The preset data dimensions are ordered sequentially as channel dimension, column dimension, row dimension, and batch dimension, and the data dimension counter is specifically configured as follows: When the count of the channel dimension overflows, the count value of the column dimension is incremented by 1, and the count value of the channel dimension is initialized. When the column dimension count overflows, the row dimension count is incremented by 1, and the channel dimension and column dimension counts are initialized. When the count of the row dimension overflows, the count value of the batch dimension is incremented by 1, and the count values ​​of the channel dimension, the column dimension, and the row dimension are initialized. or, The preset data dimensions, in order, include channel dimension, row dimension, column dimension, and batch dimension. The data dimension counter is specifically configured as follows: When the count of the channel dimension overflows, the count value of the row dimension is incremented by 1, and the count value of the channel dimension is initialized. When the row dimension count overflows, the column dimension count is incremented by 1, and the channel dimension and row dimension counts are initialized. When the count of the column dimension overflows, the count value of the batch dimension is incremented by 1, and the count values ​​of the channel dimension, the row dimension, and the column dimension are initialized.

11. The data processing apparatus according to claim 10, wherein, The data dimension counter is further configured to generate the first overflow signal when the count value of the row dimension reaches the row boundary value corresponding to the currently read data block and the count value of the column dimension exceeds the column boundary value corresponding to the currently read data block; The segmentation counter is further configured to, in response to the first overflow signal generated by the data dimension counter, increment the count value of the data block dimension by 1 and send the updated count value of the data block dimension to the address generation unit when the count value of the data block dimension is less than a second preset threshold; the second preset threshold is determined based on the dimension information of the input array and the dimension information of the data block. The address generation unit is further configured to switch the starting address corresponding to the current data block to the starting address corresponding to the next data block in response to the updated count value of the data block dimension. The data dimension counter is further configured to initialize the count values ​​of the column dimension and the row dimension in the data dimension counter after the split counter increments the count value of the current data block by 1, while keeping the count values ​​of the channel dimension and the batch dimension unchanged.

12. The data processing apparatus according to claim 11, wherein, The segmentation counter is further configured to generate a second overflow signal in response to the first overflow signal generated by the data dimension counter when the count value of the data block dimension reaches the second preset threshold. The control signal sending unit is further configured to stop sending the first write enable signal to the cache circuit in response to the second overflow signal, so as to control the cache circuit to stop storing the data elements in the input array; And when it is detected that all the data elements stored in the cache circuit have been sent to the interpolation circuit, the read enable signal is stopped from being sent to the cache circuit; The read enable signal is sent by the control signal sending unit to the cache circuit when it detects that the number of data elements stored in the cache circuit has reached a first preset threshold, so as to control the cache circuit to output the data elements to the interpolation circuit.

13. The data processing apparatus according to any one of claims 6-12, wherein, The configuration instruction information also includes the target magnification factor of the input array, where the target magnification factor is 2 raised to the power of N, and N is a positive integer; The controller is also configured to: After each time the output array is determined, the number of iterations completed is incremented by 1; If the number of completed iterations has not reached N, the currently output array is determined as the input array for the next iteration. The cache circuit is controlled to store the newly determined input array, and the interpolation circuit is controlled to perform interpolation operations based on the newly determined input array until the number of completed iterations reaches N. If the number of iterations reaches N, stop the iteration and determine the output array obtained in this iteration as the final output array.

14. The data processing apparatus according to claim 8, wherein, The interpolation circuit also includes a first row register, a second row register, and a data selector; The first row register is configured to store the i-th row of data elements read from the cache circuit, where i is an integer greater than or equal to 0; The second row register is configured to store the (i+2)th row of data elements read from the cache circuit; The first row register is electrically connected to the first input terminal of the addition calculation sub-circuit, the first row register and the second row register are respectively electrically connected to the input terminal of the data selector, and the output terminal of the data selector is electrically connected to the second input terminal of the addition calculation sub-circuit; The data selector is configured as follows: In row interpolation mode, in response to the first data selection signal sent by the control signal sending unit, the bus between the second row register and the second input terminal of the addition calculation sub-circuit is selected, so that the addition calculation sub-circuit performs addition operation on at least one pair of data elements located in the same column in the first row register and the second row register respectively to obtain the first row sum data corresponding to the row direction, and the halving calculation sub-circuit performs halving operation on each of the first sum data in the first row sum data to obtain the row interpolation data; In column interpolation mode, in response to the second data selection signal sent by the control signal sending unit, the bus between the first row register and the second input terminal of the addition calculation sub-circuit is turned on, so that the addition calculation sub-circuit performs addition operation on at least one pair of adjacent data elements in the first row register to obtain the first column sum data corresponding to the column direction, and the halving calculation sub-circuit performs halving operation on each of the first sum data in the first column sum data to obtain the column interpolation data; The data selection signal includes the first data selection signal and the second data selection signal.

15. A data processing method, comprising: The buffer circuit stores multiple data elements of the input array; An addition operation is performed on two adjacent data elements stored in the cache circuit to obtain the first sum data; Perform a halving operation on the first summed data to obtain the interpolated data; The interpolated data corresponding to adjacent data elements is stored in the free storage location of the cache circuit; The output array is determined based on the interpolated data.

16. A computer-readable storage medium storing a computer program that is executed by a processor to perform the data processing method of claim 15.

17. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the data processing method of claim 15.

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