A first-level data cache device, a processor and a computer device

Abstract

The application discloses a kind of primary data cache device, processor and computer equipment, comprising: main cache module, sacrificial cache module, execution control module and query module;Query module is electrically connected with processor core, for receiving the instruction to be executed that processor core issues;The query module according to the address of the instruction to be executed parallelly inquires the hit state of the main cache module and the sacrificial cache module, obtains hit state signal;The execution control module is electrically connected with the query module, for according to the hit state signal control sacrificial cache module executes operation operation;The sacrificial cache module is used for executing operation according to the instruction to be executed and obtains operation result and execution completion signal, and the sacrificial cache module transmits the execution completion signal to the processor core.In the application, the hit state of main cache module and sacrificial cache module is inquired by query module in parallel, and the overall operation efficiency of processor is improved.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a level 1 data cache device, a processor, and a computer device. Background Technology

[0002] The L1 cache is a high-speed buffer between the processor core and external memory, and its access latency and throughput directly determine the overall operating efficiency of the processor. With the popularization of multi-core processor architectures, atomic operations, as the core mechanism for achieving synchronization and mutual exclusion among multiple cores, have become a key bottleneck restricting the concurrency capabilities of multi-core processor architectures.

[0003] In existing technologies, first-level data caches generally adopt a two-level storage architecture of main cache and sacrificial cache. When the instruction to be executed hits the sacrificial cache, it is still necessary to wait for the main cache query to be completed and for the main cache to be determined to be missing before the sacrificial cache query can be initiated, resulting in low running efficiency. Summary of the Invention

[0004] This invention provides a primary data caching device, processor, and computer equipment that solves the core problem of excessive latency in atomic operations caused by serial queries between the main cache and the sacrificial cache through a parallel query architecture, thereby improving operating efficiency.

[0005] According to one aspect of the present invention, a primary data caching device is provided, comprising: a main cache module, a sacrificial cache module, an execution control module, and a query module; The query module is electrically connected to the processor core and is used to receive the instruction to be executed issued by the processor core; the query module queries the hit status of the main cache module and the sacrificial cache module in parallel according to the address of the instruction to be executed, and obtains the hit status signal. The execution control module is electrically connected to the query module and is used to control the sacrificial cache module to perform computational operations according to the hit status signal; The sacrificial cache module is used to perform operations according to the instruction to be executed to obtain the operation result and the execution completion signal, and the sacrificial cache module transmits the execution completion signal to the processor core.

[0006] Optional, also includes: Memory access control module, collaborative arbitration module, cross-queue data forwarding module, and protocol linkage module; The execution control module is electrically connected to the memory access control module, the collaborative arbitration module, the cross-queue data forwarding module, and the protocol linkage module, respectively, and is used for scheduling. The memory access control module is electrically connected to the sacrificial cache module and is used to control the block-level read and write operations of the sacrificial cache module. The collaborative arbitration module is electrically connected to the main cache module and the sacrificial cache module respectively, and is used to schedule the execution of memory access instructions and atomic operation instructions; The cross-queue data forwarding module is electrically connected to the collaborative arbitration module and is used to realize data forwarding between the main cache module and the sacrificial cache module. The protocol linkage module is electrically connected to the sacrificial cache module and the external consistency bus respectively, and is used to implement cache consistency control.

[0007] Optionally, the sacrificial cache module includes an atomic operation unit, a register array unit, a verification unit, and a data write-back unit; The register array unit is used to store the instruction to be executed, intermediate values, and the result of the operation. The verification unit is electrically connected to the register array unit and is used to verify and correct the original data corresponding to the instruction to be executed, so as to obtain the verified data. The atomic arithmetic unit is used to perform calculations based on the instruction to be executed and the verified data to obtain the calculation result; The data write-back unit is electrically connected to the atomic operation unit and is used to write the operation result into the cache line corresponding to the verified instruction to be executed.

[0008] Optionally, the query module includes: an address splitting unit, a parallel tag query unit, a parallel comparison unit, and a result merging unit; The address splitting unit is used to split the address of the instruction to be executed into a tag segment, an index segment, and an offset segment; The parallel tag query unit is electrically connected to the address splitting unit and is used to query tag data in parallel according to the index segment to obtain the main cache tag data and the sacrifice cache tag data. The parallel comparison unit is electrically connected to the parallel tag query unit and is used to compare the tag segment with the main cache tag data and the sacrifice cache tag data respectively to obtain the first hit result and the second hit result. The result merging unit is electrically connected to the parallel comparison unit and is used to standardize the first hit result and the second hit result to obtain a hit status signal. The hit status signal includes a main cache hit signal, a main cache miss signal, a sacrifice cache hit signal, and a sacrifice cache miss signal.

[0009] Optionally, the memory access control module includes a block address resolution unit, a block access detection unit, a read path control unit, a byte enable mask generation unit, and a block control unit; The block address parsing unit parses and calculates block information based on the instruction to be executed, and the block information includes block number and intra-block offset; The block access detection unit is electrically connected to the block address resolution unit and is used to determine the block access status based on the block information. The block access status includes full access and partial access. The read path control unit is electrically connected to the block access detection unit and is used to output a read path control signal according to the access status. The read path control signal includes a read path fully closed signal and a read path partially closed signal. The byte enable mask generation unit is electrically connected to the block address parsing unit and the query module, and is used to obtain the byte enable mask according to the offset segment and the byte bits corresponding to the intra-block offset enable. The block control unit is electrically connected to the read path control unit and the byte enable mask generation unit, and is used to generate a block write enable signal and a block read enable signal according to the read path control signal and the enable mask.

[0010] Optionally, the execution control module is also electrically connected to the processor core; The execution control module includes: The token generation unit, token storage unit, address conflict detection unit, and token release unit are all included. The token generation unit is used to receive the instruction to be executed and to generate a different token tag for each instruction to be executed. The token register unit is used to store a token information list, which includes token information for at least one instruction; the token information includes the token tag, target address, operation status, and block number, and the operation status includes waiting, executing, and completing. The token release unit is used to clear the token information corresponding to the instruction to be executed after the sacrifice cache module issues the execution completion signal; The address conflict detection unit is electrically connected to the token register unit and is used to compare the address of the instruction to be executed with the address of the instruction to be executed to obtain a comparison result. The address of the instruction to be executed is the target address corresponding to the instruction whose operation state is executed. When the comparison results are the same, the token register unit stores the token information of the instruction to be executed and sets the operation state to wait; When the comparison results are different, the token register unit stores the token information of the instruction to be executed and sets the operation state to execution.

[0011] Optionally, the collaborative arbitration module includes a main cache storage queue unit, a sacrifice cache storage queue unit, a two-level write merging unit, and a dynamic priority arbitration unit; The main cache storage queue unit is used to store memory access instructions; The sacrifice cache storage queue unit is used to store atomic operation instructions; The dynamic priority arbitration unit is electrically connected to the main cache storage queue unit and the sacrifice cache storage queue unit, and is used to arbitrate the instruction release order according to the preset priority rules to obtain the arbitration result. The two-level write merging unit is used to merge the write instructions in the memory access instructions and the atomic operation instructions at the byte level and the address level to obtain batch write data and batch write control signals; It also includes a cross-queue data forwarding module; The cross-queue data forwarding module is electrically connected to the main cache storage queue unit and the sacrifice cache storage queue unit, and is used for cross-queue data forwarding.

[0012] Optionally, the protocol linkage module includes an extended status register unit, a status comparison and discrimination unit, an exclusive request generation unit, a consistency broadcast control unit, and a sniffing response unit; The extended status register unit is used to store the consistency status of each cache line in the sacrifice cache module. The consistency status includes modified, exclusive, shared, invalid, atomic exclusive, and atomic modified. The state comparison and discrimination unit is electrically connected to the token register unit and the extended state register unit, and is used to obtain a discrimination result based on the token information and the consistency state. The discrimination result includes cache line status and permission change signal. The exclusive request generation unit is electrically connected to the state comparison and discrimination unit, and is used to send an exclusive request signal to the external consistency bus according to the permission change signal. The consistency broadcast control unit is electrically connected to the state comparison and discrimination unit and is used to generate a state change broadcast message according to the state transition instruction. The sniffing response unit is electrically connected to the external consistency bus and is used to receive external listening requests and respond to the listening requests according to state transition instructions.

[0013] According to a second aspect of the invention, a processor is provided, the processor including at least one first-level data cache device as described above.

[0014] According to a third aspect of the present invention, a computer device is provided, the computer device comprising at least one processor, the processor including at least one first-level data cache device as described above.

[0015] A primary data caching device provided in this invention includes: a main cache module, a sacrificial cache module, an execution control module, and a query module. The query module is electrically connected to the processor core and is used to receive instructions to be executed issued by the processor core. The query module queries the hit status of the main cache module and the sacrificial cache module in parallel according to the address of the instruction to be executed, and obtains a hit status signal. The execution control module is electrically connected to the query module and is used to control the sacrificial cache module to perform arithmetic operations according to the hit status signal. The sacrificial cache module performs arithmetic operations according to the instruction to be executed, obtains a result and an execution completion signal, and transmits the execution completion signal to the processor core. This invention eliminates the additional latency of sacrificial cache hits in traditional serial query architectures by using a query module to query the hit status of the main cache module and the sacrificial cache module in parallel, thereby improving the overall operating efficiency of the processor.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a module structure diagram of a primary data caching device provided in an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, any variations of the terms "comprising" and "having" are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions: It should be noted that, in order to more clearly demonstrate the technical solution of this embodiment, the process of the first-level data cache device receiving and executing the instruction to be executed is divided into clock cycles T0-T8, and then the workflow of each module is described according to the clock cycle.

[0022] Figure 1 This is a module structure diagram of a primary data caching device provided in an embodiment of the present invention, with reference to... Figure 1 This embodiment provides a primary data caching device comprising: a main cache module 1, a sacrificial cache module 2, an execution control module, and a query module; the query module is electrically connected to the processor core and is used to receive instructions to be executed issued by the processor core; the query module 4 queries the hit status of the main cache module 1 and the sacrificial cache module 2 in parallel according to the address of the instructions to be executed, and obtains a hit status signal; the execution control module 3 is electrically connected to the query module 4 and is used to control the sacrificial cache module 2 to perform arithmetic operations according to the hit status signal; the sacrificial cache module 2 is used to perform arithmetic operations according to the instructions to be executed to obtain a calculation result and an execution completion signal, and the sacrificial cache module 2 transmits the execution completion signal to the processor core.

[0023] In this embodiment, the instructions to be executed include memory access instructions and atomic operation instructions. For example, memory access instructions include read instructions and write instructions, and atomic operation instructions include atomic load increment, atomic load decrement, atomic bitwise AND, atomic bitwise OR, atomic bitwise XOR, and atomic comparison swap.

[0024] The specific workflow is as follows: Clock cycle T0: The processor core issues an instruction to be executed, which includes a 64-bit physical address, operation type, and operands. The physical address is sent to the query module 4, where the 64-bit physical address is the address of the instruction to be executed. Clock cycle T1: Query module 4 simultaneously sends query requests to both main cache module 1 and sacrificial cache module 2; Clock cycle T2: Query module 4 queries the hit status of main cache module 1 and sacrificed cache module 2 based on the 64-bit physical address and obtains the hit status signal; Clock cycle T3: If the execution control module 3 hits the sacrificial cache module 2 based on the hit status signal, it sends an operation enable signal to the sacrificial cache module 2. Clock cycles T4-T8: Sacrifice cache module 2 executes atomic operation instructions and returns an execution completion signal to the processor core upon completion.

[0025] In this embodiment, the query module 4 queries the hit status of the main cache and the sacrificial cache in parallel. The sacrificial cache query can be initiated without waiting for the main cache query to complete, which improves the overall operating efficiency of the processor. On the other hand, in this embodiment, the sacrificial cache module 2 can execute atomic operation instructions locally without moving data to the main cache module 1 or other cache modules, which further improves the overall operating efficiency of the processor.

[0026] In one implementation, the primary data caching device provided in this embodiment further includes: a memory access control module, a collaborative arbitration module, a cross-queue data forwarding module, and a protocol linkage module; the execution control module 3 is electrically connected to the memory access control module, the collaborative arbitration module, the cross-queue data forwarding module, and the protocol linkage module respectively, and is used for scheduling; the memory access control module is electrically connected to the sacrificial cache module 2, and is used to control the block-level read and write operations of the sacrificial cache module 2; the collaborative arbitration module is electrically connected to the main cache module 1 and the sacrificial cache module 2 respectively, and is used to schedule the execution of memory access instructions and atomic operation instructions; the cross-queue data forwarding module is electrically connected to the collaborative arbitration module, and is used to realize data forwarding between the main cache module 1 and the sacrificial cache module 2; the protocol linkage module is electrically connected to the sacrificial cache module 2 and the external consistency bus respectively, and is used to realize cache consistency control.

[0027] In this embodiment, block-level read / write refers to reading and writing operations on a per-BANK basis, where each block can be addressed and switched on and off independently. The external coherence bus is an on-chip bus that is electrically connected to the caches of each core in the multi-core processor. It is used to transmit cache coherence requests and response signals. The external coherence bus adopts the standard Network On Chip (NoC) physical layer protocol.

[0028] Specifically, in this embodiment, the execution control module 3 uniformly schedules the execution of the memory access control module, the collaborative arbitration module, the cross-queue data forwarding module, and the protocol linkage module. The memory access control module controls the block-level read and write operations of the sacrificial cache module 2. The collaborative arbitration module schedules the execution order of memory access instructions and atomic operation instructions. The cross-queue data forwarding module realizes data forwarding between the main cache module 1 and the sacrificial cache module 2. The protocol linkage module realizes multi-core cache consistency control. After receiving the hit status signal output by the query module 4, the execution control module 3 sends enable signals to the corresponding modules based on the hit result: if the sacrificial cache hits, it sends a memory access enable signal to the memory access control module and a consistency check enable signal to the protocol linkage module; if the main cache hits, it sends a main cache memory access enable signal to the collaborative arbitration module; if both caches are missing, it sends a secondary data cache access enable signal to the collaborative arbitration module.

[0029] In one possible implementation, the sacrificial cache module 2 includes an atomic operation unit, a register array unit, a verification unit, and a data write-back unit; the register array unit is used to store the instruction to be executed, intermediate operation values, and the operation results; the verification unit is electrically connected to the register array unit and is used to verify and correct the original data corresponding to the instruction to be executed to obtain the verified data. The atomic operation unit is used to perform operations based on the instruction to be executed and the verified data to obtain the operation result; the data write-back unit is electrically connected to the atomic operation unit and is used to write the operation result into the cache line corresponding to the verified instruction to be executed.

[0030] Specifically, in this embodiment, the atomic operation unit is a 64-bit multi-mode operation circuit implemented with hard-wired combinational logic, supporting six types of atomic operations: atomic loading increment, atomic loading decrement, atomic bitwise AND, atomic bitwise OR, atomic bitwise XOR, and atomic comparison swap. It supports dynamic bit width switching of 8-bit, 16-bit, 32-bit, and 64-bit, directly controlled by the lowest 3 bits of the instruction to be executed, with a switching latency of 0. The register array unit consists of a grouped register array composed of 12 64-bit D flip-flops, physically divided into an operation array, an intermediate result group, and a write-back result group, with 4 registers in each group. The write latency is 0, and the read latency is 1 / 4 clock cycle. The verification unit adopts a real-time verification and error correction circuit with a (72,64) Hamming code structure, which can complete single-bit error correction and double-bit error detection in a single cycle, and synchronously report the error status to the processor error status register. The data write-back unit is a 4-to-1 multiplexer structure, with input sources including the atomic operation unit output, the register array unit output, the main cache queue forwarding data, and the secondary cache fill data. The output directly drives the sacrificial cache module 2.

[0031] In this embodiment, the sacrificial cache module 2 also includes a sacrificial cache data storage array for storing data. The specific workflow is as follows: Clock cycle T2: When the sacrificial cache hit signal is valid, the sacrificial cache module 2 enable signal is pulled high, the sacrificial cache data storage array starts the read operation, and reads the 64-bit original data and 8-bit error correction code (ECC) of the target cache line. Clock cycle T3: The read raw data is sent to the verification unit to complete the verification and error correction. If there is no error, the verified data is directly sent to the operation array of the register array unit. If there is a single bit error, the verification unit automatically corrects the error and sends the verified data to the operation array, while reporting the error correction status. If there is a double bit error, an uncorrectable error is reported and the instruction is resent. Clock cycle T4: The instruction type signal sent by the execution control module 3 controls the atomic operation unit to enter the corresponding working mode. The verified data and the operands given by the processor are sent into the atomic operation unit in parallel, and the atomic operation unit starts combinational logic operation. Clock cycle T5: After the atomic operation is completed, the operation result is sent to the intermediate result group latch of the register array unit, and at the same time the protocol linkage module starts the consistency status check. Clock cycle T6: After the consistency status check passes, the intermediate results are transferred from the intermediate result group to the write-back result group for temporary storage, in preparation for write-back; Clock cycle T7: The data write-back unit selects the write-back result group output, writes the calculation result into the corresponding cache line of the sacrificial cache module 2, and sets the dirty bit of the cache line to 1, while keeping the tag information unchanged; Clock cycle T8: Sacrifice cache module 2 outputs an execution completion signal to execution control module 3 and processor core, the exclusive mark is cleared, and this atomic operation exits the execution unit.

[0032] This embodiment achieves local full-process execution of atomic operations by integrating independent atomic operation units, register array units, verification units, and data write-back units within the sacrificial cache module 2. This eliminates the need to move data to the main cache or secondary data cache device, reducing the latency of memory access levels and data movement.

[0033] In one possible implementation, the query module 4 includes: an address splitting unit, a parallel tag querying unit, a parallel comparison unit, and a result merging unit; the address splitting unit is used to split the address of the instruction to be executed into a tag segment, an index segment, and an offset segment; the parallel tag querying unit is electrically connected to the address splitting unit and is used to query tag data in parallel according to the index segment to obtain main cache tag data and sacrifice cache tag data; the parallel comparison unit is electrically connected to the parallel tag querying unit and is used to compare the tag segment with the main cache tag data and the sacrifice cache tag data respectively to obtain a first hit result and a second hit result; the result merging unit is electrically connected to the parallel comparison unit and is used to standardize the first hit result and the second hit result to obtain a hit status signal, the hit status signal including a main cache hit signal, a main cache miss signal, a sacrifice cache hit signal, and a sacrifice cache miss signal.

[0034] In this embodiment, the tag segment is the high 42 bits of the physical address, used to identify the memory address range corresponding to the cache line; the index segment is the middle 13 bits of the physical address, used to address the storage location of the cache line in the tag memory (Random Access Memory, RAM); the offset segment is the low 9 bits of the physical address, used to locate the specific byte position within the cache line; standardizing the first hit result and the second hit result means converting the preliminary level signal output by the parallel comparison unit into a standard digital signal with a unified format and no glitches, keeping it stable until the next clock cycle, ensuring that the downstream module can sample stably.

[0035] The specific workflow is as follows: Clock cycle T0: The processor core issues an instruction to be executed, and the 64-bit physical address of the instruction to be executed is sent to the address splitting unit; Clock cycle T1: The address splitting unit splits the physical address into a 42-bit tag segment, a 13-bit index segment, and a 9-bit offset segment. The index segment is simultaneously sent to the main cache tag RAM and the sacrificial cache dual-port tag RAM in the parallel tag query unit. Clock cycle T2: The parallel tag query unit reads the main cache tag data and the sacrifice cache tag data in parallel. The parallel comparison unit compares the tag segment with the two tag data respectively to generate the first hit result and the second hit result. The first hit result is either the main cache module 1 is hit or the main cache module 1 is missing. The second hit result is either the sacrifice cache module 2 is hit or the sacrifice cache module 2 is missing. Clock cycle T3: The result merging unit latches and standardizes the two hit results, generates four hit status signals, and sends them to the execution control module 3.

[0036] In this embodiment, the query module 4 also embeds a result priority rule. The result priority principle is that when the main cache module 1 and the sacrifice cache module 2 are both hit, the main cache path is selected first; when the main cache module 1 is missing and the sacrifice cache module 2 is hit, the execution path of the sacrifice cache is directly switched, without waiting for the main cache missing process, and without sending a missing request to the second-level cache.

[0037] In one possible implementation, the memory access control module includes a block address parsing unit, a block access detection unit, a read path control unit, a byte enable mask generation unit, and a block control unit. The block address parsing unit parses and calculates block information based on the instruction to be executed, the block information including a block number and an intra-block offset. The block access detection unit is electrically connected to the block address parsing unit and is used to determine the block access state based on the block information, the block access state including full access and partial access. The read path control unit is electrically connected to the block access detection unit and is used to output a read path control signal based on the access state, the read path control signal including a read path full disable signal and a read path partial disable signal. The byte enable mask generation unit is electrically connected to the block address parsing unit and the address splitting unit and is used to obtain a byte enable mask based on the byte bits corresponding to the offset segment and the intra-block offset enable. The block control unit is electrically connected to the read path control unit and the byte enable mask generation unit and is used to generate a block write enable signal and a block read enable signal based on the read path control signal and the enable mask.

[0038] In this embodiment, the block number refers to the unique 4-bit number that identifies the 14 physical blocks in the sacrificial cache module 2; the block offset refers to the specific byte position inside the physical block, which is 7 bits in total; the byte enable mask refers to the 8-bit binary signal corresponding to the 14 physical blocks, with each bit corresponding to the read / write enable of one byte, where 1 indicates that the byte needs to be read / written, and 0 indicates that the byte does not need to be operated.

[0039] The specific workflow is as follows: Clock cycle T2: The block address resolution unit receives the physical address and instruction length of the instruction to be executed, and calculates the target block number and the offset within the block; Clock cycle T3: The block access detection unit determines whether it is a full access or a partial access based on the number of bytes accessed; the read path control unit generates a read path control signal based on the access status, and closes the read path for a full access; for a partial access, it outputs a read path partial close signal, opening only the target physical block read path and closing the idle physical block read path; the byte enable mask generation unit generates a precise byte enable mask based on the offset segment and the block offset; Clock cycle T4: The block control unit combines the read path control signal and the byte enable mask to generate the final block write enable signal and block read enable signal and send them to the sacrificial buffer module 2.

[0040] In this embodiment, the memory access control module locates the target physical block through the block address resolution unit. During non-aligned access, the block access detection unit identifies the block access status as partial access, the read path control unit closes the read path of the idle physical block, the core byte enable mask generation unit generates a byte enable mask, and only activates the non-accessed bytes. Finally, the block control unit outputs read and write enable, so that non-aligned access does not require full physical block read and write, but only operates on the target byte, reducing invalid operations and reducing latency and power consumption.

[0041] In one possible implementation, the execution control module 3 is also electrically connected to the processor core; the execution control module 3 includes: a token generation unit, a token register unit, an address conflict detection unit, and a token release unit; the token generation unit is used to receive the instruction to be executed and generate a different token tag for each instruction to be executed; the token register unit is used to store a token information list, the token information list including token information for at least one instruction; the token information includes the token tag, target address, operation status, and block number, the operation status including waiting, executing, and completing; the address conflict detection unit is connected to the token register unit... The storage unit is electrically connected and is used to compare the address of the instruction to be executed with the address of the instruction to be executed to obtain a comparison result. The address of the instruction to be executed is the target address corresponding to the instruction whose operation state is executed. When the comparison result is the same, the token storage unit stores the token information of the instruction to be executed and sets the operation state to wait. When the comparison result is different, the token storage unit stores the token information of the instruction to be executed and sets the operation state to execute. The token release unit is used to clear the token information corresponding to the instruction to be executed after the sacrifice cache module 2 issues the execution completion signal.

[0042] In this embodiment, the token tag is an 8-bit unique identifier generated using a Linear Feedback Shift Register (LFSR) to distinguish different instruction instances. It is generated in a single cycle and has no duplicates. The token information list refers to a register array with a depth of 32 entries, used to store information on all instructions to be executed and currently being executed in the current system. The address conflict detection unit adopts a Content Addressed Memory (CAM) structure, which compares the physical address of a newly entered atomic operation instruction with the address currently being executed in the register array in parallel, and outputs a conflict signal in a single cycle.

[0043] The specific workflow is as follows: Clock cycle T0: The instruction to be executed is sent to the token generation unit to generate a unique 8-bit token tag; Clock cycle T1: Token information is written to the token register unit. The address conflict detection unit compares the physical address of the instruction to be executed with the addresses of all currently executing instructions in the register array in parallel. If the comparison result is that the addresses are different, it is determined that there is no conflict, the operation state is set to execute, and the execution process is started immediately. If the comparison result is that the addresses are the same, it is determined that there is a conflict, the operation state is set to wait, and the instruction is temporarily stored in the token register unit. Clock cycle T7: Sacrifice cache module 2 outputs execution completion signal, token release unit clears the corresponding token item, and wakes up the next instruction at the same address in the waiting queue.

[0044] In this embodiment, if the verification unit of the sacrifice cache module 2 reports an uncorrectable error and triggers instruction retransmission, the token information in the execution control module 3 is forcibly invalidated, and the token generation unit re-receives the next instruction to be executed. This embodiment uses a tokenized non-blocking scheduling mechanism to replace the traditional cache line locking, blocking only subsequent atomic operation instructions at the same address, allowing atomic operation instructions and memory access instructions at different addresses to execute in parallel, thus improving the processor's operating efficiency.

[0045] In one implementation, the collaborative arbitration module includes a main cache storage queue unit, a sacrifice cache storage queue unit, a two-level write merging unit, and a dynamic priority arbitration unit; the main cache storage queue unit is used to store memory access instructions; the sacrifice cache storage queue unit is used to store atomic operation instructions. The dynamic priority arbitration unit is electrically connected to the main cache storage queue unit and the sacrifice cache storage queue unit, and is used to arbitrate the instruction release order according to the preset priority rules to obtain the arbitration result. The two-level write merging unit is used to merge the write instructions in the memory access instructions and the atomic operation instructions at the byte level and the address level to obtain batch write data and batch write control signals; it also includes a cross-queue data forwarding module; the cross-queue data forwarding module is electrically connected to the main cache storage queue unit and the sacrificial cache storage queue unit, and is used for cross-queue data forwarding.

[0046] In this embodiment, the preset priority rule is a fixed weight priority, from high to low: atomic operation instructions, read instructions, write instructions, and idle operations. Instructions with the same priority are executed by hashing the address to avoid starvation. Byte-level merging refers to retaining the latest byte, overwriting the old byte, and discarding invalid old data for write instructions and atomic operation instructions with the same address but different bytes. Address-level merging refers to merging atomic operation instructions with consecutive addresses and the same type into batch operations to reduce the number of physical block accesses. Cross-queue data forwarding refers to realizing direct data transmission between the main cache storage queue and the sacrifice cache storage queue through a 256-bit hardware path, completing data transfer in a single cycle without writing to the storage array.

[0047] Specifically, in this embodiment, memory access instructions enter the main cache storage queue unit, and atomic operation instructions enter the sacrificial cache storage queue unit. The dynamic priority arbitration unit monitors the status of the two queues in real time and selects the next instruction to be executed according to the preset priority rules. The selected write instruction is sent to the two-level write merging unit, which first performs byte-level merging and then address-level merging. When an atomic operation instruction hits the sacrificial cache, but the latest data is temporarily stored in the main cache storage queue unit, the cross-queue data forwarding module detects the address match and moves the data from the main cache storage queue unit to the sacrificial cache storage queue unit in a single cycle. The corresponding item in the main cache module 1 is automatically marked as invalid and discarded. If the query module 4 determines in cycle T2 that both the main cache module 1 and the sacrificial cache module 2 are missing, the instruction to be executed is sent to the write missing buffer of the sacrificial cache module 2, and a read request is sent to the secondary data cache device. After the data from the next data cache device returns, it is directly sent across the queue to the atomic operation unit of the sacrificial cache module 2 without going through the main cache or being written to the main cache.

[0048] In one possible implementation, the protocol linkage module includes an extended state register unit, a state comparison and discrimination unit, an exclusive request generation unit, a consistency broadcast control unit, and a sniffing response unit. The extended state register unit stores the consistency status of each cache line in the sacrifice cache module 2, including modified, exclusive, shared, invalid, atomic exclusive, and atomic modified states. The state comparison and discrimination unit is electrically connected to the token register unit and the extended state register unit, and is used to obtain a discrimination result based on the token information and the consistency status. The discrimination result includes the cache line status and a permission change signal. The exclusive request generation unit is electrically connected to the state comparison and discrimination unit, and is used to send an exclusive request signal to the external consistency bus based on the permission change signal. The consistency broadcast control unit is electrically connected to the state comparison and discrimination unit, and is used to generate a state change broadcast message based on the state transition instruction. The sniffing response unit is electrically connected to the external consistency bus, and is used to receive external listening requests and respond to the listening requests based on the state transition instruction.

[0049] The specific workflow is as follows: Clock cycle T3: The state comparison and discrimination unit queries the extended state register unit. If the current state is shared (S), the exclusive request generation unit is triggered to send a "request exclusive" message. After the external consistency bus responds, the consistency state switches to atomic exclusive (AE), and then the sacrifice cache module 2 performs the operation. If the current state is exclusive (E) or modified (M), the sacrifice cache module 2 performs the operation directly without bus interaction. Clock cycles T4-T6: Maintain the atomic's dedicated state, reject external exclusive requests, and allow listening requests; Clock cycle T7: After the operation of the sacrifice cache module 2 is completed, the state is updated. consistency State transition to atomic modification (AM); consistency broadcast control unit sends state change broadcast. Message In a multi-core processor system, other processor cores invalidate the consistency status of the corresponding cache line; sniffing process: when an external listening request hits the cache line corresponding to the atomic operation instruction, the sniffing response unit returns a "busy" response, waits for the atomic operation instruction to complete, and then returns the operation data and consistency status.

[0050] In this embodiment, the protocol linkage module extends the atomic operation instruction-specific state on the basis of the standard MESI protocol. Combined with the differentiated sniffing response mechanism, it reduces the interference of external requests on the atomic operation process while ensuring the cache consistency of the multi-core processor system, avoids frequent interruptions of atomic operations, and improves the execution efficiency of atomic operation instructions.

[0051] In a second aspect, the present invention also provides a processor, the processor including at least one first-level data cache device as described above.

[0052] Thirdly, the present invention also provides a computer device comprising at least one processor, the processor including at least one first-level data cache device as described above.

[0053] The following are exemplary application examples of the primary data caching device provided in the embodiments of the present invention: I. Hardware and System Configuration Clock synchronization is performed as follows: all modules in the primary data cache use the same processor core clock, and all registers are latched uniformly on the rising edge of the clock. The signal timing constraints are as follows: address signals and control signals are latched on the rising edge of clock cycle T0 and held until the falling edge of clock cycle T3; data signals are valid on the rising edge of clock cycle T3 and held until the falling edge of clock cycle T7; result signals are output on the rising edge of clock cycle T8 and held for one clock cycle.

[0054] The hardware interconnection specifications are as follows: all interconnections between modules are hardwired, with no software configuration registers, and no I2C or SPI configuration interfaces; error signals, completion signals, and status signals are directly connected to the processor core interrupt and status ports; the coherence bus interface is a NoC physical layer protocol, compatible with mainstream multi-core processor protocols.

[0055] The power consumption control adopted is as follows: during idle periods, unused physical blocks, arithmetic units, and comparator arrays are turned off; When atomic operation instructions are executed, only the corresponding physical block and computing path are activated, resulting in a 28% to 36% reduction in dynamic power consumption compared to traditional architectures.

[0056] The application system is configured as follows: the processor core has a clock speed of 1.2GHz, each processor core integrates the level 1 data cache device described in this invention, the level 2 data cache device has a total capacity of 2MB, and the on-chip coherence bus adopts the NoC physical layer protocol. In the level 1 data cache device, the main cache module 1 adopts a 48KB direct-mapped structure, and the sacrificial cache module 2 adopts a 16KB fully associative structure.

[0057] II. Specific Application Scenarios This application example simulates a multi-core concurrent synchronization scenario: The processor core initiates a 64-bit unaligned atomic compare-swap operation with a target physical address of 0x123456789ABCDEF0. The effective access bytes are bytes 3-8, with the expected original value being 0x1122334455667788 and the new value being 0x8877665544332211. The remaining 7 processor cores continuously initiate ordinary read and write memory access instructions and atomic operations at different addresses to verify the ability to execute multiple instructions in parallel.

[0058] The overall execution strictly follows the global timing synchronization specification. Each hardware module completes its operation sequentially according to the T0-T8 clock cycles, as follows: Clock cycle T0: Token generation The processor core issues a 64-bit unaligned atomic comparison swap instruction, outputting a 64-bit target physical address, atomic comparison swap operation type, and original and new operands; the target physical address signal is sent to the address splitting unit of the query module 4, and the instruction type is simultaneously sent to the token generation unit of the execution control module 3.

[0059] The token generation unit generates a unique 8-bit token tag 0x5A based on a linear feedback shift register. The address conflict detection unit compares the target physical address with the address of the instruction being executed in the token register in parallel. In this application example, there are no atomic operations being executed at the same address, so there is no address conflict.

[0060] Clock cycle T1: Collision detection The address splitting unit splits the 64-bit target physical address into a 42-bit tag segment, a 13-bit index segment, and a 9-bit offset segment within a single cycle, and outputs the three signals synchronously to the parallel tag query unit of the query module 4; the parallel tag query unit simultaneously starts the address matching logic of the tag RAM of the main cache module 1 and the dual-port tag RAM of the sacrifice cache module 2.

[0061] The execution control module 3 writes the token tag 0x5A, the lower 16 bits of the target physical address, the operation status to "execute", and the corresponding physical block number into the token register unit with a depth of 32. It reserves a shielding channel only for subsequent atomic operation instructions at the same address, and fully opens the path for ordinary memory access instructions and atomic operations at different addresses for the other 7 processor cores.

[0062] Clock cycle T2: Data read The parallel comparison unit of query module 4 completes the comparison of two tags and outputs the main cache missing signal and the sacrifice cache hit signal; the result merging unit latches the two results and directly switches to the execution path of sacrifice cache module 2 according to the preset priority rules, without sending a missing request to the secondary data cache device.

[0063] The block address resolution unit of the memory access control module completes address resolution and calculates the block number, block offset and number of bytes accessed; the block access detection unit determines it as a partial access; the byte enable mask generation unit generates a precise 14-channel 8-bit byte enable signal, enabling only the corresponding bits of bytes 3-8; the block control unit only opens the target physical block read / write path.

[0064] The dynamic priority arbitration unit of the collaborative arbitration module prioritizes atomic comparison and exchange operations based on the priority of "atomic operation instructions > read instructions > write instructions". The remaining core read and write instructions are temporarily stored in the corresponding queue buffers after one cycle, so that they are not lost or resent.

[0065] Simultaneously, the cache hit signal is valid, and the cache module 2 starts the read operation, reading the 64-bit original data 0x1122334455667788 and the 8-bit ECC check code of the target cache line.

[0066] Clock cycle T3: State detection The verification unit of the sacrificial cache module 2 performs (72,64) Hamming code verification on the read raw data. If there is no bit error, it is directly sent to the operation array of the register array unit. If a single bit error occurs, the verification unit automatically completes the error correction and sends it to the operation array, while reporting the error correction status to the processor error status register.

[0067] Before the protocol linkage module starts execution, it performs a status check and queries the extended status register unit to find that the current consistency status of the cache line is shared (S). The status comparison and discrimination unit triggers the exclusive request generation unit to generate a 96-bit exclusive request message and sends a "request exclusive" broadcast to the other 7 processor cores through the consistency bus. After the other cores complete the sniffing response and the bus acknowledges the success, the cache line status switches to atomic exclusive (AE), allowing the start of atomic operations.

[0068] Clock cycle T4: Atomic operations The instruction type signal controls the atomic operation unit of the sacrifice cache module 2 to enter the atomic comparison and exchange operation mode. The hardware combinational logic takes effect directly, without state machine or microcode delay. The expected original value, the new value to be exchanged and the original data output by the register array unit are sent to the atomic operation unit in parallel. The original data is compared according to the atomic comparison and exchange rules: if the original data is consistent with the expected original value, the exchange is determined to be valid and the numerical replacement operation is started.

[0069] The memory access control module only opens the read path of the target physical block, while the other physical blocks remain idle, effectively reducing dynamic power consumption; the normal memory access and heterogeneous address atomic operation instructions of the other 7 processor cores are executed in parallel without any blocking.

[0070] Clock cycle T5: Result temporary storage Once the atomic operation is complete, the result 0x8877665544332211 is latched into the intermediate result group of the register array unit; the protocol linkage module maintains the atomic exclusive (AE) state of this cache line, rejects external exclusive requests, and allows read sniffing operations; the execution control module 3 continuously monitors the token status and maintains the "execute" flag.

[0071] Clock cycle T6: Write-back preparation The protocol linkage module completes the second verification of the consistency status. There is no multi-core contention conflict, and the consistency check passes. The operation result is transferred from the intermediate result group of the register array unit to the write-back result group for temporary storage, and is ready to be written back to the sacrificial cache module 2. The collaborative arbitration module continuously ensures the smooth flow of data, and the other queue instructions are scheduled normally.

[0072] Clock cycle T7: Token release The data write-back unit of Sacrifice Cache Module 2 selects the write-back result group output and accurately writes 0x8877665544332211 into the corresponding cache line of Sacrifice Cache Module 2, sets the corresponding dirty bit to 1, and keeps the tag information unchanged.

[0073] The protocol linkage module switches the cache line state from atomic exclusive (AE) to atomic modification (AM); the consistency broadcast control unit sends a state change broadcast message, and after receiving the broadcast, the other 7 processor cores set the consistency state of the corresponding cache line to invalid (I), thus completing the multi-core data consistency synchronization.

[0074] The token release unit of execution control module 3 is linked to the data write-back signal to clear the token tag 0x5A in a single cycle and release the token register unit resources; the collaborative arbitration module releases the priority of atomic operations and the delayed normal memory access instructions resume normal execution.

[0075] Clock cycle T8: Execution complete Sacrifice cache module 2 outputs an execution completion signal to execution control module 3 and processor core, clears the exclusive mark, and officially exits the execution unit for this unaligned atomic comparison and swap operation; memory access control module resets all physical block enable signals and disables the clock gating of idle physical blocks; all hardware modules return to the idle state and wait for the next instruction to be scheduled.

[0076] III. Application Effect Verification In this application example, atomic operation instructions are executed without cache line locking or pipeline pauses. Only subsequent atomic operations at the same address are blocked, while other multi-core ordinary memory access and atomic operation instructions at different addresses are executed in parallel. The atomic operation unit embedded in the sacrificial cache module 2 enables local execution of atomic comparison and exchange operations, eliminating the need to move data across levels to the main cache module 1 and the secondary data cache device. The atomic-specific state is extended through the protocol linkage module to achieve accurate guarantee of multi-core data consistency. Non-aligned operations only activate the target physical block, reducing dynamic power consumption by 32% compared to traditional architectures. The query module 4 uses dual caches for parallel querying to eliminate serial judgment latency, reducing the overall atomic operation execution latency by 41% compared to existing technologies.

[0077] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0078] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A primary data caching device, characterized in that, include: The main cache module, the sacrificial cache module, the execution control module, and the query module; The query module is electrically connected to the processor core and is used to receive the instructions to be executed issued by the processor core; The query module queries the hit status of the main cache module and the sacrifice cache module in parallel based on the address of the instruction to be executed, and obtains the hit status signal; The execution control module is electrically connected to the query module and is used to control the sacrificial cache module to perform computational operations according to the hit status signal; The sacrificial cache module is used to perform operations according to the instruction to be executed to obtain the operation result and the execution completion signal, and the sacrificial cache module transmits the execution completion signal to the processor core.

2. The primary data caching device according to claim 1, characterized in that, Also includes: Memory access control module, collaborative arbitration module, cross-queue data forwarding module, and protocol linkage module; The execution control module is electrically connected to the memory access control module, the collaborative arbitration module, the cross-queue data forwarding module, and the protocol linkage module, respectively, and is used for scheduling. The memory access control module is electrically connected to the sacrificial cache module and is used to control the block-level read and write operations of the sacrificial cache module. The collaborative arbitration module is electrically connected to the main cache module and the sacrificial cache module respectively, and is used to schedule the execution of memory access instructions and atomic operation instructions; The cross-queue data forwarding module is electrically connected to the collaborative arbitration module and is used to realize data forwarding between the main cache module and the sacrificial cache module. The protocol linkage module is electrically connected to the sacrificial cache module and the external consistency bus respectively, and is used to implement cache consistency control.

3. The primary data caching device according to claim 2, characterized in that, The sacrificial cache module includes an atomic operation unit, a register array unit, a verification unit, and a data write-back unit; The register array unit is used to store the instruction to be executed, intermediate values, and the result of the operation. The verification unit is electrically connected to the register array unit and is used to verify and correct the original data corresponding to the instruction to be executed, so as to obtain the verified data. The atomic arithmetic unit is used to perform calculations based on the instruction to be executed and the verified data to obtain the calculation result; The data write-back unit is electrically connected to the atomic operation unit and is used to write the operation result into the cache line corresponding to the verified instruction to be executed.

4. The primary data caching device according to claim 3, characterized in that, The query module includes: an address splitting unit, a parallel tag query unit, a parallel comparison unit, and a result merging unit; The address splitting unit is used to split the address of the instruction to be executed into a tag segment, an index segment, and an offset segment; The parallel tag query unit is electrically connected to the address splitting unit and is used to query tag data in parallel according to the index segment to obtain the main cache tag data and the sacrifice cache tag data. The parallel comparison unit is electrically connected to the parallel tag query unit and is used to compare the tag segment with the main cache tag data and the sacrifice cache tag data respectively to obtain the first hit result and the second hit result. The result merging unit is electrically connected to the parallel comparison unit and is used to standardize the first hit result and the second hit result to obtain a hit status signal. The hit status signal includes a main cache hit signal, a main cache miss signal, a sacrifice cache hit signal, and a sacrifice cache miss signal.

5. The primary data caching device according to claim 4, characterized in that, The memory access control module includes a block address resolution unit, a block access detection unit, a read path control unit, a byte enable mask generation unit, and a block control unit; The block address parsing unit parses and calculates block information based on the instruction to be executed, and the block information includes block number and intra-block offset; The block access detection unit is electrically connected to the block address resolution unit and is used to determine the block access status based on the block information. The block access status includes full access and partial access. The read path control unit is electrically connected to the block access detection unit and is used to output a read path control signal according to the access status. The read path control signal includes a read path fully closed signal and a read path partially closed signal. The byte enable mask generation unit is electrically connected to the block address parsing unit and the query module, and is used to obtain the byte enable mask according to the offset segment and the byte bits corresponding to the intra-block offset enable. The block control unit is electrically connected to the read path control unit and the byte enable mask generation unit, and is used to generate a block write enable signal and a block read enable signal according to the read path control signal and the enable mask.

6. The primary data caching device according to claim 5, characterized in that, The execution control module is also electrically connected to the processor core; The execution control module includes: The token generation unit, token storage unit, address conflict detection unit, and token release unit are all included. The token generation unit is used to receive the instruction to be executed and to generate a different token tag for each instruction to be executed. The token register unit is used to store a token information list, which includes token information for at least one instruction; the token information includes the token tag, target address, operation status, and block number, and the operation status includes waiting, executing, and completing. The token release unit is used to clear the token information corresponding to the instruction to be executed after the sacrifice cache module issues the execution completion signal; The address conflict detection unit is electrically connected to the token register unit and is used to compare the address of the instruction to be executed with the address of the instruction to be executed to obtain a comparison result. The address of the instruction to be executed is the target address corresponding to the instruction whose operation state is executed. When the comparison results are the same, the token register unit stores the token information of the instruction to be executed and sets the operation state to wait; When the comparison results are different, the token register unit stores the token information of the instruction to be executed and sets the operation state to execution.

7. The primary data caching device according to claim 6, characterized in that, The collaborative arbitration module includes a main cache storage queue unit, a sacrifice cache storage queue unit, a two-level write merging unit, and a dynamic priority arbitration unit. The main cache storage queue unit is used to store memory access instructions; The sacrifice cache storage queue unit is used to store atomic operation instructions; The dynamic priority arbitration unit is electrically connected to the main cache storage queue unit and the sacrifice cache storage queue unit, and is used to arbitrate the instruction release order according to the preset priority rules to obtain the arbitration result. The two-level write merging unit is used to merge the write instructions in the memory access instructions and the atomic operation instructions at the byte level and the address level to obtain batch write data and batch write control signals; It also includes a cross-queue data forwarding module; The cross-queue data forwarding module is electrically connected to the main cache storage queue unit and the sacrifice cache storage queue unit, and is used for cross-queue data forwarding.

8. The primary data caching device according to claim 7, characterized in that, The protocol linkage module includes an extended status register unit, a status comparison and discrimination unit, an exclusive request generation unit, a consistency broadcast control unit, and a sniffing response unit. The extended status register unit is used to store the consistency status of each cache line in the sacrifice cache module. The consistency status includes modified, exclusive, shared, invalid, atomic exclusive, and atomic modified. The state comparison and discrimination unit is electrically connected to the token register unit and the extended state register unit, and is used to obtain a discrimination result based on the token information and the consistency state. The discrimination result includes cache line status and permission change signal. The exclusive request generation unit is electrically connected to the state comparison and discrimination unit, and is used to send an exclusive request signal to the external consistency bus according to the permission change signal. The consistency broadcast control unit is electrically connected to the state comparison and discrimination unit and is used to generate a state change broadcast message according to the state transition instruction. The sniffing response unit is electrically connected to the external consistency bus and is used to receive external listening requests and respond to the listening requests according to state transition instructions.

9. A processor, characterized in that, The processor includes at least one level-one data cache device as described in any one of claims 1 to 8.

10. A computer device, characterized in that, The computer device includes at least one processor, the processor including at least one level-one data cache device as described in any one of claims 1 to 8.

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