Page table management structure configuration method, system, and computing system

Abstract

The application relates to a page table management structure configuration method and system and a computing system. The method is applied to a central processing unit and comprises the following steps: receiving a to-be-processed instruction sent by a memory management object; in the case that a response chip of the to-be-processed instruction is a heterogeneous processing chip, sending the to-be-processed instruction to the heterogeneous processing chip and instructing the heterogeneous processing chip to perform a page table management structure configuration operation, wherein the heterogeneous processing chip is connected with the central processing unit and is configured as a chip used for the page table management structure configuration operation. According to the above method, the central processing unit can not directly perform the page table management structure configuration operation, but can perform the page table management structure configuration operation with the aid of the heterogeneous processing chip, so that part of the central processing unit resources can be released, the resource occupation amount of the central processing unit is reduced, and the overall performance of the central processing unit is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a page table management structure configuration method, system, and computing system. Background Technology

[0002] With the continuous growth of computing demands and the continuous development of hardware architecture, the importance of memory management is becoming increasingly prominent, especially in areas such as multitasking, virtualization, and resource sharing.

[0003] Page table management is an indispensable and crucial part of memory management, and configuring the page table management structure is a vital step in the memory management process. In related technologies, the configuration operation of the page table management structure is primarily performed by the Central Processing Unit (CPU).

[0004] However, configuring the page table management structure in the related technologies can lead to significant resource consumption by the central processing unit. Summary of the Invention

[0005] Therefore, it is necessary to provide a page table management structure configuration method, system, and computing system to address the aforementioned technical problems. This system can utilize heterogeneous processing chips to perform page table management structure configuration operations without requiring direct execution through the central processing unit (CPU), thereby reducing the CPU's resource consumption.

[0006] In a first aspect, embodiments of this application provide a page table management structure configuration method, applied to a central processing unit, the method comprising:

[0007] Receive pending instructions sent by the memory management object;

[0008] When the responding chip for the instruction to be processed is a heterogeneous processing chip, the instruction to be processed is sent to the heterogeneous processing chip, instructing the heterogeneous processing chip to perform the configuration operation of the page table management structure; the heterogeneous processing chip is connected to the central processing unit and is configured as a chip for page table management structure configuration operation.

[0009] In one embodiment, the method further includes:

[0010] Receive the configuration operation completion message sent by the heterogeneous processing chip;

[0011] The operation is completed according to the configuration and the pending instruction is marked as completed.

[0012] Secondly, embodiments of this application provide a page table management structure configuration method applied to heterogeneous processing chips, the method comprising:

[0013] When the central processing unit determines that the response chip for the instruction to be processed is a heterogeneous processing chip, it receives the instruction to be processed sent by the central processing unit.

[0014] Based on the instructions to be processed, execute the configuration operation of the page table management structure;

[0015] Send a message to the central processing unit indicating that the configuration operation is complete.

[0016] In one embodiment, according to the instruction to be processed, the configuration operation of the page table management structure is performed, including:

[0017] The instructions to be processed are parsed to obtain the configuration parameters of the page table management structure carried in the instructions.

[0018] Based on the configuration parameters, determine the storage address and multiple fill information corresponding to the page table management structure;

[0019] Each piece of information is added to the storage address in parallel to complete the configuration operation.

[0020] In one embodiment, the configuration parameters include an operation type identifier; before parsing the instruction to be processed, the method further includes:

[0021] Identify the instructions to be processed;

[0022] If the operation type identifier in the instruction to be processed is identified as a configuration type identifier, the instruction to be processed is parsed and processed.

[0023] In one embodiment, the configuration parameters include the starting address, initial padding value, increment value, and number of padding entries for the page table management structure configuration operation; based on the configuration parameters, the storage address corresponding to the page table management structure and multiple padding entries are determined, including:

[0024] The starting address of each padding information is determined based on the starting address, the number of padding information, and the padding information bit width; and each padding information is determined based on the padding start value, the padding information bit width, the increment value, and the padding start value bit width.

[0025] In one embodiment, each piece of padding information is determined based on the padding start value, the padding information bit width, the increment value, and the padding start value bit width, including:

[0026] The first piece of information is determined based on the starting value, the width of the information to be filled, the increment value, and the width of the starting value to be filled. The number of pieces of information to be filled is then updated to obtain the updated number of pieces of information.

[0027] Based on the starting value, the bit width of the filling information, the increment value, and the bit width of the starting value, other filling information is determined until the number of the latest updated filling information is equal to a preset threshold, thus obtaining each filling information.

[0028] In one embodiment, the storage address includes the starting address of each padding message; adding each padding message to the storage address in parallel includes:

[0029] Given a confirmed instruction bus authorization, each padding information is added in parallel, starting from the corresponding padding start address.

[0030] Thirdly, embodiments of this application provide a page table management structure configuration system, the system including a central processing unit and a heterogeneous processing chip;

[0031] The central processing unit is configured to execute the steps of the method in any embodiment of the first aspect;

[0032] A heterogeneous processing chip for performing the steps of the method in any embodiment of the second aspect.

[0033] In one embodiment, the heterogeneous processing chip includes an instruction parsing unit, a configuration information generation unit, and multiple page table management structure configuration units;

[0034] The instruction parsing unit is used to parse and process the instruction to be processed, and obtain the configuration parameters of the page table management structure carried in the instruction to be processed;

[0035] The configuration information generation unit is used to generate the storage address and multiple fill information corresponding to the page table management structure based on the configuration parameters.

[0036] Each page table management structure configuration unit is used to add each filling information to the storage address in parallel.

[0037] In one embodiment, the configuration parameters include an operation type identifier;

[0038] The instruction parsing unit is also used to receive instructions to be processed when the heterogeneous processing chip is in instruction receiving mode, and to parse and process the instructions to be processed when the operation type identifier in the instructions to be processed is a configuration type identifier.

[0039] In one embodiment, the configuration parameters include an identifier bit; the storage address includes multiple padding start addresses;

[0040] The configuration information generation unit is also used to adjust each piece of fill information according to the identifier bit, and update each piece of fill information to the corresponding adjusted fill information.

[0041] In one embodiment, the configuration information generation unit is further configured to send the storage address and each padding information to multiple page table management structure configuration units when the instruction bus authorization is determined, and instruct the multiple page table management structure configuration units to add each padding information to the storage address in parallel.

[0042] Fourthly, embodiments of this application provide a page table management structure configuration apparatus, the apparatus comprising:

[0043] The instruction receiving module is used to receive pending instructions sent by the memory management object;

[0044] The instruction sending module is used to send the instruction to be processed to the heterogeneous processing chip when the response chip of the instruction to be processed is a heterogeneous processing chip, and to instruct the heterogeneous processing chip to perform the configuration operation of the page table management structure; the heterogeneous processing chip is connected to the central processing unit and is configured as a chip for page table management structure configuration operation.

[0045] Fifthly, embodiments of this application provide a page table management structure configuration apparatus, the apparatus comprising:

[0046] The instruction receiving module is used to receive the instruction to be processed sent by the central processing unit when the central processing unit determines that the response chip of the instruction to be processed is a heterogeneous processing chip.

[0047] The configuration operation execution module is used to perform configuration operations on the page table management structure according to the instructions to be processed;

[0048] The message feedback module is used to send a message to the central processing unit indicating that the configuration operation is complete.

[0049] In a sixth aspect, embodiments of this application also provide a computing system, which includes a memory and a central processing unit (CPU). The memory stores a computer program, and the CPU executes the computer program to implement the steps of the method in any of the embodiments of the first aspect described above.

[0050] In a seventh aspect, embodiments of this application also provide a computing system, which includes a memory and a heterogeneous processing chip. The memory stores a computer program, and the heterogeneous processing chip executes the computer program to implement the steps of the method in any of the embodiments of the second aspect described above.

[0051] Eighthly, embodiments of this application also provide a readable storage medium storing a computer program, which, when executed by a central processing unit, implements the steps of the method in any of the embodiments of the first aspect described above.

[0052] In a ninth aspect, embodiments of this application also provide a readable storage medium storing a computer program, which, when executed by a heterogeneous processing chip, implements the steps of the method in any of the embodiments of the second aspect described above.

[0053] In a tenth aspect, embodiments of this application also provide a program product comprising a computer program that, when executed by a central processing unit, implements the steps of the method in any of the embodiments of the first aspect described above.

[0054] Eleventhly, embodiments of this application also provide a program product, which includes a computer program that, when executed by a heterogeneous processing chip, implements the steps of the method in any of the embodiments of the second aspect described above.

[0055] This application provides a page table management structure configuration method, system, and computing system applied to a central processing unit (CPU). It receives a pending instruction from a memory management object. If the responding chip for the pending instruction is a heterogeneous processing chip, the pending instruction is sent to the heterogeneous processing chip, instructing it to perform a page table management structure configuration operation. The heterogeneous processing chip is connected to the CPU and configured as a chip for page table management structure configuration operations. This method eliminates the need for the CPU to directly execute page table management structure configuration operations; instead, it utilizes a heterogeneous processing chip, thereby freeing up some CPU resources, reducing CPU resource consumption, and improving the overall performance of the CPU. Attached Figure Description

[0056] Figure 1 This is an application environment diagram of the page table management structure configuration method in one embodiment;

[0057] Figure 2 This is a flowchart illustrating a page table management structure configuration method in one embodiment;

[0058] Figure 3 This is a flowchart illustrating the page table management structure configuration method in another embodiment;

[0059] Figure 4 This is a flowchart illustrating the page table management structure configuration method in another embodiment;

[0060] Figure 5 This is a flowchart illustrating the page table management structure configuration method in another embodiment;

[0061] Figure 6 This is a flowchart illustrating the page table management structure configuration method in another embodiment;

[0062] Figure 7 This is a schematic diagram of the composition structure of the instruction to be processed in one embodiment;

[0063] Figure 8 This is a flowchart illustrating the page table management structure configuration method in another embodiment;

[0064] Figure 9 This is a structural block diagram of a page table management structure configuration device in one embodiment;

[0065] Figure 10 This is a structural block diagram of the page table management structure configuration device in another embodiment;

[0066] Figure 11 This is a diagram of the internal structure of a computing system in one embodiment. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0068] In fields such as multitasking, virtualization, and resource sharing, memory management technology is becoming increasingly important. Among these technologies, page table management structures are an indispensable and crucial part of memory management, and configuring them is a vital step in the memory management process. In related technologies, the configuration of page table management structures is primarily performed by the central processing unit (CPU). However, this method of configuring page table management structures by the CPU can result in significant CPU resource consumption. Therefore, this application provides a page table management structure configuration method that utilizes heterogeneous processing chips to perform the configuration operations, eliminating the need for direct CPU intervention and thus reducing CPU resource consumption.

[0069] The page table management structure configuration method provided in this application embodiment is applicable to... Figure 1The application environment diagram shown is illustrated. This application environment includes a page table management structure configuration system, which may include a central processing unit (CPU) and a heterogeneous processing chip. In this embodiment, the heterogeneous processing chip can be understood as a chip capable of parallel processing. The CPU and the heterogeneous processing chip can be deployed in the same computing system or in different computing systems. This embodiment uses the deployment of the CPU and the heterogeneous processing chip in the same computing system as an example. This computing system can be an independent data processing system, a computer device, or a server, etc., and this embodiment does not limit its scope. Optionally, the CPU and the heterogeneous processing chip can be connected via communication, such as through Wi-Fi, mobile network, or Bluetooth. Optionally, the computing system can be, but is not limited to, a personal computer, desktop computer, tablet computer, laptop computer, smart TV, or smartwatch. This embodiment does not limit the specific form of the computing system. For simplicity, [further details are omitted]. Figure 1 This example illustrates direct communication between the central processing unit (CPU) and the heterogeneous processing chip. The following sections will use both the CPU and the heterogeneous processing chip as the execution entities for the page table management structure configuration method to describe the specific process.

[0070] like Figure 2 The diagram shown is a flowchart illustrating the page table management structure configuration method provided in this embodiment of the application. This method is applied to a central processing unit and can be implemented through the following steps:

[0071] S101, Receive the pending instructions sent by the memory management object.

[0072] The aforementioned memory management object can be at least one processing unit or a chip with corresponding functions deployed in any computing system. The computing system can be a computing system to which the central processing unit belongs, or it can be other computing systems. This application embodiment does not limit this.

[0073] In practical applications, if there are multiple memory management objects, each memory management object sends different instructions to be processed. In this embodiment, a single memory management object is used as an example for illustration.

[0074] S102. If the responding chip for the instruction to be processed is a heterogeneous processing chip, the instruction to be processed is sent to the heterogeneous processing chip, instructing the heterogeneous processing chip to perform a page table management structure configuration operation. The heterogeneous processing chip is connected to the central processing unit and is configured as a chip for page table management structure configuration operations.

[0075] Specifically, the central processing unit (CPU) can analyze and process the instruction to be processed to determine the corresponding chip for the instruction; in addition, the CPU can also obtain the operation type of the instruction to be processed and determine the corresponding chip for the instruction based on the operation type.

[0076] Furthermore, if it is determined that the responding chip of the instruction to be processed is a heterogeneous processing chip, the instruction to be processed can be sent to the heterogeneous processing chip to instruct it to perform the configuration operation of the page table management structure.

[0077] It should be noted that, in addition to configuring page table management structures, heterogeneous processing chips can also perform other operations, such as image rendering, image display, and video processing.

[0078] In the embodiments of this application, the above-mentioned page table management structure can be a Page Directory Entry (PDE) or a Page Table Entry (PTE).

[0079] In one embodiment, the method of performing the page table management structure configuration operation according to the instruction to be processed can be that the heterogeneous processing chip calls the configuration template of the page table management structure according to the instruction to be processed, and configures the page table management structure according to the configuration template. In another embodiment, the method of performing the page table management structure configuration operation according to the instruction to be processed can also be that the heterogeneous processing chip obtains a preset configuration method of the page table management structure according to the instruction to be processed, and performs the configuration of the page table management structure according to the configuration method.

[0080] The technical solution in this application embodiment is applied to a central processing unit (CPU). It receives a pending instruction sent by a memory management object. If the responding chip for the pending instruction is a heterogeneous processing chip, the pending instruction is sent to the heterogeneous processing chip, instructing it to perform a page table management structure configuration operation. The heterogeneous processing chip is connected to the CPU and configured as a chip for page table management structure configuration operations. This method eliminates the need for the CPU to directly perform page table management structure configuration operations; instead, it utilizes a heterogeneous processing chip, thereby freeing up some CPU resources, reducing CPU resource consumption, and improving the overall performance of the CPU.

[0081] In practical applications, after the heterogeneous processing chip completes the configuration operation of the page table management structure, it can also send a configuration operation completion message back to the central processing unit (CPU) to inform the CPU that the configuration operation of the page table management structure is complete. The feedback process of the configuration operation completion message is described below. In one embodiment, after executing the steps in S102 above, as follows... Figure 3 As shown, the above method may further include the following steps:

[0082] S103, Receive the configuration operation completion message sent by the heterogeneous processing chip.

[0083] In practical applications, after completing the configuration operation of the page table management structure, the heterogeneous processing chip can generate a configuration operation completion message and send the configuration operation completion message to the central processing unit.

[0084] Correspondingly, the central processing unit can receive a configuration operation completion message sent by the heterogeneous processing chip. Optionally, the configuration operation completion message can be represented by a completion identifier, or by related text, images, or videos indicating the completion of the configuration operation.

[0085] S104. Based on the configuration operation completion message, respond to the pending instruction with a completion mark.

[0086] Furthermore, after receiving the configuration operation completion message, the central processing unit can mark the instruction to be processed with a response completion flag to record that the instruction to be processed has been completed. After that, the central processing unit can continue to process other instructions to be processed that do not carry a response completion flag.

[0087] The technical solution in this application embodiment receives a configuration operation completion message sent by a heterogeneous processing chip, and marks the pending instruction as having completed the response according to the configuration operation completion message. The above method can mark the pending instruction as having completed the response when the pending instruction has been completed. On this basis, it can avoid the central processing unit from missing other pending instructions that have not completed the response, and improve the central processing unit's response performance to different pending instructions.

[0088] In one embodiment, this application also provides a page table management structure configuration method applied to a central processing unit, the method comprising the following steps:

[0089] S11. Receive pending instructions sent by the memory management object;

[0090] S12. If the chip responding to the instruction to be processed is a heterogeneous processing chip, the instruction to be processed is sent to the heterogeneous processing chip, instructing the heterogeneous processing chip to perform the configuration operation of the page table management structure; the heterogeneous processing chip is connected to the central processing unit and is configured as a chip for page table management structure configuration operation.

[0091] S13. Receive the configuration operation completion message sent by the heterogeneous processing chip;

[0092] S14. Based on the configuration operation completion message, respond to the pending instruction with a completion mark.

[0093] The specific execution process of steps S11 to S14 above can be found in the description of the above embodiments. The implementation principle and technical effect are similar, and will not be repeated here.

[0094] To address the issue of high CPU resource consumption during page table management structure configuration in related technologies, this application provides a page table management structure configuration method. This method utilizes heterogeneous processing chips to perform page table management structure configuration operations, eliminating the need for direct CPU execution and thus reducing CPU resource consumption. The following embodiments will detail the specific process of the page table management structure configuration method, focusing on the execution entity. Figure 1 This section uses heterogeneous processing chips in a page table management structure configuration system to illustrate the specific process of configuring a page table management structure.

[0095] like Figure 4 The diagram shown is a flowchart illustrating the page table management structure configuration method provided in this embodiment of the application. This method is applied to heterogeneous processing chips and can be implemented through the following steps:

[0096] S201. When the central processing unit determines that the response chip of the instruction to be processed is a heterogeneous processing chip, it receives the instruction to be processed sent by the central processing unit.

[0097] In this embodiment of the application, the central processing unit can only send the instruction to be processed to the heterogeneous processing chip if it determines that the response chip of the instruction to be processed is a heterogeneous processing chip. Correspondingly, the heterogeneous processing chip receives the instruction to be processed sent by the central processing unit.

[0098] S202. Based on the instructions to be processed, perform the configuration operation of the page table management structure.

[0099] In one implementation, the configuration operation of the page table management structure according to the instruction to be processed can be performed by a heterogeneous processing chip calling the configuration template of the page table management structure according to the instruction to be processed, and configuring the page table management structure according to the configuration template.

[0100] In another implementation, the method of executing the page table management structure configuration operation according to the instruction to be processed can also be that the heterogeneous processing chip obtains the preset page table management structure configuration method according to the instruction to be processed, and executes the page table management structure configuration according to the configuration method.

[0101] In another implementation, the method of executing the configuration operation of the page table management structure according to the instruction to be processed can be that the heterogeneous processing chip pre-trains an algorithm model, and then the instruction to be processed is input into the algorithm model, which executes the configuration operation of the page table management structure according to the instruction to be processed.

[0102] S203. Send a configuration operation completion message to the central processing unit.

[0103] Specifically, after the heterogeneous processing chip completes the configuration operation of the page table management structure, it can generate a configuration operation completion message and send the configuration operation completion message to the central processing unit.

[0104] The technical solution in this application embodiment is applied to a heterogeneous processing chip. When the central processing unit (CPU) determines that the responding chip for the instruction to be processed is a heterogeneous processing chip, it receives the instruction to be processed sent by the CPU, performs the configuration operation of the page table management structure according to the instruction, and sends a configuration operation completion message back to the CPU. The above method does not require the CPU to directly perform the configuration operation of the page table management structure; it can be performed by the heterogeneous processing chip, thereby freeing up some CPU resources, reducing the CPU's resource consumption, and improving the overall performance of the CPU. At the same time, since the configuration operation of the page table management structure is performed by the heterogeneous processing chip, which has higher memory bandwidth, it can write information faster to a certain extent during the configuration operation of the page table management structure, thereby improving the configuration performance of the heterogeneous processing chip.

[0105] The process of performing the page table management structure configuration operation according to the instruction to be processed is described below. In one embodiment, as... Figure 5 As shown, the steps in S202 above can be implemented in the following ways:

[0106] S212. Parse and process the instruction to be processed to obtain the configuration parameters of the page table management structure carried in the instruction to be processed.

[0107] In one embodiment, the heterogeneous processing chip can pre-train an instruction parsing model, then input the instruction to be processed into the instruction parsing model to parse and process the instruction, and output the configuration parameters of the page table management structure carried in the instruction. Optionally, the above instruction parsing model can be implemented by at least one of the following: convolutional neural network model, long short-term memory neural network model, recurrent recurrent neural network model, fully connected neural network model, etc.

[0108] In another embodiment, the heterogeneous processing chip can call an instruction parsing function to parse and process the instruction to be processed to obtain the configuration parameters of the page table management structure carried in the instruction to be processed.

[0109] S222. Based on the configuration parameters, determine the storage address and multiple filling information corresponding to the page table management structure.

[0110] Specifically, the heterogeneous processing chip can perform arithmetic operations based on configuration parameters to obtain the memory address corresponding to the page table management structure and multiple padding information. In this embodiment, the memory address may include the starting address of each padding information.

[0111] Optionally, the above arithmetic operations can be implemented by at least one of addition, subtraction, multiplication, division, logarithmic operations, and exponential operations.

[0112] In addition, the heterogeneous processing chip can calculate the memory address and multiple padding information corresponding to the page table management structure according to the configuration parameters and a preset processing method.

[0113] S232. Add each piece of information to the storage address in parallel to complete the configuration operation.

[0114] In one implementation, the heterogeneous processing chip can call an information filling function to add each filling information to the storage address in parallel to complete the configuration operation.

[0115] In another implementation, the heterogeneous processing chip can add each piece of padding information to the memory address in parallel according to the padding information addition rules to complete the configuration operation. Here, the addition can be understood as the padding process.

[0116] The technical solution in this application involves parsing the instruction to be processed to obtain the configuration parameters of the page table management structure carried in the instruction. Based on the configuration parameters, the storage address and multiple padding information corresponding to the page table management structure are determined, and the padding information is added to the storage address in parallel to complete the configuration operation. The above method can add padding information according to the storage address, thereby improving the accuracy of the configured page table management structure. At the same time, the above method can realize the parallel addition of padding information, which can not only improve hardware acceleration configuration, i.e., heterogeneous processing chip acceleration configuration, but also improve the configuration speed and efficiency of the page table management structure, enabling heterogeneous processing chips to support high-performance computing.

[0117] In practical applications, heterogeneous processing chips can perform more than just page table management structure configuration operations; they can also perform other functions. Therefore, before responding to a pending instruction, the heterogeneous processing chip must first identify whether the received instruction is a page table management structure configuration instruction. The identification process is described below. In one embodiment, the configuration parameters include an operation type identifier; before executing the steps in S212 above, such as... Figure 6 As shown, the above method may further include the following steps:

[0118] S2121. Identify the instructions to be processed.

[0119] In practical applications, heterogeneous processing chips can pre-train an instruction recognition model, and then input the instruction to be processed into the instruction recognition model for recognition. Optionally, the instruction recognition model can be implemented by at least one of the following: convolutional neural network model, fully connected neural network model, long short-term memory neural network model, recurrent recurrent neural network model, residual neural network model, etc.

[0120] In addition, heterogeneous processing chips can also analyze and / or detect the instructions to be processed in order to identify the instructions.

[0121] In this embodiment of the application, if the instruction to be processed is a page table management structure configuration instruction, the instruction to be processed may carry information such as the operation type identifier (opcode) of the page table management structure configuration instruction, the starting address of the page table management structure, the identifier bit (i.e., the mask bit), the initial padding value, the padding information increment value, and the number of padding information.

[0122] The operation type identifier (opcode) is located in the lower 16 bits of the packet header of the instruction to be processed, and is used to identify the operation type corresponding to the instruction. Optionally, the opcode corresponding to the page table management structure configuration instruction can be represented by a dedicated default value. Meanwhile, the aforementioned starting address (Dst Addr) is also the starting address of the cache where the page table management structure to be configured is located. The page table management structure is filled starting from this starting address. The initial filling value (Init Data) represents the first value of the page table management structure to be configured, and subsequent filling information is also calculated from this value. The increment value (Incre) is used to accumulate the initial filling value according to this increment value when calculating the second and subsequent filling information. The flag bit can be used to adjust each filling information during calculation, allowing for more flexible calculation of each filling information. The number of filling information represents the total number of consecutively added filling information in the page table management structure to be configured.

[0123] S2122. If the operation type identifier in the instruction to be processed is identified as a configuration type identifier, the instruction to be processed is parsed and processed.

[0124] In this embodiment, when the heterogeneous processing chip recognizes that the operation type identifier in the instruction to be processed is a configuration type identifier, it can perform the step of parsing the instruction to be processed.

[0125] The technical solution in this application embodiment identifies the instruction to be processed. If the operation type identifier in the instruction to be processed is identified as a configuration type identifier, the instruction to be processed is parsed. Before responding to the instruction to be processed, the above method can first identify whether the received instruction to be processed is a page table management structure configuration instruction, and then perform the page table management structure configuration operation on the instruction to be processed according to the identification result, so as to correctly respond to the instruction to be processed.

[0126] The process of determining the storage address and multiple padding information corresponding to the page table management structure based on the configuration parameters is described below. In one embodiment, the configuration parameters include the starting address of the page table management structure configuration operation, the starting padding value, the increment value, and the number of padding information; the steps in S222 above may include: determining the starting address of each padding information based on the starting address, the number of padding information, and the padding information bit width; and determining each padding information based on the starting padding value, the padding information bit width, the increment value, and the bit width of the starting padding value.

[0127] Specifically, the heterogeneous processing chip can pre-train a padding address calculation model, and then input the starting address, the number of padding information, and the padding information bit width into the padding address calculation model. The padding address calculation model outputs the padding address of each padding information. Alternatively, the heterogeneous processing chip can perform arithmetic operations on the starting address, the number of padding information, and the padding information bit width to obtain the padding address of each padding information. Optionally, the arithmetic operations can be implemented by at least one of addition, subtraction, multiplication, division, and logarithmic operations.

[0128] In this embodiment, the padding information bit width is the same as the bit width of one padding information. Different padding information have the same bit width. For example, if the padding information bit width is 512 bits (i.e., 64B), that is, each padding information occupies 64 address spaces, then the starting address of the first padding information is equal to DstAddr+64. Starting from the second padding information, the starting address of each padding information can be equal to the starting address of the previous padding information plus 64, that is, the starting address of the Nth padding information is equal to DstAddr+64*(N-1).

[0129] Meanwhile, the heterogeneous processing chip can pre-train a padding information calculation model, and then input the padding start value, padding information bit width, increment value, and padding start value bit width into the padding information calculation model, which outputs the padding information. Additionally, the heterogeneous processing chip can perform arithmetic operations on the padding start value, padding information bit width, increment value, and padding start value bit width to obtain the padding information.

[0130] like Figure 7The diagram shows the structure of a page table management structure configuration instruction to be processed. The lower 16 bits of the first row represent the operation type identifier of the instruction. The starting address, flag bits, fill start value, and increment value are all represented by 64 bits. The lower two bits of the starting address are both 0. The starting address [31:2] represents the values ​​from the lower 3 bits to the lower 32 bits of the starting address. The starting address [63:32] represents the values ​​from the higher 32 bits of the starting address. The flag bits [31:0] represent the values ​​from the lower 32 bits of the flag bits. The flag bits [63:32] represent the values ​​from the higher 32 bits of the flag bits. The fill start value [31:0] represents the values ​​from the lower 32 bits of the flag bits. The fill start value [63:32] represents the values ​​from the higher 32 bits of the flag bits. The increment value [31:0] represents the values ​​from the lower 32 bits of the flag bits. The increment value [63:32] represents the values ​​from the higher 32 bits of the flag bits. The fill information quantity [18:0] represents the fill information quantity, represented by 19 bits.

[0131] In one embodiment, such as Figure 8 As shown, the steps described above for determining each piece of padding information based on the padding start value, padding information bit width, increment value, and padding start value bit width can be implemented in the following way:

[0132] S2221. Determine the first filling information based on the filling start value, the filling information bit width, the increment value, and the bit width of the filling start value, and update the number of filling information to obtain the updated number of filling information.

[0133] In practical applications, heterogeneous processing chips can perform arithmetic operations on the fill start value, fill information bit width, increment value, and fill start value bit width to obtain the first fill information.

[0134] Continuing with the previous example, the width of the initial padding value Init Data is 8 bits. The distribution pattern of the first padding information is Init Data+0*Incre, Init Data+1*Incre, Init Data+2*Incre, Init Data+3*Incre, Init Data+4*Incre, Init Data+5*Incre, Init Data+6*Incre and Init Data+7*Incre, that is, the first padding information includes these 8 data.

[0135] It's important to note that each time a piece of fill information is determined, the current number of fill information items can be updated to obtain the updated number of fill information items. Specifically, after determining the first piece of fill information item, the current number of fill information items can be reduced by 1 to obtain the updated number of fill information items (N-1), thus completing the update of the number of fill information items.

[0136] S2222. Based on the starting value of the fill, the width of the fill information, the increment value, and the width of the starting value of the fill, determine other fill information until the number of the latest fill information after the update is equal to the preset threshold, and obtain each fill information.

[0137] Meanwhile, the heterogeneous processing chip can also perform arithmetic operations on the fill start value, fill information bit width, increment value, and fill start value bit width to obtain other fill information.

[0138] Starting with the second fill information, the distribution pattern of the second fill information is as follows: Init Data+8*Incre, Init Data+9*Incre, Init Data+10*Incre, Init Data+11*Incre, Init Data+12*Incre, Init Data+13*Incre, Init Data+14*Incre, and Init Data+15*Incre, and so on. The distribution pattern of other fill information is similar, increasing with the increment value.

[0139] In practical applications, after determining the second piece of information, the current number of pieces of information (N-1) can be reduced by 1 to obtain the updated number of pieces of information (N-2), until the updated number of pieces of information equals 0. At this point, all the pieces of information to be added are obtained.

[0140] In one embodiment, the storage address includes the starting address of each padding information; the step of adding each padding information to the storage address in parallel may include: adding each padding information in parallel starting from the corresponding starting address when the instruction bus authorization is determined.

[0141] In the embodiments of this application, if the heterogeneous processing chip determines that the instruction bus is authorized, it can add each piece of padding information in parallel starting from the corresponding padding start address; otherwise, it waits for the instruction bus to be authorized before adding each piece of padding information in parallel starting from the corresponding padding start address.

[0142] The technical solution in this application embodiment determines the starting address of each piece of padding information based on the starting address, the number of padding information, and the padding information bit width, and determines each piece of padding information based on the starting value of padding, the padding information bit width, the increment value, and the bit width of the starting value of padding. The above method can determine each piece of padding information and the starting address of each piece of padding information required to configure the page table management structure. Based on this, the configuration operation of the page table management structure can be quickly realized, improving the configuration speed and configuration efficiency.

[0143] In one embodiment, this application also provides a page table management structure configuration method applied to heterogeneous processing chips, the method comprising the following steps:

[0144] S21. If the central processing unit determines that the response chip of the instruction to be processed is a heterogeneous processing chip, it receives the instruction to be processed sent by the central processing unit.

[0145] S22. Identify the instruction to be processed; the configuration parameters include the operation type identifier, the starting address of the page table management structure configuration operation, the initial padding value, the increment value, and the number of padding messages;

[0146] S23. If the operation type identifier in the instruction to be processed is identified as a configuration type identifier, the instruction to be processed is parsed to obtain the configuration parameters of the page table management structure carried in the instruction to be processed.

[0147] S24. Determine the starting address of each padding information based on the starting address, the number of padding information, and the padding information bit width; and determine the first padding information based on the padding start value, the padding information bit width, the increment value, and the bit width of the padding start value, and update the number of padding information to obtain the updated number of padding information.

[0148] S25. Determine other filling information based on the filling start value, filling information bit width, increment value and filling start value bit width, until the number of the latest filling information after the update is the preset threshold, and obtain each filling information;

[0149] S26. If the instruction bus authorization is determined, add each padding information in parallel starting from the corresponding padding start address;

[0150] S27. Send a message to the central processing unit that the configuration operation is complete.

[0151] The specific execution process of S21 to S27 above can be found in the description of the above embodiments. The implementation principle and technical effect are similar, and will not be repeated here.

[0152] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0153] Based on the same inventive concept, this application also provides a page table management structure configuration system, see below. Figure 1 As shown, the system includes a central processing unit and a heterogeneous processing chip;

[0154] The central processing unit is used to execute the above. Figures 2-3 The steps of the method in any of the embodiments;

[0155] Heterogeneous processing chips are used to perform the above. Figures 4-6 and Figure 8 The steps of the method in any of the embodiments.

[0156] In this embodiment, the central processing unit (CPU) and the heterogeneous processing chip can be deployed in the same computing system or in different computing systems. Optionally, the CPU and the heterogeneous processing chip can be connected via a communication link, such as Wi-Fi, mobile network, or Bluetooth.

[0157] The page table management structure configuration system provided in this application can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effects are similar, and will not be repeated here.

[0158] In one embodiment, the heterogeneous processing chip includes an instruction parsing unit, a configuration information generation unit, and multiple page table management structure configuration units;

[0159] The instruction parsing unit is used to parse and process the instruction to be processed, and obtain the configuration parameters of the page table management structure carried in the instruction to be processed;

[0160] The configuration information generation unit is used to generate the storage address and multiple fill information corresponding to the page table management structure based on the configuration parameters.

[0161] Each page table management structure configuration unit is used to add each filling information to the storage address in parallel.

[0162] It should be noted that multiple page table management structure configuration units can be deployed in a heterogeneous processing chip. These multiple page table management structure configuration units can add each padding information to the memory address in parallel, thereby demonstrating the parallel processing capability of the heterogeneous processing chip and improving its configuration speed and efficiency.

[0163] The page table management structure configuration system provided in this application can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effects are similar, and will not be repeated here.

[0164] In one embodiment, the configuration parameters include an operation type identifier;

[0165] The instruction parsing unit is also used to receive instructions to be processed when the heterogeneous processing chip is in instruction receiving mode, and to parse and process the instructions to be processed when the operation type identifier in the instructions to be processed is a configuration type identifier.

[0166] In practical applications, in order to reduce the power consumption and overall performance of heterogeneous processing chips, heterogeneous processing chips are configured with instruction receive mode and instruction reject mode. In the instruction receive mode, the instruction parsing unit in the heterogeneous processing chip can receive externally sent instructions to be processed.

[0167] Furthermore, in this embodiment, the instruction parsing unit can only receive and respond to pending instructions when it is in an idle state. Simultaneously, after the pending instruction response is completed—that is, after the page table management structure configuration operation is finished—the instruction parsing unit can be placed in an idle state to wait for receiving and responding to the next pending instruction.

[0168] The page table management structure configuration system provided in this application can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effects are similar, and will not be repeated here.

[0169] In one embodiment, the configuration parameters include an identifier bit; the storage address includes multiple padding start addresses;

[0170] The configuration information generation unit is also used to adjust each piece of fill information according to the identifier bit, and update each piece of fill information to the corresponding adjusted fill information.

[0171] The page table management structure configuration system provided in this application can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effects are similar, and will not be repeated here.

[0172] In one embodiment, the configuration information generation unit is further configured to send the storage address and each padding information to multiple page table management structure configuration units when the instruction bus authorization is determined, and instruct the multiple page table management structure configuration units to add each padding information to the storage address in parallel.

[0173] The page table management structure configuration system provided in this application can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effects are similar, and will not be repeated here.

[0174] Based on the same inventive concept, this application also provides a page table management structure configuration apparatus for implementing the page table management structure configuration method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more page table management structure configuration apparatus embodiments provided below can be found in the limitations of the page table management structure configuration method described above, and will not be repeated here.

[0175] In one embodiment, Figure 9 This is a schematic diagram of a page table management structure configuration device in one embodiment of this application. The page table management structure configuration device provided in this embodiment can be applied to a central processing unit. Figure 9 As shown, the page table management structure configuration device of this application embodiment may include: an instruction receiving module 11 and an instruction sending module 12, wherein:

[0176] The instruction receiving module 11 is used to receive pending instructions sent by the memory management object;

[0177] The instruction sending module 12 is used to send the instruction to be processed to the heterogeneous processing chip when the response chip of the instruction to be processed is a heterogeneous processing chip, and to instruct the heterogeneous processing chip to perform the configuration operation of the page table management structure; the heterogeneous processing chip is connected to the central processing unit and is configured as a chip for page table management structure configuration operation.

[0178] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0179] In one embodiment, the page table management structure configuration apparatus further includes: a message receiving module and an instruction marking module, wherein:

[0180] The message receiving module is used to receive configuration operation completion messages sent by heterogeneous processing chips;

[0181] The instruction marking module is used to mark the pending instruction as completed based on the configured operation completion message.

[0182] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0183] In another embodiment, Figure 10 This is a schematic diagram of a page table management structure configuration device in one embodiment of this application. The page table management structure configuration device provided in this embodiment can be applied to heterogeneous processing chips. Figure 10As shown, the page table management structure configuration device of this application embodiment may include: an instruction receiving module 21, a configuration operation execution module 22, and a message feedback module 23, wherein:

[0184] The instruction receiving module 21 is used to receive the instruction to be processed sent by the central processing unit when the central processing unit determines that the response chip of the instruction to be processed is a heterogeneous processing chip.

[0185] The configuration operation execution module 22 is used to perform configuration operations on the page table management structure according to the instructions to be processed;

[0186] The message feedback module 23 is used to send a configuration operation completion message to the central processing unit.

[0187] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0188] In one embodiment, the configuration operation execution module 22 includes: a parsing unit, a determining unit, and an adding unit, wherein:

[0189] The parsing unit is used to parse the instruction to be processed and obtain the configuration parameters of the page table management structure carried in the instruction to be processed.

[0190] The determination unit is used to determine the storage address and multiple padding information corresponding to the page table management structure based on the configuration parameters;

[0191] The add unit is used to add each piece of fill information to the storage address in parallel to complete the configuration operation.

[0192] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0193] In one embodiment, the configuration parameters include an operation type identifier; the configuration operation execution module 22 further includes an identification unit, wherein:

[0194] The identification unit is used to identify the instructions to be processed.

[0195] The parsing unit is used to parse and process the instruction to be processed when the operation type identifier in the instruction to be processed is identified as a configuration type identifier.

[0196] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0197] In one embodiment, the configuration parameters include the starting address of the page table management structure configuration operation, the initial filling value, the increment value, and the number of filling information; the determining unit includes an information acquisition subunit, wherein:

[0198] The sub-unit is determined to determine the starting address of each piece of padding information based on the starting address, the number of padding information, and the padding information bit width; and to determine each piece of padding information based on the padding start value, the padding information bit width, the increment value, and the bit width of the padding start value.

[0199] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0200] In one embodiment, the information acquisition subunit includes: a first determining subunit and a second determining subunit, wherein:

[0201] The first determining subunit is used to determine the first filling information based on the filling start value, the filling information bit width, the increment value and the bit width of the filling start value, and update the number of filling information to obtain the updated number of filling information.

[0202] The second determining subunit is used to determine other filling information based on the filling start value, the filling information bit width, the increment value, and the bit width of the filling start value, until the number of the latest updated filling information is equal to a preset threshold, thus obtaining each filling information.

[0203] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0204] In one embodiment, the storage address includes the starting address of each padding information; the adding unit is specifically used for:

[0205] Given a confirmed instruction bus authorization, each padding information is added in parallel, starting from the corresponding padding start address.

[0206] The page table management structure configuration device provided in this application embodiment can be used to execute the technical solutions in the above-described page table management structure configuration method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0207] Specific limitations regarding the page table management structure configuration device can be found in the limitations of the page table management structure configuration method described above, and will not be repeated here. Each module in the aforementioned page table management structure configuration device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computing system in hardware form, or stored in the memory of the computing system in software form, so that the processor can call and execute the operations corresponding to each module.

[0208] In one embodiment, a computing system is provided. This computing system can be a standalone data processing system, a computer device, or a server. This application embodiment uses a computer device as an example for illustration. A computer system can include multiple different functional units, such as a control unit, a power supply unit, etc. Figure 11 As shown in the illustration, this application uses a computer system including a display unit as an example to illustrate its internal structure. The computing system includes a processor, memory, and a network interface connected via a system bus. The processor provides processing power. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores multiple filling information and storage addresses. The network interface communicates with external endpoints via a network connection. When the computer program is executed by the processor, it implements a page table management structure configuration method.

[0209] Those skilled in the art will understand that Figure 11 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computing system on which the present application is applied. A specific computing system may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0210] In one embodiment, a computing system is also provided, including a memory and a central processing unit (CPU). The memory stores a computer program, and the CPU executes the computer program to implement the technical solutions in the above-described page table management structure configuration method embodiments of this application. The implementation principle and technical effects are similar, and will not be repeated here.

[0211] In one embodiment, a computing system is also provided, including a memory and a heterogeneous processing chip. The memory stores a computer program. When the heterogeneous processing chip executes the computer program, it implements the technical solution in the above-described page table management structure configuration method embodiment of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0212] In one embodiment, a readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a central processing unit, it implements the technical solution of the page table management structure configuration method described above in this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0213] In one embodiment, a readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a heterogeneous processing chip, it implements the technical solution of the page table management structure configuration method described above in this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0214] In one embodiment, a program product is provided, including a computer program that, when executed by a central processing unit, implements the technical solution of the page table management structure configuration method described above in this application. The implementation principle and technical effects are similar and will not be repeated here.

[0215] In one embodiment, a program product is provided, including a computer program that, when executed by a heterogeneous processing chip, implements the technical solution of the page table management structure configuration method described above in this application. The implementation principle and technical effects are similar and will not be repeated here.

[0216] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0217] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0218] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for configuring a page table management structure, characterized in that, Applied to a central processing unit, the method includes: Receive pending instructions sent by the memory management object; When the responding chip for the instruction to be processed is a heterogeneous processing chip, the instruction to be processed is sent to the heterogeneous processing chip, instructing the heterogeneous processing chip to perform a page table management structure configuration operation; the heterogeneous processing chip is connected to the central processing unit and is configured as a chip for page table management structure configuration operation.

2. The method according to claim 1, characterized in that, The method further includes: Receive the configuration operation completion message sent by the heterogeneous processing chip; The pending instruction is marked as completed in response to the configuration operation completion message.

3. A method for configuring a page table management structure, characterized in that, Applied to heterogeneous processing chips, the method includes: If the central processing unit determines that the response chip of the instruction to be processed is a heterogeneous processing chip, the instruction to be processed is received by the central processing unit. According to the instruction to be processed, the configuration operation of the page table management structure is executed; The configuration operation is completed and a message is sent back to the central processing unit.

4. The method according to claim 3, characterized in that, The step of performing the page table management structure configuration operation according to the instruction to be processed includes: The instruction to be processed is parsed to obtain the configuration parameters of the page table management structure carried in the instruction to be processed; Based on the configuration parameters, determine the storage address and multiple padding information corresponding to the page table management structure; The aforementioned filling information is added to the storage address in parallel to complete the configuration operation.

5. The method according to claim 4, characterized in that, The configuration parameters include an operation type identifier; before parsing and processing the instruction to be processed, the method further includes: The instruction to be processed is identified; If the operation type identifier in the instruction to be processed is identified as a configuration type identifier, the instruction to be processed is parsed and processed.

6. The method according to claim 4 or 5, characterized in that, The configuration parameters include the starting address, initial padding value, increment value, and number of padding entries for the page table management structure configuration operation; determining the storage address and multiple padding entries corresponding to the page table management structure based on the configuration parameters includes: The starting address of each piece of padding information is determined based on the starting address, the number of padding information, and the padding information bit width; and each piece of padding information is determined based on the padding start value, the padding information bit width, the increment value, and the bit width of the padding start value.

7. The method according to claim 6, characterized in that, Determining each piece of padding information based on the padding start value, the padding information bit width, the increment value, and the padding start value bit width includes: Based on the starting fill value, the fill information bit width, the increment value, and the bit width of the starting fill value, the first fill information is determined, and the number of fill information is updated to obtain the updated number of fill information. Based on the starting fill value, the fill information bit width, the increment value, and the bit width of the starting fill value, other fill information is determined until the number of the latest updated fill information is equal to a preset threshold, thus obtaining each fill information.

8. The method according to claim 4 or 5, characterized in that, The storage address includes the starting address of each of the padding information; the step of adding each of the padding information to the storage address in parallel includes: Given a valid instruction bus authorization, the aforementioned padding information is added in parallel, starting from the corresponding padding start address.

9. A page table management structure configuration system, the system comprising a central processing unit and a heterogeneous processing chip; in, The central processing unit is configured to perform the steps of the method as described in any one of claims 1-2; The heterogeneous processing chip is used to perform the steps of the method as described in any one of claims 3-8.

10. The system according to claim 9, characterized in that, The heterogeneous processing chip includes an instruction parsing unit, a configuration information generation unit, and multiple page table management structure configuration units. The instruction parsing unit is used to parse the instruction to be processed and obtain the configuration parameters of the page table management structure carried in the instruction to be processed. The configuration information generation unit is used to generate the storage address and multiple filling information corresponding to the page table management structure according to the configuration parameters; Each of the page table management structure configuration units is used to add the filling information to the storage address in parallel.

11. The system according to claim 9, characterized in that, The configuration parameters include an operation type identifier; The instruction parsing unit is also used to receive the instruction to be processed when the heterogeneous processing chip is in instruction receiving mode, and to parse and process the instruction to be processed when the operation type identifier in the instruction to be processed is identified as a configuration type identifier.

12. The system according to claim 10 or 11, characterized in that, The configuration parameters include an identifier bit; the storage address includes multiple padding start addresses; The configuration information generation unit is further configured to adjust each piece of fill information according to the identifier bit, and update each piece of fill information to the corresponding adjusted fill information.

13. The system according to claim 10 or 11, characterized in that, The configuration information generation unit is further configured to send the storage address and each padding information to multiple page table management structure configuration units when the instruction bus authorization is determined, and instruct the multiple page table management structure configuration units to add each of the padding information to the storage address in parallel.

14. A computing system, comprising a memory, a central processing unit, and a computer program; said computer program is stored in the memory; The central processing unit is used to run the computer program to perform the steps of the configuration method according to any one of claims 1-2.

15. A computing system, comprising a memory, a heterogeneous processing chip, and a computer program; the computer program is stored in the memory; The heterogeneous processing chip is used to run the computer program to perform the steps of the configuration method according to any one of claims 3-8.

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