Address mapping management method and apparatus

Abstract

The application provides an address mapping management method and device, and relates to the technical field of storage. The method comprises the following steps: determining a read-write type, logical address information, data length and logical address range corresponding to a current access according to a current read-write command sent by a host; determining a target mapping level from a plurality of mapping levels according to the read-write type, logical address continuity and data length; determining a mapping level corresponding to currently cached mapping table data in a mapping table cache area and a logical address range covered by the currently cached mapping table data; in a case where the currently cached mapping level is consistent with the target mapping level and a logical address range corresponding to the current access is contained in the logical address range covered by the currently cached mapping table data, determining a physical address based on the currently cached mapping table data. The application solves the problem that in the related art, in a scene where host read-write requests change complexly, an address mapping management method is difficult to efficiently complete address mapping processing.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more specifically, to an address mapping management method and apparatus. Background Technology

[0002] Storage devices typically manage data on the storage medium by running firmware through a controller. During data read / write operations, the host initiates data access based on the logical address, and the storage device determines the corresponding physical storage location according to the mapping relationship between logical and physical addresses to complete the data read or write.

[0003] However, as the type, amount of data, and access location of host read / write requests change, the address mapping process inside the storage device may be affected by different access characteristics, thereby reducing the execution efficiency of the firmware and the read / write performance of the storage device.

[0004] Therefore, in scenarios where host read and write requests are complex and constantly changing, address mapping management methods struggle to efficiently handle address mapping, which has become a problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides an address mapping management method and apparatus, which can solve the problem in related technologies where address mapping management methods are difficult to efficiently complete address mapping processing in scenarios with complex and changing host read / write requests. The technical solution is as follows:

[0006] According to one aspect of this application, an address mapping management method is applied to a storage device, the storage device including a mapping table cache, the method comprising:

[0007] Based on the current read / write command sent by the host, determine the read / write type, logical address information, data length, and logical address range corresponding to the current access;

[0008] Based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access, the access behavior corresponding to the current access is determined, and based on the access behavior and the data length, a target mapping level is determined from multiple mapping levels, wherein different mapping levels correspond to different mapping space ranges;

[0009] Determine the mapping level corresponding to the currently cached mapping table data in the mapping table cache area and the logical address range covered by the currently cached mapping table data;

[0010] If the mapping level corresponding to the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the current cached mapping table data, the physical address corresponding to the current access is determined based on the current cached mapping table data.

[0011] According to one aspect of this application, an address mapping management apparatus is deployed in a storage device, the storage device including a mapping table cache, the address mapping management apparatus comprising:

[0012] The command management module is used to obtain the parsing result of the current read / write command based on the current read / write command sent by the host;

[0013] The application scenario management module is used to determine the read / write type, logical address information, data length, and logical address range corresponding to the current access based on the parsing result of the current read / write command; to determine the access behavior corresponding to the current access based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access; and to determine the target mapping level from multiple mapping levels based on the access behavior and the data length, wherein different mapping levels correspond to different mapping space ranges.

[0014] The mapping table management module is used to determine the mapping level corresponding to the currently cached mapping table data in the mapping table cache area and the logical address range covered by the currently cached mapping table data. When the mapping level corresponding to the currently cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the currently cached mapping table data, the module determines the physical address corresponding to the current access based on the currently cached mapping table data.

[0015] In the above technical solution, the storage device can determine the target mapping level suitable for the current access based on the read / write type, logical address continuity, and data length. It further combines this with the mapping level corresponding to the currently cached mapping table data in the mapping table cache and the logical address range it covers to determine whether the currently cached mapping table data can be directly used for the current access. If the mapping level matches and the logical address range corresponding to the current access is already covered by the currently cached mapping table data, the currently cached mapping table data can be directly reused to determine the physical address corresponding to the current access, without needing to re-acquire other mapping table data for the current access. Therefore, the use of mapping table data can be adapted to the host's current access characteristics and the actual cache state of the mapping table cache, reducing unnecessary mapping table data loading or switching when the currently cached mapping table data can meet the access requirements. This improves the address mapping processing efficiency in scenarios with complex changes in host read / write requests and enhances the read / write performance of the storage device. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the implementation environment of an address mapping management method according to an exemplary embodiment;

[0017] Figure 2 This is a flowchart illustrating an address mapping management method according to an exemplary embodiment;

[0018] Figure 3 This is a schematic diagram of the hardware and functional module structure of a storage device in an application scenario;

[0019] Figure 4 This is a schematic diagram illustrating the mapping relationship between logical addresses and physical addresses corresponding to different mapping levels in an application scenario.

[0020] Figure 5 This is a user interface diagram of an application scenario used for verifying address mapping management functions. Detailed Implementation

[0021] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. Similar elements in different embodiments are referred to by related similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the present application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present application are not shown or described in the specification. This is to avoid obscuring the core parts of the present application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0022] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of certain embodiments and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0023] The serial numbers assigned to components in this application, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0024] In its research on the address mapping process of storage devices, the applicant discovered that the key factor affecting the efficiency of address mapping processing is not merely the large size of the mapping table between logical and physical addresses, but rather the interrelationship between the size of the mapping table data, the capacity of the mapping table cache, and host access behavior. Because the mapping table cache has a limited capacity, it is difficult to simultaneously store complete mapping table data between logical and physical addresses. Therefore, when the logical address accessed by the host changes, the corresponding mapping table data needs to be loaded according to the actual access location. The applicant further noted that in complex scenarios where sequential read / write and random read / write operations alternate, if the mapping table data needs to be frequently loaded or switched according to the access location, it will consume the data access time of the storage medium and may interrupt normal data transmission. Therefore, the real challenge is not simply expanding the mapping table cache or reducing a particular mapping table load, but rather, under the condition of limited mapping table cache resources, ensuring that the organization and usage of the mapping table data can adapt to the constantly changing actual access characteristics of the host.

[0025] In analyzing the aforementioned problems, the applicant first examined the approach of using a fixed mapping space range for address mapping management. While a fixed mapping space range facilitates maintaining a consistent mapping relationship, the applicant found that different host accesses have varying requirements for the mapping space range. For continuous access with large amounts of data, using a smaller mapping space range might involve multiple segments of mapping table data in a single continuous access, increasing the chances of loading and switching mapping table data. Conversely, for random access with frequent logical address jumps and relatively small single access ranges, consistently using a larger mapping space range would cause the currently loaded mapping table data to cover many logical addresses that are not needed in the current access. Therefore, a single fixed mapping space range is insufficient to simultaneously accommodate different access behaviors. Based on this, the applicant developed the idea of ​​setting multiple mapping levels, with each mapping level corresponding to a different mapping space range, thus providing a basis for subsequently selecting the appropriate mapping relationship based on actual access characteristics. This multi-mapping-level design is not simply about adding more mapping tables, but rather an adaptation mechanism to address the contradiction between reducing mapping table segment switching for large-scale continuous access and avoiding loading too many irrelevant mapping relationships for small-scale random access.

[0026] However, simply setting multiple mapping levels still doesn't solve the problem of choosing which mapping level to select at what time. Further analysis revealed that selecting the mapping level solely based on whether the current command is a read or write command fails to reflect the continuity of host access within the logical address space. The same read or write operation could manifest as continuous large-volume access or as random access with frequent logical address jumps. Furthermore, selecting based solely on logical address continuity fails to differentiate the data scale of different consecutive accesses. Therefore, instead of using a single access parameter as the basis for mapping level selection, the applicant first uses the read / write type and the continuity between the current access and the logical address information corresponding to previous accesses to determine the access behavior corresponding to the current access. Then, this access behavior is combined with the data length of the current access to determine the target mapping level. Thus, the read / write type reflects the data operation attributes of the current access, logical address continuity reflects the changing characteristics of the host access location, and data length reflects the data scale of the current access. These three factors, when correlated, form the basis for mapping level selection, ensuring that the determined target mapping level better reflects the actual characteristics of the current host access. For sequential access, different mapping levels with a larger mapping space can be selected based on the data length; for random access, a mapping level with a smaller mapping space can be used, thereby establishing a correspondence between host access characteristics and target mapping levels.

[0027] Further research into the actual use of the target mapping level revealed that simply determining the target mapping level is insufficient to decide whether to update the mapping table data in the mapping table cache. This is because the mapping table cache typically only stores a portion of all mapping table data corresponding to a given mapping level. Therefore, the fact that the currently cached mapping table data is the same as the target mapping level does not equate to the current cached mapping table data containing the address mapping required for the current access. For example, the currently cached mapping table data may belong to the first mapping level, but it may only actually cover a range of logical addresses within that first mapping level. When a new current access still requires the first mapping level, but the corresponding logical address exceeds that range, continuing to use the current mapping table data solely based on the mapping level consistency will not yield the physical address corresponding to the current access. The applicant thus identified a further cache state constraint: when determining whether the currently cached mapping table data can continue to be used, both the corresponding mapping level and the actual logical address range it covers must be considered, rather than solely judging the mapping level itself. Based on this understanding, the applicant further compared the target mapping level with the mapping level corresponding to the current cache mapping table data, and compared the logical address range corresponding to the current access with the logical address range covered by the current cache mapping table data. Only when the mapping levels are consistent and the logical address ranges match, is the current cache mapping table data directly reused to determine the physical address corresponding to the current access. This dual-condition judgment establishes a true connection between the target mapping level obtained based on the access behavior and data length and the actual cache state of the mapping table cache area.

[0028] Even with the aforementioned dual-condition judgment, the applicant still needs to address how to update the mapping table data when both conditions cannot be met simultaneously. The applicant further discovered that a miss is not a single state: one possibility is that the mapping level corresponding to the currently cached mapping table data is still consistent with the target mapping level, but cannot be used simply because the logical address range corresponding to the current access exceeds the logical address range covered by the current cached data; another possibility is that the host access behavior or data length changes, causing the target mapping level itself to differ from the current cached mapping level. If these two states are uniformly understood as a simple "reloading of the mapping table," the reasons for changes in the mapping table cache state cannot be accurately reflected. Therefore, when the mapping level is consistent but the logical address range is missed, the target mapping level can be kept unchanged, and another part of the mapping table data covering the logical address range corresponding to the current access can be loaded under the same mapping level; while when the mapping levels are inconsistent, the mapping table data covering the logical address range corresponding to the current access under the target mapping level can be loaded, realizing the switching between different mapping levels. In this way, the update of the mapping table data is no longer triggered by a single level change, but is determined by the target mapping level and the logical address coverage range. Thus, under the constraint that the mapping table cache can only store a portion of the mapping table data, a reuse, same-level update and cross-level update mechanism corresponding to the actual access needs is formed.

[0029] Through the above research, the applicant's actual need is not simply to choose a larger or smaller mapping table, nor is it simply to determine whether the current mapping table needs to be refreshed. Rather, it is to create a complete technical chain that coordinates mapping level selection, current cache status judgment, and mapping table data updates under multiple constraints, including limited mapping table cache space, dynamically changing host access behavior, different accesses having different data sizes, and the current cache mapping table only covering a portion of the logical address range. Based on this, the applicant ultimately developed an address mapping management scheme that obtains the read / write type, logical address information, and data length based on the current read / write command; determines the access behavior using the read / write type and the logical address continuity between the current access and previous accesses; determines the target mapping level based on the access behavior and data length; and then determines whether the current cache mapping table data can continue to be used by combining the mapping level and logical address coverage range of the current cache mapping table data. Based on the judgment result, it executes the current mapping table data reuse or the corresponding mapping table data update. This scheme enables mapping table data of different mapping space ranges to adapt to the actual access characteristics of the host and the cache state, reducing unnecessary loading when the current cached data can meet the access requirements, and reducing frequent mapping table switching caused by the mismatch between fixed mapping relationships and complex read and write behaviors. This improves the impact of address mapping processing on normal data read and write, and enhances the efficiency of address mapping processing and the operating performance of storage devices in complex host access scenarios.

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram of the implementation environment involved in an address mapping management method provided in this application embodiment. The implementation environment includes a host 200 and a storage device 100. The host 200 is communicatively connected to the storage device 100 and is used to send read / write commands to the storage device 100. The storage device 100 includes an address mapping management device 110 and a mapping table cache 120. The address mapping management device 110 includes a command management module 111, an application scenario management module 112, and a mapping table management module 113.

[0032] The aforementioned implementation environment represents the hardware interaction between the host 200 and the storage device 100, as well as the relevant structures within the storage device 100 involved in address mapping management. Read and write commands sent by the host 200 can be received by the storage device 100, and the address mapping management device 110 can perform corresponding address mapping management in conjunction with the mapping table data cached in the mapping table cache area 120.

[0033] In one embodiment, the command management module 111 is used to obtain the parsing result of the current read / write command based on the current read / write command sent by the host.

[0034] The parsing result of the current read / write command refers to the information obtained after parsing the command fields and access parameters in the current read / write command, which may include command type, starting logical address, and number of transport blocks, etc. The application scenario management module can determine the read / write type and logical address information corresponding to the current access based on the parsing result, and further determine the data length and logical address range corresponding to the current access.

[0035] The application scenario management module 112 is used to determine the read / write type, logical address information, data length, and logical address range corresponding to the current access based on the parsing result of the current read / write command. Based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access, it determines the access behavior corresponding to the current access. Based on the access behavior and data length, it determines the target mapping level from multiple mapping levels, where different mapping levels correspond to different mapping space ranges.

[0036] The mapping table management module 113 is used to determine the mapping level corresponding to the current cached mapping table data in the mapping table cache area and the logical address range covered by the current cached mapping table data. When the mapping level corresponding to the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the current cached mapping table data, the physical address corresponding to the current access is determined based on the current cached mapping table data.

[0037] It should be noted that the address mapping management device provided in the above embodiments is only illustrated by the division of the above functional modules when performing address mapping management. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the address mapping management device will be divided into different functional modules to complete all or part of the functions described above.

[0038] Furthermore, the address mapping management device and address mapping management method embodiments provided above belong to the same concept, and the specific methods by which each module performs its operations will be described in detail in subsequent method embodiments, and will not be repeated here. For details not disclosed in the device embodiments of this application, please refer to the method embodiments of the address mapping management method involved in this application.

[0039] Please see Figure 2 This application provides an address mapping management method applicable to storage devices, which include a mapping table cache. The structure of the storage device can be as follows: Figure 1 As shown.

[0040] In the following method embodiments, for ease of description, the execution subject of each step of the method is a storage device as an example, but this does not constitute a specific limitation.

[0041] like Figure 2 As shown, the method may include the following steps:

[0042] Step 310: Based on the current read / write command sent by the host, determine the read / write type, logical address information, data length, and logical address range corresponding to the current access.

[0043] First, it should be noted that a host is a device that communicates with a storage device and sends read and write commands to the storage device, used to initiate data read or write requests to the storage device. For example, a host can be a System on Chip (SoC) host.

[0044] The current read / write command refers to the command currently received by the storage device, instructing the storage device to perform a data read operation or a data write operation; the current access refers to the data access process triggered by the current read / write command. The storage device can parse the current read / write command to obtain information that characterizes the operation type, access location, and amount of data accessed in this data access.

[0045] The read / write type is used to characterize the type of data operation corresponding to the current access. For example, the read / write type can be either read type or write type, to indicate that the current access is a read operation or a write operation, respectively.

[0046] Logical address information is used to characterize the location of data accessed by the host within the logical address space. Logical addresses can be represented, for example, using logical block addresses (LBAs). Logical address information can include the starting logical address corresponding to the current read / write command and can be used in subsequent processing to determine whether the logical address corresponding to the current access is contiguous with the logical address corresponding to the previous access. For example, the current access can start from a certain starting LBA and access one or more consecutive logical blocks.

[0047] Data length refers to the amount of data involved in the current read / write command, used to characterize the scale of the data being accessed. Different current read / write commands can correspond to different data lengths. Subsequently, the appropriate target mapping level for the current access can be determined by combining the access behavior and data length corresponding to the current access.

[0048] The logical address range refers to the logical address interval involved in the current access, representing the range of locations covered by this access in the logical address space. For example, the logical address range corresponding to the current access could be LBA 1000~3047. In subsequent processing, the logical address range is also used to compare with the logical address range covered by the currently cached mapping table data in the mapping table cache area to determine whether the currently cached mapping table data covers the logical address required by the current access.

[0049] In step 310, the current read / write command sent by the host is converted into information that characterizes the current access, such as read / write type, logical address information, data length, and logical address range. The read / write type and logical address information provide a basis for determining the access behavior corresponding to the current access; the data length provides a basis for determining the target mapping level; and the logical address range provides a basis for determining whether the currently cached mapping table data can be directly used for the current access. This provides the foundational data for subsequent mapping level selection and address mapping processing.

[0050] In some embodiments, step 310 may further include the following steps: obtaining the read / write type, starting logical address, and number of transport blocks from the current read / write command; determining the data length based on the number of transport blocks and the data size of a single logical block; and determining the logical address range corresponding to the current access based on the starting logical address and the number of transport blocks.

[0051] The starting logical address refers to the logical address corresponding to the start position of this data access indicated by the current read / write command, used to determine the starting position of the current access in the logical address space. The number of transport blocks refers to the number of logical blocks that need to be transported in this data access indicated by the current read / write command, used to characterize the number of logical blocks involved in the current access. The data size of a single logical block refers to the amount of data corresponding to one logical block. Therefore, the data length corresponding to the current access can be determined based on the number of transport blocks and the data size of a single logical block; that is, the data length corresponding to the current access is the product of the number of transport blocks and the data size of a single logical block.

[0052] Furthermore, the logical address range corresponding to the current access can be determined based on the starting logical address and the number of transport blocks. Specifically, the starting logical address determines the starting access position corresponding to the current access, and the number of transport blocks determines the number of logical blocks to be accessed from that starting access position, thereby determining the logical address range covered by this access. For example, after the starting logical address is determined, multiple consecutive logical blocks can be determined starting from that starting logical address according to the number of transport blocks corresponding to the current read / write command, and the logical addresses corresponding to these multiple logical blocks can be determined as the logical address range corresponding to the current access.

[0053] Through the above processing, the length of the currently accessed data and the logical address range can be directly obtained using the information carried by the current read / write command. The data length is used to determine the target mapping level based on the access behavior corresponding to the current access, and the logical address range is used to determine whether the mapping relationship required by the current access is already included in the currently cached mapping table data. This allows the access parameters in the current read / write command to further participate in subsequent mapping level selection and mapping table data usage judgments.

[0054] Step 330: Based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access, determine the access behavior corresponding to the current access, and determine the target mapping level from multiple mapping levels based on the access behavior and data length.

[0055] Different mapping levels correspond to different mapping space ranges. Access behavior characterizes the data read / write method and logical address access characteristics of the current access. In this embodiment, the storage device does not determine the processing method of the current access solely based on the read or write operation indicated by the current read / write command, but further combines the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access to determine the access characteristics of the current access. Therefore, the access behavior can simultaneously reflect the read / write attributes and logical address change characteristics of the current access, serving as the basis for subsequent selection of the mapping level.

[0056] A previous access refers to a data access that precedes the current access and is temporally adjacent to it. The continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access is used to characterize whether the host's data access proceeds continuously along the logical address space. In other embodiments, the continuity of host access can also be determined by combining the logical address information corresponding to multiple prior accesses preceding the current access.

[0057] Mapping level is used to characterize the mapping space range used by the mapping table data between logical addresses and physical addresses. Different mapping levels correspond to different mapping space ranges; that is, mapping table data under different mapping levels can use different sizes of logical address mapping ranges. The target mapping level refers to the mapping level determined from multiple mapping levels based on the access behavior and data length corresponding to the current access, and is suitable for the current access. In subsequent processing, the target mapping level is used to compare with the mapping level corresponding to the currently cached mapping table data in the mapping table cache to determine whether the currently cached mapping table data has a mapping level suitable for the current access.

[0058] It should be noted that different access behaviors correspond to different data access characteristics. For example, continuous access usually involves data access along consecutive logical addresses, while non-contiguous access may involve logical address jumps; at the same time, different accesses may also have different data lengths. If only a mapping table with a fixed mapping space range is used to process read and write requests with different access characteristics, the same mapping space range will be difficult to simultaneously adapt to accesses with different logical address continuities and different data lengths. Therefore, this embodiment, after determining the access behavior corresponding to the current access, further determines the target mapping level based on the data length of the current access, so that the determined mapping level can be adapted to the access characteristics of the current access.

[0059] Specifically, access behavior reflects the read / write attributes and logical address continuity of the current access, while data length reflects the scale of data involved in the current access. Both characterize the current read / write request from different dimensions. Determining the target mapping level based on both access behavior and data length avoids situations where selecting a mapping level solely based on a single access parameter fails to fully reflect the characteristics of the current access. Furthermore, the determined target mapping level does not directly indicate that the currently cached mapping table data in the mapping table cache can be used for the current access; rather, it serves as a criterion for subsequent judgments on whether the currently cached mapping table data can continue to be used.

[0060] Step 330 allows for the further conversion of the read / write type, logical address information, and data length obtained in step 310 into access behavior and target mapping level. The access behavior reflects the current read / write method and logical address change characteristics, while the target mapping level reflects the mapping space range suitable for the current access. This provides a basis for subsequent determination, based on the current cache state of the mapping table cache, of whether address mapping can be directly performed using the current cached mapping table data.

[0061] In some embodiments, step 330 may further include the following steps:

[0062] Step 331: Determine whether the current access is a read operation or a write operation based on the read / write type.

[0063] The read / write type can be determined by the operation type indicated by the current read / write command. For example, when the current read / write command indicates reading data from the storage device, the current access can be determined as a read operation; when the current read / write command indicates writing data to the storage device, the current access can be determined as a write operation. By distinguishing between read and write operations, the data operation attribute of the current access can be determined, and the access behavior corresponding to the current access can be further refined in combination with the subsequently determined logical address continuity.

[0064] Step 333: If the logical address information corresponding to the current access is continuous with the logical address information corresponding to the previous access, the current access is determined to be a sequential access; if the logical address information corresponding to the current access is not continuous with the logical address information corresponding to the previous access, the current access is determined to be a random access.

[0065] Here, a previous access refers to a data access that precedes the current access and is temporally adjacent to it. The continuity between logical address information is used to characterize whether the current access continues the access position of the previous access in the logical address space. Specifically, it can be determined whether the logical addresses involved in the current access are continuous with those involved in the previous access based on the logical address range corresponding to the previous access and the logical address information corresponding to the current access. In other embodiments, the continuity of host access can also be determined by combining the logical address information corresponding to multiple prior accesses preceding the current access.

[0066] For example, if the previous access ended at a first logical address and the current access begins at a subsequent logical address contiguous to that first logical address, it can be determined that the current access and the previous access are contiguous in the logical address space, thus classifying the current access as a sequential access. Conversely, if the logical address of the current access jumps relative to the logical address involved in the previous access, it can be determined that the current access is a random access.

[0067] It should be noted that this embodiment does not describe the current access solely based on whether the current read or write command is a read command or a write command. Instead, it further utilizes the logical address continuity between adjacent accesses to characterize the actual data access characteristics of the host. Therefore, different accesses that are both read operations or both write operations can be further distinguished into sequential accesses with consecutive logical addresses and random accesses with discontinuous logical addresses. This allows the subsequent selection of mapping levels to simultaneously consider both data operation attributes and logical address change characteristics.

[0068] Step 335: Based on the read operation or write operation and the sequential access or random access, determine the access behavior as sequential read, sequential write, random read or random write.

[0069] Specifically, if the current access is a read operation and is a sequential access, the access behavior can be determined as sequential read; if the current access is a write operation and is a sequential access, the access behavior can be determined as sequential write; if the current access is a read operation and is a random access, the access behavior can be determined as random read; and if the current access is a write operation and is a random access, the access behavior can be determined as random write.

[0070] Therefore, access behavior does not only represent data reading or writing, but also includes the read / write attributes of the current access as well as logical address continuity. Subsequently, based on the data access characteristics presented by different access behaviors and in combination with the data length of the current access, a target mapping level suitable for the current access can be determined.

[0071] In some embodiments, the mapping space range corresponding to the first mapping level is greater than the mapping space range corresponding to the second mapping level, and the mapping space range corresponding to the second mapping level is greater than the mapping space range corresponding to the third mapping level.

[0072] The mapping space range can be understood as the range of addresses that the mapping table data at the corresponding mapping level can represent between logical addresses and physical addresses. The larger the mapping space range, the larger the range of logical addresses that the corresponding mapping table data can cover; the smaller the mapping space range, the smaller the mapping range can be used to manage the mapping relationship between logical addresses and physical addresses.

[0073] For example, the first, second, and third mapping levels can correspond to different ranges of logical-to-physical (L2P) address mappings. The first mapping level can correspond to a larger L2P mapping range, the second to a medium range, and the third to a smaller range. The main difference between the different mapping levels is the range of their mapping spaces; there is no need to restrict them to using different mapping table structures.

[0074] In some embodiments, the method further includes the following steps: when the current access is a sequential access, determining a target mapping level from a first mapping level and a second mapping level based on the data length, wherein the mapping space range of the target mapping level corresponding to the sequential access with a larger data length is not less than the mapping space range of the target mapping level corresponding to the sequential access with a smaller data length; when the current access is a random access, determining a target mapping level based on the data length, wherein if the data length belongs to the data length range corresponding to a third mapping level, the third mapping level is determined as the target mapping level.

[0075] Specifically, sequential access is characterized by accessing logically contiguous addresses. When the data length for sequential access is large, using a mapping level with a small mapping space range may require involving multiple segments of mapping table data to complete a single sequential access of a large amount of data. Correspondingly, by selecting a mapping level with a larger mapping space range, the corresponding mapping table data can cover a larger range of contiguous logical addresses. Therefore, for sequential access, a target mapping level can be selected between the first and second mapping levels based on the data length, ensuring that the selected mapping space range is compatible with the current data size for sequential access.

[0076] For example, for sequential access with a large data length, the first mapping level can be determined as the target mapping level; for sequential access with a relatively small data length, the second mapping level can be determined as the target mapping level. Here, the data length is used to distinguish sequential accesses of different sizes, and is not limited to using a specific fixed length value.

[0077] Random access to logical addresses is characterized by discontinuity or jumps, and different random accesses can have different data lengths. Therefore, when the current access is random, the target mapping level can be determined based on the data length of the current access. For example, if the data length of the current random access falls within the range corresponding to the third mapping level, the third mapping level with a smaller mapping space range can be determined as the target mapping level. This allows the mapping table data to be more targeted to the actual logical address range involved in the current random access, without introducing a large irrelevant logical address mapping range. In one example, for random reads or random writes with data lengths of 4K, 8K, 16K, or 32K, the third mapping level can be determined as the target mapping level. The above data lengths are just examples; under different storage devices or application loads, the correspondence between the data length of random access and the corresponding mapping level can be configured according to the actual access characteristics.

[0078] Therefore, this embodiment does not select the mapping level solely based on data length or logical address contiguousness. Instead, it first determines the current access behavior based on read / write type and logical address contiguousness, and then determines the target mapping level based on data length, ensuring that the target mapping level matches the current data access method and data size. The determined target mapping level can also be compared with the mapping level corresponding to the currently cached mapping table data in the mapping table cache during subsequent processing to further determine whether the currently cached mapping table data can be directly used for the current access.

[0079] Step 350: Determine the mapping level corresponding to the currently cached mapping table data in the mapping table cache area and the logical address range covered by the currently cached mapping table data.

[0080] The currently cached mapping table data refers to the mapping table data that is currently loaded and stored in the mapping table cache area and can be used for address mapping between logical addresses and physical addresses. The currently cached mapping table data corresponds to one of multiple mapping levels and covers the corresponding logical address range. Therefore, the current cached mapping table data in the mapping table cache area can represent the current mapping table cache state through its corresponding mapping level and the logical address range it covers.

[0081] The mapping level corresponding to the currently cached mapping table data is used to characterize the mapping space range adopted by the mapping table data, so as to be compared with the target mapping level determined in step 330. The logical address range covered by the currently cached mapping table data is used to characterize the logical address range in which the mapping relationship can be directly obtained using the mapping table data, so as to determine whether the logical address corresponding to the current access is already included in the currently cached mapping table data.

[0082] It should be noted that when determining whether the currently cached mapping table data can be used for the current access, simply determining the mapping level corresponding to the currently cached mapping table data is insufficient to characterize whether it can satisfy the current access. This is because, even if the mapping level corresponding to the currently cached mapping table data is the same as the target mapping level required by the current access, the currently cached mapping table data may only cover a portion of the logical address range corresponding to that mapping level, while the logical address corresponding to the current access may be located in another logical address range. Based on this, this embodiment, in addition to determining the mapping level corresponding to the currently cached mapping table data, also determines the logical address range actually covered by the mapping table data, characterizing the current mapping table cache state from two dimensions: mapping level and logical address coverage range.

[0083] For example, the mapping table cache may currently cache mapping table data corresponding to the first mapping level, and this mapping table data covers LBA 0 to 8191. In this case, the first mapping level represents the mapping space range used by the currently cached mapping table data, while LBA 0 to 8191 represents the logical address range covered by the currently cached mapping table data. The information determined in step 350 can be compared with the target mapping level and the logical address range corresponding to the current access in subsequent steps.

[0084] Step 370: If the mapping level corresponding to the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the current cached mapping table data, determine the physical address corresponding to the current access based on the current cached mapping table data.

[0085] Specifically, the target mapping level determined in step 330 can be compared with the mapping level corresponding to the current cached mapping table data determined in step 350 to determine whether the current cached mapping table data adopts a mapping level that is compatible with the current access; at the same time, the logical address range corresponding to the current access can be compared with the logical address range covered by the current cached mapping table data to determine whether the mapping relationship between the logical address and the physical address that the current access needs to query is already included in the current cached mapping table data.

[0086] When the mapping level of the currently cached mapping table data matches the target mapping level, it indicates that the mapping space range used by the currently cached mapping table data matches the mapping space range determined based on the access behavior and data length of the current access. When the logical address range corresponding to the current access is included in the logical address range covered by the currently cached mapping table data, it indicates that the mapping relationship corresponding to the logical address involved in the current access already exists in the currently cached mapping table data. When both of the above conditions are met, the currently cached mapping table data can be queried directly to obtain the physical address mapped to the logical address corresponding to the current access, without needing to obtain other mapping table data for the current access.

[0087] For example, the currently cached mapping table data in the mapping table cache corresponds to the first mapping level and covers LBA 0 to 8191; the target mapping level corresponding to the current access is also the first mapping level, and the logical address range corresponding to the current access is LBA 1000 to 3047. Since the mapping level corresponding to the currently cached mapping table data is consistent with the target mapping level, and LBA 1000 to 3047 is included in LBA 0 to 8191, the physical address corresponding to the logical address involved in the current access can be directly queried based on the currently cached mapping table data.

[0088] This embodiment simultaneously determines whether the mapping level matches and whether the logical address range is hit, rather than deciding whether to use the currently cached mapping table data based on only one of these conditions. Mapping level matching ensures that the currently cached mapping table data is compatible with the current access behavior and data length, while logical address range hitting ensures that the address mapping relationship actually needed by the current access already exists in the currently cached mapping table data. By combining these two conditions, the currently cached mapping table data can be directly reused for address mapping when it meets the current access requirements, thereby reducing unnecessary mapping table data processing and improving address mapping processing efficiency.

[0089] Through steps 350 and 370, after determining the target mapping level based on the current access behavior and data length, the actual cache state of the mapping table cache area is further combined to determine whether the current cached mapping table data can be directly used for the current access. This establishes a correlation between the determination result of the target mapping level and the current cached mapping table data, thereby avoiding the situation where the current cached mapping table data is directly used based solely on the same mapping level while ignoring its actual logical address coverage.

[0090] Through the above process, the storage device can determine the target mapping level suitable for the current access based on the read / write type, logical address continuity, and data length. It then further combines this with the mapping level corresponding to the currently cached mapping table data in the mapping table cache and the logical address range it covers to determine whether the currently cached mapping table data can be directly used for the current access. If the mapping level matches and the logical address range corresponding to the current access is already covered by the currently cached mapping table data, the currently cached mapping table data can be directly reused to determine the physical address corresponding to the current access, without needing to retrieve other mapping table data for the current access. Therefore, the use of mapping table data can be adapted to the host's current access characteristics and the actual cache state of the mapping table cache, reducing unnecessary mapping table data loading or switching when the currently cached mapping table data can meet the access requirements. This improves the address mapping processing efficiency in scenarios with complex changes in host read / write requests and enhances the read / write performance of the storage device.

[0091] In one exemplary embodiment, the amount of data that the mapping table cache can store is less than the amount of data in the mapping table between logical addresses and physical addresses; the mapping table cache is used to cache a portion of the mapping table data in the mapping table data of the corresponding mapping level, and the portion of the mapping table data covers the corresponding portion of the logical address range.

[0092] In this context, "partial mapping table data" refers to a portion of the total mapping table data corresponding to a given mapping level. Since the amount of mapping table data between logical and physical addresses exceeds the capacity of the mapping table cache, the cache does not need to store all mapping table data for a given mapping level simultaneously. Instead, it can cache a portion of the mapping table data that covers the corresponding logical address range based on current usage requirements. Accordingly, the currently cached mapping table data in the cache not only has the corresponding mapping level but also the logical address range it currently covers.

[0093] For example, the mapping table data corresponding to the first mapping level may include data representing the mapping relationship between multiple logical address ranges and their corresponding physical addresses, while the mapping table cache may currently only cache a portion of the mapping table data covering LBA 0 to 8191. In this case, even if the target mapping level determined by subsequent access is still the first mapping level, if the logical address range corresponding to the subsequent access has exceeded LBA 0 to 8191, the currently cached portion of the mapping table data still cannot directly provide the address mapping relationship required by the subsequent access.

[0094] Therefore, given the limited storage capacity of the mapping table cache, whether the currently cached mapping table data can continue to be used cannot be determined solely by whether the mapping level is consistent; it also requires consideration of the logical address range actually covered by the currently cached mapping table data. This also allows the joint judgment of mapping level and logical address coverage in steps 350 and 370 to adapt to the actual operating state where the mapping table cache only caches a portion of the mapping table data.

[0095] In some embodiments, the above method further includes the following steps: if the mapping level corresponding to the current cached mapping table data is inconsistent with the target mapping level, or if the logical address range corresponding to the current access is not included in the logical address range covered by the current cached mapping table data, load the target mapping table data that covers the logical address range corresponding to the current access into the mapping table cache area, and determine the physical address corresponding to the current access based on the target mapping table data.

[0096] The target mapping table data refers to the mapping table data that provides the mapping relationship between the logical address and the physical address required for the current access at the target mapping level. The target mapping table data is used to replace the currently cached mapping table data or update the mapping data in the mapping table cache when the currently cached mapping table data cannot meet the address mapping requirements of the current access, thereby ensuring that the mapping table cache has a mapping relationship that can be used for the current access.

[0097] Specifically, if the mapping level corresponding to the currently cached mapping table data is inconsistent with the target mapping level, it means that the mapping space range used by the currently cached mapping table data does not match the mapping space range determined based on the current access behavior and data length. In this case, the mapping table data corresponding to the target mapping level can be loaded. If the mapping level corresponding to the currently cached mapping table data is consistent with the target mapping level, but the logical address range corresponding to the current access is not included in the logical address range covered by the currently cached mapping table data, it means that although the current mapping level can be adapted to the current access, the current actual cached mapping table data does not yet contain the address mapping relationship required by the current access. In this case, it is also necessary to load the target mapping table data that can cover the logical address range corresponding to the current access.

[0098] Therefore, the determination of whether the current cached mapping table data can continue to be used considers both the mapping level and the actual logical address coverage range, ensuring that mapping table updates are not simply triggered by changes in the mapping level. Even if the mapping level has not changed, if the current access exceeds the current cache logical address range, the corresponding mapping table data can be reloaded for the current access; conversely, if both the mapping level and the logical address range meet the current access requirements, the existing mapping table data can continue to be used. This allows the mapping table data in the mapping table cache to be adjusted accordingly to the current access requirements.

[0099] In some embodiments, the loading of the target mapping table data can also employ different update methods based on the relationship between the mapping level corresponding to the currently cached mapping table data and the target mapping level.

[0100] Specifically, if the mapping level corresponding to the current cached mapping table data is the same as the target mapping level, and the logical address range corresponding to the current access is not included in the logical address range covered by the current cached mapping table data, then another mapping table data under the target mapping level that covers the logical address range corresponding to the current access will be loaded into the mapping table cache area to replace the current cached mapping table data.

[0101] In this scenario, the mapping level required for the current access has not changed. The reason why the currently cached mapping table data cannot be used directly is that the logical address range covered by the currently cached mapping table data does not match the logical address range corresponding to the current access. Therefore, there is no need to change the mapping level; instead, the cached mapping table data can be replaced within the same mapping level to ensure that the updated mapping table data covers the logical address range corresponding to the current access.

[0102] For example, the mapping table cache currently caches mapping table data covering LBA 0 to 8191 at the first mapping level, while the target mapping level for the current access is still the first mapping level, but the logical address range corresponding to the current access is LBA500000 to 502047. In this case, although the mapping levels are the same, the currently cached mapping table data cannot cover the logical address range corresponding to the current access. Therefore, another mapping table data covering LBA 500000 to 502047 at the first mapping level can be loaded to replace the original mapping table data covering LBA 0 to 8191. Thus, the mapping table cache content can be updated while maintaining the mapping level.

[0103] If the mapping level corresponding to the current cached mapping table data is inconsistent with the target mapping level, the mapping table data under the target mapping level that covers the logical address range corresponding to the current access will be loaded into the mapping table cache area to replace the current cached mapping table data.

[0104] In this scenario, the currently cached mapping table data may not only have issues with incompatible logical address coverage, but its corresponding mapping level may also differ from the target mapping level required by the current access. Therefore, the currently cached mapping table data can be switched to the mapping table data corresponding to the current access at the target mapping level, ensuring that the updated mapping table data simultaneously meets the current access's requirements for both mapping level and logical address mapping relationship.

[0105] For example, if the mapping table cache currently caches the mapping table data corresponding to the first mapping level, and the target mapping level is determined to be the third mapping level based on the current access behavior and data length, then the mapping table data under the third mapping level that covers the logical address range corresponding to the current access can be loaded into the mapping table cache to replace the current cached mapping table data corresponding to the first mapping level.

[0106] Therefore, the above mapping table update process can include at least updates to mapping table data within the same level and updates to mapping table data between different mapping levels. The former is used to resolve the problem where the logical address range of the current cache cannot satisfy the current access even though the mapping levels are the same, while the latter is used to resolve the problem where the mapping level of the current cache does not match the target mapping level required by the current access. By distinguishing between these two states, updates can be performed according to the specific reason why the current cache mapping table data cannot satisfy the current access, rather than treating all misses uniformly.

[0107] In some embodiments, the target mapping table data is a portion of the mapping table data corresponding to the target mapping level, and this portion of the mapping table data covers the logical address range corresponding to the current access.

[0108] In other words, when it's necessary to update mapping table data in the mapping table cache, it's not required to load all mapping table data corresponding to the target mapping level into the mapping table cache. Instead, a portion of the mapping table data corresponding to the target mapping level that can cover the logical address range of the current access can be determined, and this portion of mapping table data can be loaded as the target mapping table data. This ensures that the actually loaded mapping table data corresponds to the logical address range required by the current access.

[0109] For example, if the target mapping level is the first mapping level, and the total mapping table data corresponding to the first mapping level can cover multiple different logical address ranges, but the current access only involves one of the logical address ranges, then the partial mapping table data covering that logical address range under the first mapping level can be determined as the target mapping table data, without loading the total mapping table data corresponding to the first mapping level.

[0110] In conjunction with the above embodiments, when the mapping table cache cannot simultaneously store all mapping table data between logical and physical addresses, it is possible to store only the mapping table data covering a portion of the logical address range under the corresponding mapping level in the mapping table cache. When processing the current access, the system first determines whether existing mapping table data can continue to be used based on the target mapping level corresponding to the current access and the current cache state of the mapping table cache. If both the mapping level and the logical address range meet the current access requirements, the currently cached mapping table data can be directly reused. If the mapping level does not match or the logical address range is not hit, the system can further load the mapping table data corresponding to the current access logical address range under the target mapping level, and update the mapping table data within the same level or between different mapping levels, depending on whether the mapping level has changed. Therefore, within a limited mapping table cache space, the caching, reuse, and updating of mapping table data can be adapted to the access characteristics of the current access and the actual logical address requirements, reducing unnecessary mapping table data loading and switching, and improving the address mapping processing efficiency in complex read / write request scenarios.

[0111] Please see Figures 3 to 5 The above address mapping management method will be further explained below using an application scenario of a storage device.

[0112] For ease of understanding, Figure 3 This illustrates a hardware and functional module structure related to data read / write and address mapping management within a storage device. Figure 3 The application scenario management module, command management module, and mapping table management module can respectively execute the corresponding address mapping management functions in the aforementioned embodiments; the read cache and write cache can be used to cache read data and data to be written, respectively. The mapping table cache can be implemented by random access storage resources inside the storage device used to run firmware and store mapping table data.

[0113] Figure 3 The power module in the memory can be used to power related components within the storage device. The UART in the UART interface stands for Universal Asynchronous Receiver / Transmitter. The UART interface can be used for data communication between the storage device and external devices; for example, it can be used to output log information during the storage device's operation. Read-only memory can be used to store firmware programs or related fixed data; static random access memory (SRAM) can be used to store data used during the storage device's operation.

[0114] Figure 3The LDPC processing module in the system uses Low-Density Parity-Check (LDPC) code. This module encodes data written to the storage medium and decodes or verifies data read from it. The randomization module is used to randomize the data to be written to the storage medium.

[0115] Figure 3 The NAND flash memory in the address mapping module can be NAND flash memory, a non-volatile storage medium used to store user data and mapping table data between logical and physical addresses. The mapping table management module can retrieve the corresponding mapping table data from the NAND flash memory according to the actual needs of the address mapping management process for use in address mapping processing.

[0116] Figure 3 The RISC-V controller in this context can be a main controller processor using the RISC-V Instruction Set Architecture. It runs the firmware program for the storage device and coordinates the command management module, application scenario management module, mapping table management module, and data read / write related modules to complete data read / write and address mapping processing. For example, upon receiving a host read / write request, the RISC-V controller can control the corresponding modules to complete read / write command parsing, access behavior determination, mapping level selection, and mapping table data management.

[0117] In this application scenario, the storage device can be, for example, an embedded MultiMediaCard (eMMC), a Universal Flash Storage (UFS) device, or other storage devices with similar address mapping management requirements. The following explanation uses an eMMC storage device as an example, but this is not intended to be limiting.

[0118] The host can be accessed via Figure 3 The eMMC interface shown sends read and write commands to the storage device. The command management module parses the current read and write commands sent by the host. The application scenario management module can determine the read / write type, logical address information, data length, and logical address range corresponding to the current access based on the parsing results, and further determine the access behavior corresponding to the current access based on the logical address continuity between the current access and previous accesses.

[0119] Logical addresses can be represented using logical block addresses (LBAs), and physical addresses can be represented using physical block addresses (PBAs). The logical-to-physical (L2P) mapping represents the correspondence between the logical addresses used by the host and the actual physical addresses within the storage medium. The host uses LBAs when accessing data, and the storage device can use the corresponding L2P mapping table data to determine the PBA corresponding to the LBA.

[0120] Please refer to further information. Figure 4 This application scenario has multiple mapping levels, each corresponding to a different mapping space range. For example, multiple mapping levels could include a first mapping level, a second mapping level, and a third mapping level. Figure 4 In the example shown, the first mapping level can correspond to L2P-Large, the second mapping level can correspond to L2P-Middle, and the third mapping level can correspond to L2P-Small. Figure 4 The “mapping table” in the text can represent the mapping table data that is currently loaded or used, used to characterize the correspondence between LBA and PBA.

[0121] L2P-Large, L2P-Middle, and L2P-Small are all used to describe the mapping relationship between LBA and PBA. Their main difference lies in the range of the mapping space corresponding to the data in the respective mapping tables, rather than necessarily using different mapping table data structures. The mapping space range corresponding to the first mapping level can be larger than that corresponding to the second mapping level, and the mapping space range corresponding to the second mapping level can be larger than that corresponding to the third mapping level.

[0122] Combination Figure 4 As shown in Table 1, a mapping unit in L2P-Large can correspond to a larger logical address mapping range, a mapping unit in L2P-Middle can correspond to a medium logical address mapping range, and a mapping unit in L2P-Small can correspond to a smaller logical address mapping range. In one example, L2P-Large can use a mapping relationship of 1 Page LBA to 512K Page PBA, L2P-Middle can use a mapping relationship of 1 Page LBA to 64K Page PBA, and L2P-Small can use a mapping relationship of 1 Page LBA to 4K Page PBA. The above values ​​are only used to illustrate the mapping space range relationship between different mapping levels and do not constitute a fixed limitation.

[0123] Table 1

[0124]

[0125] The mapping table cache can store less data than the total mapping table data between all LBAs and PBAs on the storage device. Therefore, it is unnecessary to load all mapping table data corresponding to a certain mapping level into the mapping table cache simultaneously. The mapping table cache can store only the mapping table data covering a portion of the logical address range at the corresponding mapping level. In this way, the current state of the mapping table cache can be characterized by at least the mapping level corresponding to the currently cached mapping table data and the logical address range actually covered by that mapping table data.

[0126] For example, the mapping table cache can currently cache a portion of the mapping table data corresponding to L2P-Large, covering LBA 0 to 8191. When a subsequent host accesses the site, even if the target mapping level determined by the current access is still L2P-Large, it is still necessary to determine whether the logical address range corresponding to the current access falls within LBA 0 to 8191. Therefore, having the same mapping level does not necessarily mean that the currently cached mapping table data can be directly used for the current access.

[0127] In this application scenario, the target mapping level can be determined based on the read / write type, logical address continuity, and data length corresponding to the host's current read / write command.

[0128] Specifically, sequential write (SW), sequential read (SR), random write (RW), and random read (RR) can be considered different access behaviors. When the logical address corresponding to the current access is contiguous with the logical address corresponding to the previous access, the current access can be determined as a sequential access; when the logical address corresponding to the current access changes, the current access can be determined as a random access. Further determining whether the current access is a read or write operation allows us to further deduce SW, SR, RW, or RR.

[0129] For sequential access, since the host transmits data within a contiguous logical address range, it can select a target mapping level that matches the current data size from among the mapping levels with a larger mapping space, based on the length of the data being accessed. For example, sequential access with a larger data length can choose L2P-Large, while sequential access with a relatively smaller data length can choose L2P-Middle.

[0130] In one exemplary implementation, for SW or SR with a data length of 512K, 1M, 4M or 8M, L2P-Large can be selected as the target mapping level; for SW or SR with a data length of 64K, 128K or 256K, L2P-Middle can be selected as the target mapping level.

[0131] For example, for a sequential write operation with a data length of 8M, when one mapping range of L2P-Large corresponds to 512K, the mapping range involved in covering 8M of contiguous data can be represented by 16 corresponding mapping units; if a smaller mapping level corresponding to 64K is used, covering the same 8M of contiguous data may involve more mapping units. When the mapping table cache capacity is limited, using a mapping space range adapted to larger contiguous accesses can reduce the number of mapping table data segments that need to be processed during the completion of such contiguous accesses.

[0132] For random access, since the logical addresses of adjacent accesses may change, and different random accesses can have different data lengths, the target mapping level can be determined based on the data length of the current random access. For example, if the data length of the current random access falls within the range corresponding to the third mapping level, L2P-Small can be selected as the target mapping level. This makes the mapping table data more targeted to the actual logical address location of the current access, without introducing a large range of irrelevant logical address mappings. In one example, for RW or RR with data lengths of 4K, 8K, 16K, or 32K, L2P-Small can be selected as the target mapping level.

[0133] It should be noted that the 512K, 1M, 4M, 8M, 64K, 128K, 256K, 4K, 8K, 16K, and 32K mentioned above are example data lengths given for illustrative purposes. Other data length ranges and their corresponding mapping levels can be configured according to actual read / write characteristics under different storage devices, different hosts, or different application loads.

[0134] After determining the target mapping level corresponding to the current access, the mapping table management module can further determine the mapping level corresponding to the current cached mapping table data in the mapping table cache area and the logical address range it covers. Based on the target mapping level, the mapping level of the current cached mapping table data, the logical address range corresponding to the current access, and the logical address range covered by the current cached mapping table data, it can determine whether the current cached mapping table data can be directly used for this address mapping.

[0135] When the mapping level corresponding to the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the current cached mapping table data, the physical address corresponding to the current access can be determined directly based on the current cached mapping table data.

[0136] For example, if the mapping table cache currently caches mapping table data corresponding to L2P-Large, covering LBA 0 to 8191, and the current access is a sequential write with a data length of 1MB, and the target mapping level determined by the current access is also L2P-Large, and the logical address range corresponding to the current access is LBA 1000 to 3047, then the current target mapping level is consistent with the current cache mapping level, and LBA 1000 to 3047 is within LBA 0 to 8191. In this case, the corresponding PBA can be obtained by directly querying the current mapping table data in the mapping table cache without reloading other mapping table data.

[0137] Conversely, even if the target mapping level determined by the current access is consistent with the mapping level of the current cache, if the logical address range corresponding to the current access is not covered by the mapping table data of the current cache, the mapping table data in the mapping table cache area still needs to be updated.

[0138] For example, the mapping table cache still caches mapping table data covering LBA 0 to 8191 under L2P-Large. The current access is still a sequential access corresponding to L2P-Large, but the logical address range corresponding to the current access is LBA 500000 to 502047. In this case, although the target mapping level has not changed, the currently cached mapping table data does not contain the address mapping relationship required for this access. Therefore, another part of the mapping table data covering LBA 500000 to 502047 under L2P-Large can be loaded into the mapping table cache to replace the original part of the mapping table data. This update process can be understood as an update between different mapping table data segments within the same mapping level.

[0139] If the current cached mapping table data corresponds to a different mapping level than the target mapping level, an update between the different mapping levels can be performed. For example, if the mapping table cache currently caches the mapping table data corresponding to L2P-Large, and the host initiates a random write operation with a data length of 16K, and the target mapping level determined based on the current access is L2P-Small, then the mapping table data under L2P-Small that covers the current access logical address range can be loaded into the mapping table cache to replace the original L2P-Large mapping table data.

[0140] Therefore, in this application scenario, whether the mapping table data needs to be updated is not simply determined by whether two adjacent host commands have the same read / write type, nor solely by whether the target mapping level has changed. Instead, the actual cached logical address range in the mapping table cache is also considered. By simultaneously considering both "mapping level matching" and "whether the current access logical address range is hit," it is possible to more accurately determine whether the existing mapping table data can be directly used for the current access.

[0141] Please refer to Table 1 for further details. In Table 1, "Host Step 1" and "Host Step 2" represent two consecutive accesses of the host. To maintain consistency with the terminology in the preceding embodiments, "Host Step 1" can be understood as the previous access, and "Host Step 2" as the current access. "LBA Length" indicates the data length configuration corresponding to the access; "Table Flush" indicates whether the currently cached mapping table data in the mapping table cache needs to be updated in the corresponding scenario; "Mapping Level" indicates the target mapping level determined based on the current access; and "Mapping Table" lists exemplary mapping space ranges corresponding to different mapping levels.

[0142] Table 1 illustrates an example of mapping level selection and mapping table update relationships under different combinations of adjacent access behaviors. In one example, host step 1 can be one of the following access behaviors: SW, RW, SR, or RR. Host step 2 can also be one of the following access behaviors: SW, RW, SR, or RR. The corresponding mapping level can be determined based on the access behavior corresponding to host step 2 and the data length, and whether the mapping table data needs to be updated can be determined based on the current state of the cached mapping table data.

[0143] For example, if the previous access and the current access both correspond to the same target mapping level, and the logical address range required by the current access has already been covered by the current cache mapping table data, the current cache mapping table data does not need to be updated; when the access behavior changes and causes the target mapping level to change, the new mapping level can be switched accordingly.

[0144] It should be noted that the "Whether to refresh the table" in Table 1 is used to illustrate the mapping table data update relationship that may be caused by changes in the target mapping level when adjacent access behaviors change. It does not mean that whether to update the mapping table data in the mapping table cache is determined solely by whether the previous access behavior and the current access or the target mapping level are the same. In actual address mapping management, whether the currently cached mapping table data can continue to be used also needs to be determined by simultaneously judging whether the mapping level corresponding to the currently cached mapping table data is consistent with the target mapping level, and whether the logical address range corresponding to the current access is included in the logical address range covered by the currently cached mapping table data.

[0145] Specifically, if the mapping level of the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included within the logical address range covered by the current cached mapping table data, the current cached mapping table data does not need to be updated, and address mapping can be performed directly using the current cached mapping table data. If the mapping level of the current cached mapping table data is consistent with the target mapping level, but the logical address range corresponding to the current access is not included within the logical address range covered by the current cached mapping table data, the mapping table data still needs to be updated within the same mapping level. If the mapping level of the current cached mapping table data is inconsistent with the target mapping level, the current cached mapping table data can be updated to the mapping table data under the target mapping level that covers the logical address range corresponding to the current access. Therefore, the "whether to flush the table" shown in Table 1 is an illustrative result given to facilitate the explanation of the relationship between adjacent access behavior and mapping level changes. The reuse or update of mapping table data in the actual operation of the mapping table cache area is based on the joint judgment result of the mapping level and logical address range.

[0146] Please see Figure 5 In research and development, testing, or parameter verification scenarios, it can also be used through Figure 5 The application scenario interface shown generates different host access scenarios to verify the above address mapping management process.

[0147] Figure 5 The "Mirror" option can be used to load or set up a test image; "Configuration" can be used to configure the test system; "Test Cases" can be used to select different test scenarios; "Sequential Write," "Sequential Read," "Random Write," and "Random Read" can be used to set or record the corresponding host access behaviors; "Data Length" can be used to set or record the read / write data length; "Commands" can be used to set or record the sequence of commands sent by the host to the storage device; "Summary" can be used to statistically analyze read / write performance under different mapping levels; "Read / Write Window" can be used to display the read / write process; and "Performance Window" can be used to display the corresponding performance statistics.

[0148] Figure 5 The application scenario interface shown is mainly used to generate, configure, or verify different host access scenarios. It is not a necessary component for the storage device to execute the address mapping management method described above during actual operation. In actual use, the host can directly send read and write commands to the storage device. The storage device completes access behavior identification, target mapping level determination, and mapping table cache management based on the actual received read and write commands, without needing to know in advance whether the terminal is a mobile phone, television, or other specific product type.

[0149] In an exemplary R&D verification scenario, after the system starts up, the System-on-Chip (SoC) host can load the corresponding test program and perform initialization configuration, including configuring the test scenario type, data length, and the type of command sent by the host. The host can then generate SW, SR, RW, or RR accesses with different data lengths.

[0150] For SW and SR, the target mapping level can be determined based on the data length, choosing between a larger or medium mapping space range. For example, for sequential access of 512K, 1M, 4M, or 8M, L2P-Large can be selected; for sequential access of 64K, 128K, or 256K, L2P-Middle can be selected. For RW and RR, if the corresponding data length falls within the data length range corresponding to the third mapping level, L2P-Small can be selected. For example, for RW or RR of 4K, 8K, 16K, or 32K, L2P-Small can be selected.

[0151] On the storage device side, after power-on, the corresponding hardware initialization can be completed, and the command management module, application scenario management module, and mapping table management module can be configured. The command management module can parse the commands sent by the host; the application scenario management module can determine the access behavior and target mapping level corresponding to the current access based on the parsed read / write type, logical address information, and data length; the mapping table management module can determine whether to directly use the current mapping table data or update the mapping table data in the mapping table cache based on the target mapping level and the current cached mapping table data status.

[0152] In the aforementioned R&D verification scenario, it is possible to configure whether to enable multiple mapping levels with different mapping space ranges. When multiple mapping levels are enabled, it is possible to further determine whether the logical address range corresponding to the current access can be mapped using the currently cached mapping table data. If the conditions for direct use are met, the address mapping can be completed using the currently cached mapping table data; if the conditions for direct use are not met, the mapping table data can be updated to be compatible with the current access.

[0153] In R&D verification scenarios, the performance of read and write operations using different mapping levels can be statistically analyzed, and the read and write performance under different mapping level selection strategies can be compared to verify whether the target mapping level configuration corresponding to different access behaviors and data lengths can meet the expected requirements. After verification, the corresponding address mapping management function can be configured in the storage device, so that the storage device can automatically execute the above address mapping management process according to the actual access behavior of the host during actual operation.

[0154] therefore, Figure 5The test configuration interface shown, along with the aforementioned test configuration, performance statistics, and performance comparison process, can be used during the R&D phase to verify the mapping level selection relationship, but does not constitute a necessary step in the actual address mapping management process. During actual operation, the storage device can directly determine the current access behavior and data length based on the real-time received host read / write commands, and perform target mapping level selection, mapping table data reuse, or mapping table data update based on the current access characteristics and the actual state of the mapping table cache.

[0155] Combination Figures 3 to 5 In addition to the aforementioned R&D and verification process, this application scenario combines different read / write behaviors generated on the host side with the multi-level address mapping management within the storage device. Host read / write commands are first parsed by the command management module. The application scenario management module determines the access behavior and target mapping level corresponding to the current access based on the read / write type, logical address continuity, and data length. The mapping table management module then combines the mapping level and logical address coverage of the current cached mapping table data in the mapping table cache area to determine whether the current cached mapping table data can be directly used for the current access.

[0156] If the mapping level matches the target mapping level and the logical address range is hit, the currently cached mapping table data can be directly reused; if the mapping level is the same but the logical address range is not hit, the corresponding mapping table data segment can be updated within the same mapping level; if the mapping levels are inconsistent, the mapping table data corresponding to the currently accessed logical address range under the target mapping level can be switched.

[0157] Therefore, when the mapping table cache space cannot store all mapping relationships at the same time, the corresponding mapping level can be selected according to the actual access characteristics of the host. The mapping table data can be reused and updated in combination with the current actual cached mapping level and logical address coverage of the mapping table cache area. This makes the use of mapping table data adapt to the current read and write requirements, reduces unnecessary mapping table data loading and switching, and improves the address mapping processing efficiency in complex host read and write scenarios.

[0158] In this application scenario, the storage device can determine the target mapping level suitable for the current access based on the read / write type, logical address continuity, and data length reflected by the host's current read / write command. It further combines this with the mapping level corresponding to the currently cached mapping table data in the mapping table cache and its actual covered logical address range to determine whether the currently cached mapping table data can be directly used for the current access. If the mapping level matches and the logical address range is hit, the currently cached mapping table data can be directly reused to complete the logical address to physical address translation. If the currently cached mapping table data cannot meet the current access requirements, mapping table data covering the required logical address range under the corresponding mapping level can be loaded for the current access. This allows mapping table data with different mapping space ranges to be adapted to the host's actual access behavior, the amount of data accessed, and the current cache state. When mapping table cache space is limited, unnecessary mapping table data loading and switching are reduced, and the impact of mapping table updates on normal data read / write is minimized, thereby improving the address mapping processing efficiency in complex read / write scenarios and the overall read / write performance of the storage device.

[0159] It should be understood that although the steps in the flowcharts of the accompanying drawings are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated in this application, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0160] This application has been described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this application. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0161] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0162] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles of this application can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium can be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CD-ROMs, DVDs, Blu-ray discs, etc.), flash memory, and other similar storage media. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executed on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct a computer or other programmable data processing apparatus to operate in a specific manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture including means for implementing the specified function. Computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions executed on the computer or other programmable apparatus provide steps for performing a specified function.

[0163] While the principles of this application have been illustrated in various embodiments, many modifications to the structure, arrangement, proportions, elements, materials, and components, particularly suitable for specific environments and operational requirements, may be used without departing from the principles and scope of this application. These modifications and other changes or alterations are to be included within the scope of this application.

[0164] The foregoing detailed description has been illustrated with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this application. Therefore, considerations for this application are to be illustrative rather than restrictive, and all such modifications are to be included within its scope. Similarly, advantages, other advantages, and solutions to problems with respect to various embodiments have been described above. However, benefits, advantages, solutions to problems, and any elements that produce these, or make them more explicit, should not be construed as critical, essential, or necessary. The term "comprising" and any other variations thereof as used in this application are non-exclusive inclusion, meaning that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed or not part of the process, method, system, article, or apparatus. Furthermore, the term "coupled" and any other variations thereof as used in this application refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections, and / or any other connections.

[0165] Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the basic principles of this application. Therefore, the scope of this application should be determined only by the claims.

Claims

1. An address mapping management method, characterized in that, Applied to a storage device, the storage device including a mapping table cache, the method includes: Based on the current read / write command sent by the host, determine the read / write type, logical address information, data length, and logical address range corresponding to the current access; Based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access, the access behavior corresponding to the current access is determined, and based on the access behavior and the data length, a target mapping level is determined from multiple mapping levels, wherein different mapping levels correspond to different mapping space ranges; Determine the mapping level corresponding to the currently cached mapping table data in the mapping table cache area and the logical address range covered by the currently cached mapping table data; If the mapping level corresponding to the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the current cached mapping table data, the physical address corresponding to the current access is determined based on the current cached mapping table data.

2. The address mapping management method as described in claim 1, characterized in that, The step of determining the read / write type, logical address information, data length, and logical address range corresponding to the current access based on the current read / write command sent by the host includes: Obtain the read / write type, starting logical address, and number of transport blocks from the current read / write command; The data length is determined based on the number of transport blocks and the data size of a single logical block; The logical address range corresponding to the current access is determined based on the starting logical address and the number of transport blocks.

3. The address mapping management method as described in claim 1, characterized in that, The step of determining the access behavior corresponding to the current access based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access includes: The current access is determined to be a read operation or a write operation based on the read / write type. If the logical address information corresponding to the current access is continuous with the logical address information corresponding to the previous access, the current access is determined to be a sequential access; if the logical address information corresponding to the current access is not continuous with the logical address information corresponding to the previous access, the current access is determined to be a random access. Based on the read operation or the write operation, and the sequential access or the random access, the access behavior is determined to be sequential read, sequential write, random read, or random write.

4. The address mapping management method as described in claim 1, characterized in that, The multiple mapping levels include a first mapping level, a second mapping level, and a third mapping level; The mapping space range corresponding to the first mapping level is greater than the mapping space range corresponding to the second mapping level, and the mapping space range corresponding to the second mapping level is greater than the mapping space range corresponding to the third mapping level.

5. The address mapping management method as described in claim 4, characterized in that, The step of determining the target mapping level from multiple mapping levels based on the access behavior and the data length includes: When the current access is a sequential access, the target mapping level is determined from the first mapping level and the second mapping level according to the data length, wherein the mapping space range of the target mapping level corresponding to the sequential access with a larger data length is not less than the mapping space range of the target mapping level corresponding to the sequential access with a smaller data length. When the current access is a random access, the target mapping level is determined based on the data length, wherein if the data length falls within the data length range corresponding to the third mapping level, the third mapping level is determined as the target mapping level.

6. The address mapping management method as described in claim 1, characterized in that, The amount of data that the mapping table cache can store is less than the amount of data in the mapping table between logical addresses and physical addresses; The mapping table cache is used to cache a portion of the mapping table data in the mapping table data of the corresponding mapping level, and the portion of the mapping table data covers the corresponding portion of the logical address range.

7. The address mapping management method as described in claim 6, characterized in that, Also includes: If the mapping level corresponding to the current cached mapping table data is inconsistent with the target mapping level, or if the logical address range corresponding to the current access is not included in the logical address range covered by the current cached mapping table data, the target mapping table data that covers the logical address range corresponding to the current access under the target mapping level is loaded into the mapping table cache area, and the physical address corresponding to the current access is determined based on the target mapping table data.

8. The address mapping management method as described in claim 7, characterized in that, The step of loading the target mapping table data covering the logical address range corresponding to the current access under the target mapping level into the mapping table cache includes: If the mapping level corresponding to the current cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is not included in the logical address range covered by the current cached mapping table data, then another mapping table data under the target mapping level that covers the logical address range corresponding to the current access is loaded into the mapping table cache area to replace the current cached mapping table data. If the mapping level corresponding to the currently cached mapping table data is inconsistent with the target mapping level, the mapping table data under the target mapping level that covers the logical address range corresponding to the current access is loaded into the mapping table cache area to replace the currently cached mapping table data.

9. The address mapping management method as described in claim 7, characterized in that, The target mapping table data is a portion of the mapping table data corresponding to the target mapping level, and the portion of the mapping table data covers the logical address range corresponding to the current access.

10. An address mapping management device, characterized in that, Deployed on a storage device, the storage device including a mapping table cache, the address mapping management device includes: The command management module is used to obtain the parsing result of the current read / write command based on the current read / write command sent by the host; The application scenario management module is used to determine the read / write type, logical address information, data length, and logical address range corresponding to the current access based on the parsing result of the current read / write command; to determine the access behavior corresponding to the current access based on the read / write type and the continuity between the logical address information corresponding to the current access and the logical address information corresponding to the previous access; and to determine the target mapping level from multiple mapping levels based on the access behavior and the data length, wherein different mapping levels correspond to different mapping space ranges. The mapping table management module is used to determine the mapping level corresponding to the currently cached mapping table data in the mapping table cache area and the logical address range covered by the currently cached mapping table data. When the mapping level corresponding to the currently cached mapping table data is consistent with the target mapping level, and the logical address range corresponding to the current access is included in the logical address range covered by the currently cached mapping table data, the module determines the physical address corresponding to the current access based on the currently cached mapping table data.

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