Strap configuration method of CPLD and electronic equipment

Abstract

The application provides a strap configuration method of a CPLD and an electronic device. A strap configuration value written by an external controller is received through a communication bus and stored in a strap configuration register. The strap configuration register is monitored in real time. When a change in the strap configuration register is detected, a UFM write operation is automatically triggered to write the changed value in the strap configuration register into the UFM for solidification storage. Before a power-on or reset operation of a main chip is controlled, a UFM read operation is performed to read the strap configuration value from the UFM and drive it to a GPIO pin. After the strap level output by the GPIO pin reaches a stable state, a reset signal is released from a reset control end of the main chip or a power supply module is controlled to complete power-on.

Description

Technical Field

[0001] This application relates to CPLD technology, and more particularly to a CPLD Strap configuration method and electronic device. Background Technology

[0002] In chip system design, a Strap is a specific physical pin used for hardware configuration. Hardware Strap configuration is a technique that uses the chip to latch the level of specific pins at power-on or reset release to determine the chip's operating mode. Typical applications include: setting the CPU clock frequency, selecting the boot medium (such as SPI Flash or NAND Flash), configuring the PCIe interface speed mode (such as Gen4 or Gen5), setting the serial port baud rate, and selecting the USB interface operating mode (Host or Device). The levels of these Strap pins are typically sampled and latched at the edge of the chip's reset signal release. After sampling, these pins are often released and multiplexed for high-speed signal functions such as RGMII, RMII, and SPI.

[0003] Currently, one method for configuring chip hardware Strap uses the GPIO pins of a CPLD or MCU to control the Strap level. This approach can be further subdivided into two sub-solutions: First, the GPIO output level is hardcoded in the CPLD or MCU firmware. While this method offers some flexibility compared to pull-up / pull-down resistors, modifying the Strap configuration still requires re-flashing the firmware, making the process cumbersome. Second, configuration values ​​are written to the CPLD's registers by an external controller (such as a BMC or MCU) via a communication interface (e.g., I2C, SPI) before power-on or reset. The CPLD then drives the GPIO output to the corresponding level. Although this sub-solution achieves dynamic configuration at the communication interface level, its configuration values ​​are only stored in the CPLD's volatile registers, which are lost after each system power-down. Upon power-up, the external controller must rewrite the values, making the process cumbersome, prone to system startup anomalies due to missing or incorrect configurations, and unable to meet the requirements of mass production lines for configuration persistence. Summary of the Invention

[0004] In view of this, this application provides a CPLD Strap configuration method and an electronic device.

[0005] According to a first aspect of the embodiments of this application, a Strap configuration method for a CPLD is provided. The CPLD has a built-in user flash memory (UFM) and a Strap configuration register. The Strap configuration register is used to temporarily store the currently effective Strap configuration value. The UFM serves as a non-volatile backup storage area for permanently storing the Strap configuration value. The CPLD is connected to an external controller via a communication bus and to the Strap pin and reset control terminal of the main chip via general purpose input / output (GPIO) pins. The method includes the following steps: The communication bus receives the Strap configuration value written by the external controller and stores it in the Strap configuration register; the value of the Strap configuration register is monitored in real time, and when the value of the Strap configuration register changes, a UFM write operation is automatically triggered to write the changed value in the Strap configuration register into the UFM for fixed storage. Before controlling the main chip to perform a power-on or reset operation, a UFM read operation is performed first to read the Strap configuration value from the UFM and drive it to the GPIO pin to drive the GPIO pin to output the corresponding Strap level; After confirming that the Strap level output by the GPIO pin has reached a stable state, the main chip's reset control terminal is controlled to release the reset signal or the power supply module is controlled to power on, so that the main chip latches the Strap configuration represented by the GPIO pin at the reset release edge or power-on moment.

[0006] According to a second aspect of the embodiments of this application, an electronic device is provided, including a memory, a CPLD chip, and a computer program stored in the memory and executable on the CPLD. The CPLD has a built-in user flash memory (UFM) and a Strap configuration register. The Strap configuration register is used to temporarily store the currently effective Strap configuration value. The UFM serves as a non-volatile backup storage area for permanently storing the Strap configuration value. The CPLD is connected to an external controller via a communication bus and to the Strap pin and reset control terminal of the main chip via general purpose input / output (GPIO) pins. When the CPLD chip executes the program, it implements the steps of the method described in the first aspect.

[0007] The CPLD Strap configuration method proposed in this invention utilizes the CPLD's built-in user flash memory (UFM) as a non-volatile backup storage area, and works in conjunction with the Strap configuration register. This allows the Strap configuration value to be retained even after power failure, while new configuration values ​​can be written at any time via an external controller through the communication bus. This balances the flexible modification requirements during the debugging phase with the stable solidification requirements during mass production. Since the UFM itself is an internal resource of the CPLD, there is no need to add an external storage chip, which saves BOM costs and reduces PCB layout space, making it particularly suitable for compact board-level designs. Attached Figure Description

[0008] Figure 1a This is a logic block diagram illustrating a portion of the internal structure of a CPLD according to an exemplary embodiment of this application; Figure 1b This is a partial flowchart illustrating an exemplary embodiment of a CPLD Strap configuration method; Figure 2 This is a schematic diagram illustrating the UFM storage page structure and CRC check mechanism in an exemplary embodiment of this application; Figure 2a This is a timing diagram for safe power-down / power-up when modifying Strap configuration at runtime; Figure 3 This is a logic block diagram illustrating another internal structure of a CPLD as shown in an exemplary embodiment of this application; Figure 3a This is an exemplary embodiment of the present application illustrating an EFB embedded functional block diagram; Figure 4 This is an exemplary embodiment of the present application illustrating the CPLD-controlled Strap configuration and power-on timing diagram; Figure 5 This is a timing diagram of a Wishbone bus write operation illustrated in an exemplary embodiment of this application; Figure 6 This is a timing diagram of a Wishbone bus read operation illustrated in an exemplary embodiment of this application; Figure 7 This is a logic block diagram of an electronic device illustrated in an exemplary embodiment of this application. Detailed Implementation

[0009] In system hardware design, it is often necessary to configure hardware straps for the main chip. A hardware strap is a hardware configuration method that uses the high and low voltage levels of specific pins on the main chip during power-on or reset to inform the chip of its operating mode, clock frequency, and boot mode from memory. The voltage levels of these pins are sampled and latched at the edge of the chip's reset signal release. After latching, the chip determines its operating state based on the read voltage level combination. Because this latching action occurs only within a very short time at the reset release edge, the voltage level must be established and stabilized before this moment. Latching too early or too late will lead to latching failure, resulting in chip startup anomalies or functional errors. After sampling, these strap pins are often released and reused for high-speed signal functions such as RGMII and SPI. Therefore, the timing of the strap level output must be precisely controlled within a very narrow time window before and after the reset release. Outputs outside this window will continuously occupy the pin and affect its multiplexing function.

[0010] The inventors attempted to use an external non-volatile memory chip (such as EEPROM) in conjunction with a CPLD to achieve persistent storage of the Strap configuration.

[0011] However, while this approach formally achieves non-volatile storage of configuration values, there is room for optimization in terms of performance and implementation. This invention proposes a better implementation path that effectively avoids the shortcomings of external storage solutions.

[0012] First, the external EEPROM communicates with the CPLD via the I²C bus. However, the I²C bus speed is usually limited to 400kHz or 1MHz, and the time required to read the complete configuration data is relatively long. This makes it difficult to meet the stringent timing requirement that the Strap level must be established within a very short time window before the reset release after the main chip is powered on.

[0013] Secondly, this solution requires an additional independent EEPROM chip, which not only increases material costs but also occupies the already limited PCB layout space, making it unsuitable for board designs with very compact space.

[0014] More critically, the external EEPROM only performs simple storage functions, and its read operations are independent of the system power-on timing control. The CPLD cannot integrate configuration reading with power management, reset release, and other steps into a precise and controllable timing sequence, making it difficult to guarantee the accuracy of the timing of the Strap level output and the reset release edge. In addition, the CPLD's GPIO pins in this solution usually need to continuously drive the Strap level. After the Strap pins complete the level latching, they are often multiplexed as high-speed signal pins such as RGMII and SPI. Continuous drive of the output introduces additional load capacitance and trace stubs, which seriously degrades the signal integrity of high-speed signals.

[0015] Therefore, the inventors designed a dedicated Strap configuration management scheme that simultaneously addresses the conflicting requirements of flexible modification and power-down persistence of Strap configuration values. Furthermore, it enables rapid and reliable output of the correct Strap level within an extremely narrow timing window before the main chip resets and releases, while avoiding any impact on signal integrity caused by the Strap pin multiplexing function. This allows for effective application in chip-level hardware Strap configuration, a scenario with extremely stringent timing and signal quality requirements. Based on the above analysis, the present invention proposes the following specific implementation method.

[0016] This invention incorporates a user flash memory (UFM) within the CPLD as a non-volatile backup storage area, and correspondingly configures a Strap configuration register to temporarily store the currently effective configuration value. The CPLD receives new Strap configuration values ​​written by an external controller via the communication bus and stores them in the Strap configuration register. Simultaneously, it monitors the register's value in real time; once a change occurs, it automatically triggers a UFM write operation to solidify the new value. Before the main chip needs to perform a power-on or reset operation, the CPLD first reads the solidified Strap configuration value from the UFM and drives it to the GPIO pin to output the corresponding Strap level. After confirming that the level has reached a stable state, it releases the reset signal or controls the power module to complete the power-on process, ensuring that the main chip latches the correct Strap configuration at the reset release edge or power-on moment.

[0017] This invention reuses and expands the functions of existing hardware resources within a CPLD, and designs new logic to construct a complete processing flow.

[0018] Specifically, refer to Figure 1aThis embodiment reuses the User Flash Memory (UFM) 102a built into the CPLD chip involved. The UFM is an on-chip non-volatile memory integrated within the CPLD chip, inherently present in the CPLD chip's hardware architecture. In conventional usage, the UFM is typically used as auxiliary storage space for CPLD user logic, such as storing user-defined device identification information, firmware version number, product serial number, calibration parameters, or other small amounts of user data that need to be quickly read after power-on and not lost upon power-off. In other words, the typical role of the UFM in the prior art is as a "notepad" for CPLD user data storage; its content is usually pre-fixed by the CPLD logic code during compilation or written once during product manufacturing using a specific programming tool, and generally not frequently changed after writing. However, in this invention, the UFM 102a is used as a non-volatile fixed storage area for the Strap configuration values ​​of the main chip 106a. Specifically, this implementation expands the UFM from a "static user data storage area" to a "dynamic Strap configuration backup area." Its stored content is no longer determined solely by the CPLD logic code during the compilation phase, but can be modified and permanently stored in the UFM at any time during system operation by an external controller via the communication bus. This enables online updates and power-off retention of Strap configuration values. When the external controller writes a new Strap configuration value, that value is immediately stored in the UFM. Even if the CPLD is completely powered off, the configuration value remains in the UFM 102a. Upon the next power-on, the CPLD can directly read from the UFM 102a and output it to the Strap pin of the main chip 106a.

[0019] In addition, this invention adds a hardware register module inside the CPLD: the Strap configuration register 101a. The bit width of this register corresponds to the number of Strap pins that need to be configured. For example, when the main chip requires 8 Strap pins, this register is configured to be 8 bits wide. The function of the Strap configuration register 101a is to serve as a temporary storage unit for the currently effective Strap configuration value. That is, the new configuration value written by the external controller 104a through the communication bus is first stored in this register. The monitoring logic inside the CPLD uses the value of this register as the object for real-time monitoring, and after detecting a change, writes the current value of the register as the data source to the UFM 102a for solidification backup. This register also undertakes the function of "current value buffer": during system operation, when the CPLD needs to output the Strap level, it can directly read the current value from this register and drive it to the GPIO pin, without having to read the UFM every time. This is because although UFM reading is faster than I2C, it still has a larger access latency than register reading. In other words, the Strap configuration register 101a is located between the external controller 104a and UFM102a, and between the external controller 104a and the GPIO control module (not shown), serving as a hub and buffer for data exchange.

[0020] In addition to UFM 102a and Strap configuration register 101a, this embodiment adds several logic components within the CPLD to automate the entire process. These are discussed in conjunction with the following description of this embodiment. Figure 1b The specific steps will be explained in detail.

[0021] Regarding the connection between the CPLD and external devices, in this embodiment, the CPLD is connected to the external controller 104a via a communication bus 103a. This communication bus can be any one of I2C bus, SPI bus, JTAG interface, or SMBus bus. The CPLD is also connected to the Strap pins and reset control terminal of the main chip 106a via general purpose input / output (GPIO) pins 105a. Some GPIO pins 105a are configured in output mode and connected to various Strap pins of the main chip 106a to provide Strap levels to the main chip 106a; other GPIO pins 105a are connected to the reset control terminal of the main chip 106a to control the reset release timing of the main chip 106a; some GPIO pins 105a can also be connected to the enable terminal of the power module of the main chip 106a to control the power-on sequence of the main chip 106a. Based on the above hardware configuration, the specific implementation steps of this embodiment are as follows. Please refer to... Figure 1b .

[0022] S101 receives new Strap configuration values ​​written by an external controller via the communication bus and stores them in the Strap configuration register; S102. Monitor the value of the Strap configuration register in real time; S103. When a change in the value of the Strap configuration register is detected, a UFM write operation is automatically triggered to write the changed value in the Strap configuration register into the UFM for permanent storage. S104. Before controlling the main chip to perform power-on or reset operation, first perform UFM read operation to read the Strap configuration value from UFM and drive the Strap configuration value to the GPIO pin to drive the GPIO pin to output the corresponding Strap level. S105 confirms that the Strap level output from the GPIO pin has reached a stable state; S106 then controls the main chip's reset control terminal to release the reset signal or controls the power module to power on, so that the main chip latches the Strap configuration represented by the GPIO pin at the reset release edge or power-on moment.

[0023] When a CPLD chip leaves the factory, its UFM (Universal Window Meter) is blank, with no valid data written to it. If this blank CPLD is mounted on a printed circuit board and powered on for the first time, the CPLD will read an invalid value of all zeros from the UFM. If this invalid value is driven to the main chip's Strap pin, the main chip will fail to boot due to receiving an incorrect Strap configuration. To ensure a usable Strap configuration upon first power-on, in one embodiment, the UFM's default values ​​are compiled into the CPLD's programming file. The "programming file" refers to the binary file used to program the CPLD, containing not only the CPLD's programmable logic configuration data but also the UFM's initialization data. During the production line programming process, the programming tool writes the CPLD logic code and the UFM's default values ​​into the CPLD together—a process known as "programming before mounting." This default value is a verified Strap configuration that ensures the main chip boots correctly. After the CPLD is programmed, it is mounted on the printed circuit board. Upon initial power-up, the UFM reading module reads the default value from the UFM and drives it to the GPIO pin, ensuring that the main chip can obtain a valid Strap configuration and start normally upon the first power-up of the bare board. The CPLD itself needs to be programmed on the production line; merging the UFM default value with the logic code during programming does not add any extra steps.

[0024] The external controller needs to modify the Strap configuration at any time during system operation, and the CPLD's internal logic needs to know the specific modified values ​​to perform subsequent processing. The "communication bus" in S101 refers to the physical channel for data interaction between the CPLD and the external controller. It can be any of the following: I2C bus, SPI bus, JTAG interface, or SMBus bus. The specific bus chosen depends on the interface resources reserved between the CPLD and the external controller in the system architecture. The "external controller" refers to a device independent of the CPLD and the main chip, possessing data processing and control capabilities. It is typically a BMC (Baseboard Management Controller) or MCU (Microcontroller), and it performs functions such as system management, status monitoring, and configuration distribution. The Strap configuration register is mapped to the slave device address space of the communication bus. The external controller writes data to this address through the communication bus to update the Strap configuration value.

[0025] In one specific implementation, the communication bus is an I2C bus, and the CPLD internally implements I2C as the slave device protocol logic (hereinafter referred to as the I2C slave device logic). This I2C slave device logic includes a device address decoding part and a register read / write control part, and is configured to respond to a specific slave device address. When an external controller, acting as the master device, initiates a write operation, the I2C slave device logic parses the data frame on the bus, extracts the register address and the data to be written, and if the register address points to the Strap configuration register, the data is written into that register. The default value of the Strap configuration register can be preset during the compilation of the CPLD logic code, and a definite initial value is assigned by the internal logic during the initial reset process after the CPLD is powered on, ensuring that the CPLD has a usable default configuration before the external controller's first write. As another embodiment, other serial or parallel communication interfaces can also be used for the communication bus to write the configuration data sent by the external controller into the Strap configuration register. The choice of the specific bus type depends on the existing interface resources and design preferences of the system. Regardless of the type of bus used, its essential function is to enable the external controller to write new configuration values ​​to the Strap configuration register inside the CPLD. After step S101 is completed, the Strap configuration register has stored the latest configuration data issued by the external controller, providing a data foundation for subsequent monitoring and firmware processes.

[0026] After the Strap configuration register receives and stores the new configuration value written by the external controller in S101, the CPLD internal logic still needs to continuously monitor the value of this register. In one example, "real-time monitoring" in S102 refers to the process of sampling and recording the current output value of the Strap configuration register in each clock cycle under the drive of the CPLD's system clock, and comparing the current sampled value with the value at the previous moment. Since the value of the Strap configuration register may be rewritten by the external controller at any time, and the rewriting action occurs asynchronously with respect to the CPLD internal logic, the CPLD internal logic cannot determine whether the value of the register has actually changed through a simple write trigger signal: the external controller may write data that is the same as the current value (i.e., a "false change"), or it may write data that is different from the current value (i.e., a "true change"). In order to accurately distinguish between these two situations and avoid unnecessary responses to invalid write operations, the scheme designed in this invention requires the CPLD internal logic to actively and continuously monitor and compare the value of the register.

[0027] In one specific implementation, this monitoring function is implemented through a set of comparison logic within the CPLD. The comparison logic compares the current output value of the Strap configuration register with the sampled value from the previous moment. If they are completely identical, it indicates that the value of the Strap configuration register has not changed, and the comparison logic does not output a trigger signal; if there is a difference in any bit, it indicates that the value of the Strap configuration register has changed, and the comparison logic outputs a valid trigger signal. This real-time monitoring method based on hardware comparison logic does not rely on software polling, does not consume the processor resources within the CPLD, and has an extremely fast response speed. It can detect the change and output a trigger signal within the same clock cycle when the register value changes, which is particularly important for applications that require timely response to configuration change requests from external controllers.

[0028] Because the UFM has a limited lifespan for write cycles, typically around 100,000, while the external controller may frequently perform write operations to the Strap configuration register via the communication bus, potentially resulting in invalid operations where the written value is the same as the current value. If every I²C write triggers a UFM write, its lifespan will be rapidly depleted. Since EEPROMs typically support 100,000 to 1 million write cycles, the UFM's lifespan budget is even more limited. Therefore, by using the real-time monitoring mechanism of S102 to identify numerical changes and triggering subsequent UFM write operations only when a genuine change is detected, unnecessary writes to the UFM can be effectively avoided, extending its lifespan. Alternatively, the monitoring logic can be designed as an edge-detection method, generating a trigger signal only when the output value of the Strap configuration register changes (from 0 to 1 or from 1 to 0), rather than continuously comparing every clock cycle. The monitoring by S102 is a continuously running process, independent of the external controller's write operations, always running in the background, and outputting a trigger signal as soon as a valid change is detected.

[0029] In this specific implementation, a hardware-based step-by-step comparison mechanism is used: In each clock cycle, the sampling register samples and latches the current value of the Strap configuration register, and the comparator compares the current value bit-by-bit with the historical value sampled in the previous clock cycle. If they are inconsistent, it is determined that the value of the Strap configuration register has changed, triggering a UFM write operation; if they are consistent, a UFM write operation is not triggered. Writing the same value does not trigger UFM erasure, effectively extending the UFM's lifespan. Alternatively, edge detection can be used instead of step-by-step comparison, but bit-by-bit comparison is more reliable in multi-bit registers. This mechanism of "triggering a write only when the value actually changes" has non-obvious practical significance given that the UFM's lifespan is shorter than that of the EEPROM.

[0030] Based on the detection results obtained from real-time monitoring in S102, when the comparison logic detects a change in the value of the Strap configuration register and outputs a trigger signal, the CPLD's internal logic responds to the trigger signal and automatically initiates a UFM write operation. "Automatic triggering" in S103 means that the entire write process does not require additional instructions or confirmations from an external controller; instead, it is initiated autonomously by the CPLD's internal logic after detecting a value change, achieving a fully automatic process from configuration change to permanent storage. "Permanent storage" means that after the configuration value is written to the UFM, even if the CPLD is completely powered off, the configuration value is still stored in the UFM and can be read and used again upon the next power-on. Since the UFM is a non-volatile storage resource within the CPLD, its data is not lost after power failure. Therefore, writing the Strap configuration value to the UFM can achieve permanent storage of the configuration. However, the UFM write operation is fundamentally different from a regular register write operation—the UFM write operation is time-consuming and requires a specific operation sequence, unlike writing to a register which can be completed within a single clock cycle.

[0031] In one specific implementation, when the trigger signal is valid, the CPLD internal logic initiates a UFM write operation sequence. The CPLD internal logic first issues an erase command to the UFM, waits for the erase operation to complete, and then writes the current value of the Strap configuration register as data into the designated storage area of ​​the UFM. During the write process, the CPLD internal logic marks the UFM as busy. If an external controller attempts to initiate a new UFM operation during this period, the CPLD returns a busy signal to inform the external controller that it cannot currently respond, thereby avoiding concurrent access conflicts. In another embodiment, if the UFM integrated within the CPLD supports byte write mode, the implementation of the write operation can be simplified accordingly, directly writing at the byte address. After S103 is completed, the new Strap configuration value has been securely stored in the UFM and will not be lost even if the CPLD loses power.

[0032] After completing the UFM write operation in S103, the Strap configuration value has been permanently stored in the UFM. However, the permanently stored configuration value needs to be correctly output to the Strap pin of the main chip at the actual usage time in order to play its configuration role. In S104, the CPLD needs to perform a UFM read operation before controlling the main chip to perform a power-on or reset operation. Here, "power-on or reset operation" refers to the transition process of the main chip from a power-off state to a power-on state (power-on) or from a reset holding state to a normal operating state (reset). Both of these processes include an edge moment for the main chip to latch the Strap level. Since the main chip's Strap pin only samples and latches the level at the edge of the reset signal release or at the power-on moment, once the edge has passed, the main chip determines its own operating state according to the latched level combination, and subsequent level changes on the Strap pin will no longer be sampled. Therefore, in this invention, the CPLD establishes and maintains the correct Strap level before the main chip's reset release edge or power-on moment arrives. If the CPLD starts reading the UFM and driving the GPIO pins only after the reset is released, the main chip has already completed the sampling and latching. An incorrect Strap level will cause the main chip to start with an incorrect configuration. Therefore, S104 schedules the UFM read operation to be performed before the CPLD controls the main chip to perform a power-on or reset operation. That is, before the main chip's power supply is fully established or the reset signal is released, the CPLD has already completed the entire operation of reading the configuration value from the UFM and driving it to the GPIO pin.

[0033] See Figure 2 To ensure the data integrity of the Strap configuration value read from the UFM, this implementation divides each storage page of the UFM into a data bit area and a check bit area. Here, the "data bit area" refers to the bit area in the storage page used to store the valid data of the Strap configuration value; the "check bit area" refers to the bit area used to store the check information of the configuration value. For example, in a 128-bit page, the high 8 bits are used as the check bit area to store the CRC check value, and the other bits are used as the data bit area to store the Strap configuration value. Figure 2The following example uses a 16-bit configuration. In the S103 UFM write operation, the CPLD's internal logic simultaneously calculates the CRC checksum of the Strap configuration value while writing it to the UFM, and writes this checksum to the corresponding check bit area. In the S104 UFM read operation, the CPLD reads the Strap configuration value from the UFM while simultaneously reading the corresponding CRC checksum, and recalculates the CRC value of the data bit area, comparing it with the CRC value read from the check bit area. If they match, the data is considered complete and valid, and the Strap configuration value is loaded onto the GPIO pin for output. If they do not match, the data stored in the UFM is considered corrupted (possibly due to abnormal writing during power loss, electromagnetic interference, etc.). In this case, loading the data onto the GPIO pin is prohibited, an error flag signal is generated, and the error is reported to the external controller via the communication bus. As an alternative implementation, if the checksum fails, the CPLD can choose to enable a backup default configuration value as a safety measure, rather than simply disabling output.

[0034] After the CPLD drives the Strap configuration value to the GPIO pins, S105 needs to ensure that the levels on these pins have reached a stable state before allowing the main chip to perform sampling and latching. Here, "stable state" means that the level output by the GPIO pin has completed the transition from the initial state to the target state, the voltage value has risen or fallen to meet the requirements of the main chip's input logic level specification, and there are no further transitions during the subsequent hold time. Since there may be load capacitance on the GPIO pins, a certain transition time (i.e., rise time or fall time) is required from the change in the CPLD's internal logic output level to the actual establishment of the external voltage on the pin. If the main chip's reset signal is released before the level is fully established, the main chip may sample an intermediate level or an incorrect level, leading to configuration failure. In one specific implementation, after the CPLD's GPIO control logic drives the Strap configuration value to the GPIO pins, it starts an internal timer. The count value of this timer is set to be greater than the maximum time required for the GPIO pin level to establish. This maximum time can be calculated or measured based on parameters such as the load capacitance of the GPIO pin, the CPLD's drive current, and the input capacitance of the main chip's Strap pin. Before the timer count reaches the set value, the CPLD keeps the GPIO pin output unchanged while keeping the main chip's reset control terminal in an active state (i.e., maintaining reset) to ensure that the main chip does not sample prematurely. Alternatively, the CPLD can determine whether the level has been established and stabilized by continuously sampling the actual output voltage of the GPIO pin, rather than simply relying on a fixed delay. After S105 is completed, the CPLD has confirmed that the Strap level on the GPIO pin has been established stably and can safely allow the main chip to perform sampling latching.

[0035] When the timer count reaches the set value, the CPLD confirms that the Strap level output from the GPIO pin has reached a stable state and then enters S106. In S106, the CPLD performs one of the following two operations: If the main chip is currently in a power-off state, the CPLD controls the enable pin of the power supply module to power on the main chip, and the main chip latches the Strap level during the power-on process; if the main chip is currently in a powered-on state but in a reset holding state, the CPLD controls the reset control pin to release the reset signal (i.e., switch the reset pin from an active level to an inactive level), and the main chip latches the Strap level on the reset release edge. Here, the "reset control pin" refers to the reset input pin of the main chip, which is controlled by the CPLD. When this pin is at an active level (usually low), the main chip is in a reset state; when this pin switches to an inactive level, the main chip exits the reset state and begins normal operation. The "power supply module" refers to the power supply circuit that provides the operating voltage to the main chip. Its enable pin is controlled by the CPLD, which determines whether the main chip receives power by controlling the enable pin of the power supply module. In practical operation, the CPLD needs to precisely control the timing of release reset or power-on. It must release reset immediately after the main chip powers on, while avoiding excessive system startup delay. In one implementation, the CPLD releases the reset signal immediately after confirming that all power domains are stable and the GPIO level is established, causing the main chip to latch the Strap configuration represented by the GPIO pin on the reset release edge. After releasing the reset signal, the CPLD also needs to release the GPIO pin after the main chip completes the Strap latch. Since the Strap pin is often reused for high-speed signal functions such as RGMII and SPI after latching, if the CPLD's GPIO pin continues to drive the Strap pin after latching, it will introduce additional load capacitance and trace stubs, severely affecting the signal integrity of high-speed signals. Therefore, in one implementation, the CPLD's GPIO control logic automatically switches the GPIO pin to a high-impedance output mode after releasing the reset signal and waiting for a very short time (usually on the order of microseconds) sufficient for the main chip to complete the latch, thus completely releasing the Strap pin for its reused functions. In applications where Strap pins are multiplexed for high-speed signals such as RGMII and SPI, simply switching the GPIO to a high-impedance state cannot eliminate the signal reflection effects caused by the stub of the trace between the CPLD and the main chip. An analog switch can be set between the CPLD's GPIO pin and the main chip's Strap pin, conducting only within a predetermined time window before and after Strap level sampling, and disengaging at other times. This further eliminates the impact of the trace stub on the integrity of high-speed signals. Specific control methods will be discussed below. Figure 3Detailed Explanation. As an alternative implementation, the CPLD can also determine whether the main chip has completed Strap latching by monitoring a certain status signal of the main chip (such as a good power signal or a clock lock signal), rather than simply relying on a fixed delay. After S106 is executed, the main chip has completed the boot configuration according to the Strap configuration read from the UFM and driven to the GPIO pins by the CPLD.

[0036] When the CPLD receives a new Strap configuration value written by the external controller during normal system operation and writes the changed value to the UFM for hard storage, if it receives a reset request initiated by the external controller, it first sends a data save notification to the main chip. After the main chip completes the data save, it controls the main chip to perform a power-down or reset operation, and reads the updated Strap configuration value from the UFM to take effect before powering on or resetting.

[0037] During normal system operation, if it is necessary to change the Strap configuration and make the new configuration take effect, a safe switching of the runtime state is involved. Since the main chip may be performing data read / write operations (such as hard disk read / write, network transmission, etc.) during normal operation, directly performing a power-down or reset will lead to data loss or system abnormality. Therefore, this implementation adds a safety protection mechanism to the runtime modification process. Specifically, the external controller writes a new Strap configuration value to the CPLD through the communication bus. After the CPLD detects the change in the value of the Strap configuration register, it automatically triggers the UFM write operation to solidify the new configuration value. After the UFM write is completed, the BMC sends a reset request to the CPLD. After receiving the reset request, the CPLD does not immediately perform a reset operation, but first sends a data save notification to the main chip through the communication interface or a dedicated GPIO signal. The so-called "data save notification" refers to an interrupt signal or status indication signal sent by the CPLD to the main chip, informing the main chip that a power-down or reset operation is about to be performed, requiring the main chip to immediately flush the data to be written cached in memory to the non-volatile storage medium. Upon receiving the notification, the main chip executes the data saving process and returns a "ready" confirmation signal to the CPLD upon completion. Only after receiving this confirmation signal does the CPLD control the main chip to perform a power-down or reset operation. After power-down or reset, the CPLD follows the procedures described in S104 to S106 above, reads the updated Strap configuration value from the UFM and drives it to the GPIO pin, then releases the reset or re-energizes, allowing the main chip to start with the new configuration. Alternatively, if the main chip does not support a data saving notification mechanism, the CPLD can wait for a predetermined safety delay (e.g., 100 milliseconds to several seconds) after receiving a reset request before performing a power-down or reset. This delay is sufficient to ensure that most data write operations are completed.

[0038] Figure 2a This illustrates the complete timing sequence for applying the new Strap configuration after modification during normal system operation, using a safe power-down and power-on process. Figure 2a As shown, the timing sequence is divided into three stages. The first stage is the configuration write stage. At time T0, the external controller (such as the BMC) writes a new Strap configuration value to the CPLD via the I2C bus. After the change detection logic inside the CPLD detects the change in the value of the Strap configuration register, it automatically triggers the UFM write operation to solidify the new configuration value into the UFM. The UFM_WRITE signal is pulled high during this period. At time T1, the UFM write operation is completed, the UFM_WRITE signal is pulled low, and the external controller immediately initiates a reset request. The second stage is the safe power-down stage. At time T2, after receiving the reset request, the CPLD does not immediately perform a power-down operation. Instead, it first sends a data save notification to the main chip. After receiving the notification, the main chip performs an internal data flush operation to save the data to be written, which is cached in memory, to the non-volatile storage medium. After the data is saved, the main chip returns a power-down confirmation signal to the CPLD. After receiving the confirmation signal, the CPLD pulls the RESET signal low at time T3 and simultaneously controls the main chip's power module to shut down the output, putting the main chip into a completely power-off state. The third stage is the power-on and new configuration activation stage. At time T4, the CPLD reads the updated Strap configuration value from the UFM and drives the GPIO pin to the new Strap level. Simultaneously, it closes the analog switch to transmit the new level to the main chip's Strap pin. At time T5, after confirming that the Strap level has been established and stabilized, the CPLD releases the RESET signal, powering the main chip back on and latching the new Strap configuration on the reset release edge. Subsequently, the CPLD disconnects the analog switch and switches the GPIO pin to a high-impedance state, completing the entire safe switching process. This timing sequence ensures that during the Strap configuration switching process, the main chip will not lose data being processed by the main chip or the storage device will not be damaged due to a sudden power outage, demonstrating the comprehensive consideration of system data integrity in this solution for practical engineering applications.

[0039] Based on the above references Figure 1b Based on the described implementation methods, the present invention also provides more preferred implementation methods, respectively involving precise control of the Strap level output time window and the CPLD's overall power-on timing arrangement. The two implementation methods can be implemented independently or combined to constitute a complete solution for addressing high-speed signal multiplexing and stringent timing requirements in chip-level Strap configuration scenarios. The following is a continuation of... Figure 3 and Figure 4 Each will be explained in detail.

[0040] See Figure 3 An analog switch 107a is also provided between the CPLD's GPIO pins and the main chip's Strap pins. The CPLD only drives the GPIO pins to output Strap level within a predetermined time window before and after the main chip's reset release edge, and configures the GPIO pins to a high-impedance state outside the predetermined time window.

[0041] In actual chip system design, the function of the Strap pin 109a of the main chip 106a often switches after latching the level at the reset edge. These pins are released and reused for other functions after latching. The most typical reuse scenario is high-speed signal interfaces such as RGMII (Reduced Gigabit Media Independent Interface) and SPI. In other words, the same physical pin performs the Strap configuration function during the chip startup phase and the high-speed data transmission function during the chip's normal operation phase. If the GPIO pin 105a of the CPLD continues to drive the pin after the Strap latch is completed, that is, it continues to output and connect to the Strap pin 109a of the main chip 106a during the non-sampling period, then the trace between the CPLD and the main chip will form an additional branch (i.e., stub). This branch will introduce capacitive load and cause signal reflection, leading to eye diagram closure, increased bit error rate, and even preventing the high-speed interface from working properly. However, if the GPIO pin is released too early before sampling, the main chip 106a may not have established a stable Strap level by the reset release edge, causing it to latch into an incorrect configuration value, leading to chip startup failure or malfunction. This contradiction necessitates that the timing of the Strap level output be limited to an extremely narrow time window before and after the reset release edge: it cannot be released too early, resulting in a failure to establish the level, nor can it be released too late, affecting the quality of high-speed signals.

[0042] Furthermore, the start and end times of this time window are not fixed but depend on multiple dynamic factors, including the power module setup time, the completion time of CPLD internal logic initialization, and the time required for the main chip to complete sampling latching after reset and release. The power setup time varies between different batches of chips and under different temperature conditions, which makes it impossible to guarantee mass production consistency by simply relying on a fixed delay to estimate the window boundaries.

[0043] Therefore, such as Figure 3As shown, in this embodiment, the CPLD's GPIO control logic drives the Strap configuration value to output the corresponding Strap level on GPIO pin 105a only within a predetermined time window before and after the main chip's reset release edge. Here, the "predetermined time window" refers to a finite time period predetermined by the CPLD's internal logic based on system timing parameters. The start time of this window is no earlier than the moment when all power domains of the main chip have reached a stable state, ensuring that the level output by GPIO pin 105a can be correctly recognized by the main chip; the end time of this window is no later than the moment after the main chip 106a completes the Strap level latch and before its multiplexing function begins working, ensuring no interference with subsequent high-speed signal functions. Outside of this predetermined time window, including the period from system power-on to before the window opens, and the entire period from the main chip 106a completing latching to the system's normal operation, the CPLD configures its GPIO pin 105a to a high-impedance output mode. High impedance state means that the output driver of the GPIO pin is disabled and the pin presents a high impedance state. At this time, the GPIO pin 105a of the CPLD is electrically isolated from the Strap pin 109a of the main chip 106a. No definite level will be injected into the Strap pin 109a of the main chip 106a, nor will any additional load be introduced.

[0044] While simply switching the GPIO to a high-impedance state electrically disconnects the CPLD driver from the main chip's Strap pin, the physical connection remains due to the PCB traces themselves. The trace length between the CPLD's GPIO pin and the main chip's Strap pin is typically hundreds of mils to several inches, forming a physical branch structure. Even with the GPIO in a high-impedance state, this trace branch still acts as a stub, causing signal reflection during high-speed signal transmission. To completely eliminate the impact of this trace branch physically, this implementation incorporates an analog switch 107a between the CPLD's GPIO pin and the main chip's Strap pin. An "analog switch" is a semiconductor switching device that can be switched between on and off states by a control signal. In the on state, it exhibits low impedance (typically a few ohms to tens of ohms), allowing analog or digital signals to pass through; in the off state, it exhibits extremely high impedance (typically in the megaohm range), completely severing the electrical connection between the two sides. The enable terminal of the analog switch 107a is controlled by the CPLD. The timing control logic inside the CPLD outputs a valid enable signal within a predetermined time window, closing the analog switch and allowing the Strap level to be transmitted from the CPLD's GPIO pin to the main chip's Strap pin. Outside the predetermined time window, it outputs an invalid enable signal, opening the analog switch and thus physically and completely severing the wiring connection between the CPLD's GPIO pin and the main chip's Strap pin.

[0045] In this way, even if the GPIO pin of the CPLD remains in a high-impedance state after the main chip has completed sampling, the disconnection of the analog switch further physically eliminates the routing branch. The combination of the two achieves dual signal integrity protection: the high-impedance state eliminates the electrical influence of the driver end, and the analog switch disconnects the routing branch, so that the Strap pin can be completely restored to a pure transmission path state that only carries its multiplexed high-speed signal after the configuration is completed.

[0046] In one specific implementation, after confirming that all power domains are stable, the CPLD drives the Strap configuration value to GPIO pin 105a through its GPIO control logic. An internal timing counter within the CPLD starts counting when the power stability signal is valid; the counter's count value is configured to match the GPIO level setup time. When the count reaches a predetermined value, the CPLD determines that the GPIO level has been established and stabilized, and then outputs an enable signal to close analog switch 107a, while simultaneously monitoring for reset release commands. Upon receiving a reset release command, the CPLD controls the reset control terminal to release the reset signal. After the main chip 106a completes the Strap level latch on the reset release edge, it outputs an internal status signal (e.g., a good power indicator or a clock lock indicator). Upon detecting this signal, the CPLD immediately deactivates the enable signal of analog switch 107a and simultaneously switches GPIO pin 105a to a high-impedance state. Throughout the process, the CPLD precisely controls the entire chain from GPIO drive output to analog switch closure, reset release, and finally analog switch opening and GPIO high-impedance switching through its internal timing logic. This ensures that the Strap level is transmitted to the Strap pin 109a of the main chip 106a only within a predetermined time window before and after the reset release edge. Alternatively, if the main chip does not provide a latch completion status indication signal, the CPLD can wait for a preset, extremely short delay (e.g., 1 to 5 microseconds, which ensures the main chip completes level latching) after releasing the reset signal, and then execute the analog switch opening and GPIO high-impedance switching.

[0047] In chip-level Strap configuration scenarios, it is a common design reality that Strap pins share the same physical pins with high-speed signals such as RGMII and SPI. If the aforementioned windowed management mechanism is not adopted, the high-speed interface will directly fail to function properly.

[0048] To achieve the aforementioned precise timing control, in one embodiment, the CPLD controls the Enable terminal 111a and the reset control terminal 112a of the power module 110a of the main chip. The CPLD executes the power-on or reset operation of the main chip 106a according to a preset timing sequence. The timing sequence includes: first enabling each output of the power module, then driving the GPIO pin 105a to output the Strap level after the power supply stabilizes, and finally releasing the reset signal of the reset control terminal after the Strap level stabilizes.

[0049] In this embodiment, the CPLD is connected not only to the various Strap pins 109a of the main chip 106a via GPIO pin 105a, but also to the Enable pin 111a and reset control pin 112a of the main chip's power module via additional GPIO pins. The Enable pin 111a controls whether the power module's output is on. When the Enable pin is active, the power module 110a starts outputting a stable operating voltage; when the Enable pin 111a is inactive, the power module 110a shuts down its output. The Reset control pin 112a refers to the reset input pin of the main chip 106a. When this pin is active (usually low), the main chip 106a remains in the reset state, and its internal logic is inactive; when this pin switches to inactive (usually high), the main chip 106a exits the reset state and begins the startup process. By independently controlling these two types of pins, the CPLD gains control over the entire power-on and reset process of the main chip 106a.

[0050] The CPLD executes the above control process according to a preset timing sequence. Here, the "preset timing sequence" refers to a multi-step, sequential timing control flow that has been determined and solidified in the internal logic of the CPLD during the CPLD logic code design phase. Figure 4 The complete waveform and phase division of this time series are shown.

[0051] like Figure 4 As shown, the first stage (T0 to T1) of this timing sequence is the CPLD initialization and UFM read stage. After the system's 12V main power supply is powered on, the BMC and CPLD are the first to receive power and begin initialization. After the CPLD completes the initialization of its internal logic and clock stabilization, its UFM read / write control logic immediately starts, reading the pre-set Strap configuration value from the UFM via the on-chip bus. Throughout this stage, the CPLD's GPIO control logic keeps the GPIO connected to the main chip's Strap pin in a high-impedance state, while the analog switch remains open, ensuring that the CPLD does not affect the main chip's Strap pin at this time.

[0052] The second phase (T1 to T3) of this timing sequence is the BMC readiness and power-up phase. After the UFM read operation is completed within microseconds, the CPLD waits for the BMC to start up and issue a power-on command. As a system management controller, the BMC's startup process typically takes hundreds of milliseconds to several seconds. During this waiting period, the CPLD maintains a high-impedance GPIO state and keeps the analog switches off. Once the CPLD receives the power-on command from the BMC ( Figure 4At time T2, the CPLD's power control logic enables the various power modules of the main chip according to a preset timing sequence. Typically, the core voltage is enabled first, followed by the I / O voltage, and finally the auxiliary voltage. Each power supply is turned on sequentially according to its setup time and power-on order. Once all power domains have reached a stable state (at time T3), the CPLD confirms that the main chip has received a complete and stable power supply. Only then can the level on the Strap pin be correctly identified as a valid logic high or low by the main chip. If the GPIO outputs a Strap level before the power supply is stable, the main chip's internal input buffer operating voltage has not yet been fully established, and it may not be able to correctly distinguish the logic level.

[0053] The third stage of this timing sequence (T3 to T4) is the Strap output and window opening stage. After all power domains stabilize, the CPLD's GPIO control logic drives the Strap configuration value read from and temporarily stored in UFM in S104 to output the corresponding Strap level on the GPIO pin (at time T4), while simultaneously closing the analog switch to transmit the Strap level to the main chip's Strap pin. This stage corresponds to the opening time of the predetermined time window defined in weight 2. The CPLD then starts an internal timer to wait for the level on the GPIO pin to fully stabilize (the period between T4 and T5). This waiting time is typically on the order of microseconds, depending on the GPIO's drive capability and the load capacitance on the pin.

[0054] The fourth stage (T4 to T6) of this timing sequence is the reset, release, and latch stage. This occurs after confirming that the Strap level output from the GPIO pin has reached a stable state. Figure 4 At time T5 (corresponding to S105), the CPLD's reset control logic switches the main chip's reset control pin from an active level to an inactive level, i.e., releases the reset signal (at time T5). The main chip immediately samples and latches the level on the Strap pin at the rising or falling edge of the reset release (depending on the polarity of the reset signal).

[0055] The fifth stage (T6 to T7) of this timing sequence is the pin release and window closing stage. This occurs after the main chip completes the Strap latch ( Figure 4 At time T6, the CPLD's GPIO control logic immediately switches the GPIO pin to a high-impedance state and turns off the analog switch, ending the predetermined time window. Afterward (at time T7 and later), the Strap pin is completely released to its multiplexed high-speed signal functions and is no longer affected by the CPLD's drive. High-speed signals such as RGMII or SPI can be transmitted unimpeded on this pin.

[0056] Throughout the entire timing sequence, the CPLD's power control logic, GPIO control logic, and reset control logic work together to orchestrate all the steps—"reading configuration from UFM → waiting for BMC instructions → enabling power module → driving GPIO output Strap → closing analog switch → releasing reset → switching to high impedance state → turning off analog switch"—into a complete power-up sequence fully controlled by the CPLD and precisely controllable in a very short time. As the master timing controller, the CPLD's internal logic completely determines when each step begins and ends, the interval between steps, and the phase relationship between control signals. This full control mode ensures that the entire process of Strap level establishment, stabilization, sampling, and release is under the precise control of the CPLD, avoiding inconsistencies in timing caused by power management, configuration reading, and reset control being distributed across different devices or handled separately by different logic.

[0057] It should be noted that the above Figure 4 The timing sequence shown defines the predetermined time window between T4 and T6, encompassing the entire timing sequence from driving the GPIO to output the Strap level, to releasing the reset, and then immediately releasing the pin after sampling. The width of this window is precisely controlled to cover only the minimum time period required for Strap sampling. Specifically, its start time is no earlier than the moment all power domains stabilize, and its end time is no later than the moment after the main chip completes Strap latching and before its multiplexing function begins operation.

[0058] Based on the above references Figure 1b Based on the described basic implementation, this invention also provides an optional implementation regarding the communication method between the CPLD and the UFM and the operation management of the UFM. As described in S103 and S104, the CPLD needs to write the Strap configuration value into the UFM for fixed storage and read the configuration value from the UFM before the main chip is powered on or de-reset. However, the UFM, as an integrated Flash memory on the CPLD chip, has a significantly different access method than ordinary registers or external serial EEPROMs. Therefore, referring to... Figure 3 In this embodiment, the CPLD communicates with the UFM via the Wishbone bus; the CPLD includes a Wishbone bus master control module 103a, and both the UFM read operation and the UFM write operation are initiated by the Wishbone bus master control module 103a according to the Wishbone bus protocol; the UFM write operation needs to be performed page by page, and a page erase operation needs to be performed before each write.

[0059] Continue to refer to Figure 3 and combined Figure 3aThe CPLD chip integrates an embedded function block (EFB), a hardware unit within the CPLD used to manage on-chip peripherals and communication interfaces. This EFB includes I2C slave logic, SPI slave logic, JTAG slave logic, register control logic, and Wishbone bus master logic. An external controller can connect to the EFB via any of the I2C, SPI, or JTAG interfaces. The corresponding slave logic within the EFB receives data from the external controller and passes it to the register control logic. The register control logic then converts the data into Wishbone bus cycles via the internal Wishbone bus master logic, ultimately accessing the UFM. In other words, regardless of whether the external controller uses I2C, SPI, or JTAG, the data is ultimately read and written to the UFM via the Wishbone bus master module within the EFB. This demonstrates the diversity of communication bus types and the uniformity of the CPLD's internal architecture in this invention. In practical engineering applications, it is generally preferable to rewrite the Strap configuration register through the I2C interface and then have the CPLD internal logic uniformly schedule the Wishbone bus access to the UFM, rather than having the external controller directly operate the UFM through JTAG or SPI, in order to simplify system-level software design and avoid concurrent access conflicts.

[0060] Here, "Wishbone bus" refers to an open standard system-on-chip interconnect bus protocol. Wishbone bus provides a configurable interconnection method for semiconductor cores, enabling various cores to interconnect to form a system-on-chip. Its interface is independent of semiconductor technology, supporting both FPGA and ASIC devices. In this embodiment, the Wishbone bus serves as an on-chip communication bridge between the CPLD's internal user logic and the UFM. The "Wishbone bus master module" refers to a newly added logic module within the CPLD. This module actively initiates read and write operations to the UFM according to the timing requirements of the Wishbone bus protocol. In this embodiment, the CPLD's user logic acts as the Wishbone bus master, and the UFM acts as a Wishbone bus slave.

[0061] Since the UFM communicates with the CPLD's user logic via the Wishbone bus, the CPLD needs to implement complete Wishbone bus master control logic. This master control logic includes a Wishbone bus protocol state machine, which can generate address strobe signals (STB_O), data strobe signals, read / write enable signals, and bus cycle end acknowledgment signals (ACK_I) according to the Wishbone bus standard specification.

[0062] Specifically, when the CPLD needs to write data to the UFM, the Wishbone bus master logic first places the target address on the address bus and the data to be written on the data bus, then asserts the strobe signal and write enable signal. After the UFM detects that the strobe signal is valid, it performs the write operation and responds to the master module with an acknowledgment signal after the operation is completed, completing one bus cycle. When the CPLD needs to read data from the UFM, the Wishbone bus master logic places the target address on the address bus and asserts the strobe signal and read enable signal. The UFM places the data at the specified address on the data bus and asserts the acknowledgment signal. The master module latches the value on the data bus when the acknowledgment signal is valid.

[0063] Figure 5 This illustrates the timing sequence of signals when the Wishbone bus master module initiates a write operation to the UFM. For example... Figure 5 As shown, the write operation cycle is initiated by the Wishbone bus master module. The key signals of the Wishbone bus write cycle are marked in the figure: clock (WB_CLK), address (WB_ADR), write data (WB_DAT_O), strobe signal (WB_STB), bus cycle signal (WB_CYC), and slave device acknowledge signal (WB_ACK).

[0064] At the first rising edge of clock time T0, the Wishbone bus master module pulls the WB_CYC signal high, declaring the start of a bus cycle; simultaneously, it pulls the WB_STB signal high, enabling the strobe signal; the target memory address to be written to the UFM is output on the WB_ADR signal line; and the data to be written is output on the WB_DAT_O signal line. During this stage, the WB_ACK signal remains low, indicating that the UFM, as a slave device, has not yet completed its response, and the Wishbone bus master module needs to wait for the UFM's confirmation. At the second rising edge of clock time T1, after completing its internal operations, the UFM pulls the WB_ACK signal high, returning an acknowledgment signal to the Wishbone bus master module, indicating that the address and data have been successfully received. At the third rising edge of clock time T2, the Wishbone bus master module detects that WB_ACK is high, confirming that the write operation is complete. Immediately after the rising edge of the clock, it pulls the WB_STB and WB_CYC signals low, canceling the strobe signal and terminating the bus cycle. The UFM correspondingly pulls the WB_ACK signal low, ending the write operation acknowledgment. Throughout the entire write operation described above, the address signal and the write data signal remain stable during the entire period when WB_STB is active, to ensure that UFM can correctly latch the address and data when the acknowledgment signal goes high.

[0065] Figure 6The diagram illustrates the timing sequence of signals when the Wishbone bus master module initiates a read operation to the UFM. The key signals in the Wishbone bus read cycle are labeled: clock (WB_CLK), address (WB_ADR), strobe signal (WB_STB), bus cycle signal (WB_CYC), slave device acknowledge signal (WB_ACK), and read-back data (WB_DAT_I).

[0066] like Figure 6 As shown, the initiation method of the read operation cycle is similar to that of the write operation. At the first rising edge of the clock at time T0, the Wishbone bus master module pulls the WB_CYC signal high to declare the start of the bus cycle, pulls the WB_STB signal high to enable the strobe, and outputs the target memory address to be read on the WB_ADR signal line. Since this is a read operation, the WB_DAT_I signal line remains in a high-impedance state, waiting for the UFM, acting as a slave device, to drive this signal line. The WB_ACK signal remains low, indicating that the UFM is not yet ready for data. At the second rising edge of the clock at time T1, after the UFM completes its internal read operation, it pulls the WB_ACK signal high and simultaneously drives the WB_DAT_I signal line to the data read from the specified address. After detecting that WB_ACK is high, the Wishbone bus master module latches the data on the WB_DAT_I signal line at the third rising edge of the clock at time T2, completing the data sampling for this read operation. After the rising edge of the clock, the Wishbone bus master module pulls the WB_STB and WB_CYC signals low to cancel the strobe and terminate the bus cycle. The UFM correspondingly pulls the WB_ACK signal low and restores WB_DAT_I to the high impedance state, ending the read operation acknowledgment. Figure 5 and Figure 6 Together, they constitute the complete timing specification for Wishbone bus write and read operations. The Wishbone bus master control module inside the CPLD interacts with the UFM according to the above timing requirements.

[0067] Beyond differences in bus protocol, UFM, as a Flash memory, exhibits completely different behavioral characteristics compared to ordinary memory (such as SRAM or EEPROM) during write operations. Here, "page-by-page execution" means that UFM write operations cannot be performed randomly in units of single bytes or words, but must be performed in units of pages; that is, each write operation requires transferring an entire page of data. A "page" refers to the smallest write unit organized internally within the UFM, and its size depends on the specific CPLD device model; for example, in some CPLDs, a page is 128 bits. Even if the user only needs to update an 8-bit Strap configuration value, the CPLD's Wishbone bus master logic still needs to write the entire page of data (e.g., 128 bits) containing that configuration value into the UFM at once. Before writing new data, the flash memory cell needs to restore all bits in the target memory area to the erase state (usually logic "1") before the new data can be written. In other words, UFM write operations are not simply overwriting old data, but a combined operation consisting of two independent sub-steps: "erase" and "write." This contrasts sharply with the way external EEPROMs can be directly overwritten at any byte address without prior erasure.

[0068] In one specific implementation, when the comparator detects a change in the value of the Strap configuration register and outputs a trigger signal, the Wishbone bus master logic inside the CPLD initiates a UFM write operation sequence. The first sub-step of this sequence is a page erase operation. The Wishbone bus master logic sends a page erase command to the UFM, specifying the address of the memory page to be erased. After receiving the page erase command, the UFM starts its internal erase circuitry to restore all memory cells in that page to the erased state. The page erase operation typically takes several milliseconds to tens of milliseconds. During this period, the Wishbone bus master logic needs to maintain the bus state and wait for the UFM to return an erase completion signal. After page erasure is complete, the Wishbone bus master logic enters the second sub-step. At this point, the master logic uses the current value of the Strap configuration register as valid data and assembles it into a data block conforming to the page width according to the page write format requirements (e.g., extending an 8-bit Strap configuration value to 128 bits, where the valid bits occupy the lower 8 bits, and the remaining bits can be filled with fixed values ​​or reserved). Then, it writes this data block to the designated memory page of the UFM via the Wishbone bus. The page write operation also takes several milliseconds to tens of milliseconds. The entire write operation sequence, from page erasure to page write, is automatically completed by the Wishbone bus master logic according to a preset state machine, without the need for intervention from an external controller.

[0069] During the entire write operation, the Wishbone bus master logic marks the Wishbone bus as busy. If an external controller attempts to directly operate the UFM via the I2C bus during this period, the I2C slave logic within the CPLD will return a busy signal to inform the external controller that the UFM is currently occupied, thus avoiding concurrent access conflicts. As an example, the UFM content can be updated indirectly by rewriting the Strap configuration register, instead of the external controller directly operating the UFM. This allows the CPLD's internal logic to uniformly schedule all UFM read and write operations, fundamentally eliminating the possibility of concurrent access conflicts.

[0070] When the CPLD needs to read the Strap configuration value from the UFM, the Wishbone bus master logic also initiates a read operation according to the Wishbone bus protocol. The master logic sends a read command and read address to the UFM, and the UFM returns the data from the specified memory page via the Wishbone bus after receiving the read command. As a parallel bus, the Wishbone bus has a data width of up to 32 bits or 64 bits and a system clock of up to tens of MHz. A complete read operation can be completed in just a few clock cycles. The total time for a read operation is typically within 1 to several microseconds. In contrast, the read speed of an external I²C EEPROM is limited by the I²C bus clock rate, which is approximately 100kHz in standard mode, approximately 400kHz in fast mode, and no more than 1MHz in high-speed mode. I²C is a serial bus, transmitting only 1 bit at a time. Reading a configuration value requires sequentially transmitting multiple bytes such as the device address, register address, restart, and data read, typically taking tens to hundreds of microseconds in total. The Wishbone bus is tens to hundreds of times faster than the I²C bus.

[0071] This speed difference is significant in chip-level Strap configuration scenarios. The main chip's Strap pin only samples and latches the level at the reset-release edge. The CPLD must complete the UFM read and drive the GPIO to output the correct Strap level before the reset-release. If the read operation takes too long and misses the reset-release edge, the main chip will latch to an incorrect configuration value, leading to startup failure. This invention, implementing microsecond-level UFM reads via the Wishbone bus, fully meets the requirement of an extremely short timing window before reset-release.

[0072] The specific implementation of the above solution is described in detail below with reference to the accompanying drawings. This application can be implemented by executing several computer program code flows through an electronic device. The electronic device loads the computer program into non-volatile memory and reads these computer program instructions into memory for execution through the processor of the electronic device. A hardware structure diagram of the electronic device, besides... Figure 7In addition to the processor, memory, network interface, and non-volatile memory shown, the processor is the CPLD chip mentioned in the embodiments above. Electronic devices may also include other hardware depending on their actual functions, which will not be elaborated further.

Claims

1. A method for configuring a CPLD using Strap, characterized in that, The CPLD has a built-in user flash memory (UFM) and a Strap configuration register. The Strap configuration register is used to temporarily store the currently effective Strap configuration value, and the UFM serves as a non-volatile backup storage area for permanently storing the Strap configuration value. The CPLD is connected to an external controller via a communication bus and to the main chip's Strap pin and reset control terminal via general-purpose input / output (GPIO) pins, including the following steps: The communication bus receives the Strap configuration value written by the external controller and stores it in the Strap configuration register; the value of the Strap configuration register is monitored in real time, and when the value of the Strap configuration register changes, a UFM write operation is automatically triggered to write the changed value in the Strap configuration register into the UFM for fixed storage. Before controlling the main chip to perform a power-on or reset operation, a UFM read operation is performed first to read the Strap configuration value from the UFM and drive it to the GPIO pin to drive the GPIO pin to output the corresponding Strap level; After confirming that the Strap level output by the GPIO pin has reached a stable state, the main chip's reset control terminal is controlled to release the reset signal or the power supply module is controlled to power on, so that the main chip latches the Strap configuration represented by the GPIO pin at the reset release edge or power-on moment.

2. The method according to claim 1, characterized in that, An analog switch is provided between the GPIO pin of the CPLD and the Strap pin of the main chip; the CPLD drives the GPIO pin to output the Strap level within a predetermined time window before and after the reset release edge of the main chip; outside the predetermined time window, the CPLD configures the GPIO pin to a high impedance state and controls the analog switch to be in an open state.

3. The method according to claim 1, characterized in that, The CPLD communicates with the UFM via the Wishbone bus; the CPLD includes a Wishbone bus master module, and the UFM read operation and the UFM write operation are initiated by the Wishbone bus master module according to the Wishbone bus protocol; the UFM write operation needs to be performed page by page, and a page erase operation needs to be performed before each write.

4. The method according to claim 1, characterized in that, The UFM contains multiple storage pages, each of which is divided into a data bit area and a check bit area; the data bit area is used to store the Strap configuration value, and the check bit area is used to store the CRC check value of the Strap configuration value. When the CPLD reads the Strap configuration value from the UFM, it also reads the corresponding CRC check value and performs verification. If the verification passes, the Strap configuration value is loaded into the GPIO pin; If the verification fails, the Strap configuration value will be prevented from being loaded onto the GPIO pin, and an error flag signal will be generated.

5. The method according to claim 1, characterized in that, The step of real-time monitoring of the value of the Strap configuration register and automatically triggering a UFM write operation when a change in the value of the Strap configuration register is detected specifically includes: The current value of the Strap configuration register is sampled in each clock cycle and compared with the historical value sampled in the previous clock cycle. If the two are inconsistent, it is determined that the value of the Strap configuration register has changed, and the UFM write operation is triggered. If the two are consistent, the UFM write operation is not triggered.

6. The method according to claim 1, characterized in that, When the CPLD receives the new Strap configuration value written by the external controller during normal system operation and writes the changed value into the UFM for hardening storage, if it receives a reset request initiated by the external controller, it first sends a data saving notification to the main chip. After the main chip completes the data saving, it controls the main chip to perform a power-down or reset operation, and reads the updated Strap configuration value from the UFM to take effect before powering on again or resetting.

7. The method according to claim 1, characterized in that, The CPLD's programming file contains the default value of the UFM; when the CPLD is programmed on the production line, the default value of the UFM is programmed together with the CPLD logic code into the CPLD, so that the CPLD can read it from the UFM when it is powered on for the first time.

8. The method according to claim 1, characterized in that, The CPLD controls the Enable and Reset control terminals of the power module of the main chip. The steps of controlling the main chip to perform power-on or reset operations are executed by the CPLD according to a preset timing sequence. The timing sequence includes: first enabling each output of the power module, driving the GPIO pin to output the Strap level after the power supply stabilizes, and releasing the reset signal of the reset control terminal after the Strap level stabilizes.

9. The method according to claim 2, characterized in that, The start time of the predetermined time window is no earlier than the time when all power domains of the main chip reach a stable state, and the end time of the predetermined time window is no later than the time after the main chip completes the Strap level latch and before its multiplexing function starts working.

10. An electronic device comprising a memory, a CPLD chip, and a computer program stored in the memory and executable on the CPLD, wherein the CPLD has a built-in user flash memory (UFM) and a Strap configuration register, the Strap configuration register being used to temporarily store currently effective Strap configuration values, and the UFM serving as a non-volatile backup storage area for permanently storing the Strap configuration values; and the CPLD being connected to an external controller via a communication bus and connected to the Strap pin and reset control terminal of the main chip via general purpose input / output (GPIO) pins, characterized in that... When the CPLD chip executes the program, it implements the steps of the method according to any one of claims 1 to 9.

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