Channel interleaving in a multi-lane communication interface link

Abstract

The present disclosure relates to lane staggering of a multi-lane communication interface link. A device connected to a link of a multi-lane communication interface causes link traffic to migrate from a plurality of lanes of the multi-lane communication interface to a subset of the plurality of lanes of the multi-lane communication interface. One or more tasks are performed on another subset of the plurality of lanes, causing link traffic to resume on the plurality of lanes.

Description

Technical Field

[0001] Various aspects and embodiments of this disclosure relate to communication interfaces in computing systems, and more particularly to lane staggering in multi-channel communication interface links. Background Technology

[0002] Communication interfaces enable data transfer between various components in a computing system, such as the central processing unit (CPU), graphics processing unit (GPU), data processing unit (DPU), network interface controller (NIC), and data storage devices. Attached Figure Description

[0003] Various embodiments according to this disclosure will be described with reference to the accompanying drawings, in which: Figure 1A This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 1B This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 1C This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 1D This is a block diagram of an example system architecture for a communication system according to an embodiment; Figure 2 This is a block diagram of an example device in a communication system according to an embodiment; Figure 3A A sequence of link states during a link bandwidth change operation according to an embodiment is described; Figure 3B A sequence of link states during link maintenance operations according to an embodiment is described; Figure 4 This is a flowchart of an example method for channel interleaving in a multi-channel communication interface link according to an embodiment; Figure 5 This is a block diagram illustrating an exemplary computer system according to an embodiment; Figure 6 It is a block diagram of a computing system having two processing devices coupled to each other and multiple networks according to an embodiment; Figure 7 This is a block diagram of a computing system having a CPU and a GPU in a single integrated circuit according to an embodiment; and Figure 8 This is a block diagram of a computing system with a tensor core GPU according to an embodiment. Detailed Implementation

[0004] This disclosure relates to multi-channel communication interfaces in computing systems. Multi-channel communication interfaces enable data transfer between various components within a computing system, such as central processing units (CPUs), graphics processing units (GPUs), data processing units (DPUs), network interface controllers (NICs), data storage devices, etc. Multi-channel communication interfaces can use one or more channels to connect two devices to form a link, where channel aggregation can achieve higher bandwidth for the link compared to a single channel. Examples of multi-channel communication interfaces include High-Speed ​​Peripheral Component Interconnect (PCIe), Compute Fast Link (CXL), NVLINK, InfiniBand, and Ethernet. Multi-channel communication interfaces can be used in a wide range of applications, from data centers (e.g., high-performance computing, artificial intelligence, gaming, etc.) to consumer electronics (e.g., desktops, mobile devices) to motor vehicles.

[0005] Some multi-channel communication interfaces support link width resizing, where the number of channels used in a link can be dynamically reduced or increased on demand based on factors such as bandwidth utilization and power consumption. Link width resizing can be achieved through negotiation between linked devices. However, multi-channel communication interfaces may be limited in terms of enabling or disabling channels, and disabled channels may not be usable for any purpose while in dormant mode. Furthermore, various link maintenance tasks, such as transitions between power states, changes in link bandwidth, link equalization, and link training, can be time-consuming and resource-intensive, and may block traffic flow on the link. Therefore, devices using multi-channel communication interfaces may experience traffic interruptions due to slow transitions between link states and occasional link maintenance, such as rebalancing.

[0006] This disclosure addresses the aforementioned and other challenges by providing a multi-channel communication interface that supports selective enabling and disabling of channel sets, as well as swapping between enabled and disabled channel sets. Furthermore, disabled channels can be in a semi-active state, supporting link maintenance tasks such as bandwidth upgrades and link training. Therefore, link traffic can be temporarily migrated to a subset of channels while maintenance tasks are performed on another subset, and then the subsets can be swapped. When all maintenance tasks are completed, link traffic can be restored to the full set of channels. Thus, devices can continue to send and receive traffic using the link while performing maintenance tasks. This minimizes traffic interruptions for linked devices and improves power state transition times.

[0007] In one embodiment, a device connected to a link of a multi-channel communication interface can negotiate with another device on the link to change the link width to a subset of the channels and migrate traffic to those channels. The device can then collaborate with other devices to perform maintenance tasks on the disabled channels while maintaining the normal operation of that subset of channels. Upon completion of the maintenance tasks, the devices can negotiate to restore the link width to the full set of channels.

[0008] In one embodiment, before restoring full-link bandwidth, devices can negotiate to switch traffic from enabled channels to disabled channels and perform the same or similar maintenance tasks on the newly disabled channels. Therefore, tasks such as bandwidth upgrades and link training can be performed on the entire link while maintaining traffic flow. In one embodiment, the link can be divided into more than two channel subsets, each of which can be switched to one of an enabled state, a maintenance disabled state, or a fully disabled state.

[0009] In one embodiment, channel switching and incremental maintenance tasks can be initiated within the device via software (such as a driver or application). This allows for optimal timing of link maintenance tasks for different use cases, such as high-performance computing, artificial intelligence, gaming, and motor vehicle use cases. Consequently, computing systems using these multi-channel communication interfaces can continue to support traffic flow on a subset of channels while link maintenance tasks are in progress, thereby reducing traffic interruptions and link downtime.

[0010] Figure 1A This is a block diagram of an example system architecture 100A for a communication system according to an embodiment. System architecture 100A (also referred to herein as the "system") includes a switch 110, upstream devices 120A-120N, and downstream devices 130A-130N. System 100A also includes communication interface links 122A-122N and 132A-132N connecting the aforementioned components. In various embodiments, system 100A may include configuration and... Figure 1A The components described may have different configurations, with more or fewer components. For example, system 100A may include additional switches operating upstream or downstream of switch 110.

[0011] Communication system 100A is associated with a communication interface. A communication interface can define the common media and / or protocols that devices and applications running on it can use to communicate with each other. For example, a communication interface can define one or more layers of the Open Systems Interconnection (OSI) model, such as the physical layer, data link layer, application layer, etc. Examples of communication interfaces that can be associated with communication system 100A include High-Speed ​​Peripheral Component Interconnect (PCIe), Compute Fast Link (CXL), NVLINK, InfiniBand, Ethernet, Universal Serial Bus (USB), Internal Integrated Circuit (I2C), Serial Peripheral Interface (SPI), etc.

[0012] Devices participating in the communication system 100A can be connected together via links compatible with the communication interface. A link can be a unidirectional or bidirectional channel for sending and / or receiving data between two devices and can be associated with the underlying physical medium and protocols defined by the communication interface. Link performance can be characterized in various ways. For example, link bandwidth can refer to the amount of data that can traverse the link within a time period, while link latency can refer to the time it takes for data to traverse the link. Link error rate can refer to the frequency at which data is lost or corrupted on the link. In various embodiments, some of these performance characteristics can be tunable. For example, a link can be associated with multiple bandwidth states that can support more or less bandwidth depending on the needs of the connected devices / applications. In various embodiments, a link can be temporarily disabled to allow transitions between bandwidth states or to allow other operations (such as link maintenance) to be performed on the link.

[0013] In various embodiments, the communication interface may support different types of devices, such as switches and endpoint devices. Switch 110 may be a device that routes data traffic between two or more devices connected to switch 110. In various embodiments, switch 110 may use lookup tables, addresses embedded in data packets, and / or other techniques to determine which device(s) to route traffic to. In various embodiments, data packets received at switch 110 may be routable to any connected device or a subset of connected devices. For example, switch 110 may be a physical device that implements two or more virtual switches, which may be associated with a corresponding routable device tree connected to switch 110.

[0014] In various embodiments, upstream devices 120A-120N are endpoint devices capable of performing host or controller roles. Upstream devices 120A-120N can be connected to one or more downstream devices 130A-130N via switch 110. In various embodiments, downstream devices 130A-130N can perform managed or controlled roles. Examples of upstream devices include PCIe root complexes or their root ports and USB host-class devices. Examples of downstream devices include PCIe endpoint devices and USB device-class devices. In one embodiment, the communication system may have a single upstream device and one or more downstream devices.

[0015] Figure 1B This is a block diagram of an example system architecture 100B for a communication system according to an embodiment. System architecture 100B (also referred to herein as the "system") includes a switch 110 and endpoint devices 140A-140N. System 100B also includes communication interface links 142A-142N connecting the aforementioned components. In various embodiments, system 100B may include configuration and... Figure 1B The described components may have different configurations with more or fewer components. For example, system 100B may include additional switches operating upstream or downstream of switch 110. System 100B differs from system 100A in that there is no distinction between upstream and downstream devices; all devices can perform host / device, controller / controlled, transmitter / receiver, or other types of roles. An example communication system that may correspond to system 100B is an Ethernet system. In various embodiments, the device roles of systems 100A-100B may be combined with aspects of one or more systems 100C-100D.

[0016] Figure 1C This is a block diagram of an example system architecture 100C for a communication system according to an embodiment. System architecture 100C (also referred to herein as the "system") includes a bus 150 and endpoint devices 140A-140N. System 100C also includes communication interface links 142A-142N connecting the aforementioned components. In various embodiments, system 100C may include configuration and... Figure 1C The described components may have different configurations with more or fewer components. For example, system 100C may include an additional bus 150. System 100C differs from systems 100A-100B in that there is no switch connecting multiple devices; instead, all devices share the same physical or virtual media bus 150. An example communication system that may correspond to system 100C is an I2C system. In various embodiments, the bus configuration of system 100C may be combined with aspects of one or more of systems 100A, 100B, or 100D.

[0017] Figure 1DThis is a block diagram of an example system architecture 100D for a communication system according to an embodiment. System architecture 100D (also referred to herein as the "system") includes a switch 110, upstream devices 120A-120N, and downstream devices 130A-130N. System 100D also includes multi-channel communication interface links 124A-124N and 134A-134N connecting the aforementioned components. In various embodiments, system 100D may include configuration and... Figure 1D The described components may be configured with more or fewer components. For example, system 100D may include additional switches operating upstream or downstream of switch 110. System 100D includes communication interface links, each of which may have two or more channels. An example communication system that may correspond to system 100D is a PCIe system. In various embodiments, the multi-channel communication interface links of system 100D may be combined with aspects of one or more systems 100A-100C.

[0018] Multichannel communication interface links 124A-124N may each have two or more channels for sending and / or receiving traffic, and the number of active channels (also referred to as the “link width”) may be configurable in various embodiments. For example, multichannel communication interface link 124A may be configured with active channels, while multichannel communication interface link 124B may be configured with four active channels. In another example, multichannel communication interface link 124A may transition from one active channel to four active channels at a certain point in time, possibly with downtime to facilitate the transition. The bandwidth characteristics described above may refer to the overall bandwidth of the link, while the channel bandwidth characteristics may refer to the bandwidth of a single channel. In a multichannel communication interface link, the link bandwidth may be the sum of the bandwidths of the individual channels. As described above, some embodiments of the communication system may support tunable link bandwidth, which in systems such as system 100D may include changing the link width (e.g., from one to four) or changing the bandwidth of individual channels (e.g., from low bandwidth to high bandwidth).

[0019] Figure 2 This is a block diagram of an example device 200 in a communication system according to an embodiment. In one embodiment, device 200 may be... Figures 1A-1D The device 200 is a switch 110 or one of devices 120A-120N, 130A-130N, or 140A-140N. Device 200 is connected to one or more additional devices via one or more communication interface links 210A-210N. In various embodiments, the communication interface links 210A-210N may be multi-channel links. Device 200 includes a link negotiation module 220, a link task execution module 230, and a link traffic transmission / reception module 240. In various embodiments, device 200 may include more than... Figure 2 The device may include more or fewer of the components depicted. For example, device 200 may include a module for generating data to be transmitted on links 210A-210N, or a module for processing data received on links 210A-210N. In various embodiments, device 200 may be a PCIe device, an Ethernet device, a USB device, or other types of devices.

[0020] The link negotiation module 220 can communicate with connected devices to configure the connection link and can implement various protocols to accomplish this configuration. The link negotiation module 220 can be used to activate or deactivate the link (e.g., for link initialization / deinitialization or for link maintenance). The link negotiation module 220 can also be used to update link parameters. For example, the link negotiation module 220 can negotiate updated bandwidth status. In a multi-channel communication interface link, the updated bandwidth status can be a change in the link width or a change in the bandwidth of each channel.

[0021] In one embodiment, link negotiation module 220 can be used to configure a subset of channels connecting the link, such as channel subsets 212A-212N. For example, link negotiation module 220 can be used to activate a channel subset, deactivate a second channel subset, and / or update the bandwidth status of a third channel subset. A channel subset can be in one or more states associated with a link configuration, such as an inactive state (e.g., deactivated, disconnected), an active state (e.g., active, transmitting / receiving traffic), and / or an active unused state (e.g., active, in maintenance mode). Link negotiation module 220 can implement various additional or modified protocols to support configuring link subsets. For example, link negotiation module 220 can specify which channel subset to use when narrowing (e.g., reducing the number of channels in active use) or widening (e.g., increasing the number of channels in active use). Link negotiation module 220 can also support different channel subsets operating in different configurations (e.g., operating with different bandwidths or in different states), and can also specify that two or more subsets of channel configurations / statuses should be switched. In one embodiment, link negotiation module 220 may support a subset of the link configurations described herein. In one embodiment, link negotiation module 220 may indicate to one or more connected devices which configurations it supports, or may indicate whether it supports or does not support a configuration requested by one or more connected devices (e.g., via additional data accompanying an acknowledgment or rejection response).

[0022] The link task execution module 230 can perform one or more tasks on a link or a subset of channels of a link. For example, the link task execution module 230 can perform a margin test or equalization (e.g., electrical tuning) on ​​the link before activation, or perform re-equalization at a later time (e.g., due to excessive link errors, due to temperature or other environmental parameters affecting channel characteristics, etc.). The link traffic transmission / reception module 240 can use the link or a subset of channels of a link to transmit data to or receive data from a connected device. In one embodiment, the link task execution module 230 and the link traffic transmission / reception module 240 may not operate simultaneously on the same subset of channels of a link, but may operate simultaneously on different subsets of channels of a link.

[0023] In one embodiment, the various components of device 200 can be configurable. For example, the link can be configured to be divided into one or more subsets of channels and the tasks performed on them for different use cases. The components of device 200 can be configured in hardware or software. For example, device 200 can be configured by a software driver or an application, such as application 250. Examples of applications that can configure device 200 include high-performance computing (HPC) applications, artificial intelligence (AI) applications, gaming applications, and so on. In one embodiment, device 200 can be configured using an application programming interface (API), such as an API provided by a device driver.

[0024] Figure 3A A sequence 300 depicts link states during a link bandwidth change operation according to an embodiment. Each link state in sequence 300 depicts a left subset and a right subset, where each subset may include one or more channels of the link. The initial link state is depicted as an active usage state, where both the left and right subsets are used (e.g., via link traffic transmit / receive module 240) to send and / or receive link traffic. In various embodiments, different initial link states, such as an inactive state, may be used.

[0025] At operation 302, the right subset is configured to be in an active, unused state (as depicted by the dashed line), while the left subset remains in an active, used state. This configuration can be, for example, by... Figure 2 The link negotiation module 220 performs this operation. At operation 304, the right subset, which is in an active but unused state, is configured to a different bandwidth state (e.g., higher or lower bandwidth, as depicted by a change in linewidth). This configuration can be performed, for example, by the link negotiation module 220. Meanwhile, the left subset continues to send and receive traffic.

[0026] At operation 306, the states of the left and right subsets are swapped, such that the left subset is configured as active and unused, while the right subset is configured as active and in use. Therefore, link traffic continues uninterrupted. This configuration swap can be performed, for example, by the link negotiation module 220.

[0027] At operation 308, the left subset, which is in an active, unused state, is configured to a different bandwidth state. This different bandwidth state can be the same as or different from the (new) bandwidth state configured for the right subset. This configuration can be performed, for example, by link negotiation module 220. At operation 310, the right subset is configured to be in an active, used state, and link traffic is restored to the full link under one or more new bandwidths.

[0028] In one embodiment, sequence 300 can be extended to be used for links that are divided into more than two subsets. For example, a link with three subsets can sequentially configure each subset as a new bandwidth, while one or two subsets in the remaining subsets carry the link traffic. In various embodiments, the different subsets can have the same or different numbers of channels. In one embodiment, sequence 300 can be simplified to configure one subset as a new bandwidth while preserving another subset in its original bandwidth configuration (e.g., similar to...). Figure 3B sequence 320).

[0029] Figure 3B A sequence 320 depicts link states during link maintenance operations according to an embodiment. Each link state in sequence 320 depicts a left subset and a right subset, where each subset may include one or more channels of the link. The initial link state is depicted as an active, in-use state, where both the left and right subsets are used (e.g., via link traffic transmit / receive module 240) to send and / or receive link traffic. In various embodiments, different initial link states, such as an inactive state, may be used.

[0030] At operation 322, the right subset is configured to an active, unused state, while the left subset remains in an active, used state. This configuration can be performed, for example, by the link negotiation module 220. At operation 324, a link maintenance task is performed on the right subset, while the left subset continues to send and receive traffic. Therefore, link traffic continues uninterrupted. The link maintenance task can be performed by the link task execution module 230 and can include channel margin testing, channel balancing, or other types of tasks. At operation 326, the right subset is configured to an active, used state, and link traffic is restored to the full link.

[0031] In one embodiment, sequence 300 can be extended to perform the same or similar link maintenance tasks on the left subset (e.g., similar to...). Figure 3B(Sequence 300). In one embodiment, sequence 320 can also be extended to be used for links that are divided into more than two subsets. For example, a link with three subsets can perform maintenance tasks sequentially on each subset, while link traffic is carried by one or two subsets of the remaining subsets.

[0032] Figure 4 This is a flowchart of an example method 400 for channel interleaving in a multi-channel communication interface link according to at least one embodiment. Method 400 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, etc.), computer-readable instructions such as software or firmware (e.g., running on a general-purpose computing system or a dedicated machine), or a combination thereof. For example, the example system may include a memory and a processing device coupled to the memory device to perform operations including the block of method 400. Method 400 may also be associated with a set of instructions stored on a non-transitory computer-readable medium (e.g., a disk or optical disk, etc.). When executed by the processing device, the instructions may cause the processing device to perform operations including the block of method 400. In at least one embodiment, method 400 is performed by… Figures 1A-1D The method is performed by one or more of the switches 110 or devices 120A-120N, 130A-130N, or 140A-140N, or components thereof. In at least one embodiment, method 400 is performed by... Figure 5 The computing system 500 executes. In some embodiments, Figure 4 The boxes depicted may be executed simultaneously or in a different order than those depicted. Various embodiments may include... Figure 4 Additional boxes not depicted in the text or Figure 4 A subset of the boxes depicted in the text.

[0033] At block 402, the processing logic of a device connected to a link of a multi-channel communication interface receives an instruction to perform one or more tasks on that link. This device may be switch 110, device 120A-120N, 130A-130N, or 140A-140N, or device 200. The link of the communication interface may be one of communication interface links 122A-122N, 124A-124N, 132A-132N, 142A-142N, or 210A-210N. The communication interface may be a PCIe interface, CXL interface, InfiniBand interface, Ethernet interface, USB interface, etc. In one embodiment, one or more tasks include: changing the bandwidth of the link; balancing the link in response to one or more communication errors; balancing the link in response to one or more changes in environmental parameters; or other types of tasks. In one embodiment, the link of the multi-channel communication interface is a high-speed peripheral component interconnect (PCIe) link, and one or more tasks include upgrading the PCIe link from a first PCIe generation rate (e.g., Gen 1 rate) to a second PCIe generation rate (e.g., Gen 6 rate). In one embodiment, the instructions for performing one or more tasks are associated with an application (e.g., application 250), such as one or more of a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

[0034] At box 404, the processing logic causes link traffic to be migrated from multiple channels of the multi-channel communication interface to a first subset of the multiple channels of the multi-channel communication interface. The first subset of the multiple channels could be, for example,... Figure 3A - The left subset of Figure B (e.g., the subset that remains in active use). In one embodiment, migrating link traffic from multiple channels to a first subset of multiple channels includes sending a request to a second device connected to the link to reduce the link width from multiple channels to a first subset of multiple channels. For example, this request may be sent by link negotiation module 220 to reduce the link width of a second subset of channels (e.g., Figure 3A - The right subset of Figure B) is reconfigured to an active unused state, and / or traffic is migrated to the first subset. In one embodiment, box 404 corresponds to Figure 3A - Operations 302 and / or 322 in Figure B.

[0035] At block 406, the processing logic executes one or more tasks on a second subset of the multiple channels. In various embodiments, one or more tasks may be executed by the link negotiation module 220, the link task execution module 230, or other components of the device. In one embodiment, while link traffic is being processed by the first subset, one or more tasks are executed on the second subset. Thus, link traffic continues to flow without interruption. In one embodiment, block 406 corresponds to operations 304 and / or 324.

[0036] At block 408, the processing logic causes link traffic to be migrated to a second subset of the multiple channels. In one embodiment, block 408 corresponds to operation 306. At block 410, the processing logic performs one or more tasks on a first subset of the multiple channels. In various embodiments, the tasks performed on the first subset may be the same as or different from the tasks performed on the second subset. In one embodiment, block 410 corresponds to operation 308. At block 412, the processing logic causes link traffic to be restored to the multiple channels. In one embodiment, block 412 corresponds to operation 310.

[0037] In various embodiments, the link may be divided into more than two subsets, and one or more boxes 402-412 may be repeated or extended to one or more additional subsets. In one embodiment, a third subset of multiple channels may be dormant or inactive, while the first and second subsets are in active use or inactive use. In one embodiment, the first, second, and third subsets of multiple channels are mutually exclusive (e.g., no channel in the link belongs to more than one subset).

[0038] Figure 5 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system having interconnect devices and components, a system-on-a-chip (SOC), or some combination thereof with a processor 500, which may include an execution unit for executing instructions. In at least one embodiment, according to this disclosure (such as in the embodiments described herein), the computing system 500 may include, but is not limited to, components such as a processor 502, which employs an execution unit including logic for performing algorithms for processing data. In at least one embodiment, the computer system 500 may include processors available from Intel Corporation, Santa Clara, California, such as the Pentium® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core. TM Or Intel® Nervana TMThe microprocessor may also be used, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 500 may execute a version of the Windows operating system available from Microsoft Corporation, Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0039] These embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, an edge device, an Internet of Things (“IoT”) device, or any other system that can execute one or more instructions according to at least one embodiment.

[0040] In at least one embodiment, the computer system 500 may include, but is not limited to, a processor 502, which may include, but is not limited to, one or more execution units 508 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 500 is a single-processor desktop or server system, but in another embodiment, the computer 500 may be a multiprocessor system. In at least one embodiment, the processor 502 may include, but is not limited to, a Complex Instruction Set Computer (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, a processor implementing instruction set combinations, or any other processor device, such as, for example, a digital signal processor. In at least one embodiment, the processor 502 may be coupled to a processor bus 510, which can transmit data signals between the processor 502 and other components in the computer system 500.

[0041] In at least one embodiment, processor 502 may include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 504. In at least one embodiment, processor 502 may have a single internal cache or multiple internal cache levels. In at least one embodiment, the cache memory may reside external to processor 502. Depending on the specific implementation and requirements, other embodiments may also include a combination of both internal and external caches. In at least one embodiment, register file 506 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0042] In at least one embodiment, execution unit 508 (including, but not limited to, logic for performing integer and floating-point operations) also resides in processor 502. In at least one embodiment, processor 502 may further include a microcode (“ucode”) read-only memory (“ROM”) storing microcode for certain macro instructions. In at least one embodiment, execution unit 508 may include logic for disposing of packaged instruction set 509. In at least one embodiment, by including packaged instruction set 509 along with associated circuitry for executing instructions in the instruction set of general-purpose processor 502, packaged data in general-purpose processor 502 can be used to perform operations used by many multimedia applications. In one or more embodiments, by using the full width of the processor data bus to perform operations on packaged data, the execution of many multimedia applications can be accelerated and performed more efficiently, thereby eliminating the need to transfer smaller data units across the processor data bus to perform one or more operations at a time.

[0043] In at least one embodiment, execution unit 508 may also be used as a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, computer system 500 may include, but is not limited to, memory 520. In at least one embodiment, memory 520 may be implemented as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 520 may store one or more instructions 519 and / or data 521 represented by data signals executable by processor 502.

[0044] In at least one embodiment, the system logic chip may be coupled to the processor bus 510 and the memory 520. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 516, and the processor 502 may communicate with the MCH 516 via the processor bus 510. In at least one embodiment, the MCH 516 may provide a high-bandwidth memory path 518 to the memory 520 for instruction and data storage and for storing graphics commands, data, and textures. In at least one embodiment, the MCH 516 may direct data signals between the processor 502, the memory 520, and other components in the computer system 500, and bridge data signals between the processor bus 510, the memory 520, and the system I / O 522. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 516 may be coupled to the memory 520 via the high-bandwidth memory path 518, and the graphics / video card 512 may be coupled to the MCH 516 via an Accelerated Graphics Port (“AGP”) interconnect 514.

[0045] In at least one embodiment, computer system 500 may use system I / O 522, which serves as a proprietary hub interface bus, to couple MCH 516 to I / O controller hub (“ICH”) 530. In at least one embodiment, ICH 530 may provide direct connectivity to some I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to memory 520, chipset, and processor 502. Examples may include, but are not limited to, an audio controller 529, a firmware hub (“Flash BIOS”) 528, a wireless transceiver 526, a data storage device 524, a conventional I / O controller 523 including a user input and keyboard interface 525, a serial expansion port 527 (such as Universal Serial Bus (“USB”)), and a network controller 534, which in some embodiments may include a data processing unit. Data storage device 524 may include a hard disk drive, floppy disk drive, CD-ROM device, flash memory device, or other mass storage device.

[0046] In at least one embodiment, Figure 5 The illustration depicts a system including interconnecting hardware devices or "chips," while in other embodiments, Figure 5An exemplary system-on-a-chip (“SoC”) may be illustrated. In at least one embodiment, the devices may be interconnected via proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 500 are interconnected using compute fast link (CXL) interconnects. In at least one embodiment, system 500 may correspond to systems 100A-100D or components thereof, such as devices 120A-120N, 130A-130N, 140A-140N, 200 and connection links 122A-122N, 124A-124N, 132A-132N, 142A-142N, and 210A-210N.

[0047] Figure 6 This is a block diagram of a computing system 600 having two processing devices coupled to each other and multiple networks according to at least one embodiment. The computing system 600 is designed with multiple integrated circuits (referred to as processing devices), each including a CPU and two GPUs, forming a powerful and flexible architecture. These processing devices are interconnected via NVLink (or other high-speed interconnects) to enable high-speed communication between the processing devices; and are also connected via network interface cards (NICs) or data processing units (DPUs) to ensure efficient data transfer across the computing system 600. Coupling the processing devices via NVLink enables seamless data exchange and parallel processing, thereby improving overall computing performance. Additionally, these processing devices are connected to multiple networks via one or more network interface cards (NICs) or DPUs, enabling the system to handle complex multi-network tasks with high bandwidth and low latency. This configuration makes the computing system 600 ideal for demanding applications requiring high processing power, such as artificial intelligence (AI), machine learning (ML), and data-intensive computing, while ensuring robust connectivity and scalability across various networked environments. The integrated circuits of the computing system 600 may include one or more CPUs and one or more GPUs. Figure 6 The diagram illustrates an example architecture for a multi-GPU architecture.

[0048] like Figure 6As illustrated, computing system 600 includes processing device 602 with a multi-GPU architecture. Specifically, processing device 602 includes CPU 606, GPU 608, and GPU 610. CPU 606 may be coupled to GPU 608 via die-to-die (D2D) or chip-to-chip (C2C) interconnect 612 (such as a ground reference signaling interconnect (GRS interconnect)). CPU 606 may be coupled to GPU 610 via D2D or C2C interconnect 614. CPU 606 may also be coupled to GPU 608 and GPU 610 via PCIe interconnect. CPU 606 may be coupled to one or more network interface cards (NICs) or data processing units (DPUs), which in turn are coupled to one or more networks. For example, as Figure 6 As illustrated, CPU 606 is coupled to a first NIC / DPU 626, which is coupled to network 630. CPU 606 is also coupled to a second NIC / DPU 628, which is coupled to network 630. NIC / DPU 626 and NIC / DPU 628 can be coupled to network 630 via Ethernet (ETH) or InfiniBand (IB) connections.

[0049] The computing system 600 also includes a processing device 604 with a multi-GPU architecture. Specifically, the processing device 604 includes a CPU 616, a GPU 618, and a GPU 620. The CPU 616 can be coupled to the GPU 618 via a D2D or C2C interconnect 622. The CPU 616 can be coupled to the GPU 620 via a D2D or C2C interconnect 624. The CPU 616 can also be coupled to the GPUs 618 and 620 via a PCIe interconnect. The CPU 616 can be coupled to one or more NICs or DPUs, which in turn are coupled to one or more networks. For example, as... Figure 6 As illustrated, CPU 616 is coupled to a first NIC / DPU 632, which is coupled to network 636. CPU 616 is also coupled to a second NIC / DPU 634, which is coupled to network 636. NIC / DPU 632 and NIC / DPU 634 can be coupled to network 636 via Ethernet (ETH) or InfiniBand (IB) connections.

[0050] In at least one embodiment, processing device 602 and processing device 604 can communicate with each other via NIC / DPU 638 (such as via PCIe interconnect). Processing device 602 and processing device 604 can also communicate with each other via high-bandwidth communication interconnect 640 (such as NVLink interconnect or other high-speed interconnect).

[0051] In at least one embodiment, the computing system 600 is used for high-speed network communication and includes processing units (e.g., CPU 606, GPU 608, GPU 610, CPU 616, GPU 618, GPU 620, NIC / DPU 626, NIC / DBU 628, NIC / DDU 632, NIC / DMU 634, or NIC / DPU 638), memory coupled to one or more processing units, and a network interface coupled to one or more processing units and memory via a link through a communication interface. In various embodiments, one or more linked devices may include reference devices. Figure 2 The described component is used to interleave channels of a multi-channel communication interface and perform one or more tasks on each channel.

[0052] Figure 7This is a block diagram of a computing system 700 having a CPU 702 and a GPU 704 on a single integrated circuit, according to at least one embodiment. The computing system 700 can be a highly integrated design where the CPU 702 and GPU 704 are connected on a single integrated circuit, thereby enabling fast, low-latency communication between the two processing units using an NVLink C2C (chip-to-chip) interconnect 706. This tight integration allows for efficient data transfer and parallel processing between the CPU 702 and GPU 704, thereby optimizing the execution of complex computational tasks. The GPU elements within the computing system 700 can be interconnected using an NVLink network, allowing for scalability of up to 256 GPU elements, creating a robust and unified processing environment particularly suitable for large-scale AI, ML, and high-performance computing applications. The NVLink network can be a GPU construct with a high-bandwidth communication interconnect 710. Additionally, the computing system 700 can be designed to interface with high-speed I / O via a PCIe interconnect 708, thereby ensuring fast data transfer with external devices, further enhancing the system's ability to handle data-intensive tasks and providing robust connectivity to peripheral components. It should be noted that since the CPU 702 and GPU 704 reside on the same integrated circuit, the C2C interconnect 706 can be considered a D2D interconnect. The integrated circuit may include CPU memory (also referred to as main memory) and GPU memory, and the CPU 702 and GPU 704 can access the CPU memory and GPU memory respectively via a high-speed interconnect. The computing system 700 can integrate the performance of the GPU 704 with the versatility of the CPU 702. The CPU 702 can be connected to the high-bandwidth and memory-coherent C2C interconnect 706 within a single integrated circuit. The computing system 700 can support a link-switching system.

[0053] In at least one embodiment, the computing system 700 is used for high-speed network communication and includes processing units (e.g., CPU 702, GPU 704, NVLink network), memory coupled to one or more processing units, and a network interface coupled to one or more processing units and memory via a link of a communication interface. In various embodiments, one or more linked devices may include reference devices. Figure 2 The described component is used to interleave channels of a multi-channel communication interface and perform one or more tasks on each channel.

[0054] Figure 8This is a block diagram of a computing system 800 having a tensor core GPU 808 according to at least one embodiment. The computing system 800 may be a DGX H100 system, which is a high-performance computing platform designed to meet the needs of AL, ML, and deep learning (DL) workloads. The computing system 800 may include multiple tensor core GPUs 808 (e.g., NVIDIA H100 tensor core GPUs). Each tensor core GPU 808 may be one of the above-described... Figure 7 One of the integrated circuits described is the Tensor Core GPU 808, which is optimized for AI / ML / DL applications, delivering superior performance for deep learning training, inference, and high-performance computing tasks. The Tensor Core GPUs 808 within the computing system 800 are interconnected using high-speed communication interfaces such as NVLink, enabling rapid data transfer between them, which is crucial for handling large-scale AI models and datasets with low latency. The computing system 800 is designed for scalability, allowing additional GPUs to be integrated as needed, making it sufficiently versatile for research, development, and deployment in data centers used for production AI workloads. Each GPU is equipped with a Tensor Core, a dedicated processing unit that accelerates matrix operations and is a fundamental component of AI and deep learning algorithms. These Tensor Cores enable the system to perform mixed-precision computations efficiently, balancing speed and accuracy. Given the power consumption and heat generation of multiple Tensor Core GPUs 808, the computing system 800 may include advanced cooling solutions and power management features to ensure safe operation while maintaining peak performance. It is powered by a comprehensive software ecosystem that includes NVIDIA's CUDA programming model, AI frameworks such as TensorFlow and PyTorch, and other HPC and AI software tools that enable developers and researchers to leverage the full power of the TensorCore GPU 808 for their specific applications. The Computing System 800 is well-suited for large-scale AI model training, real-time inference, scientific simulations, data analysis, and other compute-intensive tasks requiring significant parallel processing power.

[0055] The Tensor Core GPU 808 can be coupled to multiple CPUs, such as CPU 802 and CPU 804, using a switch 806 (e.g., a CX7 HCA / NIC with a PCIe switch). The Tensor Core GPU 808 can be coupled to each other via a switch 810 (e.g., an NVSwitch). Switches 806 and 810 can be coupled to a high-speed transceiver module 812. The high-speed transceiver module 812 can be an Octal Small Pluggable (OSFP) module. OSFP modules are high-speed transceiver modules designed for fast data communication, specifically in environments requiring high bandwidth, such as data centers and high-performance computing systems. These modules support extremely high data rates, typically up to 400 Gbps per module, with future expansion capabilities to 800 Gbps or higher. OSFP modules interface with the system via a PCIe interface, enabling fast and efficient data transfer between the integrated CPU-GPU components and external networks or other connected systems. Their hot-swappable nature allows for easy insertion or removal without shutting down the system, providing flexibility and maintainability crucial in critical uptime environments. Additionally, OSFP modules are designed for high density, maximizing the number of high-speed connections within limited spaces, such as densely packed server racks. By complying with the latest networking standards, OSFP modules ensure that the Compute System 800 can meet ever-increasing data demands and can be upgraded to support future network speed increases, thus contributing to improved overall system performance and scalability.

[0056] In at least one embodiment, the computing system 800 can be viewed as a data network configuration with full-bandwidth in-server NVLink. In this example, all eight tensor core GPUs 808 can simultaneously saturate eighteen NVLinks of other GPUs within the server. Bandwidth is limited by oversubscription from multiple other GPUs. In another embodiment, the data network configuration can be half-bandwidth in-server NVLink. In this example, all eight tensor core GPUs 808 can subscribe to eighteen NVLinks from GPUs in other servers. Four tensor core GPUs 808 can saturate eighteen NVLinks of GPUs in other servers. This is equivalent to full bandwidth on all-reduce with a scalable hierarchical aggregation and reduction protocol (SHARP). The reduction of all-to-all (all-2-all, All2All) bandwidth is a trade-off between server complexity and cost. In at least one embodiment, all eight tensor core GPUs 808 can independently transmit data in a multi-track InfiniBand / Ethernet configuration using the Remote Direct Memory Access (RDMA) protocol via their own dedicated switches (e.g., 400Gb / s HCA / NIC). In this example, the total full-duplex bandwidth for non-NVLink network devices is 800 GB / s.

[0057] In at least one embodiment, the computing system 800 is used for high-speed network communication and includes a processing unit (e.g., CPU 802, CPU 804, switch 806, tensor core GPU 808, switch 810, high-speed transceiver module 812) and a network interface coupled to the processing unit via a link through a communication interface. In various embodiments, one or more linked devices may include reference devices. Figure 2 The described component is used to interleave channels of a multi-channel communication interface and perform one or more tasks on each channel.

[0058] Other variations are within the spirit of this disclosure. Therefore, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments are shown in the accompanying drawings and have been described in detail above. However, it should be understood that this disclosure is not intended to be limited to one or more specific forms disclosed, but rather is intended to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of this disclosure as defined by the appended claims.

[0059] Unless otherwise indicated herein or obviously contradicted by the context, the terms “a,” “an,” and “the,” and similar designations, used in the context of describing the disclosed embodiments (especially in the context of the following claims), should be interpreted as encompassing both the singular and plural, and not as definitions of the terms. Unless otherwise stated, the terms “comprising,” “having,” “including,” and “containing” are to be interpreted as open-ended terms (meaning “including, but not limited to”). The term “connection,” when unmodified and referring to a physical connection, is to be interpreted as partially or completely contained, attached to, or combined, even with intervening elements. Unless otherwise indicated herein, statements of value ranges herein are intended only as a shorthand for individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually stated herein. Unless otherwise indicated or contradicted by the context, the use of the terms “set” (e.g., “item set”) or “subset” is to be interpreted as a non-empty set comprising one or more members. Furthermore, unless otherwise indicated or contradicted by the context, the term "subset" in the context of a corresponding set does not necessarily mean a proper subset of the corresponding set, but rather that a subset and the corresponding set can be equal.

[0060] Unless explicitly stated otherwise or clearly contradicted by the context, connective language (such as phrases of the form "at least one of A, B, and C" or "at least one of A, B, and C") is otherwise understood, along with the context, as generally used to represent any non-empty subset of a set, such as items, terms, etc., that can be A or B or C, or A and B and C. For example, in an illustrative example of a set with three members, the connective phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Therefore, such connective language is generally not intended to imply that certain embodiments require the existence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise indicated by or contradicted by the context, the term "multiple" indicates a state of multiple (e.g., "multiple items" indicates many items). Multiple means at least two items, but can be more when explicitly indicated or indicated by the context. Furthermore, unless otherwise stated or clearly implied by the context, the phrase “based on” means “at least partially based on” rather than “based on only”.

[0061] Unless otherwise indicated herein or clearly contradicted by the context, the operations of the processes described herein may be performed in any suitable order. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are executed under the control of one or more computer systems configured with executable instructions and are implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more application programs) that executes jointly on one or more processors. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable storage medium that does not include transient signals (e.g., propagation of transient electrical or electromagnetic transmissions) but includes non-transitory data storage circuitry (e.g., buffers, caches, and queues) within a transceiver that includes transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) that, when executed by one or more processors of a computer system (i.e., due to being executed), cause the computer system to perform the operations described herein. In at least one embodiment, the set of non-transitory computer-readable storage media comprises a plurality of non-transitory computer-readable storage media, and one or more of the various non-transitory storage media lack all the code, while the plurality of non-transitory computer-readable storage media collectively store all the code. In at least one embodiment, the executable instructions are executed such that different instructions are executed by different processors; i.e., for example, the non-transitory computer-readable storage media stores the instructions, and the main central processing unit (“CPU”) executes some of the instructions, while the graphics processing unit (“GPU”) executes the others. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0062] Therefore, in at least one embodiment, the computer system is configured to implement one or more services that individually or collectively perform the processes described herein, and such a computer system is configured with applicable hardware and / or software capable of performing the operations. Further, the computer system implementing at least one embodiment of this disclosure is a single device, and in another embodiment, it is a distributed computer system comprising multiple devices that operate in different ways such that the distributed computer system performs the operations described herein, and that a single device does not perform all the operations.

[0063] The use of any and all examples or exemplary language (e.g., “such as”) provided herein is intended only to better illustrate embodiments of this disclosure and, unless otherwise required, does not constitute a limitation on the scope of the disclosure. No language in the specification should be construed as indicating that any unclaimed element is essential for implementing this disclosure.

[0064] All references cited herein, including publications, patent applications and patents, are incorporated herein by reference to the same extent that each reference is separately and specifically indicated to be incorporated by reference and fully elaborated herein.

[0065] The terms “coupled” and “connected” and their derivatives may be used in the specification and claims. It should be understood that these terms are not intended to be synonyms with each other. Rather, in specific examples, “connected” or “coupled” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” can also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0066] Unless otherwise explicitly stated, it should be understood throughout this specification that terms such as “processing,” “computing,” “calculating,” “determining,” etc., refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate and / or transform data representing physical (such as electronic) quantities in the registers and / or memory of the computing system into other data representing physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0067] Similarly, the term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory and transforms that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a CPU or a GPU. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Furthermore, each process can refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" are used interchangeably herein, provided that a system can embody one or more methods and a method can be considered a system.

[0068] This document describes the process of acquiring, obtaining, receiving, or inputting analog or digital data into a subsystem, computer system, or computer implementation machine. Acquiring, obtaining, receiving, or inputting analog and digital data can be accomplished in various ways, such as by receiving data as a parameter to a function call or a call to an application programming interface (API). In some implementations, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of acquiring, obtaining, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference can also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as an input or output parameter to a function call, an API, or an inter-process communication mechanism.

[0069] While the foregoing discussion illustrates exemplary implementations of the described technologies, other architectures may also be used to implement the aforementioned functionality and are intended to fall within the scope of this disclosure. Furthermore, although specific assignments of responsibilities have been defined above for discussion purposes, various functions and responsibilities may be distributed and divided in different ways depending on the circumstances.

[0070] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or actions described. Rather, specific features and actions are disclosed as exemplary forms for implementing the claims.

Claims

1. A method comprising: A device connected to a link to a multi-channel communication interface causes link traffic to be migrated from multiple channels of the multi-channel communication interface to a first subset of the multiple channels of the multi-channel communication interface; Perform one or more tasks on a second subset of the plurality of channels; as well as This allows the link traffic to be restored to the multiple channels.

2. The method as described in claim 1, wherein, While the link traffic is being processed by the first subset, the one or more tasks are executed on the second subset.

3. The method of claim 1, further comprising: This causes the link traffic to be migrated to the second subset of the multiple channels; as well as The one or more tasks are performed on the first subset of the plurality of channels.

4. The method of claim 1, wherein the one or more tasks comprise: Change the bandwidth of the link; or In response to one or more communication errors, the link is balanced.

5. The method of claim 1, wherein, The first subset of the links that migrates traffic from the plurality of channels to the plurality of channels includes: A request is sent to a second device connected to the link to reduce the link width from the plurality of channels to a first subset of the plurality of channels.

6. The method of claim 1, wherein, The link of the multi-channel communication interface is a high-speed peripheral component interconnect PCIe link, and wherein the one or more tasks include: upgrading the PCIe link from a first PCIe generation rate to a second PCIe generation rate.

7. The method of claim 1, wherein, A third subset of the plurality of channels is in a dormant state, wherein the first subset, the second subset, and the third subset of the plurality of channels are mutually exclusive.

8. The method of claim 1, further comprising: The device receives instructions to perform the one or more tasks.

9. The method of claim 8, wherein, The instructions for performing the one or more tasks are associated with an application, wherein the application is one of the following: a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

10. A system for connecting a device to a link of a multi-channel communication interface, the system comprising: Memory; as well as One or more processing units, coupled to the memory, to perform operations including: This causes link traffic to be migrated from multiple channels of the multi-channel communication interface to a first subset of the multiple channels of the multi-channel communication interface; Perform one or more tasks on a second subset of the plurality of channels; as well as This allows the link traffic to be restored to the multiple channels.

11. The system of claim 10, wherein, While the link traffic is being processed by the first subset, the one or more tasks are executed on the second subset.

12. The system of claim 10, wherein the operation further comprises: This causes the link traffic to be migrated to the second subset of the multiple channels; as well as The one or more tasks are performed on the first subset of the plurality of channels.

13. The system of claim 10, wherein the one or more tasks include: Change the bandwidth of the link; or In response to one or more communication errors, the link is balanced.

14. The system of claim 10, wherein, The first subset of the links that migrates traffic from the plurality of channels to the plurality of channels includes: A request is sent to a second device connected to the link to reduce the link width from the plurality of channels to a first subset of the plurality of channels.

15. The system of claim 10, wherein, The link of the multi-channel communication interface is a high-speed peripheral component interconnect PCIe link, and wherein the one or more tasks include: upgrading the PCIe link from a first PCIe generation rate to a second PCIe generation rate.

16. The system of claim 10, wherein, A third subset of the plurality of channels is in a dormant state, wherein the first subset, the second subset, and the third subset of the plurality of channels are mutually exclusive.

17. The system of claim 10, wherein the operation further comprises: Receive instructions for performing the one or more tasks.

18. The system of claim 17, wherein, The instructions for performing the one or more tasks are associated with an application, wherein the application is one of the following: a high-performance computing (HPC) application, an artificial intelligence (AI) application, or a gaming application.

19. A non-transitory computer-readable medium comprising instructions that, when executed by a processing unit of a device connected to a link of a multi-channel communication interface, cause the processing unit to perform operations including: This causes link traffic to be migrated from multiple channels of the multi-channel communication interface to a first subset of the multiple channels of the multi-channel communication interface; Perform one or more tasks on a second subset of the plurality of channels; as well as This allows the link traffic to be restored to the multiple channels.

20. The non-transitory computer-readable medium of claim 19, wherein, While the link traffic is being processed by the first subset, the one or more tasks are executed on the second subset.

21. The non-transitory computer-readable medium of claim 19, wherein the operation further comprises: This causes the link traffic to be migrated to the second subset of the multiple channels; as well as The one or more tasks are performed on the first subset of the plurality of channels.

22. The non-transitory computer-readable medium of claim 19, wherein the one or more tasks include: Change the bandwidth of the link; or In response to one or more communication errors, the link is balanced.

23. A system for high-speed network communication in a data center, the system comprising: One or more processing units; A memory coupled to one or more processing units; as well as A network interface, coupled to the one or more processing units and the memory via a link of a multi-channel communication interface, wherein the network interface is used to perform operations including: This causes link traffic to be migrated from multiple channels of the multi-channel communication interface to a first subset of the multiple channels of the multi-channel communication interface; Execute one or more tasks on a second subset of the plurality of channels; and This allows the link traffic to be restored to the multiple channels.

24. The system of claim 23, wherein, While the link traffic is being processed by the first subset, the one or more tasks are executed on the second subset.

25. The system of claim 23, wherein the operation further comprises: This causes the link traffic to be migrated to the second subset of the multiple channels; as well as The one or more tasks are performed on the first subset of the plurality of channels.

26. The system of claim 23, wherein the one or more tasks comprise: Change the bandwidth of the link; or In response to one or more communication errors, the link is balanced.

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