Information processing apparatus and information processing system

Abstract

Embodiments of the present disclosure relate to an information processing device and an information processing system. An information processing device includes: a dynamically reconfigurable processor capable of dynamically reconfiguring processing content; an accelerator configured to accelerate inference of an AI model; a shared buffer provided between the dynamically reconfigurable processor and the accelerator and connected to the dynamically reconfigurable processor through a dedicated first bus and to the accelerator through a dedicated second bus, respectively; a shared bus connected to the dynamically reconfigurable processor, the accelerator, and the shared buffer; and a transfer circuit connected to an external memory and capable of transferring data using the shared bus. A computation result of the accelerator is stored in the shared buffer via the second bus, the dynamically reconfigurable processor receives the computation result of the accelerator stored in the shared buffer via the first bus and compresses the received computation result, and the transfer circuit transfers the compressed data via the shared bus to be stored in the external memory.

Description

Cross-reference to related applications

[0001] The disclosure of Japanese Patent Application No. 2025-067417, filed on April 16, 2025, which includes a specification, drawings and an abstract, is incorporated herein by reference in its entirety. Background Technology

[0002] This disclosure relates to information processing equipment, and specifically to information processing equipment and systems for AI learning.

[0003] Devices that perform computational processing include dynamically reconfigurable processors (DRPs: also known as array processors), which have higher processing performance than central processing units (CPUs). A dynamically reconfigurable processor is a processor that can dynamically reconfigure circuitry by switching the computational content of each of multiple processor elements and the connection relationships between multiple processor elements according to sequentially given operation instructions.

[0004] The technologies listed below have been disclosed.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2019-219753

[0006] For example, Patent Document 1 discloses a process that uses DRP in large-scale computational processing such as deep learning processing. Summary of the Invention

[0007] On the other hand, further improvements are needed to perform high-speed data processing. This disclosure provides an information processing apparatus and an information processing system capable of performing high-speed data processing.

[0008] Other issues and novel features will become apparent from the description and accompanying drawings in this specification.

[0009] The information processing apparatus according to this disclosure includes: a dynamically reconfigurable processor capable of dynamically reconfiguring processed content; an accelerator configured to accelerate inference of an AI model; the dynamically reconfigurable processor; a shared buffer; a shared bus; and a transmission circuit. The shared buffer is disposed between the dynamically reconfigurable processor and the accelerator, and is connected to the dynamically reconfigurable processor via a dedicated first bus and to the accelerator via a dedicated second bus. The shared bus is connected to the dynamically reconfigurable processor, the accelerator, and the shared buffer. The transmission circuit is connected to external memory and is capable of transmitting data using the shared bus. The computation results of the accelerator are stored in the shared buffer via the second bus, the dynamically reconfigurable processor receives the computation results of the accelerator stored in the shared buffer via the first bus and compresses the received computation results, and the transmission circuit transmits the compressed data via the shared bus for storage in external memory.

[0010] The information processing system according to this disclosure includes: a dynamically reconfigurable processor capable of dynamically reconfiguring processing content; an accelerator configured to accelerate inference of an AI model; the dynamically reconfigurable processor; a shared buffer; a shared bus; and a transmission circuit. The shared buffer is disposed between the dynamically reconfigurable processor and the accelerator, and is connected to the dynamically reconfigurable processor via a dedicated first bus and to the accelerator via a dedicated second bus. The shared bus is connected to the dynamically reconfigurable processor, the accelerator, and the shared buffer. The transmission circuit is connected to external memory and is capable of transmitting data using the shared bus. The computation results of the accelerator are stored in the shared buffer via the second bus, the dynamically reconfigurable processor receives the computation results stored in the shared buffer via the first bus and compresses the received computation results, and the transmission circuit transmits the compressed data via the shared bus for storage in external memory.

[0011] The information processing equipment and information processing system disclosed herein are capable of performing high-speed data processing. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating the hardware configuration of the information processing system 1 according to the first embodiment.

[0013] Figure 2 This is a flowchart illustrating the computational processing operation of deep learning using AI accelerator 140 according to the first embodiment.

[0014] Figure 3 This is a flowchart illustrating the processing of the MPU 100 according to the first embodiment.

[0015] Figure 4A and Figure 4B This is a diagram illustrating the process flow (part 1) according to the first embodiment.

[0016] Figure 5A and Figure 5B This is a diagram illustrating the process flow (part 2) according to the first embodiment.

[0017] Figure 6A and Figure 6B This is a diagram illustrating the process flow (part 3) according to the first embodiment.

[0018] Figure 7A and Figure 7B This is a diagram illustrating the process flow (part 4) according to the first embodiment.

[0019] Figure 8A and Figure 8BThis is a diagram illustrating the process flow (part 5) according to the first embodiment.

[0020] Figure 9A and Figure 9B This is a diagram illustrating the process flow (part 6) according to the first embodiment.

[0021] Figure 10A and Figure 10B This is a diagram illustrating the process flow (part 7) according to the first embodiment.

[0022] Figure 11A and Figure 11B This is a diagram illustrating the process flow (part 8) according to the first embodiment.

[0023] Figure 12A and Figure 12B This is a diagram illustrating the process flow (part 9) according to the first embodiment.

[0024] Figure 13A and Figure 13B This is a diagram illustrating the process flow (part 10) according to the first embodiment.

[0025] Figure 14 This is a diagram illustrating an example of compression processing performed by the dynamically reconfigurable circuit 120 according to a first embodiment.

[0026] Figure 15A and Figure 15B This is a diagram illustrating another example of compression processing performed by the dynamically reconfigurable circuit 120 according to the first embodiment.

[0027] Figure 16A and Figure 16B This is a diagram illustrating the processing time of the information processing system 1 according to the comparative example and the first embodiment.

[0028] Figure 17 This is a block diagram illustrating the hardware configuration of the information processing system 1# according to the second embodiment.

[0029] Figure 18 This is a block diagram illustrating the hardware configuration of the information processing system 1A according to the third embodiment.

[0030] Figure 19 This is a flowchart illustrating the computational processing operation of deep learning using AI accelerator 140 according to the fourth embodiment.

[0031] Figure 20 This is a diagram illustrating the hardware configuration of the information processing system 1B according to the fourth embodiment.

[0032] Figure 21This is a flowchart illustrating the processing of the MPU 100 according to the fourth embodiment. Detailed Implementation

[0033] In the following description, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same or corresponding parts are indicated by the same reference numerals and their descriptions will not be repeated.

[0034] First Embodiment

[0035] Figure 1 This is a block diagram illustrating the hardware configuration of the information processing system 1 according to the first embodiment. (See reference) Figure 1 The information processing system 1 includes a dynamic random access memory (DRAM) 20 and a microprocessor unit (MPU) 100 as an information processing device. In this example, the information processing system 1 with a configuration including an MPU is described; the MPU is a single information processing device, but it may also have a configuration including multiple information processing devices operating collaboratively. The MPU 100 includes a central processing unit (CPU) 110, a dynamically reconfigurable circuit (DRP) 120, a shared buffer 130, an AI accelerator (AI-MAC) 140, a shared bus 150, a direct memory access (DMA) circuit 180, and dedicated buses 160 and 170. The DMA circuit 180 is connected to the DRAM 20 and is capable of high-speed access to the DRAM 20 via the shared bus 150 to transfer data to another circuit. The DMA circuit 180 is a circuit capable of performing high-speed transfers from another circuit to the DRAM 20 via the shared bus 150.

[0036] A shared bus 150 connects to each circuit of each unit of the MPU 100. The DRP 120 includes multiple processor elements arranged in an array, multiple switching elements corresponding to the processor elements, and a state management unit. The state management unit issues instruction pointers predetermined by a program to each processor element. Each processor element includes, for example, at least an instruction memory and a computation unit. The computation unit performs computation processing according to an operation instruction specified by the instruction pointer from the state management unit among multiple operation instructions stored in the instruction memory. The computation unit may be, for example, a 16-bit calculator performing computation processing on data with a 16-bit width, but it could also be a calculator performing computation processing on data with other bit widths. Alternatively, the computation unit may include multiple calculators. Furthermore, each switching element sets the connection relationship between a corresponding processor element and another processor element according to an operation instruction read from the instruction memory of the corresponding processor element. As a result, the DRP 120 can dynamically switch circuit configurations according to sequentially given operation instructions. In this example, for example, the DRP 120 operates as a compression circuit for compressing data or a decompression circuit for decompressing compressed data.

[0037] AI accelerator 140 is a circuit that accelerates inference for AI models. It performs computational processing in parallel based on the AI ​​model. AI accelerator 140 receives input data from shared buffer 130, performs computational processing, and stores the computation results back in shared buffer 130. In this example, a dedicated bus 170 is positioned between shared buffer 130 and AI accelerator 140, enabling high-speed data exchange.

[0038] A shared buffer 130 is positioned between DRP 120 and AI-MAC 140, connected by dedicated buses 160 and 170, and configured to exchange data at high speed. Although connected to the shared bus 150, high-speed data exchange with the connection destination is possible through the use of dedicated buses 160 and 170.

[0039] The CPU 110 issues instructions to perform various operations. The DRAM 20, serving as external memory, stores software programs, data, etc., used to implement various functions. In this example, for instance, the DRAM 20 stores, for example, a compression program 21 that enables the dynamically reconfigurable circuitry 120 to function as a compression circuit, a decompression program 22 that enables the dynamically reconfigurable circuitry 120 to function as a decompression circuit corresponding to the compression circuit, and AI model data 23 for the AI ​​accelerator 140. The AI ​​model is configured by connecting multiple layers, and the AI ​​model data has data specific to each layer.

[0040] Note that the information processing system can be connected to a display device and an input device. The display device performs screen display. The input device inputs user commands into the information processing system. Examples of input devices include a keyboard that receives character input from the user, and a mouse that specifies any location on the display device's screen and receives input corresponding to an icon displayed at that location. However, the devices connected to the information processing system 1 are not limited to these.

[0041] Figure 2 This is a flowchart illustrating the computational processing operations of deep learning using the AI ​​accelerator 140 according to the first embodiment. (Reference) Figure 2 The AI ​​accelerator 140 constructs layer A1 of the AI ​​model (step S2). Then, the AI ​​accelerator 140 acquires feature D1 (step S4). Subsequently, the AI ​​accelerator 140 uses the acquired feature D1 to perform computational processing based on layer A1 of the AI ​​model (step S6). Specifically, this involves performing a product sum operation that multiplies the input data by weights, performing operations such as activation on the result of the product sum operation, and outputting the computational result.

[0042] Through this process, AI accelerator 140 calculates feature D2 (step S8). Then, AI accelerator 140 constructs layer A2 of the AI ​​model (step S10). Next, AI accelerator 140 acquires feature D2 (step S11). Then, AI accelerator 140 uses the acquired feature D2 to perform computational processing based on layer A2 of the AI ​​model (step S12). This involves performing a product sum operation that multiplies the input data by weights, performing operations such as activation on the result of the product sum operation, and outputting the computation result.

[0043] Through the above processing, AI accelerator 140 calculates feature D3 (step S13). Then, AI accelerator 140 constructs layer A3 of the AI ​​model (step S14). Next, AI accelerator 140 acquires feature D3 (step S15). Then, AI accelerator 140 uses the acquired feature D3 to perform computation processing based on layer A3 of the AI ​​model (step S16). This involves performing a product sum operation that multiplies the input data by weights, performing operations such as activation on the result of the product sum operation, and outputting the computation result. Through the above processing, AI accelerator 140 calculates feature D4 (step S17). Necessary features can be extracted by sequentially repeating the same procedure.

[0044] Figure 3 This is a flowchart illustrating the processing of the MPU 100 according to the first embodiment. (Reference) Figure 3 MPU 100 constructs layer A1 of the AI ​​model (step S20).

[0045] Figure 4 is a diagram illustrating the process flow (part 1) according to the first embodiment. (See reference) Figure 4A Assume that DRAM 20 pre-stores feature D1. For example, feature D1 could be initial value data. DMA circuit 180 accesses DRAM 20, for example, according to instructions from CPU 110, and transfers AI model data 23 stored in DRAM 20 to AI accelerator 140. AI accelerator 140 constructs layer A1 of the AI ​​model based on AI model data 23.

[0046] refer to Figure 4B The diagram illustrates the process of transmitting AI model data 23 to AI accelerator 140 at time T0 and constructing layer A1 of the AI ​​model.

[0047] Reference Figure 3 MPU 100 then transfers feature D1 from DRAM 20 to shared buffer 130 (step S21). Subsequently, MPU 100 transfers data from shared buffer 130 to AI accelerator 140 (step S22).

[0048] Figure 5 is a diagram illustrating the process flow (part 2) according to the first embodiment. (See reference) Figure 5A Specifically, the DMA circuit 180 retrieves the data of feature D1 stored in DRAM 20 according to instructions from CPU 110, and transfers the data to shared buffer 130 via shared bus 150. (See reference) Figure 5B The AI ​​accelerator 140 is in a state of waiting to receive data from the shared buffer 130 after the layer A1 of the AI ​​model has been built.

[0049] Reference Figure 3 MPU 100 then transfers the data from shared buffer 130 to AI accelerator 140 (step S22). Subsequently, MPU 100 performs processing based on layer A1 of the AI ​​model (step S24). Subsequently, MPU 100 stores the computation results of AI accelerator 140 in shared buffer 130 (step S26).

[0050] Figure 6 is a diagram illustrating the process flow (part 3) according to the first embodiment. (See reference) Figure 6A The shared buffer 130 transmits the data of feature D1 to the AI ​​accelerator 140 via a dedicated bus 170. The AI ​​accelerator 140 follows a procedure that performs a product sum operation on the data of feature D1 (which is the input data) multiplied by weights, performs activation operations on the result, and outputs the computation result. Then, the AI ​​accelerator 140 transmits the data of feature D2, which is the computation result, to the shared buffer 130. (See reference...) Figure 6B The diagram illustrates a series of processes performed by the AI ​​accelerator 140 on layer A1 based on the AI ​​model at time T1.

[0051] Reference Figure 3 The MPU 100 then constructs the compression circuit in the dynamically reconfigurable circuit 120 (step S30).

[0052] Figure 7 is a diagram illustrating the process flow (part 4) according to the first embodiment. (See reference) Figure 7A During processing between the shared buffer 130 and the AI ​​accelerator 140, the DMA circuit 180 accesses the DRAM 20 according to instructions from the CPU 110 and transfers the compression program 21 stored in the DRAM 20 to the dynamically reconfigurable circuit 120. The dynamically reconfigurable circuit 120 constructs a compression circuit based on the compression program 21. (See reference...) Figure 7B The illustration shows that at time T2, the DMA circuit 180 transfers the compression program 21 stored in the DRAM 20 to the dynamically reconfigurable circuit 120, and constructs the compression circuit according to the compression program 21.

[0053] Reference Figure 3Subsequently, MPU 100 causes the dynamically reconfigurable circuit 120 to perform compression processing on the data of feature D2 (step S32). Then, MPU 100 transmits the compressed data to DRAM 20 (step S34).

[0054] Figure 8A and Figure 8B This is a diagram illustrating the process flow (part 5) according to the first embodiment. (See reference) Figure 8A Feature D2 is transferred from shared buffer 130 to dynamically reconfigurable circuitry 120. Dynamically reconfigurable circuitry 120 operates as a compression circuit and stores compressed data of feature D2 in DRAM 20 via DMA circuitry 180. (See reference) Figure 8B The illustration shows that at time T3 after the processing of AI accelerator 140, the dynamically reconfigurable circuit 120 performs compression processing and transfers the compressed data to DRAM 20 via DMA circuit 180.

[0055] Reference Figure 3 MPU 100 constructs layer A2 of the AI ​​model (step S35). Subsequently, MPU 100 constructs the decompression circuit of dynamically reconfigurable circuit 120 (step S36).

[0056] Figure 9A and Figure 9B This is a diagram illustrating the process flow (part 6) according to the first embodiment. (See reference) Figure 9A The DMA circuit 180 accesses DRAM 20 according to instructions from CPU 110 and transfers AI model data 23 stored in DRAM 20 to AI accelerator 140. AI accelerator 140 constructs layer A2 of the AI ​​model based on AI model data 23. Furthermore, the DMA circuit 180 accesses DRAM 20 according to instructions from CPU 110 and transfers decompression program 22 corresponding to compression program 21 stored in DRAM 20 to dynamically reconfigurable circuit 120. Dynamically reconfigurable circuit 120 constructs decompression circuitry based on decompression program 22. (Reference) Figure 9B After the compressed data of feature D2 is stored in DRAM 20, at time T4, DMA circuit 180 accesses DRAM 20 according to instructions from CPU 110 and transfers AI model data 23 stored in DRAM 20 to AI accelerator 140. AI accelerator 140 constructs layer A2 of the AI ​​model based on AI model data 23. The illustration shows DMA circuit 180 transferring decompression program 22 stored in DRAM 20 to dynamically reconfigurable circuit 120 according to instructions from CPU 110 and constructing decompression circuitry based on decompression program 22.

[0057] Reference Figure 3 The MPU 100 then transfers the compressed data stored in the DRAM 20, which acts as external memory, to the dynamically reconfigurable circuit 120 (step S38). Subsequently, the MPU 100 performs decompression processing in the dynamically reconfigurable circuit 120 (step S40). Then, the MPU 100 transfers the decompressed feature D2 from the dynamically reconfigurable circuit 120 to the shared buffer 130 (step S42).

[0058] Figure 10A and Figure 10B This is a diagram illustrating the process flow (part 7) according to the first embodiment. (See reference) Figure 10A The dynamically reconfigurable circuitry 120, for example, decompresses compressed data according to instructions from the CPU 110 and transfers the decompressed data to the shared buffer 130. (See reference...) Figure 10B The diagram illustrates the situation at time T5, where the dynamically reconfigurable circuit 120 decompresses the compressed data, and the decompressed data of feature D2 is stored in the shared buffer 130. Note that the dynamically reconfigurable circuit 120 can decompress the compressed data according to a pre-read program without going through the CPU 110, and transfer the decompressed data to the shared buffer 130.

[0059] Reference Figure 3 MPU 100 then transfers the decompressed feature D2 from shared buffer 130 to AI accelerator 140 (step S44).

[0060] Subsequently, MPU 100 performs processing based on layer A2 of the AI ​​model (step S46). Afterward, processing similar to that described in step S26 is performed.

[0061] Figure 11A and Figure 11B This is a diagram illustrating the process flow (part 8) according to the first embodiment. (See reference) Figure 11A The shared buffer 130 transmits the data of feature D2 to the AI ​​accelerator 140 via a dedicated bus 170. The AI ​​accelerator 140 follows a procedure that performs a product sum operation on the data of feature D2 (which is the input data) multiplied by weights, performs activation operations on the result, and outputs the computation result. Then, the AI ​​accelerator 140 transmits the data of feature D3, which is the computation result, to the shared buffer 130. (See reference...) Figure 11B The diagram illustrates a series of processes performed by the AI ​​accelerator 140 on layer A1 based on the AI ​​model at time T6.

[0062] Figure 12A and Figure 12B This is a diagram illustrating the process flow (part 9) according to the first embodiment. (See reference) Figure 12ADuring processing between the shared buffer 130 and the AI ​​accelerator 140, the DMA circuit 180 accesses the DRAM 20 according to instructions from the CPU 110 and transfers the compression program 21 stored in the DRAM 20 to the dynamically reconfigurable circuit 120. The dynamically reconfigurable circuit 120 constructs a compression circuit based on the compression program 21. (See reference...) Figure 12B The illustration shows that at time T7, the DMA circuit 180 transfers the compression program 21 stored in the DRAM 20 to the dynamically reconfigurable circuit 120, and constructs the compression circuit according to the compression program 21.

[0063] Figure 13A and Figure 13B This is a diagram illustrating the process flow (part 10) according to the first embodiment. (See reference) Figure 13A Feature D3 is transferred from shared buffer 130 to dynamically reconfigurable circuitry 120. Dynamically reconfigurable circuitry 120 operates as a compression circuit and stores compressed data of feature D3 in DRAM 20 via DMA circuitry 180. (See reference) Figure 13B The illustration shows that at time T8 after the processing of AI accelerator 140, the dynamically reconfigurable circuit 120 performs compression processing and transfers the compressed data to DRAM 20 via DMA circuit 180.

[0064] Figure 14 This is a diagram illustrating an example of compression processing performed by the dynamically reconfigurable circuitry 120 according to a first embodiment. For example, sparse data compression will be described. (See reference...) Figure 14 As an example, a scheme for compressing data is illustrated by breaking down the data group input to the shared buffer 130 into 8-bit units and transmitting code data indicating the location of 0 instead of the value of 0. Conversely, a scheme for decompressing compressed data based on encoded data is illustrated. Therefore, the amount of data transmitted can be reduced.

[0065] Figure 15A and Figure 15B This is a diagram illustrating another example of the compression process performed by the dynamically reconfigurable circuitry 120 according to the first embodiment. As an example, bit-packed compression is described. Reference Figure 15A This illustration shows the case where data falls within 9 bits as a data distribution. In this case, 16 bits are used for computational processing. Since the effective bits are 9, 7 bits are removed, and 9 bits of data are transferred with DRAM 20. Therefore, the amount of data transferred can be reduced. Conversely, in the case of decompression, where decompression is performed by the dynamically reconfigurable circuitry 120, 16 bits can be output by formally adding 7 bits to the 9-bit data.

[0066] The compression and decompression processes described above are examples, and the invention is not limited thereto. Processes such as run-length encoding and Huffman coding can be used.

[0067] Figure 16A and Figure 16B This is a diagram illustrating the processing time of the information processing system 1 according to the comparative example and the first embodiment. (Reference) Figure 16A The diagram illustrates the processing time of an information processing system according to a comparative example. In the information processing system according to the comparative example, each unit is connected via a shared bus, and no dedicated bus 160 is provided between the shared buffer 130 and the dynamically reconfigurable circuitry 120, nor is a dedicated bus 170 provided between the shared buffer 130 and the AI ​​accelerator 140. Here, data transfer (read) refers to the process of reading data from DRAM and transferring the data to the AI ​​accelerator. Data transfer (write) refers to the process of transferring data from the AI ​​accelerator to DRAM for writing. In this configuration, since only the shared bus is used for data transfer, a considerable amount of time may be required for data transfer.

[0068] The information processing system 1 according to the first embodiment has a configuration of a dedicated bus 160 disposed between the shared buffer 130 and the dynamically reconfigurable circuit 120, and a dedicated bus 170 disposed between the shared buffer 130 and the AI ​​accelerator 140. Therefore, the time required for data transmission using the shared buffer can be greatly reduced.

[0069] The first data transfer (read) refers to the processing used to read data from DRAM 20 and transfer the data to AI accelerator 140. Since the first data is the data before compression, the data transfer may take some time. On the other hand, information about the processed data of AI accelerator 140 is transmitted to dynamic reconfigurable circuit 120 via dedicated buses 160 and 170, compressed by dynamic reconfigurable circuit 120, and the compressed data is written to DRAM 20. Furthermore, since the amount of compressed data stored in DRAM 20 is small, the time to transmit the compressed data to dynamic reconfigurable circuit 120 is also shortened. Since the data decompressed by dynamic reconfigurable circuit 120 is transmitted to AI accelerator 140 via dedicated buses 160 and 170, it is possible to start AI model-based data processing earlier. Therefore, the information processing system 1 according to this disclosure can perform high-speed data processing.

[0070] In this example, for instance, the DMA circuit 180 is described as accessing DRAM 20 and performing various operations according to instructions from CPU 110, but the invention is not limited thereto. For example, the Dynamically Reconfigurable Circuit (DRP) begins operation by loading a program stored in DRAM 20 according to instructions from CPU 110, but the execution process utilizing DMA circuit 180 can be pre-configured in the program. For example, the Dynamically Reconfigurable Circuit (DRP) can issue instructions directly to DMA circuit 180 without going through CPU 110. Furthermore, the AI ​​accelerator 140 begins operation by loading a program stored in DRAM 20 according to instructions from CPU 110, but the execution process utilizing DMA circuit 180 can be pre-configured in the program. For example, the AI ​​accelerator 140 can issue instructions directly to DMA circuit 180 without going through CPU 110. The following also apply.

[0071] Second Embodiment

[0072] Figure 17 This is a block diagram illustrating the hardware configuration of the information processing system 1# according to the second embodiment. (See reference) Figure 17 The difference in information processing system 1# is that DRAM 20 is replaced with DRAM 20#. DRAM 20# stores the compressed AI model data 23# of AI accelerator 140.

[0073] In this configuration, DMA circuit 180 accesses DRAM 20# according to instructions from CPU 110 and transfers the compressed AI model data 23# stored in DRAM 20# to dynamic reconfigurable circuit 120. Dynamic reconfigurable circuit 120 decompresses the compressed AI model data 23# and transfers it to AI accelerator 140 via shared buffer 130. Since the data transferred from DRAM 20# to dynamic reconfigurable circuit 120 is compressed data, the transfer time can be shortened. Furthermore, the AI ​​model data 23# decompressed by dynamic reconfigurable circuit 120 is transferred to AI accelerator 140 using dedicated buses 160 and 170. Therefore, AI accelerator 140 can build AI model layers earlier based on the decompressed AI model data 23#.

[0074] Third Embodiment

[0075] Figure 18 This is a block diagram illustrating the hardware configuration of the information processing system 1A according to a third embodiment. (See reference) Figure 18The difference in information processing system 1A is that DRAM 20 is replaced by DRAM 20A. DRAM 20A stores compression program 21#. Compression program 21# incorporates both the activation function processing function and the compression circuit function in dynamically reconfigurable circuit 120. Specifically, dynamically reconfigurable circuit 120 performs compression processing on data processed by the activation function.

[0076] In this configuration, DMA circuit 180 accesses DRAM 20A according to instructions from CPU 110 and transmits compression program 21# stored in DRAM 20A to dynamically reconfigurable circuit 120. Dynamically reconfigurable circuit 120 constructs activation function processing circuitry and compression circuitry based on compression program 21#. For example, dynamically reconfigurable circuit 120 performs Modified Linear Unit (ReLU) processing as an activation function on data transferred from shared buffer 130 and compresses the processed data. ReLU is a function whose output value is always 0 when the input value is 0 or less, and whose output value is the same as the input value when the input value is greater than 0.

[0077] By utilizing processing circuitry other than compression circuitry to construct and combine dynamically reconfigurable circuitry 120, it is possible to further increase overall processing speed.

[0078] This example describes the combination of activation function processing and compression processing, but the invention is not limited thereto; compression processing can be performed in combination with other processing.

[0079] Fourth embodiment

[0080] Figure 19 This is a flowchart illustrating the computational processing operations of deep learning using the AI ​​accelerator 140 according to the fourth embodiment. The illustration shows... Figure 2 The flowchart described in the document is similar to the one in the document. Here, an example of the distribution of the calculated features D2 to D4 is illustrated.

[0081] Specifically, the data for feature D2 has a frequency that peaks at 0 and decreases as the value increases. Furthermore, the data for feature D3 has a frequency that increases as the value decreases from 0. Additionally, the data for feature D4 has a frequency that decreases uniformly as the value moves away from 0.

[0082] As shown in the distribution, the data distribution configuration varies depending on the features. That is, the appropriate compression scheme also varies depending on the data distribution. For example, compression code E1 has a high compression ratio for data with feature D2. Furthermore, compression code E2 has a high compression ratio for data with feature D3. Additionally, compression code E3 has a high compression ratio for data with feature D4.

[0083] Figure 20This is a diagram illustrating the hardware configuration of the information processing system 1B according to the fourth embodiment. (See reference) Figure 20 The difference between information processing system 1B and information processing system 1 is that DRAM 20 is replaced by DRAM 20B, and MPU 100 is replaced by MPU 100B. Compared to DRAM 20, DRAM 20B stores multiple types of compression and decompression programs. Specifically, it stores compression programs 21A and 21B that enable the dynamically reconfigurable circuitry 120 to act as a compression circuit, and decompression programs 22A and 22B that enable the dynamically reconfigurable circuitry to act as a decompression circuit. Note that the invention is not limited to this; additional types of compression and decompression programs may be stored.

[0084] The MPU 100B differs from the MPU 100 in that it also includes a feature analysis circuit 190. Other configurations and references... Figure 1 The configurations described are the same, and their detailed descriptions will not be repeated.

[0085] Feature analysis circuit 190 analyzes the features of the computation results of AI accelerator 140 stored in shared buffer 130. Specifically, as shown in reference... Figure 19 The feature analysis circuit analyzes the data distribution of the features and outputs information about the appropriate compression code as the analysis result to the CPU 110.

[0086] CPU 110 issues instructions to DMA circuit 180 based on, for example, compression code information from feature analysis circuit 190. Specifically, DMA circuit 180 accesses DRAM 20B according to the instructions of CPU 110 and transmits the best compression program among multiple types of compression programs stored in DRAM 20B to dynamic reconfigurable circuit 120. For example, the best compression program is selected from compression programs 21A and 21B stored in DRAM 20B and transmitted to dynamic reconfigurable circuit 120. For example, compression program 21A is selected and transmitted to dynamic reconfigurable circuit 120. Similarly, DMA circuit 180 accesses DRAM 20B according to the instructions of CPU 110 and transmits the best decompression program among multiple types of decompression programs stored in DRAM 20B to dynamic reconfigurable circuit 120. For example, the best decompression program is selected from decompression programs 22A and 22B stored in DRAM 20B and transmitted to dynamic reconfigurable circuit 120. For example, decompression program 22A is selected and transmitted to dynamically reconfigurable circuit 120.

[0087] In this example, for instance, the DMA circuit 180 is described as accessing the DRAM 20B according to instructions from the CPU 110, but the invention is not limited thereto. For example, the feature analysis circuit 190 can access the DMA circuit 180 without going through the CPU 110 based on information about the compression code from a pre-read program, and the DMA circuit 180 can transfer the best compression program among multiple types of compression programs stored in the DRAM 20B to the dynamically reconfigurable circuit 120.

[0088] Figure 21 This is a flowchart illustrating the processing of the MPU 100 according to the fourth embodiment. (Reference) Figure 21 The flowchart of the fourth embodiment and Figure 3 The difference in the flowchart is the addition of step S27, and the replacement of steps S30 and S36 with steps S30# and S36#. Other configurations and references. Figure 3 The configurations described are similar, and their detailed descriptions will not be repeated.

[0089] In step S26, after the computation results of the AI ​​accelerator 140 are stored in the shared buffer 130, the MPU 100 analyzes feature D2 (step S27). Specifically, the feature analysis circuit 190 analyzes the features of the computation results of the AI ​​accelerator 140 stored in the shared buffer 130. Specifically, as referenced... Figure 19 The feature analysis circuit 190 analyzes the data distribution of the features and outputs information about the appropriate compression code as the analysis result to the CPU 110.

[0090] Subsequently, MPU 100 constructs a compression circuit in the dynamically reconfigurable circuitry (step S30#). Specifically, CPU 110 issues an instruction to DMA circuit 180 based on information about the compression code from feature analysis circuit 190. DMA circuit 180 accesses DRAM 20B according to the instruction from CPU 110, selects the optimal compression program from compression programs 21A and 21B stored in DRAM 20B, and transfers the selected compression program to the dynamically reconfigurable circuitry 120. For example, suppose compression program 21A is selected. Dynamically reconfigurable circuitry 120 constructs a compression circuit based on compression program 21A.

[0091] Subsequently, MPU 100 performs compression processing on the data of feature D2 in the dynamically reconfigurable circuit 120 (step S32). Then, MPU 100 transfers the compressed data to DRAM 20 (step S34). Next, MPU 100 constructs layer A2 of the AI ​​model (step S35). Then, MPU 100 constructs the decompression circuit of the dynamically reconfigurable circuit 120 (step S36). CPU 110 issues instructions to DMA circuit 180 based on information about the compressed code from feature analysis circuit 190. DMA circuit 180 accesses DRAM 20B according to the instructions from CPU 110, selects the optimal decompression program from decompression programs 22A and 22B stored in DRAM 20B, and transfers the selected decompression program to the dynamically reconfigurable circuit 120. For example, assume that decompression program 22A corresponding to compression program 21A is selected. The dynamically reconfigurable circuit 120 constructs the decompression circuit based on decompression program 22A.

[0092] Since the subsequent processing is basically the same as the reference Figure 3 The processing described is similar, so its detailed description will not be repeated.

[0093] Using this configuration, it is possible to construct compression and decompression circuits in the dynamically reconfigurable circuit 120 that are best suited to the calculated characteristics, and it is possible to suppress the amount of data transmitted and further accelerate the entire process.

[0094] Although the present disclosure has been specifically described above based on embodiments, the present disclosure is not limited to these embodiments and various modifications can be made without departing from the spirit of the present disclosure.

Claims

1. An information processing device, comprising: A dynamically reconfigurable processor, which is capable of dynamically reconfiguring the processing content; An accelerator, configured to accelerate the inference of an AI model; A shared buffer is disposed between the dynamically reconfigurable processor and the accelerator, and is connected to the dynamically reconfigurable processor via a dedicated first bus and to the accelerator via a dedicated second bus, respectively. A shared bus is connected to the dynamically reconfigurable processor, the accelerator, and the shared buffer; as well as A transmission circuit, which is connected to an external memory and is capable of transmitting data using the shared bus. The calculation results of the accelerator are stored in the shared buffer via the second bus. The dynamically reconfigurable processor receives the computation results of the accelerator stored in the shared buffer via the first bus, and compresses the received computation results. The transmission circuit transmits compressed data via the shared bus for storage in the external memory.

2. The information processing device according to claim 1, The external memory includes a compression program and a decompression program. The compression program is used to reconfigure the dynamically reconfigurable processor as a compression circuit for compressing input data, and the decompression program is used to reconfigure the dynamically reconfigurable processor as a decompression circuit for decompressing input data. in, After being reconfigured into the decompression circuit according to the decompression procedure, the dynamically reconfigurable processor receives input of the compressed data stored in the external memory, decompresses the compressed data, and transmits the decompressed data to the accelerator via the shared buffer. Wherein, after being reconfigured as the compression circuit according to the compression program, the dynamically reconfigurable processor receives the computation results of the accelerator via the shared buffer and compresses the computation results.

3. The information processing device according to claim 1, The dynamically reconfigurable processor transmits the compressed data via burst transfer through the shared bus for storage in the external memory.

4. The information processing device according to claim 1, The dynamically reconfigurable processor receives input of the compressed data from the external memory via burst transfer through the shared bus and decompresses the compressed data, and transmits the decompressed data to the shared buffer via the first bus.

5. The information processing device according to claim 1, The external memory includes multiple compression programs and multiple decompression programs. The compression programs are used to reconfigure the dynamically reconfigurable processor corresponding to each of the multiple AI models as a compression circuit for compressing input data, and the decompression programs are used to reconfigure the dynamically reconfigurable processor as a decompression circuit for decompressing input data. in, After being reconfigured into the decompression circuit according to the decompression procedure corresponding to the AI ​​model, the dynamically reconfigurable processor receives input of the compressed data stored in the external memory, decompresses the compressed data, and transmits the decompressed data to the accelerator via the shared buffer. The dynamically reconfigurable processor, after being reconfigured as the compression circuit according to the compression program corresponding to the AI ​​model, receives the computation results of the accelerator via the shared buffer and compresses the computation results.

6. The information processing device according to claim 1, The external memory stores compressed weight data used to construct the AI ​​model of the accelerator. in, After being reconfigured into the decompression circuit according to the decompression procedure, the dynamically reconfigurable processor receives input of the compressed weight data stored in the external memory, decompresses the compressed weight data, and transmits the decompressed weight data to the accelerator via the shared buffer. The accelerator constructs the AI ​​model based on the weight data.

7. The information processing device according to claim 1, The compression program is a program for reconfiguring the dynamically reconfigurable processor into a compression circuit that compresses the input data after performing activation function processing on the input data. in, After being reconfigured as the compression circuit according to the compression program, the dynamically reconfigurable processor receives the calculation results of the accelerator via the shared buffer and compresses the data to which the activation function has been applied, and transmits the compressed data via the shared bus for storage in the external memory.

8. The information processing device according to claim 1, The external memory includes multiple compression programs and multiple decompression programs. The compression programs are used to reconfigure the dynamically reconfigurable processor as a compression circuit for compressing input data, and the decompression programs are used to reconfigure the dynamically reconfigurable processor as a decompression circuit for decompressing input data. The information processing device further includes an analysis unit configured to analyze features of the computation results of the accelerator stored in the shared buffer. in, After the dynamically reconfigurable processor is reconfigured as the compression circuit from the plurality of compression programs selected based on the analysis results of the analysis unit, it receives the computation results of the accelerator via the shared buffer and compresses the computation results. The dynamically reconfigurable processor, after being reconfigured as the decompression circuit from the plurality of decompression programs selected based on the analysis results of the analysis unit, receives input of the compressed data stored in the external memory and decompresses the compressed data, and transmits the decompressed data to the accelerator via the shared buffer.

9. An information processing system, comprising: A dynamically reconfigurable processor, which is capable of dynamically reconfiguring the processing content; An accelerator, configured to accelerate the inference of an AI model; A shared buffer is disposed between the dynamically reconfigurable processor and the accelerator, and is connected to the dynamically reconfigurable processor via a dedicated first bus and to the accelerator via a dedicated second bus, respectively. A shared bus is connected to the dynamically reconfigurable processor, the accelerator, and the shared buffer; as well as A transmission circuit, which is connected to an external memory and is capable of transmitting data using the shared bus. The calculation results of the accelerator are stored in the shared buffer via the second bus. The dynamically reconfigurable processor receives the computation results of the accelerator stored in the shared buffer via the first bus, and compresses the received computation results. The transmission circuit transmits compressed data via the shared bus for storage in the external memory.

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