Remapping control circuit, chip and electronic device

Abstract

The remapping control circuit, the chip and the electronic equipment provided by the embodiments of the present application have the following advantages. The remapping control module is configured to remap the initial address of the mapping block and generate a notification signal when initiating the configuration of the mapping block. The flash control module is configured to determine whether the initial address falls into the one-time programmable area by using the erase-write comparison logic of the one-time programmable area to generate a comparison result signal when the notification signal is received, so that the remapping control circuit does not need to set the judgment logic for each mapping block. On this basis, the remapping control module is further configured to configure the mapping block according to the comparison result signal, so that the remapping control circuit can effectively reduce the area overhead of the comparison function while realizing the area access protection, thereby reducing the production cost of the chip provided with the remapping control circuit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a remapping control circuit, chip, and electronic device. Background Technology

[0002] In integrated circuit memory control applications, overlay controllers are typically used to remap accesses to NVM (Non-Volatile Memory) to on-chip memory to support system calibration development. However, when the system needs to restrict remapping operations to OTP (One-Time Programmable) regions, and the remapping regions are divided into mapping blocks, the hardware area overhead for implementing this comparison function becomes excessive because separate judgment logic needs to be set for the start address of each mapping block. Therefore, a remapping control circuit that can reduce the hardware area overhead of implementing the comparison function is needed. Summary of the Invention

[0003] In view of the above problems, embodiments of this application provide a remapping control circuit, chip, and electronic device to solve the above technical problems.

[0004] In a first aspect, embodiments of this application provide a remapping control circuit, including a remapping control module and a flash memory control module. The remapping control module is used to remap the initial address of a mapping block and generate a notification signal when configuring the mapping block to enable. The flash memory control module includes a one-time programmable region protection unit. Upon receiving the notification signal, the one-time programmable region protection unit is used to multiplex the erase / write comparison logic of the one-time programmable region to determine whether the initial address falls within the one-time programmable region, thereby generating a comparison result signal. The remapping control module is further used to configure the mapping block to enable based on the comparison result signal.

[0005] Secondly, embodiments of this application also provide a chip including the aforementioned remapping control circuit.

[0006] Thirdly, embodiments of this application also provide an electronic device, including a device body and a remapping control circuit as described above disposed on the device body, or including a device body and a chip as described above disposed on the device body.

[0007] The remapping control circuit, chip, and electronic device provided in this application embodiment remap the initial address of the mapping block and generate a notification signal when configuring the mapping block enable. When the flash memory control module receives the notification signal, it reuses the erase / write comparison logic of the one-time programmable area to determine whether the initial address falls into the one-time programmable area to generate a comparison result signal. This eliminates the need for the remapping control circuit to set up judgment logic for each mapping block separately. Furthermore, the remapping control module is also used to configure the mapping block enable according to the comparison result signal. This enables the remapping control circuit to effectively reduce the area overhead of implementing the comparison function while achieving area access protection, thereby reducing the manufacturing cost of the chip equipped with the remapping control circuit.

[0008] These or other aspects of this application will become more apparent from the description of the following embodiments. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of an architecture of the remapping control circuit provided in an embodiment of this application is shown.

[0011] Figure 2 This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0012] Figure 3 This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0013] Figure 4 This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0014] Figure 5 This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0015] Figure 6 This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0016] Figure 7 The diagram shows the timing of the remapping control circuit provided in the embodiment of this application when performing serial comparison of multiple mapping blocks.

[0017] Figure 8This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0018] Figure 9 This illustration shows another schematic diagram of the remapping control circuit provided in an embodiment of this application.

[0019] Figure 10 A schematic diagram of the architecture of a chip provided in an embodiment of this application is shown. Detailed Implementation

[0020] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only used to explain this application, and should not be construed as limiting this application.

[0021] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0022] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0023] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0024] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0025] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0026] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0027] In some applications, the overlay controller supports calibration development by providing remapping functionality, routing logical non-volatile memory (NVM) accesses to on-chip system RAM (Random Access Memory). Furthermore, the overlay controller supports a configurable function to map NVM accesses to on-chip calibration RAM. The overlay controller listens for NVM read interfaces, and when an enabled mapping region hit is detected, it generates an overlay RAM read request at the corresponding physical RAM address. The system synchronizes the data read from RAM to ensure timing consistency between NVM and overlay accesses.

[0028] In specific security control applications of integrated circuits, it is often necessary to restrict the remapping controller OVERLAY_CTRLx from performing remapping operations on one-time programmable OTP regions to prevent unauthorized overlay access. However, the existing OVERLAY_CTRLx remapping controllers typically configure the remapping regions according to overlay blocks. Each overlay block requires separate hardware configuration registers for storing the 32-bit logical start address, the 32-bit physical start address, the block size configuration register, and the corresponding OTP judgment logic.

[0029] Because the OTP judgment logic requires a separate physical comparator for each mapped block when performing out-of-bounds checks on the logical address of each mapped block and the accumulated boundary between the logical address and the block size, it leads to a large amount of redundant stacking of hardware comparison logic, resulting in excessive hardware area overhead for this comparison judgment function. Therefore, a remapping control circuit is needed that can both ensure the safety of multi-block remapping access and effectively reduce the hardware area overhead of implementing the comparison function.

[0030] To address this, this application provides a remapping control circuit, including a remapping control module and a flash memory control module. The remapping control module remaps the initial address of a mapping block and generates a notification signal when enabling the mapping block. Upon receiving the notification signal, the flash memory control module reuses the erase / write comparison logic of a one-time programmable region to determine whether the initial address falls within the one-time programmable region, generating a comparison result signal. This eliminates the need for the remapping control circuit to set separate judgment logic for each mapping block. Furthermore, the remapping control module also configures the mapping block enable based on the comparison result signal, enabling the remapping control circuit to effectively reduce the area overhead of the comparison function while implementing region access protection, thereby reducing the production cost of the chip equipped with the remapping control circuit.

[0031] First, refer to Figure 1 , Figure 1 The diagram shows an architecture of a remapping control circuit provided in an embodiment of this application. The remapping control circuit includes a remapping control module OVERLAY_CTRLx and a flash memory control module FMCx.

[0032] In one embodiment, the remapping control module OVERLAY_CTRLx is used to remap the initial address ovly_blk_addr of the overlay block and generate a notification signal when enabling the configuration of the overlay block is initiated. Specifically, the remapping control module OVERLAY_CTRLx can be a remapping controller. By providing remapping functionality, the remapping controller can map the access routes of the logical non-volatile memory (NVM) to the on-chip memory (overlay RAM), and the configuration of this remapping region can be divided according to the overlay block.

[0033] When the overlay control module OVERLAY_CTRLx is enabled, it generates a corresponding notification signal ovly_blk_addr_vld and sends the notification signal ovly_blk_addr_vld and the initial address ovly_blk_addr corresponding to the overlay block to the flash memory control module FMCx.

[0034] In one embodiment, the flash memory control module FMCx includes a one-time programmable region protection unit PF_OTP. The one-time programmable region protection unit PF_OTP is used to determine whether the initial address ovly_blk_addr falls into the one-time programmable region when the notification signal ovly_blk_addr_vld is received, by multiplexing the erase / write comparison logic PF_OTP_EP_PROT of the one-time programmable region, so as to generate a comparison result signal ovly_baddr_cmp_result. Specifically, the flash memory control module FMCx can be a flash memory controller. Its internal one-time programmable area protection unit PF_OTP is connected to the remapping control module OVERLAY_CTRLx. When the flash memory control module FMCx receives the notification signal ovly_blk_addr_vld issued by the remapping control module OVERLAY_CTRLx, it reuses the internal erase / write comparison logic PF_OTP_EP_PROT to check whether the initial address ovly_blk_addr of the received overlay block falls within the one-time programmable area, i.e., the PFx_OTP protection area. Based on the address comparison, it generates a corresponding comparison result signal ovly_baddr_cmp_result and then feeds back the comparison result signal ovly_baddr_cmp_result to the remapping control module OVERLAY_CTRLx.

[0035] In one embodiment, the remapping control module OVERLAY_CTRLx is also used to configure the mapping block enable based on the comparison result signal ovly_baddr_cmp_result. Specifically, after receiving the comparison result signal ovly_baddr_cmp_result from the flash memory control module FMCx, the remapping control module OVERLAY_CTRLx determines the configuration status of the mapping block based on the address validity indicated by the comparison result signal ovly_baddr_cmp_result. For example, if the comparison result signal ovly_baddr_cmp_result indicates that the initial address ovly_blk_addr illegally falls into the one-time programmable region, i.e., falls into the PFx_OTP protection region, then the remapping control module OVERLAY_CTRLx considers this configuration illegal and ineffective, thereby restricting and protecting the remapping operation of a specific region. If the comparison result signal ovly_baddr_cmp_result indicates that the initial address ovly_blk_addr does not fall into the one-time programmable region, i.e., does not fall into the PFx_OTP protection region, then the remapping control module OVERLAY_CTRLx considers this configuration valid and enables the corresponding mapping block.

[0036] The remapping control circuit provided in this embodiment of the application, when the remapping control module OVERLAY_CTRLx initiates the configuration of the overlay block, sends the initial address ovly_blk_addr and the notification signal ovly_blk_addr_vld to the flash memory control module FMCx. The flash memory control module FMCx reuses the existing one-time programmable area erase / write protection comparison logic PF_OTP_EP_PROT to perform address validity checks and returns the comparison result signal ovly_baddr_cmp_result to the remapping control module OVERLAY_CTRLx. Based on this, the remapping control module OVERLAY_CTRLx determines whether the current overlay block configuration is effective according to the comparison result signal ovly_baddr_cmp_result. Thus, by utilizing the interaction mechanism of reused judgment logic, it is not necessary to configure the corresponding erase / write protection comparison logic separately for each overlay block, thereby effectively reducing the hardware area overhead of implementing the comparison function.

[0037] In one embodiment, reference is made to Figure 2 , Figure 2This illustration shows another architecture diagram of the remapping control circuit provided in an embodiment of this application. The remapping control module OVERLAY_CTRLx includes multiple overlay blocks. When the configuration of multiple overlay blocks is initiated, the remapping control module OVERLAY_CTRLx is used to send the initial address ovly_blk_addr corresponding to the multiple overlay blocks to the flash memory control module FMCx.

[0038] Specifically, the remapping region configuration of the OVERLAY_CTRLx remapping control module is divided according to multiple overlay blocks. For example, the OVERLAY_CTRLx remapping control module includes x+1 overlay blocks. When the configuration of the OVERLAY_CTRLx remapping control module's overlay block region is enabled, the OVERLAY_CTRLx remapping control module sends the initial addresses corresponding to these multiple overlay blocks, such as the initial address ovly_blk_addr0 corresponding to overlay block0, ..., and the initial address ovly_blk_addrx corresponding to overlay blockx, to the one-time programmable region protection unit PF_OTP of the flash memory control module FMCx. Thus, the existing one-time programmable region erase / write protection comparison logic PF_OTP_EP_PROT at the flash memory control module FMCx performs address validity checks on these initial addresses ovly_blk_addr to feed back the comparison result signal ovly_baddr_cmp_result for each overlay block, thereby reducing the area overhead of the comparison logic function and thus reducing chip manufacturing costs.

[0039] In one embodiment, the initial address ovly_blk_addr of the overlay block includes a start address start_addr and an end address end_addr. The remapping control module OVERLAY_CTRLx is used to send the start address start_addr and end address end_addr of the corresponding initial address ovly_blk_addr to the one-time programmable area protection unit PF_OTP of the flash memory control module FMCx within one clock cycle.

[0040] Specifically, the initial address ovly_blk_addr of each overlay block is divided into a start address (start_addr) and an end address (end_addr). When the remapping control module OVERLAY_CTRLx enables the OverlayBlock region and serially sends the initial addresses ovly_blk_addr of multiple overlay blocks, the OVERLAY_CTRLx sends the 64-bit start address (start_addr) and 64-bit end address (end_addr) of each overlay block to the one-time programmable region protection unit PF_OTP of the flash memory control module FMCx within the same clock cycle. This allows the one-time programmable region protection unit PF_OTP to quickly obtain the complete address boundary of the overlay block to be verified. Thus, when using a single erase / write comparison logic PF_OTP_EP_PROT for comparison, the efficiency of range-based valid comparison of multiple overlay blocks is improved while reducing the hardware area overhead of implementing the comparison function.

[0041] In one embodiment, reference is made to Figure 3 , Figure 3 This illustration shows another architecture diagram of the remapping control circuit provided in an embodiment of this application. The remapping control module OVERLAY_CTRLx includes an error status register, which contains error flags ovly_baddr_comp_result corresponding to each overlay block. When there is a comparison result signal ovly_baddr_cmp_result corresponding to the initial address ovly_blk_addr indicating that the initial address ovly_blk_addr falls into the one-time programmable region, the remapping control module OVERLAY_CTRLx is used to set the corresponding error flag ovly_baddr_comp_result. The setting of the error flag ovly_baddr_comp_result does not interrupt the comparison process between other initial addresses ovly_blk_addr and the one-time programmable region.

[0042] Specifically, the remapping control module OVERLAY_CTRLx is internally configured with an error status register. This error status register contains multiple error flags ovly_baddr_comp_result corresponding to each overlay block. For example, the error flag ovly_baddr0_comp_result corresponds to overlay block0, and the error flag ovly_baddrx_comp_result corresponds to overlay blockx. During the process of sequentially sending the initial addresses ovly_blk_addr corresponding to multiple overlay blocks to the flash memory control module FMCx for address validity checks, when the remapping control module OVERLAY_CTRLx receives the comparison result signal ovly_baddr_cmp_result from the flash memory control module FMCx indicating that the initial address ovly_blk_addr of the currently checked overlay block illegally falls into the one-time programmable area, i.e., the PFx_OTP protection area, the remapping control module OVERLAY_CTRLx considers this configuration illegal and ineffective, and simultaneously sets the error flag ovly_baddr_comp_result corresponding to the overlay block in the error status register to generate an error flag.

[0043] Furthermore, during the process of sending the initial addresses ovly_blk_addr of multiple overlay blocks to the one-time programmable area protection unit PF_OTP for address validity checks, even if an overlay block triggers the corresponding error flag ovly_baddr_comp_result, the setting of the error flag ovly_baddr_comp_result will not interrupt or terminate the validity check process of the initial addresses ovly_blk_addr of other overlay blocks and the queued addresses of the one-time programmable area. Thus, by setting an independent error flag ovly_baddr_comp_result corresponding to each overlay block in the overlay control module OVERLAY_CTRLx, effective protection of the one-time programmable area is achieved while ensuring the integrity of the serial verification process of multiple overlay blocks.

[0044] In one embodiment, reference is made to Figure 4 , Figure 4This illustration shows another architecture diagram of the remapping control circuit provided in an embodiment of this application. The remapping control module OVERLAY_CTRLx is also used to generate a busy flag signal crd_en_busy when initiating the configuration of multiple overlay blocks. The busy flag signal crd_en_busy is used to prevent the remapping control module OVERLAY_CTRLx from performing the clearing operation for the error flag bit ovly_baddr_comp_result and the configuration enabling operation for the overlay block.

[0045] Specifically, when the remapping control module OVERLAY_CTRLx enables the corresponding overlay block and sends the initial address ovly_blk_addr of the overlay block to the flash memory control module FMCx to initiate address comparison, it generates a busy flag signal crd_en_busy during the comparison process. This busy flag signal crd_en_busy is used to tell the host computer that the current remapping configuration of the overlay block is not yet effective, and the remapping control module OVERLAY_CTRLx is not allowed to perform configuration enabling operations on the overlay block, nor can the previously generated error flag ovly_baddr_comp_result be cleared. This restricts the external operation permissions during the address verification of the overlay block, preventing configuration modifications or accidental erasure of error states during the queuing verification of the one-time programmable area protection unit PF_OTP, thereby improving the reliability of the overlay block enabling.

[0046] In one embodiment, reference is made to Figure 5 , Figure 5 This illustration shows another architectural diagram of the remapping control circuit provided in this application embodiment. The remapping control module OVERLAY_CTRLx further includes a request generation unit. The request generation unit is used to generate a comparison request signal crd_en_start_req for the current overlay block based on the enable state wr_crd_en of each overlay block and the busy flag signal crd_en_busy of the preceding overlay block. The comparison request signal crd_en_start_req is used to initiate a comparison process between the initial address ovly_blk_addr of the current overlay block and the one-time programmable region. The preceding overlay block is the overlay block that is located before the current overlay block in the transmission order.

[0047] Specifically, the remapping control module OVERLAY_CTRLx also includes a request generation unit. When a mapping block is enabled, it triggers the generation of the enable state wr_crd_en corresponding to the overlay block. For example, the enable state wr_crd_enn corresponds to the nth overlay block n. When generating the request to initiate the current overlay block n, the request generation unit combines the enable state wr_crd_enn of the current overlay block n with the busy flag signals crd_en_busy of all other overlay blocks preceding the current overlay block n in the queue, i.e., the busy flag signals crd_en0_busy to crd_enn-1_busy of the preceding overlay blocks from overlay block 0 to overlay block n-1. When the busy flag signals crd_en0_busy to crd_enn-1_busy of blockn-1 are all in a non-busy state, it means that the logical expression ~(|crd_en_busy[x-1:0]) is satisfied. Combined with the pulse of the enable state wr_crd_enn of the current overlay blockn, a comparison request signal crd_enn_start_req is generated for the current overlay blockn. After this comparison request signal crd_enn_start_req is output to the one-time programmable area protection unit PF_OTP, the process of comparing the initial address ovly_blkn_addr of the current overlay blockn with the legality of the PFx_OTP protection area is formally initiated. This achieves serial queuing of the address verification process for multiple overlay blocks, ensuring timing stability when multiplexing comparison logic.

[0048] In one embodiment, the remapping control module OVERLAY_CTRLx is specifically used to sequentially send the initial addresses ovly_blk_addr corresponding to multiple overlay blocks to the flash memory control module FMCx in a serial manner.

[0049] Specifically, when enabling multiple overlay blocks, the remapping control module OVERLAY_CTRLx sends the initial addresses ovly_blk_addr corresponding to these multiple overlay blocks in a predetermined queuing order. For example, the initial address ovly_blk_addr0 corresponding to overlay block 0, ..., the initial address ovly_blk_addrx corresponding to overlay block x is sent serially to the one-time programmable area protection unit PF_OTP of the flash memory control module FMCx. Through this serial queuing mechanism, the flash memory control module FMCx can time-division multiplex the same set of one-time programmable area erase / write protection comparison logic PF_OTP_EP_PROT to process the validity check of the received initial addresses in sequence, and sequentially feed back the comparison result signal ovly_baddr_cmp_result for each overlay block. This reduces the hardware area overhead of the comparison function and lowers the chip manufacturing cost while implementing multi-block remapping access protection.

[0050] In one embodiment, reference is made to Figure 6 , Figure 6This illustration shows another architectural diagram of the remapping control circuit provided in an embodiment of this application. The remapping control module OVERLAY_CTRLx is used to restrict the remapping operation of the one-time programmable region (i.e., the PFx_OTP protected region). When configuring the overlay_block region of the overlay control module OVERLAY_CTRLx for enabling the mapping block, in order to reduce the area overhead of the hardware implementation, the scheme of this application reuses the erase / write comparison logic PF_OTP_EP_PROT of the one-time programmable region protection unit PF_OTP in the flash memory control module FMCx for address verification. The remapping control module OVERLAY_CTRLx initiates an address comparison, taking the start address start_addr and end address end_addr of each overlay_block as the initial address ovly_blk_addr, along with the notification signal ovly_blk_addr_vld. The data is transmitted serially to the flash memory control module FMCx. Further, after receiving the initial address ovly_blk_addr of each overlay block, the flash memory control module FMCx uses its internal erase / write protection comparison logic PF_OTP_EP_PROT to check whether the initial address ovly_blk_addr falls into the one-time programmable region, i.e., the PFx_OTP protection region. The comparison result is then fed back to the remapping control module OVERLAY_CTRLx through the result validity signal ovly_blk_addr_cmp_result_vld and the comparison result signal ovly_baddr_cmp_result.

[0051] During the process of enabling the corresponding mapped block and initiating a comparison with the flash memory control module FMCx, the remapping control module OVERLAY_CTRLx generates a busy flag signal crd_en_busy to indicate that the current software configuration is not yet effective. Under this busy flag, configuration enabling is not allowed, and error flags cannot be cleared. When the verification is complete, if the received comparison result signal ovly_baddr_cmp_result indicates that the initial address ovly_blk_addr falls within the one-time programmable region, the remapping control module OVERLAY_CTRLx considers this configuration illegal and ineffective, and simultaneously generates an error flag ovly_baddr_comp_result. This allows for queuing and verification by serially sending the addresses of multiple mapped blocks to an OTP comparison logic, effectively reducing circuit area overhead while achieving access protection.

[0052] Among them, AXIF is the AXI bus interface, which is the data bus channel through which the system master device initiates high-speed data read or access requests to the flash memory control module FMCx via the advanced extensible interface protocol; AHB_CFG is the AHB configuration bus interface, which is the control bus channel through which the system software layer enables and configures the internal registers of the remapping control module OVERLAY_CTRLx and the flash memory control module FMCx via the advanced high-performance bus protocol; UCFG_PF_OTP_CFG is the user protection configuration block, which is used to statically latch and provide the configuration unit with the specific address boundary parameters of the PF_OTP protected area to the one-time programmable area protection logic.

[0053] Reference Figure 7 , Figure 7 The diagram illustrates the timing of the remapping control circuit provided in this application when performing serial comparison of multiple mapping blocks. At label ①, when the software writes mapping block enable signals, such as wr_crd_en0 and wr_crd_en1, the corresponding temporary request signal crd_enx_start_req_tmp will be pulled high. Specifically, the comparison request signal crd_en0_start_req for the first mapping block overlay block 0 is directly pulled high by the pulse at label ①. For subsequent mapping blocks overlay block x, as shown in labels ④ and ⑦, the corresponding comparison request signal crd_enx_start_req is generated by its own temporary request signal crd_enx_start_req_tmp and the non-busy state of all preceding mapping blocks overlay blocks, i.e., the logical expression ~(|crd_en_busy[x-1:0]), thus ensuring that multiple mapping blocks strictly follow the order in initiating comparison requests.

[0054] Furthermore, as shown in labels ②, ⑤, and ⑧, corresponding to the rising edge of each comparison request signal crd_enx_start_req, the address valid signal ovly_baddr_vld output by the remapping control module OVERLAY_CTRLx is the OR logic output of all rising edge signals; and, within the same clock cycle, the remapping control module OVERLAY_CTRLx sends the corresponding overlay block, including the 64-bit start address start_addr and the 64-bit end address end_addr, to the flash memory control module FMCx for verification.

[0055] Subsequently, as shown in labels ③, ⑥, and ⑨, after the flash memory control module FMCx completes the address comparison of the current overlay block, the remapping control module OVERLAY_CTRLx clears the corresponding busy flag state by receiving the feedback comparison result signal ovly_baddr_comp_result, thereby releasing the current verification process from being occupied, and triggering and allowing the next overlay block in the waiting state to perform the comparison operation in sequence.

[0056] In some embodiments, the remapping control module OVERLAY_CTRLx needs to cooperate with the flash memory control module FMCx in hardware during system calibration development. When the client performs data calibration, the calibration data needs to be stored at a first specific logical address, such as PFx logical address 0x15xx, while the program code reads from a second specific logical address, such as PFx logical address 0x11xx. During calibration, when configuring the remapping control module OVERLAY_CTRLx through the calibration tool, the corresponding first specific logical address can be remapped to the on-chip calibration memory overlay LRAM to realize the actual operation of retrieving calibration data from the LRAM.

[0057] However, in actual hardware architectures, the flash memory control module (FMCx) typically includes a buffer unit to improve read performance, and this buffer unit caches data from the two different logical addresses simultaneously during operation. In the calibration data flow, when the calibration tool or software updates the calibration data in the remapped RAM area, if a cache similar to a D-cache exists in the read path, or if the data in the cache unit is not invalidated in time, if a subsequent read operation hits that cache unit, the hardware will not retrieve the latest calibration data from the underlying remapped RAM, resulting in the obtained read result still being the old data, which can easily lead to data inconsistency issues.

[0058] Based on this, in one embodiment, reference is made to Figure 8 , Figure 8This illustration shows another architecture diagram of the remapping control circuit provided in an embodiment of this application. The remapping control module OVERLAY_CTRLx further includes a consistency control unit, and the flash memory control module FMCx further includes a cache management unit. The consistency control unit is used to send a cache invalidation signal buffer_valid_clr_req to the cache management unit after the storage data associated with the overlay block is updated. The cache management unit is used to set the data validity flag Buffer valid in the cache unit Buffer within the flash memory control module FMCx to an invalid state according to the cache invalidation signal buffer_valid_clr_req.

[0059] Specifically, in data calibration and other processes, after the calibration tool or software updates the storage data (i.e., calibration data) associated with the overlay block in the OVERLAY_CTRLx remapping control module, the consistency control unit of the OVERLAY_CTRLx remapping control module triggers the generation of a buffer invalidation signal (buffer_valid_clr_req) by writing to the Overlay_Ctrl register, for example, by generating a pulse software clearing request. Then, this buffer invalidation signal (buffer_valid_clr_req) is sent to the cache management unit of the FMCx flash memory control module. Upon receiving the buffer invalidation signal (buffer_valid_clr_req), the cache management unit of the FMCx flash memory control module sets the data validity flag (Buffer valid) of the buffer units within the FMCx that support caching functions to an invalid state, i.e., clears the data validity flag (buffer valid).

[0060] In one embodiment, when the data validity flag bit Buffer valid of the buffer unit Buffer is set to invalid, the buffer management unit is also used to send a buffer invalid acknowledgment signal buffer_valid_clr_ack to the remapping control module OVERLAY_CTRLx.

[0061] Specifically, after clearing the data validity flag Buffer valid, the cache management unit of the flash memory control module FMCx replies with a cache invalidation acknowledgment signal buffer_valid_clr_ack to the remapping control module OVERLAY_CTRLx to complete the handshake confirmation. This avoids situations where a cache hit occurs but the latest data is not read from the remapped RAM, thereby solving the data consistency problem during the remapping access process and effectively improving the reliability of data access during the remapping access process.

[0062] In a data calibration application scenario, after the calibration tool initializes a certain mapping block and configures it to the enabled state, the calibration tool will usually perform multiple modification operations on the calibration data in the overlay LRAM associated with the overlay block. This repeated modification and updating of the data in the overlay memory area will continue until all the functional calibration operations corresponding to the overlay block are completed.

[0063] In one embodiment, reference is made to Figure 9 , Figure 9 This diagram illustrates another architecture of the remapping control circuit provided in this application embodiment. The system master control device initiates a system program flash read access to the flash memory control module FMCx via the system bus interface AXIFx. The flash memory control module FMCx is internally configured with an AXI protocol parsing module, a prefetch buffer, a buffer unit, and a multiplexer Ovly_Mux. Simultaneously, this circuit architecture also includes a remapping control module OVERLAY_CTRLx and the underlying program flash memory PFlash x, which are communicatively connected to the flash memory control module FMCx. The remapping control module OVERLAY_CTRLx is connected to the on-chip remapping memory OVLY_RAM via the internal interconnect network NIC_OVERLAY and NIC_RAM, respectively.

[0064] When a read operation occurs, the flash memory control module FMCx outputs the physical address pf_addr and the read enable signal pf_rd_en to the underlying program flash memory PFlash x to initiate a physical read. The underlying program flash memory PFlash x then sends back a data ready signal pf_data_rdy after the data is ready. During this period, the remapping control module OVERLAY_CTRLx outputs a remapping selection signal ovly_sel to the multiplexer Ovly_Mux of the flash memory control module FMCx based on the received system address and identity identifier signals MID / VMID sys_addr and the match status of the physical address pf_addr. The multiplexer Ovly_Mux then switches between the physical read data pf_rdata and the remapping data ovly_rdata based on this selection signal ovly_sel, and transmits the selected 256-bit data to the AXI protocol parsing module for return to the system master device.

[0065] In system calibration applications, customers typically store calibration data at a specific logical address, such as PFx logical address 0X15xx, while program code reads data from another logical address, such as PFx logical address 0X11xx. In this case, the prefetch buffer in the flash memory controller module FMCx only supports prefetching to logical address 0X11xx, but the cache unit buffer supports caching both logical addresses 0X11xx and 0X15xx. If the data cache unit buffer is not processed after the calibration data is updated, a cache hit may occur when the system master device reads address 0X15xx again, causing it to directly read the old calibration data from the buffer instead of fetching the latest data from the underlying updated LRAMx, thus leading to data inconsistency issues.

[0066] Therefore, in this application, after the calibration tool or software updates the calibration data in OVLY_RAM, the remapping control module OVERLAY_CTRLx sends a buffer invalidation request signal buffer_valid_clr_req to the flash memory control module FMCx by writing to registers or other means. Upon receiving the buffer invalidation request signal buffer_valid_clr_req, the flash memory control module FMCx sets the data validity flag Buffer valid corresponding to the buffer unit to an invalid state to clear the cached data. After the clearing operation is completed, it sends a buffer invalidation confirmation signal buffer_valid_clr_ack back to the remapping control module OVERLAY_CTRLx, thereby effectively ensuring the data consistency of the read path in the calibration process.

[0067] Additionally, refer to Figure 10 , Figure 10 This application illustrates an architecture diagram of a chip provided in an embodiment of the present application. The present application also provides a chip 200, which includes the aforementioned remapping control circuit. The chip 200 may be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. Since the chip 200 of this application possesses the remapping control circuit of the above embodiments, it has all the beneficial effects of the remapping control circuit in the above embodiments, and will not be repeated here.

[0068] In addition, this application also provides an electronic device, which includes a device body and a remapping control circuit or chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car infotainment screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. Since the electronic device of this application possesses the remapping control circuit or chip described in the above embodiments, it has all the beneficial effects of the remapping control circuit or chip described in the above embodiments, which will not be repeated here.

[0069] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different beneficial effects.

[0070] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any indirect modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A remapping control circuit, characterized in that, include: The remapping control module is used to remap the initial address of the mapping block and generate a notification signal when the configuration of the mapping block is initiated. The flash memory control module includes a one-time programmable area protection unit, which is used to determine whether the initial address falls within the one-time programmable area by reusing the erase / write comparison logic of the one-time programmable area when the notification signal is received, so as to generate a comparison result signal. The remapping control module is also used to configure the mapping block to be enabled based on the comparison result signal.

2. The remapping control circuit according to claim 1, characterized in that, The remapping control module includes multiple mapping blocks; when enabling multiple mapping blocks is initiated, the remapping control module is also used to send the initial addresses corresponding to the multiple mapping blocks to the flash memory control module.

3. The remapping control circuit according to claim 2, characterized in that, The initial address includes a start address and an end address. The remapping control module is also used to send the start address and the end address to the one-time programmable area protection unit of the flash memory control module within one clock cycle.

4. The remapping control circuit according to claim 2, characterized in that, The remapping control module includes an error status register, which contains error flag bits corresponding to each of the mapping blocks. When a comparison result signal corresponding to the initial address indicates that the initial address falls within the one-time programmable region, the remapping control module sets the corresponding error flag bit, and setting the error flag bit does not interrupt the comparison process between other initial addresses and the one-time programmable region.

5. The remapping control circuit according to claim 4, characterized in that, The remapping control module is also configured to generate a busy flag signal when initiating the configuration enable of multiple mapping blocks. The busy flag signal is used to prevent the remapping control module from performing the clearing operation for the error flag bit and the configuration enable operation for the mapping block.

6. The remapping control circuit according to claim 5, characterized in that, The remapping control module further includes a request generation unit, which is used to generate a comparison request signal for the current mapping block based on the enable state of each mapping block and the signal state of the busy flag signal of the preceding mapping block. The comparison request signal is used to initiate a comparison process between the initial address of the current mapping block and the one-time programmable region. The preceding mapping block is the mapping block that precedes the current mapping block in the transmission order.

7. The remapping control circuit according to claim 2, characterized in that, The initial addresses corresponding to the multiple mapping blocks are sequentially sent to the flash memory control module in a serial manner.

8. The remapping control circuit according to claim 1, characterized in that, The remapping control module further includes a consistency control unit, and the flash memory control module further includes a cache management unit. The consistency control unit is used to send a cache invalidation signal to the cache management unit after the storage data associated with the mapping block is updated; The cache management unit is used to set the data validity flag of the cache unit in the flash memory control module to an invalid state according to the cache invalid signal.

9. The remapping control circuit according to claim 8, characterized in that, When the data validity flag of the cache unit is invalid, the cache management unit is also used to send a cache invalidation confirmation signal to the remapping control module.

10. A chip, characterized in that, Includes the remapping control circuit as described in any one of claims 1 to 9.

11. An electronic device, characterized in that, It includes a device body and a remapping control circuit as described in any one of claims 1 to 9 disposed on the device body, or it includes a device body and a chip as described in claim 10 disposed on the device body.

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