Method and device for synchronous processing of asynchronous data of SPI slave

Abstract

The application discloses a kind of synchronous processing method and device of SPI slave machine asynchronous data, and it is related to integrated circuit technical field.The method keeps invalid in data preparation phase clock detection state machine setting flag, state machine detects SCK but does not generate setting response;After data preparation is completed, preparation completion flag is synchronized to the clock domain of state machine by cross-clock domain synchronizer, and enables setting flag after confirming effective;After enabling, state machine is normally set at the next group of effective SCK clock edge, and triggers data sending module to send the data prepared according to SPI protocol to host computer.The application separates and sequencizes the data preparation and sending trigger in timing, makes the sending starting point strictly align effective clock edge, fundamentally eliminates the frame header problem caused by cross-clock domain asynchronism without increasing pin, and improves communication reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a method and apparatus for synchronizing asynchronous data of an SPI slave device. Background Technology

[0002] The Serial Peripheral Interface (SPI) is a commonly used synchronous serial communication interface, with a master and a slave device communicating. The master generates a serial clock SCK, which is used to control the shifting and sampling of data bits; driven by SCK, the slave device sends data to the master or receives data from the master via the MOSI or MISO data lines.

[0003] In SPI slave communication, the transmission of slave data is controlled by SCK, with the transmitting side timing operating in the SCK clock domain. The data content, however, is prepared by the slave's internal logic driven by its own internal clock, with the preparation side timing operating in the slave's internal clock domain. SCK is generated by the master and is independent of the slave's internal clock, with no fixed phase relationship; therefore, these two clock domains are asynchronous. If the master initiates a read operation before the slave has completed data preparation, the slave may send invalid data due to incomplete data preparation, resulting in data loss or header loss, and consequently, incomplete application layer data.

[0004] Regarding how the master device knows that the slave device's data is ready and starts receiving, the existing technology typically uses the following three methods: Method 1: Add a dedicated synchronization signal line. After the slave device completes data preparation, it sends an indication signal to the master device via the synchronization signal line. Upon receiving the signal, the master device initiates the SPI read operation. This method can reliably achieve data synchronization, but it requires an additional hardware pin, which is often unacceptable in applications where pin resources are scarce.

[0005] Method 2: Synchronization based on software delay. The master waits for the slave to complete data preparation for a preset delay time, and then initiates data reading after the delay expires. This method does not require additional hardware resources, but setting the delay time presents a dilemma: if the waiting time is too long, it will reduce communication efficiency; if the time is insufficient, the master will initiate reading before the slave has completed data preparation, resulting in data loss.

[0006] Method 3: Synchronization based on protocol header. Both the master and slave agree to add a protocol header byte before the valid data. The slave sends this header first to notify the master that the data is ready. The master then begins reading the subsequent valid data after detecting the header. Theoretically, this method eliminates the need to consider synchronization issues, but in practical applications, there is still a small probability of header loss, leading to the loss of the entire data frame.

[0007] Analysis revealed that the root cause of the protocol header loss in Method 3 was a timing mismatch due to asynchronous clocking: when the master started reading, the slave had not yet completed the preparation of the protocol header and the setting of the status flag. The transmitting state machine sent invalid data because it detected that the data was not ready. After the transmission round was completed, when the slave prepared subsequent valid data, the new data would overwrite the original protocol header, ultimately leading to the loss of the protocol header and the loss of communication data.

[0008] Therefore, under the constraints of limited hardware pin resources and the need to ensure high-throughput communication, how to eliminate timing mismatches caused by cross-clock domain asynchronous communication, solve the problem of frame header loss, and ensure the integrity and reliability of communication data are technical problems that urgently need to be solved in this field. Summary of the Invention

[0009] In view of this, the present invention aims to propose a method and apparatus for synchronizing asynchronous data of SPI slave devices, so as to solve the technical problem in the prior art that timing mismatch caused by asynchronous operation across clock domains leads to frame header loss.

[0010] To achieve the above objectives, the technical solution of the present invention is implemented as follows: This invention provides a method for synchronizing asynchronous data from an SPI slave device. The SPI slave device includes a data preparation module, a synchronization control logic module, a clock detection state machine module, and a data transmission module. The synchronization control logic module includes a cross-clock domain synchronizer and a set flag controller. The clock detection state machine module has a set flag. The method for synchronizing asynchronous data from an SPI slave device includes the following steps: During the data preparation phase, the set flag remains in an invalid state, and the clock detection state machine module detects the serial clock SCK signal of the SPI host but does not generate a set response; After the data preparation is completed, the preparation completion flag signal generated by the data preparation module is synchronized by the synchronization control logic module to the clock domain where the clock detection state machine module is located via the cross-clock domain synchronizer, and the set flag controller enables the set flag after confirming that the preparation completion flag is valid. After the set flag is enabled, the clock detection state machine module will generate a set signal normally when it detects the next valid SCK clock edge; After receiving the set signal, the data transmission module reads the data prepared by the data preparation module and sends it to the SPI master according to the SPI protocol timing.

[0011] Furthermore, prior to the data preparation phase, the following steps are also included: after the system is powered on, the SPI slave completes the initialization configuration and is configured as an SPI slave; the data preparation module and the clock detection state machine module enter the standby state; the set flag is initialized to an invalid state; the clock detection state machine module begins to continuously detect the external clock signal on the SCK pin, and the set function is disabled.

[0012] Furthermore, the data preparation stage includes: receiving a data preparation instruction; writing the data to be sent into the data buffer; determining whether data preparation is complete, and if not, continuing to determine whether preparation is complete; and generating and outputting a preparation completion flag signal by the preparation completion indication logic after preparation is complete.

[0013] Furthermore, the clock domain of the data preparation module is driven by the slave's internal clock, while the clock domain of the clock detection state machine module is driven by the SCK clock; the two are asynchronous clock domains. The cross-clock domain synchronizer is a two-stage flip-flop synchronizer, consisting of a first flip-flop and a second flip-flop connected in series, both driven by the SCK clock. The first flip-flop samples the preparation completion flag signal for the first time to handle metastable convergence, and the second flip-flop samples the output of the first flip-flop for the second time and outputs the synchronized preparation completion flag. The synchronizer has two flip-flop stages, and the synchronization delay is two SCK clock cycles. The setting logic of the clock detection state machine module satisfies the following: the clock detection state machine module generates a set signal only when the set flag enable signal and the valid clock detection signal of SCK are both valid; when the set flag is invalid, the clock detection state machine module does not set regardless of whether a valid SCK edge is detected; when the set flag is enabled and no valid SCK edge is detected, the clock detection state machine module does not set.

[0014] Furthermore, after the current data frame is sent, the process includes: the data sending module sets the sending completion flag and notifies the clock detection state machine module; the clock detection state machine module returns to the standby state and the flag set controller restores the flag set to invalid; if new data needs to be sent, the data preparation stage and its subsequent steps are repeated; if no further sending is required, the clock detection state machine module remains in the standby state and waits for the next communication command.

[0015] Furthermore, the method for synchronizing asynchronous data from an SPI slave device also includes at least one of the following: The interrupt triggering step is to generate an interrupt signal to notify the CPU to start data transmission when the set flag is enabled and a valid SCK clock edge is detected. The multi-frame prefetching step prepares the data for the next frame in advance during the transmission of the current frame; The software configuration steps include providing a register interface to dynamically configure at least one of the following: enabling / disabling synchronization control, number of synchronizer stages, and clock edge polarity.

[0016] Based on the same concept, the present invention also provides a device for synchronizing asynchronous data of an SPI slave, comprising: The data preparation module includes a data buffer and preparation completion indication logic. It is responsible for the internal preparation of slave data within the data preparation clock domain driven by the slave's internal clock, and generates a preparation completion flag signal after preparation is completed. The clock detection state machine module has a set flag, which is used to continuously detect the SCK clock signal in the data transmission clock domain driven by the SCK clock. During the data preparation period, the set flag is kept invalid so as not to generate a set response at the edge of the SCK clock. After the set flag is enabled, a set signal is generated normally when the next set of valid SCK clock edges is detected. The synchronization control logic module includes a cross-clock domain synchronizer and a set flag controller, which is used to synchronize the preparation complete flag signal from the data preparation clock domain to the data transmission clock domain, and enable the set flag after confirming that the preparation complete flag is valid. The data transmission module is used to read the data prepared by the data preparation module and send it to the SPI master according to the SPI protocol timing when triggered by the set signal.

[0017] Furthermore, the clock detection state machine module includes SCK edge detection logic and state machine set logic; the data transmission module includes a shift register and an output buffer; after receiving the set signal, the data transmission module reads data from the data buffer, and shifts the data bit by bit through the shift register under the drive of SCK, and outputs it to the SPI master through the MOSI or MISO pin.

[0018] Furthermore, the cross-clock domain synchronizer is a two-stage flip-flop synchronizer, including a first flip-flop and a second flip-flop connected in series. Both flip-flops are driven by the SCK clock. The first flip-flop samples the preparation completion flag signal for the first time to undertake metastable convergence, and the second flip-flop samples the output of the first flip-flop for the second time and outputs the synchronized preparation completion flag. The synchronizer has two flip-flop stages, and the synchronization delay is two SCK clock cycles. The set logic of the clock detection state machine module satisfies the following: the clock detection state machine module generates a set signal only when the set flag enable signal and the valid clock detection signal of SCK are both valid.

[0019] Based on the same concept, the present invention also provides a chip including the aforementioned SPI slave asynchronous data synchronization processing device.

[0020] Compared with the prior art, the SPI slave asynchronous data synchronization processing method and apparatus described in this invention have the following advantages: First, it fundamentally eliminates the problem of frame header loss caused by cross-clock domains, significantly improving communication reliability. This invention achieves hard separation and sequentiality between the data preparation process and the transmission triggering process by forcibly keeping the state machine set flag invalid during the data preparation phase, enabling the data only after cross-clock domain synchronization when it is ready, and strictly aligning with the next set of valid SCK clock edges after enabling. This prevents the protocol header from being overwritten by invalid transmissions, thus eliminating frame header loss caused by timing mismatches at the mechanism level.

[0021] Secondly, it achieves highly robust synchronization and optimizes resource utilization without adding hardware pins. This invention does not require an additional dedicated synchronization signal line; it only relies on the set flag management inside the slave device and a two-stage flip-flop synchronizer to complete cross-clock domain handshaking, making it suitable for applications with limited pin resources.

[0022] Third, it maintains high throughput communication efficiency without additional communication delay overhead. Once enabled, this invention only needs to wait for the arrival of the next valid SCK clock edge to trigger transmission, eliminating the lengthy waiting inherent in software delay methods, and the communication efficiency is not affected by the synchronization mechanism.

[0023] Fourth, it has low hardware implementation cost and good integrability and portability. The dual-stage trigger synchronizer and set flag control logic used in this invention are small in scale, can be implemented purely in hardware, and are easy to integrate and port to various chips that support SPI slave communication.

[0024] Fifth, the solution is simple and reliable, with good testability and maintainability. Each module of this invention has a clear responsibility and a closed-loop process, and supports multiple operating modes such as interrupt triggering, multi-frame prefetching, and software configurability, facilitating testing, maintenance, and flexible adaptation to different application needs. Attached Figure Description

[0025] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 A system architecture block diagram of an SPI slave module provided in an embodiment of the present invention; Figure 2 This is a main flowchart of the method provided in an embodiment of the present invention; Figure 3 This is a circuit diagram of a cross-clock domain synchronizer provided in an embodiment of the present invention; Figure 4 A flowchart of the data preparation module provided in this embodiment of the invention; Figure 5 A flowchart illustrating the operation of the clock detection state machine module provided in an embodiment of the present invention; Figure 6 This is a flowchart illustrating the operation of a set flag controller provided in an embodiment of the present invention. Figure 7 A flowchart illustrating the workflow of the data transmission module provided in this embodiment of the invention; Figure 8 The flowchart illustrates the operation of the synchronization control logic module provided in this embodiment of the invention. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0027] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for describing particular embodiments only and is not intended to limit the invention. Embodiments of the invention and the technical features thereof may be combined with each other without conflict.

[0031] To facilitate understanding, the following section will first explain some of the terms and related mechanisms used in this article.

[0032] Serial Peripheral Interface (SPI) is a synchronous serial communication interface involving a master and a slave device. The master generates a serial clock, SCK, to control the shifting and sampling of data bits. Driven by SCK, the slave device sends data to or receives data from the master via the MOSI or MISO data lines. In this embodiment, the slave sending data to the master corresponds to the master receiving data; these are descriptions of the same communication process on different sides. In SPI slave communication, when the slave sends a data frame to the master, the shifting and transmission of the frame data on the data lines is controlled by SCK, meaning the transmitting side timing operates in the SCK clock domain. The content of the frame data is prepared by the slave's internal logic under the drive of its own internal clock, meaning the data preparation side timing operates in the slave's internal clock domain. SCK is generated by the master and is independent of the slave's internal clock, with no fixed phase relationship; therefore, these two clock domains are asynchronous. In this paper, clk_prep represents the clock in the data preparation clock domain, and clk_sck represents the clock in the data transmission clock domain.

[0033] When a signal generated by one clock domain is directly sampled or used by another asynchronous clock domain, the uncertain phase relationship between the signal transition edge and the sampling clock edge may cause the sampling flip-flop to enter a metastable state. This manifests as the output level not being able to stabilize at a definite high or low level for a period of time, leading to subsequent logic misjudgments; this is the cross-clock domain problem. To suppress the propagation of metastability, a synchronizer structure is usually used. This involves using the target clock domain's clock to sample the cross-domain signal through multiple stages of flip-flops. The first stage flip-flop handles the convergence of the metastable state, while the second stage flip-flop outputs a stable and reliable synchronized signal. This embodiment of the invention uses a two-stage flip-flop synchronizer structure, that is, using two stages of series-connected flip-flops to achieve cross-clock domain synchronization.

[0034] The state machine described in this document refers to a clock-detecting state machine, which continuously detects the clock edge on the SCK pin and generates a set signal to trigger data transmission when predetermined conditions are met. The set flag described in this document is a control flag used to control whether the state machine is allowed to generate a set response; when the set flag is invalid, the state machine continuously detects SCK but does not generate a set response to any clock edge; when the set flag is enabled, the state machine sets the flag normally when it detects the next valid SCK edge. The frame described in this document refers to a complete data unit transmitted by the slave device in one transmission. A frame of data may include a protocol header byte and subsequent valid data bytes.

[0035] To facilitate understanding of the problems solved by the embodiments of the present invention, the relevant mechanisms are explained below. In the protocol header-based synchronization method, the master and slave agree to add a protocol header byte before the valid data. The slave first sends the protocol header to notify the master that the data is ready, and the master starts reading the subsequent valid data after detecting the protocol header. Analysis shows that the root cause of protocol header loss is the timing mismatch caused by asynchronous clocks: when the master starts reading, the slave has not yet completed the preparation of the protocol header and the setting of the status flag. The sending state machine sends invalid data because it detects that the data is not ready; after the transmission is completed, when the slave prepares the subsequent valid data, the new data will overwrite the original protocol header, ultimately leading to the loss of the protocol header and causing communication data loss. The embodiments of the present invention address this mechanism by coordinating the data preparation process and the data sending clock detection state machine within the slave to eliminate the above-mentioned timing mismatch.

[0036] Example 1 See Figure 1 , Figure 1 This is a system architecture block diagram of an SPI slave module provided in an embodiment of the present invention. The present invention provides a synchronization processing device, or synchronization processing system, for asynchronous data from an SPI slave, applied to chips that support SPI slave communication, such as the CCP917T chip. The SPI slave module includes a data preparation module, a synchronization control logic module, a clock detection state machine module, and a data transmission module.

[0037] The data preparation module is responsible for the internal preparation of slave device data, and includes a data buffer and preparation completion indication logic. The data buffer is used to temporarily store data to be sent; the preparation completion indication logic is used to generate a preparation completion flag signal when data preparation is complete. The data preparation module operates in the data preparation clock domain.

[0038] The synchronization control logic module coordinates cross-clock domain signal interactions between modules to ensure timing matching. It includes a cross-clock domain synchronizer and a set flag controller, with the set flag controller being the core synchronization control unit. The cross-clock domain synchronizer employs a two-stage flip-flop structure to synchronize the preparation completion flag signal generated in the data preparation clock domain to the data transmission clock domain. The set flag controller manages the enabling and disabling of the state machine's set flag.

[0039] The clock detection state machine module is used to detect the SCK clock signal from the external SPI host and control the timing of data transmission. It includes SCK edge detection logic and state machine set logic. The SCK edge detection logic continuously detects the clock edge on the SCK pin; the state machine set logic generates a set signal when the set flag is enabled and a valid SCK edge is detected. The clock detection state machine module operates in the data transmission clock domain.

[0040] The data transmission module includes a shift register and an output buffer, used to send the prepared data to the host according to the SPI protocol when triggered by the state machine. Specifically, after receiving the set signal, the data transmission module reads data from the data buffer, shifts the data bit by bit through the shift register under the drive of SCK, and outputs it to the host through the MOSI or MISO pin.

[0041] Depend on Figure 1 As shown in the connection diagram, the data preparation module, synchronization control logic module, and clock detection state machine module are all connected to the data transmission module. The data preparation module sends the prepared data to the buffer of the data transmission module, and the synchronization control logic module and the clock detection state machine module jointly control the start timing of the data transmission module. Therefore, the data transmission module, as the sole data outlet, only initiates transmission after the state machine is set, and does not proactively initiate transmission itself, thus ensuring a unique and controllable control path for transmission initiation. Through this module division, the three functions of data preparation, cross-domain synchronization, and clock detection are separated, and the risk of asynchrony is confined within the synchronization control logic module, preventing it from propagating to the data transmission link.

[0042] Example 2 See Figure 2 , Figure 2 This is a main flowchart of a method provided in an embodiment of the present invention. An embodiment of the present invention provides a method for synchronizing asynchronous data from an SPI slave device, applied to the SPI slave module described in Embodiment 1. The method includes the following steps.

[0043] Step S1: Slave Initialization and Status Detection. After the system powers on, the SPI slave completes its initialization configuration and is configured as an SPI slave. The data preparation module and the clock detection state machine module enter standby mode. The set flag controller initializes the set flag of the state machine to an invalid state. The clock detection state machine begins to continuously detect the external clock signal on the SCK pin, but the set function is disabled at this time. Step S1 initializes the set flag to invalid, so that the system is in a default masked state at the beginning of power-on, ensuring that the state machine does not generate a set response to any SCK transition before data preparation is completed, thereby avoiding false triggering during the power-on phase.

[0044] Step S2, Slave Data Preparation Phase. The slave device receives a data preparation command from its internal logic, and the data preparation module begins data preparation. During data preparation, the set flag of the data transmission clock detection state machine remains invalid. At this time, although the state machine continues to detect the SCK clock edge normally, it does not generate a set response to ensure that the transmission process is not accidentally triggered when the data is not ready. The data preparation module writes the prepared data into the buffer, and after completion, the preparation completion indication logic generates a preparation completion flag signal. It should be noted that the state machine's continuous detection of SCK and the data preparation module's preparation actions are performed in parallel time, but the set response can only be generated after the set flag is enabled. Step S2 reflects the hard separation of preparation and transmission in terms of timing: during the preparation phase, any transition of SCK is only detected and not responded to.

[0045] Step S3, Flag Setting Enable Stage. The synchronization control logic module receives the preparation completion flag signal output by the data preparation module; the flag signal is synchronized to the clock domain of the clock detection state machine via the cross-clock domain synchronizer, that is, sampled step by step by the two-stage flip-flops with clk_sck; after confirming that the preparation completion flag is valid after synchronization, the flag setting controller sets the flag of the state machine to enable; after the enable operation is completed, the state machine enters the waiting-to-trigger state, hereinafter referred to as the waiting-to-trigger state, that is, the state waiting for the next set of valid SCK clocks.

[0046] Step S4, Data Transmission Trigger Phase. After the set flag is enabled, the clock detection state machine continuously monitors the clock signal on the SCK pin. When the next valid clock edge conforming to the SPI protocol specification is detected, the state machine generates a set signal normally. After receiving the set signal, the data transmission module starts reading data from the transmit buffer and transmits it to the SPI master through the MOSI or MISO pins according to the SPI protocol timing. The next valid SCK clock edge referred to in this article refers to the first clock edge conforming to the SPI protocol specification that appears after the set flag is enabled. Its specific polarity and sampling phase depend on the configured clock edge polarity. Since the set flag is enabled after the data is fully ready, and the set is strictly aligned to the next valid SCK edge after the enable, the start boundary of each frame only crosses the clock domain after the data is fully ready, and the transmission start point is strictly aligned with the valid clock edge.

[0047] Step S5, Communication Continuation and Looping. After the current data frame is sent, the slave device returns to step S2 to prepare for the next data frame. If new data needs to be sent during the preparation process, the process from step S2 to step S4 is repeated. If no further transmission is needed, the state machine returns to the standby state, waiting for the next communication command. If a transmission request is generated again in the standby state, the loop from step S2 to step S4 is restarted. If communication ends, the process terminates.

[0048] Through the above steps, the data preparation process and the transmission triggering process are sequentialized: prepare first, then enable, and then trigger. The transmission of any frame is initiated after the data is fully ready, fundamentally eliminating the timing mismatch caused by the asynchronous operation of the two clock domains.

[0049] Each step of the above method can be implemented with pure hardware logic, or by the processor executing firmware, or by a combination of hardware and firmware.

[0050] Example 3 See Figure 4 , Figure 4 The workflow diagram for the data preparation module is as follows: receiving data preparation instructions; writing data into the transmission buffer; determining whether data preparation is complete, and if not, returning to continue determining until preparation is complete; generating a preparation completion flag and outputting the preparation completion flag upon completion.

[0051] It should be noted that the data buffer is also called the send buffer; they are different names for the same buffer.

[0052] Depend on Figure 4As can be seen, the entire data preparation process occurs within the data preparation clock domain, and the completion time is determined by the slave's internal logic, making its duration uncertain and unpredictable by the external clock domain. The data preparation module outputs only a preparation completion flag as a handshake signal to the outside domain, without exposing any intermediate states. This minimizes the interface for cross-domain interaction, making the synchronization object singular and controllable. The preparation completion flag serves as the sole input event for subsequent cross-clock domain synchronization, reflecting the design philosophy of using frame-level data readiness events as cross-domain handshake nodes.

[0053] Example 4 See Figure 3 , Figure 3 This is a schematic diagram of a cross-clock domain synchronizer circuit. The preparation completion flag signal in the data preparation clock domain is generated by clk_prep and sent to a two-stage flip-flop synchronizer in the data transmission clock domain. The two-stage flip-flop synchronizer consists of a first flip-flop FF1 and a second flip-flop FF2 connected in series, both driven by clk_sck. The first flip-flop samples the preparation completion flag signal for the first time, handling metastability convergence; the second flip-flop samples the output of the first flip-flop for the second time, outputting the synchronized preparation completion flag. This preparation completion flag signal is a stable signal, safe for use by subsequent logic in the data transmission clock domain.

[0054] To facilitate the description of the time delay introduced by the synchronization process, the following mathematical expression is given: (1); in, For synchronization delay time, The number of flip-flop stages in the synchronizer. The clock cycle of the SCK clock. This represents multiplication. In this embodiment... In this embodiment, the synchronizer has two flip-flop stages, and the synchronization delay is two SCK clock cycles, corresponding to the description of the enable flag being set approximately two SCK cycles later in the application example. In some embodiments, the number of flip-flops can be increased through register configuration. The value of is chosen to increase the synchronization level, thereby achieving higher reliability.

[0055] See Figure 8 , Figure 8This is a flowchart of the synchronization control logic module's workflow. The synchronization control logic module's operation includes: initializing the synchronization control logic after system power-on or reset; monitoring the preparation completion flag signal from the data preparation module within the data preparation clock domain; determining if the flag is valid, and if invalid, returning to continue monitoring; if valid, performing cross-clock domain synchronization processing, i.e., synchronization via a two-stage flip-flop; the synchronized flag signal reaching the set flag controller; the set flag controller enabling the state machine to set the flag; and subsequently, outputting an enable signal to the clock detection state machine within the data transmission clock domain.

[0056] Depend on Figure 8 As can be seen, the monitoring action operates in the clk_prep domain, while the enable signal output operates in the clk_sck domain. The cross-domain process is handled solely by a two-stage flip-flop synchronizer. That is, a flag is generated in one domain, synchronized safely across domains, and enabled in the other domain. Each logic resides in its own domain and does not overstep its authority. Since the enable action and subsequent setting and edge detection are all in the same clock domain, cross-domain contention between the enable signal and the SCK edge is avoided. Furthermore, the object being synchronized is not an arbitrary single-bit signal, but a frame-level preparation completion event. That is, synchronization enable is triggered when the entire frame of data is ready, binding the synchronization action to the frame boundary. This is the asynchronous clock domain synchronization strategy based on frame boundary awareness.

[0057] Example 5 See Figure 6 , Figure 6 This is a flowchart of the set flag controller's operation. The set flag controller's operation process includes: after the system is powered on or reset, the set flag is initialized to invalid; continuously monitoring the preparation completion flag of the data preparation module; determining whether preparation is complete, and if not, returning to continue monitoring; if preparation is complete, enabling the set flag; outputting the enable signal to the clock detection state machine; and then entering the waiting state, waiting for the state machine to complete the setting on the valid SCK edge.

[0058] The above process embodies the principles of default safety and dynamic enabling: the set flag is invalid by default upon power-up, and enabling is not always enabled, but rather authorized during a runtime operation after data readiness is confirmed. Before enabling, the state machine only checks the clock without generating a set response; only after enabling can the state machine normally set the flag on the next valid SCK edge. Thus, the data preparation process and the transmission triggering process are rigidly separated and sequentially ordered in terms of timing, eliminating erroneous triggering when data is not ready at the mechanism level.

[0059] Example 6 See Figure 5 , Figure 5This is a flowchart of the clock detection state machine module's operation. The clock detection state machine module's operation includes: after the system powers on or resets, the state machine enters standby mode; it begins to continuously detect the clock signal on the SCK pin; it determines whether the set flag is valid; if the set flag is invalid, the state machine does not set the flag regardless of whether a valid SCK edge is detected, and returns to continue detection; if the set flag is valid, it detects the next set of valid SCK edges and generates a set signal normally when an edge is detected; the data transmission module starts the data transmission process accordingly; after transmission is completed, the state machine returns to standby mode, waiting for the next frame of data.

[0060] The above set logic can be described by the truth table as follows: To more clearly express the set logic, the following mathematical expression is given: (2); in, This is the set output of the state machine. This is the enable signal for the set flag. The valid clock detection signal for SCK. Indicates logical AND. When and When both are logic 1 The logic value is 1, meaning the state machine is set; otherwise... It is logic 0, meaning it is not set. The mathematical expression corresponds exactly to the truth table above.

[0061] As can be seen from the above logic, the existence of a valid SCK clock is only a necessary condition, not a sufficient condition, for setting the bit. The sufficient condition is that the set flag is enabled. The state machine's detection and response functions are thus decoupled: when the set flag is invalid, the state machine only detects SCK and does not respond; after the set flag is enabled, the state machine's setting and the next set of valid SCK edges after enabling form a one-to-one latch relationship, ensuring that only one transmission is triggered after synchronization is completed, avoiding repeated triggering or empty triggering within multiple cycles, and achieving closed-loop timing matching between signal synchronization and transmission triggering.

[0062] Example 7 See Figure 7 , Figure 7 This is a flowchart of the data transmission module's workflow. The data transmission module's operation includes: detecting a set signal from the state machine and waiting for a trigger signal; determining whether the trigger signal is valid, and if invalid, returning to continue waiting; if valid, reading data from the transmission buffer and transmitting the data; determining whether the current frame data has been transmitted completely, and if not, continuing to transmit until completion; after the current frame is transmitted, setting the transmission completion flag and notifying the state machine, causing the state machine to return to standby; and then waiting for the next frame data to be triggered.

[0063] The data transmission module is normally in a passive waiting state, only reading the buffer and initiating transmission when the trigger signal is valid. It ensures that the entire frame bit stream is transmitted continuously and completely according to the SPI timing by automatically determining whether the current frame has been transmitted. After transmission is completed, it sends a transmission completion flag back to the state machine, allowing the state machine to return to standby and the set flag to be invalidated. This enables the complete process of preparation, enable, and triggering to be re-executed for the next frame, forming a frame-level closed-loop control.

[0064] Example 8 See Figure 1 This invention also provides a synchronization processing device for asynchronous data from an SPI slave, namely the device configuration of the SPI slave module in Embodiment 1, comprising: a data preparation module, responsible for the internal preparation of slave data, including a data buffer and preparation completion indication logic; a synchronization control logic module, used to coordinate cross-clock domain signal interaction between modules, including a cross-clock domain synchronizer and a set flag controller; a clock detection state machine module, used to detect the SCK clock signal of the external SPI master and control the timing of data transmission; and a data transmission module, used to send the prepared data to the master according to the SPI protocol under the trigger of the state machine.

[0065] The functions and coordination relationships of each module and its sub-units are as described in Embodiment 1, and will not be repeated here. It should be understood that the module division in the embodiments of the present invention is only a logical function division, and can be merged or split in actual implementation: for example, the set flag controller can be implemented as a sub-unit of the synchronization control logic module, or it can be implemented as an independent logic module; some logic of the data preparation module and the synchronization control logic module can be merged into the same hardware circuit; the above equivalent transformations are all within the protection scope of the embodiments of the present invention.

[0066] Example 9 This invention also provides a chip including the SPI slave module or synchronization processing device described in any of the above embodiments. Specifically, each module of the SPI slave module can be implemented as hardware logic circuits within the chip. For example, the cross-clock domain synchronizer can be implemented as a two-stage series flip-flop, the clock detection state machine module can be implemented as a synchronization state machine driven by clk_sck, and the data transmission module can be implemented as a shift register and an output buffer. In some embodiments, some functions can also be implemented by the processor executing firmware, for example, in interrupt-triggered mode, the CPU responds to an interrupt signal to initiate data transmission. The chip can be, for example, a CCP917T chip. Since the chip provided by this invention includes the above modules or devices, it can achieve the same or corresponding beneficial effects.

[0067] Application Example 1 Assume the SPI master needs the slave to send a 16-byte data frame. The slave prepares the data in its internal data preparation clock domain, which takes approximately [time missing]. During this period, the external SCK clock has undergone several transitions, but the state machine's set flag is invalid, and the state machine does not respond. After the data preparation is completed, the preparation completion flag is synchronized by a two-stage flip-flop, and the set flag is enabled after about 2 SCK cycles. The master continues to send the SCK clock, and the state machine is set normally when the first set of valid edges is detected. The slave starts sending, and 16 bytes of data are sent completely without frame header loss.

[0068] Application Example 2 In continuous transmission scenarios, after the first frame is sent, the data preparation module immediately begins preparing the second frame of data. During the preparation of the second frame, the state machine set flag is restored to invalid, and all SCK clocks during the period are blocked. After the second frame is prepared, the enable process is repeated, waiting for the next set of valid clocks. This cycle is repeated to ensure that the transmission of each frame starts after the data is fully prepared, effectively eliminating the risk of frame header loss.

[0069] Variant In another embodiment, in addition to state machine polling detection, it can also be configured as an interrupt-triggered mode: when the set flag is enabled and a valid SCK clock edge is detected, an interrupt signal is generated to notify the CPU to start data transmission.

[0070] In another embodiment, for high throughput scenarios, it can be extended to multi-frame data prefetching, that is, preparing the next frame data in advance during the current frame transmission, further improving communication efficiency, and the synchronization control logic maintains a consistent set flag management strategy.

[0071] In another embodiment, a register interface is provided, allowing software to dynamically configure parameters such as enabling and disabling synchronization control, selecting the number of synchronizer stages, and clock edge polarity, flexibly adapting to different application requirements. For example, the number of synchronizer stages... It can be configured by the register to a value of 2 or greater.

[0072] In conjunction with the above specific embodiments, the present invention has at least the following beneficial effects.

[0073] First, it fundamentally eliminates the problem of frame header loss caused by cross-clock domains. Because the flag is forcibly invalidated during the preparation phase, enabled by cross-domain synchronization after readiness, and sent only after aligning with the next set of valid SCK edges, the protocol header is no longer covered by invalid transmissions, significantly improving communication reliability.

[0074] Secondly, it achieves highly robust synchronization without adding hardware pins. No dedicated synchronization signal line is required; cross-domain handshaking can be completed solely through the slave's internal set flag management and a two-stage trigger synchronizer, optimizing resource utilization.

[0075] Third, it maintains high throughput communication efficiency. The wait after enabling is only for the arrival of the next valid SCK edge, without the long wait inherent in software delay methods, and without additional communication delay overhead.

[0076] Fourth, the hardware implementation cost is low. The two-stage trigger synchronizer and set flag control logic are small in scale and have good integrability and portability.

[0077] Fifth, the solution is simple and reliable, with clear responsibilities for each module, a closed-loop process, and good testability and maintainability.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for synchronizing asynchronous data from an SPI slave device, applied to an SPI slave device, the SPI slave device comprising a data preparation module, a synchronization control logic module, a clock detection state machine module, and a data transmission module, wherein the synchronization control logic module includes a cross-clock domain synchronizer and a set flag controller, and the clock detection state machine module has a set flag; characterized in that, The method for synchronizing asynchronous data from an SPI slave device includes the following steps: During the data preparation phase, the set flag remains in an invalid state, and the clock detection state machine module detects the serial clock SCK signal of the SPI host but does not generate a set response; After the data preparation is completed, the preparation completion flag signal generated by the data preparation module is synchronized by the synchronization control logic module to the clock domain where the clock detection state machine module is located via the cross-clock domain synchronizer, and the set flag controller enables the set flag after confirming that the preparation completion flag is valid. After the set flag is enabled, the clock detection state machine module will generate a set signal normally when it detects the next valid SCK clock edge; After receiving the set signal, the data transmission module reads the data prepared by the data preparation module and sends it to the SPI master according to the SPI protocol timing.

2. The method for synchronizing asynchronous data from an SPI slave according to claim 1, characterized in that, Before the data preparation phase, the following steps are also included: after the system is powered on, the SPI slave completes the initialization configuration and is configured as an SPI slave mode; the data preparation module and the clock detection state machine module enter the standby state; the set flag is initialized to an invalid state; the clock detection state machine module starts to continuously detect the external clock signal on the SCK pin, and the set function is in the disabled state.

3. The method for synchronizing asynchronous data from an SPI slave according to claim 1, characterized in that, The data preparation phase includes: receiving a data preparation instruction; writing the data to be sent into the data buffer; determining whether data preparation is complete, and if not, continuing to determine whether preparation is complete; and generating and outputting a preparation completion flag signal by the preparation completion indication logic after preparation is complete.

4. The method for synchronizing asynchronous data from an SPI slave according to claim 1, characterized in that, The clock domain of the data preparation module is driven by the internal clock of the slave device, while the clock domain of the clock detection state machine module is driven by the SCK clock. The two are asynchronous clock domains. The cross-clock domain synchronizer is a two-stage flip-flop synchronizer, which includes a first flip-flop and a second flip-flop connected in series. Both stages of the flip-flop are driven by the SCK clock. The first flip-flop samples the preparation completion flag signal for the first time to handle metastable convergence. The second flip-flop samples the output of the first flip-flop for the second time and outputs the synchronized preparation completion flag. The synchronizer has two flip-flop stages, and the synchronization delay is two SCK clock cycles. The set logic of the clock detection state machine module satisfies the following: the clock detection state machine module generates a set signal only when the set flag enable signal and the valid clock detection signal of SCK are both valid. When the set flag is invalid, the clock detection state machine module does not set the flag, regardless of whether a valid SCK edge is detected. When the set flag is enabled and no valid SCK edge is detected, the clock detection state machine module does not set the flag.

5. The method for synchronizing asynchronous data from an SPI slave according to claim 1, characterized in that, After the current data frame is sent, the process includes: the data sending module sets the sending completion flag and notifies the clock detection state machine module; the clock detection state machine module returns to the standby state and the flag set controller restores the flag set to invalid; if new data needs to be sent, the data preparation stage and its subsequent steps are repeated; if no further sending is required, the clock detection state machine module remains in the standby state and waits for the next communication command.

6. The method for synchronizing asynchronous data from an SPI slave according to any one of claims 1 to 5, characterized in that, It also includes at least one of the following: The interrupt triggering step is to generate an interrupt signal to notify the CPU to start data transmission when the set flag is enabled and a valid SCK clock edge is detected. The multi-frame prefetching step prepares the data for the next frame in advance during the transmission of the current frame; The software configuration steps include providing a register interface to dynamically configure at least one of the following: enabling / disabling synchronization control, number of synchronizer stages, and clock edge polarity.

7. A device for synchronizing asynchronous data from an SPI slave device, characterized in that, include: The data preparation module includes a data buffer and preparation completion indication logic. It is responsible for the internal preparation of slave data within the data preparation clock domain driven by the slave's internal clock, and generates a preparation completion flag signal after preparation is completed. The clock detection state machine module has a set flag, which is used to continuously detect the SCK clock signal in the data transmission clock domain driven by the SCK clock. During the data preparation period, the set flag is kept invalid so as not to generate a set response at the edge of the SCK clock. After the set flag is enabled, a set signal is generated normally when the next set of valid SCK clock edges is detected. The synchronization control logic module includes a cross-clock domain synchronizer and a set flag controller, which is used to synchronize the preparation complete flag signal from the data preparation clock domain to the data transmission clock domain, and enable the set flag after confirming that the preparation complete flag is valid. The data transmission module is used to read the data prepared by the data preparation module and send it to the SPI master according to the SPI protocol timing when triggered by the set signal.

8. The SPI slave asynchronous data synchronization processing device according to claim 7, characterized in that, The clock detection state machine module includes SCK edge detection logic and state machine set logic; the data transmission module includes a shift register and an output buffer; after receiving the set signal, the data transmission module reads data from the data buffer, shifts the data bit by bit through the shift register under the drive of SCK, and outputs the data to the SPI master through the MOSI or MISO pin.

9. The SPI slave asynchronous data synchronization processing device according to claim 7, characterized in that, The cross-clock domain synchronizer is a two-stage flip-flop synchronizer, consisting of a first flip-flop and a second flip-flop connected in series. Both flip-flops are driven by the SCK clock. The first flip-flop samples the ready-to-complete flag signal for the first time to handle metastable convergence, and the second flip-flop samples the output of the first flip-flop for the second time and outputs the synchronized ready-to-complete flag. The synchronizer has two flip-flop stages, and the synchronization delay is two SCK clock cycles. The set logic of the clock detection state machine module satisfies the following condition: the clock detection state machine module generates a set signal only when the set flag enable signal and the valid clock detection signal of SCK are both valid.

10. A chip, characterized in that, Includes a synchronization processing device for asynchronous data from an SPI slave as described in any one of claims 7 to 9.

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