Antenna wave control module, data transmission method and antenna system
Patent Information
- Application Number
- CN202510478309.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2026-10-23
AI Technical Summary
[0037]本公开实施方式中，基于处理器包括的EXMC，实现了处理器与控制芯片之间通过EXMC总线的数据传输，即实现了处理器与控制芯片之间数据的并行传输，有效提高了处理器与控制芯片之间控制参数的传输速率，进而保证相控阵天线的波束响应速率；另外，设置控制芯片的时钟频率大于EXMC的时钟频率，以保证EXMC在控制芯片上的异步写入特性，且使得控制芯片能够更精准的读取EXMC写入的控制参数，从而保证控制参数传输的稳定性，即保证相控阵天线的波束响应的可靠性。
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Abstract
Description
Technical Field
[0001] This disclosure relates to the field of communication technology, and more specifically, to an antenna wave control module, a data transmission method, and an antenna system. Background Technology
[0002] With the development of satellite communication technology, phased array antennas have been widely used, and the requirements for the response of phased array antennas are also getting higher and higher.
[0003] In related technologies, for antenna beam control modules used in conjunction with phased array antennas, after receiving relevant parameters (such as antenna azimuth, elevation, frequency, etc.) sent by the control host, the antenna beam control module first calculates the corresponding control parameters (such as bias voltage, etc.) based on the relevant parameters, and then transmits the calculated control parameters to the phased array antenna's drive module to control the phased array antenna based on the drive module.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this disclosure is to provide an antenna beam control module, a data transmission method, and an antenna system that can improve the data transmission rate and stability.
[0006] According to one aspect of this disclosure, an antenna beam control module is provided, comprising:
[0007] The processor includes a data processing module and an external memory controller EXMC, the data processing module being used to connect to the control host;
[0008] The EXMC bus includes address signal lines, write signal lines, read signal lines, and multiple parallel data address multiplexed lines, wherein the address signal lines, the write signal lines, the read signal lines, and the multiple data address multiplexed lines are all coupled to the EXMC.
[0009] The control chip is coupled to the address signal line, the write signal line, the read signal line and a plurality of the data address multiplexed lines, and the clock frequency of the control chip is greater than the clock frequency of the EXMC.
[0010] According to any of the antenna beam control modules described in this disclosure, the EXMC bus further includes a chip select signal line, which is coupled to the EXMC and the control chip respectively.
[0011] According to any of the antenna wave control modules described in this disclosure, the ratio of the clock frequency of the control chip to that of the EXMC is greater than or equal to 2.
[0012] According to any of the antenna beam control modules described in this disclosure, the processor further includes a configuration module, the configuration module being connected to the EXMC;
[0013] The configuration module is used to configure the address mapping relationship, pin parameters, clock frequency, clock division factor and timing parameters of the EXMC. The address mapping relationship refers to the correspondence with the memory address of the control chip. The pin parameters refer to the parameters of the control pins coupled to the EXMC bus. The timing parameters include the memory address setup time and hold time, as well as the data setup time and hold time.
[0014] According to any of the antenna beam control modules described in this disclosure, the EXMC has a clock frequency of 10MHz, an address setup time of 9 nanoseconds, an address hold time of 1 nanosecond, a data setup time of 8 nanoseconds, and a data hold time of 2 nanoseconds.
[0015] According to any of the antenna beam control modules described in this disclosure, the control pins include a chip select pin, an address pin, a write pin, a read pin, and multiple data address multiplexed pins.
[0016] According to one aspect of this disclosure, a data transmission method for an antenna beam control module is provided, the method being applied to the antenna beam control module described in the above aspect, the method comprising:
[0017] The data processing module calculates the parameters transmitted by the control host and sends the calculated control parameters to the EXMC.
[0018] The EXMC transmits an address valid signal to the address signal line and simultaneously transmits the storage address of the calculated control parameters to multiple data address multiplexing lines. The address valid signal is used to instruct the data address multiplexing lines to transmit address information.
[0019] The control chip reads the address valid signal, and when the address valid signal is valid, reads the storage address transmitted by the multiple data address multiplexing lines;
[0020] The EXMC transmits a data valid signal to the address signal line, a write enable signal to the write signal line, and the calculated control parameters to the multiple data address multiplexing lines. The data valid signal is used to instruct the data address multiplexing lines to transmit data information.
[0021] The control chip reads the data valid signal and the write enable signal, and when the data valid signal and the write enable signal are valid, it reads the calculated control parameters transmitted by the multiple data address multiplexing lines, and stores the calculated control parameters according to the storage address.
[0022] According to any method described in this disclosure, the method further includes:
[0023] The EXMC transmits a data valid signal to the address signal line and a read enable signal to the read signal line at the same time.
[0024] The control chip reads the data valid signal and the read enable signal, and when the data valid signal and the read enable signal are valid, the control chip transmits the feedback parameters that need to be transmitted to the processor to multiple data address multiplexing lines.
[0025] The EXMC reads the feedback parameters transmitted by the multiple data address multiplexing lines and sends the feedback parameters to the data processing module.
[0026] According to any method described in this disclosure, the EXMC bus further includes a chip select signal line, and the method further includes:
[0027] The EXMC transmits a chip select signal to the chip select signal line;
[0028] The write enable signal being valid includes: the logical OR signal of the chip select signal and the write enable signal being a valid write signal;
[0029] The read enable signal being valid includes: the logical OR signal of the chip select signal and the read enable signal being a valid read signal.
[0030] According to any method described in this disclosure, the address valid signal, the valid write signal, and the valid read signal are all signals that transition from a high level to a low level, and the high level and the low level are maintained for multiple clock cycles;
[0031] The valid data signal is a signal that ranges from low to high, and the low and high levels are maintained for multiple clock cycles.
[0032] According to one aspect of this disclosure, an antenna system is provided, including a phased array antenna and the antenna beam control module described in one aspect above;
[0033] The phased array antenna includes a driving module and multiple antenna elements distributed in an array. The antenna wave control module is electrically connected to the driving module, and the driving module is electrically connected to the multiple antenna elements.
[0034] According to any of the antenna systems described in this disclosure, the control chip has a bus transmitter and the drive module has a bus receiver;
[0035] The antenna system also includes a low-voltage differential signal MINI-Lvds bus, which is connected to the bus transmitter and the bus receiver respectively.
[0036] The embodiments disclosed herein include at least the following technical effects:
[0037] In this embodiment of the disclosure, based on the EXMC included in the processor, data transmission between the processor and the control chip is realized through the EXMC bus, that is, parallel data transmission between the processor and the control chip is realized, which effectively improves the transmission rate of control parameters between the processor and the control chip, thereby ensuring the beam response rate of the phased array antenna. In addition, the clock frequency of the control chip is set to be greater than the clock frequency of the EXMC to ensure the asynchronous writing characteristics of the EXMC on the control chip, and to enable the control chip to read the control parameters written by the EXMC more accurately, thereby ensuring the stability of the control parameter transmission, that is, ensuring the reliability of the beam response of the phased array antenna.
[0038] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0040] Figure 1 This is a schematic diagram of the structure of an antenna wave control module provided in this embodiment.
[0041] Figure 2 This is a schematic diagram illustrating the partitioning of the access space of an EXMC according to an embodiment of this disclosure.
[0042] Figure 3 This is a data writing timing diagram for an antenna wave control module provided in an embodiment of the present disclosure.
[0043] Figure 4 This is a schematic diagram of the data transmission process of an antenna wave control module provided in this embodiment of the present disclosure.
[0044] Figure 5 This is a schematic diagram of an antenna system provided for an embodiment of the present disclosure.
[0045] Figure label:
[0046] 10. Antenna system;
[0047] 1. Antenna beam control module; 2. Phased array antenna;
[0048] 11. Processor; 12. Control chip;
[0049] 111. Data Processing Module; 112. EXMC; 113. Configuration Module;
[0050] 121. Memory; 122. Bus transmitter;
[0051] NADV, Address signal line; WR, Write signal line; RD, Read signal line; CS, Chip select signal line;
[0052] 21. Antenna unit; 22. Drive module; 23. Bus receiver. Detailed Implementation
[0053] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.
[0054] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.
[0055] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.
[0056] The antenna beam control module includes a processor and a control chip. The processor is connected to the control host to receive relevant parameters (such as antenna azimuth, elevation, frequency, etc.) sent by the control host, and calculates the corresponding control parameters (such as bias voltage, etc.) based on the relevant parameters. The control chip is connected to the processor to receive the control parameters calculated by the processor and transmit them to the phased array antenna drive module.
[0057] After careful research, the inventors discovered that the transmission rate of control parameters between the processor and the control chip was slow and time-consuming, which seriously affected the dynamic changes of the phased array antenna beam.
[0058] This disclosure provides a schematic diagram of the structure of an antenna beam control module 1. For example... Figure 1 As shown, the antenna beam control module 1 includes: a processor 11, an EXMC112 (External Memory Controller) bus, and a control chip 12. The processor 11 includes a data processing module 111 and an EXMC112. The data processing module 111 is used to connect to the control host. The EXMC112 bus includes an address signal line NADV, a write signal line WR, a read signal line RD, and multiple parallel data address multiplexed lines. The address signal line NADV, the write signal line WR, the read signal line RD, and the multiple data address multiplexed lines are all coupled to the EXMC112. The control chip 12 is coupled to the address signal line NADV, the write signal line WR, the read signal line RD, and the multiple data address multiplexed lines. The clock frequency of the control chip 12 is greater than the clock frequency of the EXMC112.
[0059] In this embodiment of the disclosure, based on the EXMC112 included in the processor 11, data transmission between the processor 11 and the control chip 12 via the EXMC bus is realized, that is, parallel data transmission between the processor 11 and the control chip 12 is realized, which effectively improves the transmission rate of control parameters between the processor 11 and the control chip 12, thereby ensuring the beam response rate of the phased array antenna 2. In addition, the clock frequency of the control chip 12 is set to be greater than the clock frequency of the EXMC112 to ensure the asynchronous writing characteristics of the EXMC112 on the control chip 12, and to enable the control chip 12 to read the control parameters written by the EXMC112 more accurately, thereby ensuring the stability of the control parameter transmission, that is, ensuring the reliability of the beam response of the phased array antenna 2.
[0060] The processor 11 can be an ARM processor 11, an Intel processor 11, a MIPS processor 11, etc. Taking the ARM processor 11 as an example, the processor 11 can be a GigaDevice GD32F470 series processor 11 with an internal EXMC112. The data processing module 111 is mainly used to receive relevant parameters transmitted by the control host (such as a host computer) and calculate the relevant parameters to obtain the control parameters of the phased array antenna 2. For details, please refer to relevant technologies. The EXMC112 is mainly used to manage the reading and writing of control parameters on external memory (such as SRAM, NOR Flash, NAND Flash, SDRAM, PSRAM, etc.) to ensure the reliability of control parameter transmission. For details, please refer to relevant technologies.
[0061] The control chip 12 can be an FPGA (Field Programmable Gate Array) chip, etc. The control chip 12 serves as external memory for the EXMC112, enabling the EXMC112 to control the control chip 12, such as... Figure 1 As shown, the control chip 12 includes a memory 121. The EXMC 112 can convert the AMBA protocol into a communication protocol corresponding to the memory 121 of the control chip 12, so as to realize data reading and writing of the EXMC 112 on the memory 121 included in the control chip 12.
[0062] In some implementations, the ratio of the clock frequency of the control chip 12 to that of the EXMC112 is greater than or equal to 2.
[0063] In this way, the ratio of the clock cycle when EXMC112 writes data to the clock cycle when the control chip 12 samples the EXMC bus transmission signal is greater than or equal to 2, so as to ensure the reliability of the signal sampled by the control chip 12.
[0064] For example, the ratio of the clock frequency of the control chip 12 to that of the EXMC112 is 2, 4, 6, 8, 10, 12, etc. For instance, the clock frequency of the EXMC112 is 10MHz, with a corresponding clock period of 100 nanoseconds, and the clock frequency of the control chip 12 is 100MHz, with a corresponding clock period of 10 nanoseconds; or the clock frequency of the EXMC112 is 20MHz, with a corresponding clock period of 50 nanoseconds, and the clock frequency of the control chip 12 is 100MHz, with a corresponding clock period of 10 nanoseconds.
[0065] In this embodiment of the disclosure, when EXMC112 is reading and writing on the control chip 12, the configuration parameters of EXMC112 can be configured through an external configuration module 113, or as follows: Figure 1As shown, the processor 11 also includes a configuration module 113, which is connected to the EXMC 112 and configures the configuration parameters of the EXMC 112 using the configuration module 113 included in the processor 11.
[0066] The EXMC112 includes registers, and its configuration parameters can be stored in these registers. These configuration parameters primarily include address mapping, pin parameters, clock frequency, clock divider, and timing parameters. Address mapping refers to the correspondence between the EXMC112 and the memory addresses of the control chip 12. Pin parameters refer to the parameters of the control pins coupled to the EXMC bus. Timing parameters include the setup and hold times for memory addresses, as well as the setup and hold times for data. Furthermore, the address mapping, pin parameters, clock frequency, clock divider, and timing parameters can be configured using the embedded program within the EXMC112. The seamless integration between the embedded program and the EXMC112 ensures reliable read / write operations on the control chip 12. The embedded programs for different configuration parameters within the EXMC112 can be found in relevant technical documents.
[0067] Based on the address mapping relationship of EXMC112, EXMC112 can control the control chip 12. That is, EXMC112 can convert the AMBA protocol into the corresponding communication protocol of the control chip 12 to control the control chip 12, that is, to realize data reading and writing on the control chip 12 by EXMC112.
[0068] The EXMC112's access space is divided into multiple memory areas (e.g., memory area 0, memory area 1, memory area 2, memory area 3, etc.), and each memory area is further divided into multiple regions (e.g., region 0, region 1, region 2, region 3, etc.). Each memory region supports a specific memory type. Therefore, based on the type of memory 121 included in the control chip 12, the address mapping relationship of the EXMC112 can be configured to enable the EXMC112 to control the control chip 12. For example, if the memory 121 of the control chip 12 is of type NOR Flash, then... Figure 2 As shown, storage area 0 can be selected, and the address mapping relationship of EXMC112 can be configured as 0x6000 0000-0x63FF FFFF, so that EXMC112 can read and write data in area 0 included in storage area 0 of control chip 12.
[0069] For the EXMC112 pin parameters, the EXMC112's control pins can include address pins, write pins, read pins, and multiple data address multiplexed pins. The address signal line NADV is coupled to the address pins, the write signal line WR is coupled to the write pins, the read signal line RD is coupled to the read pins, and the data address multiplexed lines are coupled to the data address pins. Taking the data address multiplexed pins as an example, the EXMC112's data address multiplexed pins need to be configured to have multiplexing functionality (e.g., configuring the EXMC112's data address multiplexed pins as GPIO_AF_12) to ensure the multiplexed transmission of storage addresses and control parameters on the data address multiplexed lines.
[0070] When configuring the pin parameters of EXMC112, the number of data address multiplexed pins can be configured, that is, the width of the data address multiplexed lines can be configured. For example, the control pins of EXMC112 include 16 data address multiplexed pins, and the corresponding EXMC bus includes 16 parallel data address multiplexed lines.
[0071] For the clock frequency and clock division factor of EXMC112, for example, the clock frequency of EXMC112 can be configured to be 5MHz, 10MHz, 15MHz, 20NHz, etc., as long as it is less than the clock frequency of control chip 12; the clock division factor of EXMC112 can be configured to be 4, 8, 16, 32, etc., and the smaller the clock division factor, the higher the frequency used by EXMC bus, and the faster the data transmission rate of EXMC bus, that is, the higher the communication efficiency between processor 11 and control chip 12.
[0072] For the timing parameters of EXMC112, for example, taking a clock cycle of 10 nanoseconds for the control chip 12, the address setup time of EXMC112 can be configured to be 9 nanoseconds, the address hold time to be 1 nanosecond, the data setup time to be 8 nanoseconds, and the data hold time to be 2 nanoseconds; or the address setup time to be 8 nanoseconds, the address hold time to be 2 nanoseconds, the data setup time to be 7 nanoseconds, and the data hold time to be 3 nanoseconds, etc., as long as the data address multiplexing line can reliably transmit control parameters and store addresses.
[0073] In some implementations, such as Figure 1 As shown, the EXMC bus also includes a chip select signal line CS, which is coupled to the EXMC112 and the control chip 12 respectively.
[0074] In this way, the selection confirmation between EXMC112 and control chip 12 can be realized based on the chip select signal line CS, thereby ensuring the operability of EXMC112 for reading and writing on control chip 12.
[0075] The antenna beam control module 1 may include one or more control chips 12. When the antenna beam control module 1 includes multiple control chips 12, the control chip 12 selected by EXMC112 can be effectively confirmed based on the chip select signal line CS, thereby ensuring the reliability of reading and writing on the selected control chip 12.
[0076] In addition, in conjunction with the configuration module 113 configured for the pin parameters of EXMC112 as described above, the control pins of EXMC112 also include a chip select pin, so as to realize the selection between EXMC112 and control chip 12 based on the coupling between the chip select signal line CS and the chip select pin.
[0077] In some implementations, after receiving the control parameters calculated by the data processing module 111, the EXMC112 can divide the control parameters into multiple data packets, add a protocol header to the beginning of each data packet, and add a checksum to the end of each data packet, so as to ensure the reliability of each data packet transmission based on the protocol header and checksum of each data packet.
[0078] Taking the target data packet among multiple data packets as an example, the data writing process of EXMC112 on the control chip 12 mainly includes an address reading stage and a data writing stage. In the address reading stage, EXMC112 transmits an address valid signal to the address signal line NADV and simultaneously transmits the storage address of the control parameters (target data packet) to multiple data address multiplexing lines. The address valid signal is used to indicate the address information transmitted by the data address multiplexing lines. The control chip 12 reads the address valid signal and, when the address valid signal is valid, reads the storage address transmitted by the multiple data address multiplexing lines. In the data writing stage, EXMC112 transmits a data valid signal to the address signal line NADV and simultaneously transmits a write enable signal to the write signal line WR and simultaneously transmits the calculated control parameters (target data packet) to multiple data address multiplexing lines. The data valid signal is used to indicate the data address multiplexing lines to transmit data information. The control chip 12 reads the data valid signal and the write enable signal, and, when both the data valid signal and the write enable signal are valid, reads the control parameters (target data packet) transmitted by the multiple data address multiplexing lines and stores the control parameters (target data packet) according to the storage address.
[0079] Figure 3 The following example illustrates the write timing of EXMC112 on the memory 121 included in the control chip 12 in this disclosure embodiment, such as... Figure 3As shown, within clock cycles 95 to 110, an address valid signal is transmitted based on the address signal line NADV, and simultaneously the first memory address (i.e., the starting address) is transmitted based on the data address multiplexed line. The first memory address 0000 is determined when the address valid signal is valid. Then, a data valid signal is transmitted based on the address signal line NADV, the first data packet is transmitted based on the data address multiplexed line, the chip select signal is transmitted based on the chip select signal line CS, and a write enable signal is transmitted based on the write signal line WR. The first data packet 0010 is determined when the data valid signal is valid and the logical OR signal of the chip select signal and the write enable signal is valid. From 110 to... Within a 130-clock cycle, an address valid signal is transmitted based on the address signal line NADV, and simultaneously, a second memory address (i.e., an offset address based on the starting address) is transmitted based on the data address multiplexed line. The second memory address 0001 is determined when the address valid signal is valid. Afterwards, a data valid signal is transmitted based on the address signal line NADV, a second data packet is transmitted based on the data address multiplexed line, a chip select signal is transmitted based on the chip select signal line CS, and a write enable signal is transmitted based on the write signal line WR. The second data packet 00EB is determined when the data valid signal is valid and the logical OR signal of the chip select signal and the write enable signal is valid. From 130 to... Within a 150-clock cycle, an address valid signal is transmitted based on the address signal line NADV, and simultaneously, the third memory address (i.e., the offset address based on the second memory address) is transmitted based on the data address multiplexed line. The third memory address 0002 is determined when the address valid signal is valid. Afterwards, a data valid signal is transmitted based on the address signal line NADV, the third data packet is transmitted based on the data address multiplexed line, the chip select signal is transmitted based on the chip select signal line CS, and the write enable signal is transmitted based on the write signal line WR. The third data packet 00E3 is determined when the data valid signal is valid and the logical OR signal of the chip select signal and the write enable signal is valid. In 1... During clock cycles from 50 to 170, the address valid signal is transmitted based on the address signal line NADV, and the fourth memory address (i.e., the offset address based on the third memory address) is transmitted based on the data address multiplexing line. The fourth memory address 0003 is determined when the address valid signal is valid. Then, the data valid signal is transmitted based on the address signal line NADV, the fourth data packet is transmitted based on the data address multiplexing line, the chip select signal is transmitted based on the chip select signal line CS, and the write enable signal is transmitted based on the write signal line WR. The fourth data packet 0003 is determined when the data valid signal is valid and the logical OR signal of the chip select signal and the write enable signal is valid.During clock cycles of 170 to 190, the address valid signal is transmitted via the address signal line NADV, while the fifth memory address (i.e., the offset address based on the fourth memory address) is transmitted via the data address multiplexed line. The fifth memory address (0004) is determined when the address valid signal is valid. Subsequently, the data valid signal is transmitted via the address signal line NADV, the fifth data packet is transmitted via the data address multiplexed line, the chip select signal is transmitted via the chip select signal line CS, and the write enable signal is transmitted via the write signal line WR. The fifth data packet (00CC) is determined when the data valid signal is valid and the logical OR of the chip select and write enable signals is valid. This process continues. Through writing to the control chip 12 using the EXMC112, 984 bytes of control parameters can be achieved in just 59.06 microseconds, with a data transfer rate as high as 16.66 MBytes / second, ensuring a high data transfer rate.
[0080] The data reading process of EXMC112 on the control chip 12 mainly includes: EXMC112 transmitting a data valid signal to the address signal line NADV and a read enable signal to the read signal line RD; the control chip 12 reading the data valid signal and the read enable signal, and when both the data valid signal and the read enable signal are valid, the control chip 12 transmitting the feedback parameters that need to be transmitted to the processor 11 to multiple data address multiplexing lines; EXMC112 reading the feedback parameters transmitted by the multiple data address multiplexing lines and sending the feedback parameters to the data processing module 111.
[0081] The feedback parameters are used to characterize whether the control chip 12 has read the target data packet transmitted by the EXMC112. If the feedback parameters transmitted by the control chip 12 to the multiple data address multiplexing lines indicate that the control chip 12 has accurately read the target data packet transmitted by the EXMC112, then the EXMC112 writes the next data packet to the control chip 12. If the feedback parameters transmitted by the control chip 12 to the multiple data address multiplexing lines indicate that the control chip 12 has not read the target data packet transmitted by the EXMC112, then the EXMC112 can rewrite the target data packet to the control chip 12, or skip the target data packet and write the next data packet to the control chip 12.
[0082] In accordance with the above, when the EXMC bus includes a chip select signal line CS, the EXMC112 transmits a chip select signal to the chip select signal line CS. Thus, when writing to the control chip 12, the control chip 12 can read the chip select signal and the write enable signal, and determine that the write enable signal is valid based on the chip select signal and the write enable signal. Specifically, a valid write enable signal includes the logical OR of the chip select signal and the write enable signal as a valid write signal. When reading from the control chip 12, the control chip 12 can read the chip select signal and the read enable signal, and determine that the read enable signal is valid based on the chip select signal and the read enable signal. Specifically, a valid read enable signal includes the logical OR of the chip select signal and the read enable signal as a valid read signal.
[0083] It should be noted that the address valid signal, write enable signal, read enable signal, valid write signal, and valid read signal mentioned above are all signals that transition from a high level to a low level, and the high and low levels are maintained for multiple clock cycles; the data valid signal is a signal that transitions from a low level to a high level, and the low and high levels are maintained for multiple clock cycles. For example, the address valid signal, write enable signal, read enable signal, valid write signal, and valid read signal are all high-high-low-low level signals (e.g., 1100), that is, signals that transition from a high level to a low level, and the high and low levels are maintained for two clock cycles; the data valid signal is a low-low-high-high level signal (e.g., 0011), that is, signals that transition from a low level to a high level, and the low and high levels are maintained for two clock cycles.
[0084] In this embodiment of the disclosure, the processor 11 and the control chip 12 communicate via an SPI (Serial Peripheral Interface) bus as an example. In this case, the processor 11 includes a data processing module 111 and an SPI controller.
[0085] The SPI controller features a MISO pin for master input / slave output, a MOSI pin for master output / slave input, a SCK pin for serial clock, and an NSS pin for slave select. Furthermore, the SPI controller's pin parameters (such as GPIO_AF_5), clock frequency, and clock divider can be configured before data transmission.
[0086] The processor 11 can act as a master device and the control chip 12 can act as a slave device. The processor 11 can send control parameters to the control chip 12 through the MOSI pin of the SPI controller. Since the SPI bus is a serial bus, only one bit of data can be sent per clock cycle, so the transmission rate between the processor 11 and the control chip 12 is only 2.5 MBytes / second.
[0087] This disclosure also provides a data transmission method for an antenna beam control module, which is applied to the antenna beam control module described in the above embodiments. For example... Figure 4 As shown, the method includes the following steps S110 to S150.
[0088] Step S110: The data processing module calculates the parameters transmitted by the control host and sends the calculated control parameters to EXMC.
[0089] In step S120, EXMC transmits an address valid signal to the address signal line and simultaneously transmits the storage address of the calculated control parameters to multiple data address multiplexing lines. The address valid signal is used to indicate the address information transmitted by the data address multiplexing lines.
[0090] Step S130: The control chip reads the address valid signal, and when the address valid signal is valid, it reads the storage address transmitted by multiple data address multiplexing lines.
[0091] In step S140, EXMC transmits a data valid signal to the address signal line, a write enable signal to the write signal line, and the calculated control parameters to multiple data address multiplexing lines. The data valid signal is used to indicate the data address multiplexing lines to transmit data information.
[0092] Step S150: The control chip reads the data valid signal and the write enable signal. When both the data valid signal and the write enable signal are valid, it reads the calculated control parameters transmitted by multiple data address multiplexing lines and stores the calculated control parameters according to the storage address.
[0093] In this embodiment of the disclosure, based on the EXMC included in the processor, data transmission between the processor and the control chip is realized through the EXMC bus, that is, parallel data transmission between the processor and the control chip is realized, which effectively improves the data writing rate of the processor on the control chip, thereby ensuring the reliability of the beam response of the phased array antenna when applied to the antenna system.
[0094] The specific implementation process of writing control parameters onto the control chip in steps S120 to S150 above can be referred to the above-described combination. Figure 3 The content explained in the timing diagram is not repeated here. In addition, before step S120 above, the EXMC clock can be enabled first, and the control pin clock of EXMC can be enabled; then the address mapping relationship, pin parameters, clock frequency, clock division factor and timing parameters of EXMC can be configured, as described in the above embodiments.
[0095] In some implementations, the address valid signal and the write enable signal are both high-to-low signals, and the high and low levels are maintained for multiple clock cycles; the data valid signal is a low-to-high signal, and the low and high levels are maintained for multiple clock cycles.
[0096] For example, the address valid signal and write enable signal are both high-high-low-low level signals (e.g., 1100), that is, signals that transition from high level to low level, and the high and low levels last for two clock cycles; the data valid signal is low-low-high-high level signal (e.g., 0011), that is, signals that transition from low level to high level, and the low and high levels last for two clock cycles.
[0097] In some implementations, the data transmission method of the antenna beam control module further includes: the EXMC transmitting a data valid signal to the address signal line and a read enable signal to the read signal line; the control chip reading the data valid signal and the read enable signal, and when both the data valid signal and the read enable signal are valid, the control chip transmitting the feedback parameters that need to be transmitted to the processor to multiple data address multiplexing lines; the EXMC reading the feedback parameters transmitted by the multiple data address multiplexing lines and sending the feedback parameters to the data processing module.
[0098] The meaning of the feedback parameters can be referred to the above implementation method. After receiving the feedback parameters, the data processing module can write subsequent data on the control chip based on the feedback parameters.
[0099] In some implementations, the read enable signal is a high-to-low transition signal, and the high and low levels are maintained for multiple clock cycles. For example, the read enable signal is a high-high-low-low level signal (e.g., 1100), that is, a high-to-low transition signal, and the high and low levels are maintained for two clock cycles.
[0100] In some implementations, the EXMC bus also includes a chip select signal line, and the data transmission method of the antenna beam control module further includes: the EXMC transmitting a chip select signal to the chip select signal line; the write enable signal being valid includes: the logical OR signal of the chip select signal and the write enable signal being a valid write signal; the read enable signal being valid includes: the logical OR signal of the chip select signal and the read enable signal being a valid read signal.
[0101] In some implementations, both the valid write signal and the valid read signal are high-to-low transition signals, and the high and low levels are maintained for multiple clock cycles.
[0102] For example, both the valid write signal and the valid read signal are high-high-low-low level signals (e.g., 1100), that is, signals that transition from high level to low level, and the high and low levels last for two clock cycles.
[0103] It should be noted that although the steps of the data transmission method of the antenna beam control module in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.
[0104] This disclosure also provides an antenna system 10, such as... Figure 5 As shown, the antenna system 10 includes a phased array antenna 2 and an antenna beam control module 1 as described in the above embodiment; the phased array antenna 2 includes a driving module 22 and multiple antenna elements 21 distributed in an array, the antenna beam control module 1 is electrically connected to the driving module 22, and the driving module 22 is electrically connected to the multiple antenna elements 21.
[0105] In some implementations, such as Figure 5 As shown, the control chip 12 has a bus transmitter 122, and the drive module 22 has a bus receiver 23; the antenna system 10 also includes a MINI-Lvds (Low-Voltage Differential Signaling) bus, which is connected to the bus transmitter 122 and the bus receiver 23 respectively.
[0106] In this way, the data transmission efficiency between the processor 11 and the driver module 22 can be effectively improved through the cooperation of the MINI-Lvds bus and the EXMC bus, thereby ensuring the beam response rate of the phased array antenna 2 and improving the antenna performance of the phased array antenna 2.
[0107] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.
Claims
1. An antenna beam control module, characterized in that, include: The processor includes a data processing module and an external memory controller EXMC, the data processing module being used to connect to the control host; The EXMC bus includes address signal lines, write signal lines, read signal lines, and multiple parallel data address multiplexed lines, wherein the address signal lines, the write signal lines, the read signal lines, and the multiple data address multiplexed lines are all coupled to the EXMC. The control chip is coupled to the address signal line, the write signal line, the read signal line and a plurality of the data address multiplexed lines, and the clock frequency of the control chip is greater than the clock frequency of the EXMC.
2. The antenna beam control module as described in claim 1, characterized in that, The EXMC bus also includes a chip select signal line, which is coupled to the EXMC and the control chip respectively.
3. The antenna beam control module as described in claim 1, characterized in that, The ratio of the clock frequency of the control chip to that of the EXMC is greater than or equal to 2.
4. The antenna beam control module as described in any one of claims 1-3, characterized in that, The processor further includes a configuration module, which is connected to the EXMC; The configuration module is used to configure the address mapping relationship, pin parameters, clock frequency, clock division factor and timing parameters of the EXMC. The address mapping relationship refers to the correspondence with the memory address of the control chip. The pin parameters refer to the parameters of the control pins coupled to the EXMC bus. The timing parameters include the memory address setup time and hold time, as well as the data setup time and hold time.
5. The antenna beam control module as described in claim 4, characterized in that, The EXMC has a clock frequency of 10MHz, an address setup time of 9 nanoseconds, an address hold time of 1 nanosecond, a data setup time of 8 nanoseconds, and a data hold time of 2 nanoseconds.
6. The antenna beam control module as described in claim 4, characterized in that, The control pins include a chip select pin, an address pin, a write pin, a read pin, and multiple data address multiplexed pins.
7. A data transmission method for an antenna beam control module, characterized in that, The method is applied to the antenna beam control module according to any one of claims 1-6, and the method includes: The data processing module calculates the parameters transmitted by the control host and sends the calculated control parameters to the EXMC. The EXMC transmits an address valid signal to the address signal line and simultaneously transmits the storage address of the calculated control parameters to multiple data address multiplexing lines. The address valid signal is used to instruct the data address multiplexing lines to transmit address information. The control chip reads the address valid signal, and when the address valid signal is valid, reads the storage address transmitted by the multiple data address multiplexing lines; The EXMC transmits a data valid signal to the address signal line, a write enable signal to the write signal line, and the calculated control parameters to the multiple data address multiplexing lines. The data valid signal is used to instruct the data address multiplexing lines to transmit data information. The control chip reads the data valid signal and the write enable signal, and when the data valid signal and the write enable signal are valid, it reads the calculated control parameters transmitted by the multiple data address multiplexing lines, and stores the calculated control parameters according to the storage address.
8. The method as described in claim 7, characterized in that, The method further includes: The EXMC transmits a data valid signal to the address signal line and a read enable signal to the read signal line at the same time. The control chip reads the data valid signal and the read enable signal, and when the data valid signal and the read enable signal are valid, the control chip transmits the feedback parameters that need to be transmitted to the processor to multiple data address multiplexing lines. The EXMC reads the feedback parameters transmitted by the multiple data address multiplexing lines and sends the feedback parameters to the data processing module.
9. The method as described in claim 8, characterized in that, The EXMC bus also includes a chip select signal line, and the method further includes: The EXMC transmits a chip select signal to the chip select signal line; The write enable signal being valid includes: the logical OR signal of the chip select signal and the write enable signal being a valid write signal; The read enable signal being valid includes: the logical OR signal of the chip select signal and the read enable signal being a valid read signal.
10. The method as described in claim 9, characterized in that, The address valid signal, the valid write signal, and the valid read signal are all signals that transition from a high level to a low level, and the high and low levels are maintained for multiple clock cycles. The valid data signal is a signal that ranges from low to high, and the low and high levels are maintained for multiple clock cycles.
11. An antenna system, characterized in that, Includes a phased array antenna and the antenna beam control module as described in any one of claims 1-6; The phased array antenna includes a driving module and multiple antenna elements distributed in an array. The antenna wave control module is electrically connected to the driving module, and the driving module is electrically connected to the multiple antenna elements.
12. The antenna system as claimed in claim 11, characterized in that, The control chip has a bus transmitter, and the drive module has a bus receiver; The antenna system also includes a low-voltage differential signal MINI-Lvds bus, which is connected to the bus transmitter and the bus receiver respectively.