Serial communication level conversion circuit and compatible communication device

Abstract

The application relates to the technical field of industrial communication, and provides a serial port communication level conversion circuit and a compatible communication device. The serial port communication level conversion circuit comprises a microprocessor and a level conversion module, the microprocessor is electrically connected with the level conversion module to control signal transceiving, the level conversion module comprises a TTL level conversion circuit and a duplex differential transceiving circuit, an input port of the TTL level conversion circuit receives an asynchronous serial port signal and converts the asynchronous serial port signal into a TTL signal, and then the TTL signal is transmitted to an input port of the duplex differential transceiving circuit. The duplex differential transceiving circuit further converts the TTL signal into a duplex serial communication signal, and finally outputs the duplex serial communication signal through an output port. The compatible communication device provided by the application adopts the above serial port communication level conversion circuit, realizes efficient level conversion, and meets the data interaction requirements of multiple protocols.

Description

Technical Field

[0001] This invention relates to the field of industrial communication technology, and in particular to a serial communication level conversion circuit and a compatible communication device. Background Technology

[0002] In today's industrial control and embedded systems field, efficient, stable, and reliable communication is crucial. RS232 (asynchronous serial communication) and RS485 (full-duplex serial communication) signals are commonly used communication protocols in this field, each playing an irreplaceable role. For example, in intelligent embedded gateway devices, RS232 signals can be used to connect to a local debugging terminal, facilitating device debugging and parameter configuration for developers; while RS485 signals can be used to connect multiple sensor nodes, enabling efficient data collection and transmission. The widespread application of these two protocols has driven the development of industrial control and embedded systems, meeting the data interaction needs between devices in different scenarios.

[0003] However, RS232 and RS485 signals differ significantly in physical levels, electrical standards, and communication methods. Furthermore, existing RS485 solutions often operate in half-duplex mode, requiring strict control of signal transmission and reception directions between communicating parties. Improper handling can easily lead to bus conflicts, data loss, or communication failures, making it difficult to adapt to the interconnection needs of different devices. Therefore, a solution integrating efficient level conversion, bidirectional communication, and compatibility with multiple protocols (half-duplex and full-duplex) is urgently needed. Summary of the Invention

[0004] To address the aforementioned shortcomings in the prior art, this invention provides a serial communication level conversion circuit, comprising a microprocessor and a level conversion module. The microprocessor is electrically connected to the level conversion module to control signal transmission and reception. The level conversion module includes a TTL level conversion circuit and a duplex differential transceiver circuit. The input port of the TTL level conversion circuit is used to receive asynchronous serial port signals, and the TTL level conversion circuit is used to convert the asynchronous serial port signals into TTL signals. The output port of the TTL level conversion circuit is connected to the input port of the duplex differential transceiver circuit, and the duplex differential transceiver circuit is used to convert the TTL signals into duplex serial communication signals. The output port of the duplex differential transceiver circuit outputs the converted duplex serial communication signal.

[0005] In one embodiment, the TTL level conversion circuit includes a TTL level conversion chip U1, capacitors C1, C2, C3, C4, and C5; capacitor C1 is connected in parallel between the C1+ and C1- pins of the TTL level conversion chip U1, capacitor C2 is connected in parallel between the C2+ and C2- pins of the TTL level conversion chip U1, capacitor C3 is connected in series with the V+ pin of the TTL level conversion chip U1 and then grounded, capacitor C4 is connected in series with the V- pin of the TTL level conversion chip U1 and then grounded, and capacitor C5 is connected in parallel between the GND and VCC pins of the TTL level conversion chip.

[0006] In one embodiment, the duplex differential transceiver circuit includes a differential signal transceiver chip U2, a resistor R1, and a connector J1; the resistor R1 is connected in parallel between pin A and pin B of the differential signal transceiver chip U2; a branch at pin A of the differential signal transceiver chip U2 is connected to pin 4 of the connector J1, a branch at pin Y of the differential signal transceiver chip U2 is connected to pin 3 of the connector J1, a branch at pin B of the differential signal transceiver chip U2 is connected to pin 2 of the connector J1, and a branch at pin Z of the differential signal transceiver chip U2 is connected to pin 1 of the connector J1.

[0007] In one embodiment, the FORCEON pin and / FORCEOFF pin of the TTL level conversion chip U1 are both connected to the VCC pin.

[0008] In one embodiment, the RO pin of the differential transceiver chip U2 is connected to the DIN pin of the TTL level conversion chip U1; one branch of the DI pin of the differential transceiver chip U2 is connected to the ROUT pin of the TTL level conversion chip U1, and another branch of the DI pin is connected to the serial transmit pin of the microprocessor; the DE pin of the differential transceiver chip U2 is connected to the transmit enable control pin of the microprocessor; and the / RE pin of the differential transceiver chip U2 is connected to the receive enable control pin of the microprocessor.

[0009] In one embodiment, the TTL level conversion chip U1 is model MAX3221.

[0010] In one embodiment, the differential signal transceiver chip U2 is model MAX1482.

[0011] In one embodiment, the asynchronous serial port signal input to the serial communication level conversion circuit has a level range of ±3V to ±15V; the full-duplex serial communication signal output by the serial communication level conversion circuit has a level range of ±1.5V to ±5V.

[0012] The present invention also provides a compatible communication device, including a serial communication level conversion circuit as described above, and further including a comparator and a bridge chip. The comparator is connected to the input ports of the TTL level conversion circuit and the bridge chip respectively. The output port of the duplex differential transceiver circuit is connected to the input port of the bridge chip. The bridge chip is used to convert the duplex serial communication signal into a USB signal.

[0013] In one embodiment, the output port of the bridging chip is connected to the receiving port of the duplex differential transceiver circuit.

[0014] Based on the above, compared with the prior art, the serial communication level conversion circuit provided by the present invention uses a TTL level conversion circuit to stably convert asynchronous serial port signals (such as RS232 signals) with an input range of ±3V to ±15V into TTL signals. Then, through a duplex differential transceiver circuit, the TTL signals are converted into duplex serial communication signals (such as RS485 signals) with a level range of ±1.5V to ±5V. This successfully realizes smooth conversion between signals of different level standards and eliminates communication obstacles caused by level differences.

[0015] Addressing the issues that existing RS485 signals are mostly half-duplex, and that improper signal transmission and reception control between communicating parties can easily lead to bus conflicts, this invention's duplex differential transceiver circuit design not only achieves full-duplex communication, but also effectively avoids signal conflicts and ensures reliable data transmission by using appropriate chip selection (such as using MAX1482 as a differential signal transceiver chip) and pin connection configuration, in conjunction with the microprocessor's transmit enable control and receive enable control, greatly improving the stability and efficiency of communication.

[0016] Other features and beneficial effects of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other beneficial effects of the invention can be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships shown in the drawings in the following description are based on the direction in which the components are drawn in the figure.

[0018] Figure 1This is a schematic diagram of the serial communication level conversion circuit provided in an embodiment of the present invention; Figure 2 The circuit diagram of a level conversion module provided in an embodiment of the present invention is shown below. Figure 3 This is a schematic diagram of the structure of a compatible communication device provided in an embodiment of the present invention.

[0019] Figure label: 100 - Serial communication level conversion circuit; 110 - Microprocessor; 120 - Level conversion module; 121 - TTL level conversion circuit; 122 - Full-duplex differential transceiver circuit; 200 - Comparator; 300 - Bridge chip; 400 - First external device; 500 - Second external device. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. The technical features designed in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be noted that all terms used in this invention (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and should not be construed as limiting the invention; it should be further understood that the terms used in this invention should be understood to have the same meaning as those in the context of this specification and in the relevant field, and should not be understood in an idealized or overly formal sense, except as expressly defined in this invention.

[0022] See Figure 1 The present invention provides a serial communication level conversion circuit 100, including a microprocessor 110 and a level conversion module 120.

[0023] In specific implementation, the microprocessor 110 serves as the control core and is electrically connected to the level conversion module 120 to control signal transmission and reception. The level conversion module 120 includes a TTL level conversion circuit 121 and a duplex differential transceiver circuit 122. The input port of the TTL level conversion circuit 121 is used to receive asynchronous serial port signals, and the TTL level conversion circuit 121 is used to convert asynchronous serial port signals into TTL signals. The output port of the TTL level conversion circuit 121 is connected to the input port of the duplex differential transceiver circuit 122, and the duplex differential transceiver circuit 122 is used to convert TTL signals into duplex serial communication signals. The output port of the duplex differential transceiver circuit 122 outputs the converted duplex serial communication signal.

[0024] The asynchronous serial port signal input to the serial communication level conversion circuit 100 has a level range of ±3V to ±15V; the full-duplex serial communication signal output by the serial communication level conversion circuit 100 has a level range of ±1.5V to ±5V. Through the above path, the asynchronous serial port signal, i.e., the RS232 signal, can be effectively converted into a full-duplex serial communication signal, i.e., the RS485 signal, which is more suitable for long-distance transmission and complex electromagnetic environments.

[0025] Preferably, the TTL level conversion circuit 121 includes a TTL level conversion chip U1, capacitors C1, C2, C3, C4, and C5; capacitor C1 is connected in parallel between the C1+ and C1- pins of the TTL level conversion chip U1, capacitor C2 is connected in parallel between the C2+ and C2- pins of the TTL level conversion chip U1, capacitor C3 is connected in series with the V+ pin of the TTL level conversion chip U1 and then grounded, capacitor C4 is connected in series with the V- pin of the TTL level conversion chip U1 and then grounded, and capacitor C5 is connected in parallel between the GND and VCC pins of the TTL level conversion chip U1. The FORCEON and / FORCEOFF pins of the TTL level conversion chip U1 are both connected to the VCC pin.

[0026] In specific implementation, such as Figure 2 As shown, preferably, the TTL level conversion chip U1 is a MAX3221, which can convert the high and low levels of RS232 signals (-3V to -15V represents logic "1", +3V to +15V represents logic "0") to the high and low levels of TTL signals (0V to 0.8V represents logic "0", 2V to 5V represents logic "1"), and vice versa.

[0027] The input port (RIN pin) of the MAX3221 chip is used to receive RS232 signals sent by the first external device 400; the transmit port (DOUT pin) of the MAX3221 chip is used to send RS232 signals to the first external device 400 to achieve bidirectional transmission of RS232 signals. The output port (ROUT pin) of the MAX3221 chip is used to output a standard TTL signal after internal conversion, which is then input to the full-duplex differential transceiver circuit 122; the receive port (DIN pin) of the MAX3221 chip is used to receive the TTL signal returned from the full-duplex differential transceiver circuit 122 to achieve bidirectional transmission of TTL signals.

[0028] The MAX3221 integrates a charge pump circuit, requiring only a single power supply to generate the positive and negative voltages needed for RS232 signals. To ensure proper operation of the charge pump, the MAX3221 requires several external capacitors. Capacitor C1 is connected to the C1+ and C1- pins of the MAX3221, respectively, while capacitor C2 is connected to the C2+ and C2- pins. Capacitors C1 and C2 act as flying capacitors for the charge pump. The internal charge pump circuit utilizes the charging and discharging processes of these two capacitors to convert the single-supply voltage into the voltage required for RS232 signal communication. Capacitor C3 is connected between the V+ pin and ground to stabilize the positive voltage output; capacitor C4 is connected between the V− pin and ground to stabilize the negative voltage output; and capacitor C5 is connected between the VCC and GND pins for power supply decoupling, improving power supply stability.

[0029] In the MAX3221 chip, the FORCEON pin is for "forced receiver on". Connecting the FORCEON pin to the VCC pin keeps the receiver always enabled. In the MAX3221 chip, the / FORCEOFF pin is for "forced receiver off". Connecting the / FORCEOFF pin to the VCC pin avoids forcibly turning off the receiver.

[0030] Preferably, the duplex differential transceiver circuit 122 includes a differential signal transceiver chip U2, a resistor R1, and a connector J1; a resistor R1 is connected in parallel between pin A and pin B of the differential signal transceiver chip U2; a branch at pin A of the differential signal transceiver chip U2 is connected to pin 4 of the connector J1, a branch at pin Y of the differential signal transceiver chip U2 is connected to pin 3 of the connector J1, a branch at pin B of the differential signal transceiver chip U2 is connected to pin 2 of the connector J1, and a branch at pin Z of the differential signal transceiver chip U2 is connected to pin 1 of the connector J1.

[0031] In practical implementation, preferably, the differential signal transceiver chip U2 is a MAX1482. The input port of the MAX1482 chip, i.e., the DI pin, is connected to the output port ROUT of the TTL level conversion chip U1 to introduce TTL signals. The transmit port of the MAX1482 chip, i.e., the RO pin, is connected to the receive port DIN of the TTL level conversion chip U1 to transmit TTL signals back, so as to realize bidirectional transmission of TTL signals.

[0032] The A and B pins of the MAX1482 are differential signal receivers, used to receive RS485 signals; the Y and Z pins are differential drive signal outputs, used to output RS485 signals. For example... Figure 2 As shown, a resistor R1 is connected in parallel between pins A and B of the MAX1482. The resistance of R1 is typically 120Ω, and it primarily serves as an impedance match. In differential signal transmission, to reduce signal reflection and improve signal transmission quality, the characteristic impedance of the transmission line needs to be matched with the load impedance. By connecting resistor R1 in parallel between pins A and B, the output impedance of the differential transceiver chip U2 can be matched with the characteristic impedance of the transmission line, thereby reducing signal reflection and distortion during transmission and ensuring reliable signal transmission.

[0033] See Figure 2 Connector J1 has four pins. One branch from pin A of the MAX1482 connects to pin 4 of connector J1; one branch from pin Y connects to pin 3 of connector J1; one branch from pin B connects to pin 2 of connector J1; and one branch from pin Z connects to pin 1 of connector J1. This forms two pairs of differential signal transmission channels. Pins A and B form the receiving channel, and pins Y and Z form the output channel, enabling bidirectional transmission of RS485 signals. It can be configured for half-duplex or full-duplex mode according to actual usage requirements.

[0034] Preferably, another branch at the DI pin is connected to the serial transmit pin of the microprocessor 110; the DE pin of the differential signal transceiver chip U2 is connected to the transmit enable control pin of the microprocessor 110; and the / RE pin of the differential signal transceiver chip U2 is connected to the receive enable control pin of the microprocessor 110.

[0035] To control the direction of data transmission and reception, the microprocessor 110 participates in the signal control logic. Preferably, the microprocessor 110 is a PIC12C508A chip. It should be noted that the microprocessor 110 is not limited to the model selected in this embodiment. In fact, the microprocessor 110 can also be other 8-bit, 16-bit, or 32-bit general-purpose MCU chips with serial communication control functions, including but not limited to the STM8 series, STM32 series, LPC series, and MSP430 series, all of which fall within the protection scope of this invention. Figure 2 As shown, pin GP2 is connected to the DI pin of the MAX1482 chip for transmitting data; pin GP1 is connected to the DE pin of the MAX1482 for controlling the enable of the transmit function; and pin GP0 is connected to the / RE pin of the MAX1482 for controlling the receive state. By controlling the level states of GP0 and GP1, the transmit and receive states of the MAX1482 chip can be dynamically switched.

[0036] For example, in a half-duplex communication scenario, before sending data, the microprocessor 110 first pulls the DE pin and / RE pin high, thereby enabling the driver and disabling the receiver, ensuring that the data is not mistakenly received by its own receiver during transmission. After transmission is complete, it pulls the DE pin and / RE pin low, enabling the receiver and disabling the driver, re-entering the receiving state. In full-duplex communication mode, the / RE pin can be pulled low via the connector J1 jumper, keeping the receiver always enabled, while the driver is controlled by the DE pin, thus achieving simultaneous transmission and reception.

[0037] It should be noted that the TTL level conversion chip U1 and the differential signal transceiver chip U2 are not limited to the models selected in this embodiment. The TTL level conversion chip U1 can also be other chips of the same type, such as MAX3232, SP232, ST3232, HIN232, ICL3221, etc.; the differential signal transceiver chip U2 can also be other chips of the same type, such as SN75176, MAX485, SP485, ADM485, AM26C31, etc., all of which fall within the protection scope of this invention.

[0038] The present invention also provides a compatible communication device, which employs the serial communication level conversion circuit 100 described above, and further includes a comparator 200 and a bridge chip 300. The comparator 200 is connected to the input ports of the TTL level conversion circuit 121 and the bridge chip 300, respectively. The output port of the duplex differential transceiver circuit 122 is connected to the input port of the bridge chip 300. The bridge chip 300 is used to convert the duplex serial communication signal into a USB signal.

[0039] In practical implementation, comparator 200 plays a crucial role in signal type identification within the circuit. It compares and judges the input signal to distinguish whether it is an RS232 or RS485 signal. Comparator 200 is connected to the input ports of TTL level conversion circuit 121 and bridge chip 300. When comparator 200 identifies the input signal as an RS485 signal, it directly transmits the signal to bridge chip 300; if it identifies it as an RS232 signal, it inputs the signal to TTL level conversion circuit 121 in serial communication level conversion circuit 100, first converting the RS232 signal to a TTL signal, then converting it to an RS485 signal through duplex differential transceiver circuit 122, and finally transmitting it to bridge chip 300.

[0040] The bridge chip 300 has input ports, output ports, transmit ports, and receive ports, such as... Figure 3 As shown, the input port of the bridge chip 300 is used to receive RS485 signals from the comparator 200 or the duplex differential transceiver circuit 122. Internally, the bridge chip 300 converts the RS485 signals into USB signals and outputs the processed USB signals from the transmit port to the second external device 500, enabling devices that previously could only communicate via serial port to communicate with other devices via USB. The receive port of the bridge chip 300 is used to receive USB signals returned from the second external device 500, thus achieving bidirectional signal transmission.

[0041] Preferably, the output port of the bridging chip 300 is connected to the receiving port of the duplex differential transceiver circuit 122.

[0042] In practical implementation, in some application scenarios that require bidirectional communication, the bridging chip 300 converts the RS485 signal into a USB signal and sends it to the second external device 500. The USB signal returned by the second external device 500 is converted into an RS485 signal by the bridging chip 300. This signal can then enter the duplex differential transceiver circuit 122, and be converted into a suitable level signal (such as a TTL signal) and transmitted to the TTL level conversion circuit 121 to achieve bidirectional data interaction.

[0043] In another embodiment, the output port of the bridging chip 300 is directly connected to the first external device 400. The USB signal returned by the second external device 500 is converted into an RS485 signal by the bridging chip 300 and transmitted directly to the first external device 400 through this connection, thereby realizing short-distance and efficient signal control of the first external device 400 by the second external device 500.

[0044] In summary, compared with the prior art, the serial communication level conversion circuit and compatible communication device provided by the present invention have the following advantages:

[0045] I. This invention utilizes a two-stage level conversion architecture of RS232 to TTL and TTL to RS485 to enable direct communication between RS232 interface devices and RS485 bus systems, thereby expanding the applicability of traditional serial port devices in industrial networks.

[0046] Second, it supports both half-duplex and full-duplex working modes of RS485 communication to meet the communication needs of different application scenarios and improve the applicability and flexibility of the system.

[0047] Third, the circuit adopts a highly integrated level conversion chip and transceiver, with fewer peripheral components and a compact layout, making it easy to embed into various terminal controllers or communication modules, thus reducing the difficulty and cost of hardware implementation.

[0048] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.

[0049] Although this document frequently uses terms such as microprocessor, level conversion module, TTL level conversion circuit, duplex differential transceiver circuit, asynchronous serial port signal, TTL signal, and duplex serial communication signal, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention. The terms "first," "second," etc. (if present), in the specification, claims, and accompanying drawings of the embodiments of the invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A serial communication level conversion circuit, characterized in that, include: A microprocessor and a level conversion module, wherein the microprocessor is electrically connected to the level conversion module to control signal transmission and reception; The level conversion module includes a TTL level conversion circuit and a duplex differential transceiver circuit. The input port of the TTL level conversion circuit is used to receive asynchronous serial port signals. The TTL level conversion circuit is used to convert the asynchronous serial port signals into TTL signals. The output port of the TTL level conversion circuit is connected to the input port of the duplex differential transceiver circuit. The duplex differential transceiver circuit is used to convert the TTL signals into duplex serial communication signals. The output port of the duplex differential transceiver circuit outputs the converted duplex serial communication signals.

2. The serial communication level conversion circuit according to claim 1, characterized in that: The TTL level conversion circuit includes a TTL level conversion chip U1, capacitors C1, C2, C3, C4, and C5. Capacitor C1 is connected in parallel between the C1+ and C1- pins of the TTL level conversion chip U1; capacitor C2 is connected in parallel between the C2+ and C2- pins of the TTL level conversion chip U1; capacitor C3 is connected in series with the V+ pin of the TTL level conversion chip U1 and then grounded; capacitor C4 is connected in series with the V- pin of the TTL level conversion chip U1 and then grounded; and capacitor C5 is connected in parallel between the GND and VCC pins of the TTL level conversion chip.

3. The serial communication level conversion circuit according to claim 1, characterized in that: The duplex differential transceiver circuit includes a differential signal transceiver chip U2, a resistor R1, and a connector J1; the resistor R1 is connected in parallel between pins A and B of the differential signal transceiver chip U2; one branch of pin A of the differential signal transceiver chip U2 is connected to pin 4 of the connector J1, one branch of pin Y of the differential signal transceiver chip U2 is connected to pin 3 of the connector J1, one branch of pin B of the differential signal transceiver chip U2 is connected to pin 2 of the connector J1, and one branch of pin Z of the differential signal transceiver chip U2 is connected to pin 1 of the connector J1.

4. The serial communication level conversion circuit according to claim 2, characterized in that: The FORCEON and / FORCEOFF pins of the TTL level conversion chip U1 are both connected to the VCC pin.

5. The serial communication level conversion circuit according to claim 3 or 4, characterized in that: The RO pin of the differential transceiver chip U2 is connected to the DIN pin of the TTL level conversion chip U1; one branch of the DI pin of the differential transceiver chip U2 is connected to the ROUT pin of the TTL level conversion chip U1, and the other branch of the DI pin is connected to the serial transmit pin of the microprocessor; the DE pin of the differential transceiver chip U2 is connected to the transmit enable control pin of the microprocessor; and the / RE pin of the differential transceiver chip U2 is connected to the receive enable control pin of the microprocessor.

6. The serial communication level conversion circuit according to claim 5, characterized in that: The TTL level conversion chip U1 is model MAX3221.

7. The serial communication level conversion circuit according to claim 5, characterized in that: The differential signal transceiver chip U2 is model MAX1482.

8. The compatible communication device according to claim 1, characterized in that: The asynchronous serial port signal level range of the serial communication level conversion circuit is ±3V to ±15V; the level range of the full-duplex serial communication signal output by the serial communication level conversion circuit is ±1.5V to ±5V.

9. A compatible communication device, characterized in that: The circuit includes a serial communication level conversion circuit as described in any one of claims 1-8; it also includes a comparator and a bridge chip, wherein the comparator is connected to the input ports of the TTL level conversion circuit and the bridge chip respectively, the output port of the duplex differential transceiver circuit is connected to the input port of the bridge chip, and the bridge chip is used to convert the duplex serial communication signal into a USB signal.

10. The compatible communication device according to claim 9, characterized in that: The output port of the bridging chip is connected to the receiving port of the duplex differential transceiver circuit.

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