Inter-chip interconnect structure allocation method and device, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure provide a chip interconnection structure distribution method and device, electronic equipment and storage medium, which belong to the chip technical field. The chip interconnection structure distribution method comprises: determining a plurality of chip interconnection lines and a plurality of chip interconnection structures, the starting point and the ending point of the chip interconnection line are located on two vertically stacked chips respectively, and the chip interconnection line is electrically connected through the chip interconnection structure; determining cost information according to the plurality of chip interconnection lines and the plurality of chip interconnection structures, the cost information comprises the cost of the chip interconnection line when different chip interconnection structures are allocated to the chip interconnection line, and the cost of the chip interconnection line is determined according to the length increment of the chip interconnection line when the chip interconnection structure is allocated to the chip interconnection line; and obtaining a distribution result of the chip interconnection structure according to the cost information, and the distribution result minimizes the total cost of the plurality of chip interconnection lines. The present scheme can guarantee the performance of the chip.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more particularly to a method, apparatus, electronic device, and storage medium for allocating inter-chip interconnect structures. Background Technology

[0002] With the development of integrated circuits, chip performance is constantly improving, and the functions integrated into a single chip are becoming increasingly numerous. When the chip size exceeds the limit of the photomask size, it leads to a decrease in manufacturing yield and consequently an increase in chip cost. Three-dimensional integrated circuits (3D-ICs) are a chip stacking technology used for semiconductor packaging. They break down the functions of a single chip into multiple chips for implementation, stacking these chips vertically and interconnecting them using through-silicon vias (TSVs) and micro-bumps. However, due to limitations in integrated circuit manufacturing processes, the number of TSVs / micro-bumps is finite and must adhere to specific rules.

[0003] Currently, when setting up through-silicon vias / microbumps for interconnecting stacked chips, multiple through-silicon vias / microbumps are randomly selected from a plurality of candidate through-silicon vias / microbumps, and the selected through-silicon vias / microbumps are used to achieve interconnection between chips.

[0004] However, the location of through-silicon vias / microbumps can affect the signal routing between two chips and within the chip. Randomly selected locations of through-silicon vias / microbumps are not reasonable. Inappropriate locations of through-silicon vias / microbumps can increase the signal routing distance between chips, resulting in poor chip performance. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a method, apparatus, electronic device, and storage medium for allocating inter-chip interconnect structures to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a method for allocating inter-chip interconnect structures is provided, comprising: determining a plurality of inter-chip interconnects and a plurality of inter-chip interconnect structures, wherein the start point and end point of the inter-chip interconnects are respectively located on two vertically stacked chips, and the start point and end point of the inter-chip interconnects are electrically connected through the inter-chip interconnect structures; determining cost information based on the plurality of inter-chip interconnects and the plurality of inter-chip interconnect structures, the cost information including the cost of the inter-chip interconnect when different inter-chip interconnect structures are allocated to the inter-chip interconnects, the cost of the inter-chip interconnect being determined based on the line length increment of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect; and obtaining an allocation result of the inter-chip interconnect structures based on the cost information, the allocation result minimizing the sum of the costs of the plurality of inter-chip interconnects.

[0007] According to a second aspect of the present disclosure, an inter-chip interconnect structure allocation apparatus is provided, comprising: a first determining unit, configured to determine a plurality of inter-chip interconnects and a plurality of inter-chip interconnect structures, wherein the start point and end point of the inter-chip interconnects are respectively located on two vertically stacked chips, and the start point and end point of the inter-chip interconnects are electrically connected through the inter-chip interconnect structures; a second determining unit, configured to determine cost information based on the plurality of inter-chip interconnects and the plurality of inter-chip interconnect structures, the cost information including the cost of the inter-chip interconnect when different inter-chip interconnect structures are allocated to the inter-chip interconnects, the cost of the inter-chip interconnect being determined based on the line length increment of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect; and an allocation unit, configured to obtain an allocation result of the inter-chip interconnect structures based on the cost information, the allocation result minimizing the sum of the costs of the plurality of inter-chip interconnects.

[0008] According to a third aspect of the present disclosure, an electronic device is provided, comprising a processor, a communication interface, a memory, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform an operation corresponding to the inter-chip interconnect structure allocation method described in the first aspect above.

[0009] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the method described in the first aspect above.

[0010] According to a fifth aspect of the present disclosure, a computer program product is provided, the computer program product being tangibly stored on a computer-readable medium and including computer-executable instructions that, when executed, cause at least one processor to perform the method as described in the first aspect above.

[0011] According to the scheme provided in this disclosure, after determining multiple inter-chip interconnects and multiple inter-chip interconnect structures, cost information is determined based on these interconnects. The cost information includes the cost of allocating different inter-chip interconnect structures to the inter-chip interconnects. Then, the allocation result of the inter-chip interconnect structures is determined based on the cost information, such that the total cost of each inter-chip interconnect is minimized when allocating inter-chip interconnect structures to each interconnect according to the allocation result. Since the cost of an inter-chip interconnect can indicate the negative impact of the allocation of inter-chip interconnect structures on chip performance, inter-chip interconnect structures can be allocated to each interconnect based on the cost information including each cost, minimizing the total negative impact on chip performance corresponding to each inter-chip interconnect and ensuring chip performance. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0013] Figure 1 This is a schematic diagram of an exemplary system applied in one embodiment of this disclosure;

[0014] Figure 2 This is a flowchart of an embodiment of the inter-chip interconnect structure allocation method disclosed herein;

[0015] Figure 3 This is a schematic diagram of a stacked chip according to an embodiment of the present disclosure;

[0016] Figure 4 This is a flowchart of a cost information determination method according to an embodiment of this disclosure;

[0017] Figure 5 This is a schematic diagram of the line length increment according to an embodiment of this disclosure;

[0018] Figure 6 This is a flowchart of a method for obtaining allocation results according to an embodiment of this disclosure;

[0019] Figure 7 This is a schematic diagram of the inter-chip interconnect structure and the distribution of inter-chip interconnects according to an embodiment of this disclosure;

[0020] Figure 8 This is a schematic diagram showing the allocation result of an inter-chip interconnect structure according to an embodiment of this disclosure;

[0021] Figure 9 This is a schematic diagram of an inter-chip interconnect structure allocation device according to an embodiment of the present disclosure;

[0022] Figure 10 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0023] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0024] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0025] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0026] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0027] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0028] First, some nouns or terms appearing in the description of the embodiments of this disclosure shall be interpreted as follows:

[0029] Chip: Also known as an integrated circuit (IC), a chip is a miniature electronic device that integrates a large number of electronic components (such as transistors, resistors, capacitors, etc.) onto a small semiconductor material. Chips can be classified into various types based on their function and application, such as Central Processing Units (CPUs), Application-Specific Integrated Circuits (ASICs), and Field-Programmable Gate Arrays (FPGAs).

[0030] Three-dimensional integrated circuits (3D-ICs) are a type of integrated circuit technology that stacks multiple chip layers vertically and utilizes technologies such as through-silicon vias (TSVs) to achieve interlayer interconnection. 3D-ICs can integrate chip modules with different functions into a highly integrated system.

[0031] Worst-case conditions: In timing static analysis, worst-case conditions refer to the situation where a circuit or system exhibits the slowest or most unfavorable timing characteristics under all possible operating conditions.

[0032] Static Timing Analysis (STA) involves traversing all timing paths of a circuit, calculating the propagation delay of signals on these paths based on timing library files under a given operating condition (PVT), checking whether the setup and hold times of signals meet the constraints, and identifying errors that violate timing constraints based on the maximum and minimum path delays.

[0033] Netlist: A netlist is a file used in Electronic Design Automation (EDA) to describe the connections between circuit components. A netlist is typically a text file containing connection information between each component in the circuit.

[0034] Through Silicon Via (TSV): TSVs enable vertical electrical interconnects between chips by creating vertical vias in a silicon wafer. TSV technology can reduce interconnect length and signal delay, and decrease capacitance and inductance, thereby achieving low-power, high-speed communication and higher interconnect density between chips.

[0035] Microbumps: Microbumps are used to achieve interconnects between chips. They are small in size, typically on the micrometer scale. Microbumps can improve the space utilization of the package structure, increase interconnect density, and provide mechanical support.

[0036] Copper bonding: Copper bonding (Cu-Cu Bonding) is an advanced interconnect technology that achieves direct copper-to-copper bonding between chips. Copper bonding features low resistivity and good resistance to electromigration.

[0037] Manhattan distance, also known as city block distance or L1 distance, is a method for measuring the distance between two points. It refers to the total distance traveled between two points along the coordinate axes in a grid-like environment.

[0038] Exemplary System

[0039] Figure 1 An exemplary system is shown that provides a method for allocating inter-chip interconnect structures applicable to embodiments of this disclosure. For example... Figure 1 As shown, the system may include a server 102, a communication network 104, and / or one or more user devices 106. Figure 1 The example in the text shows multiple user devices.

[0040] Server 102 can be any suitable server for storing information, data, programs, and / or any other suitable type of content. In some embodiments, server 102 can perform any suitable function. For example, in some embodiments, server 102 can be used for inter-chip interconnect structure allocation. As an optional example, in some embodiments, server 102 can optimize the inter-chip interconnect structure allocated to inter-chip interconnects based on the cost of the inter-chip interconnects when allocating different inter-chip interconnect structures, so as to minimize the total cost of each inter-chip interconnect, thereby reducing the distance of signal traces between chips, improving chip reliability, and reducing chip timing violation problems.

[0041] In some embodiments, communication network 104 may be any suitable combination of one or more wired and / or wireless networks. For example, communication network 104 may include any one or more of the following: the Internet, intranet, wide area network (WAN), local area network (LAN), wireless network, digital subscriber line (DSL) network, frame relay network, asynchronous transfer mode (ATM) network, virtual private network (VPN), and / or any other suitable communication network. User equipment 106 may be connected to communication network 104 via one or more communication links (e.g., communication link 112), and communication network 104 may be linked to server 102 via one or more communication links (e.g., communication link 114). Communication links may be any communication link suitable for transmitting data between user equipment 106 and server 102, such as network links, dial-up links, wireless links, hardwired links, any other suitable communication links, or any suitable combination of such links.

[0042] User equipment 106 may include any one or more user equipments suitable for performing inter-chip interconnect architecture allocation. In some embodiments, user equipment 106 may include any suitable type of device. For example, in some embodiments, user equipment 106 may include mobile devices, tablet computers, laptop computers, desktop computers, wearable computers, game consoles, media players, and / or any other suitable type of user equipment. User equipment 106 may send instructions to server 102 via communication network 104 to control server 102 to complete inter-chip interconnect architecture allocation.

[0043] Although server 102 is illustrated as a single device, in some embodiments, any suitable number of devices may be used to perform the functions performed by server 102. For example, in some embodiments, multiple devices may be used to implement the functions performed by server 102. Alternatively, cloud services may be used to implement the functions of server 102.

[0044] Inter-chip interconnection structure allocation method

[0045] Based on the above system, embodiments of this disclosure provide a method for allocating inter-chip interconnect structures, such as... Figure 2 As shown, the inter-chip interconnection structure allocation method includes the following steps:

[0046] Step 201: Determine multiple inter-chip interconnects and multiple inter-chip interconnect structures.

[0047] Inter-chip interconnects are used to connect two vertically stacked chips, enabling unidirectional or bidirectional signal transmission between them. The start and end points of the interconnect are located on the two vertically stacked chips. For example, if the first and second chips are stacked vertically, the interconnect starts on the first chip and ends on the second chip. It's important to note that the start and end points refer to the two ends of the interconnect. Since bidirectional transmission is possible between the two chips via the interconnect, signals can be transmitted from the start to the end point or vice versa.

[0048] Since the two chips are stacked vertically, the interconnects between the chips need to be connected across the chips. Therefore, an inter-chip interconnect structure needs to be set in the two chips. The inter-chip interconnects connect the start and end points through the inter-chip interconnect structure, so that the two chips can transmit signals through the inter-chip interconnects.

[0049] In one example, such as Figure 3 The schematic diagram of the stacked chips shown depicts a first chip 301 and a second chip 302 stacked vertically. Interconnect lines between the chips include interconnect segments 311 and 312. Interconnect segment 311 is located on the first chip 301, and interconnect segment 312 is located on the second chip 302. One end of interconnect segment 311 is the starting point 313 of the inter-chip interconnect, and the other end is electrically connected to the inter-chip interconnect structure 303. One end of interconnect segment 312 is electrically connected to the inter-chip interconnect structure 303, and the other end is the ending point 314 of the inter-chip interconnect. Interconnect segments 311, 312, and the inter-chip interconnect structure 303 are all conductors. When the first chip 301 transmits a signal to the second chip 302, the signal travels from the starting point 313 through interconnect segments 311, the inter-chip interconnect structure 303, and interconnect segment 312 to the ending point 314. When the second chip 302 transmits a signal to the first chip 301, the signal travels from the endpoint 314 through interconnect segment 312, inter-chip interconnect structure 303, and interconnect segment 311 to the starting point 313.

[0050] Inter-chip interconnects can be distributed on the upper surface, lower surface, or inside of the chip. Inter-chip interconnect structures can penetrate two vertically stacked chips, or be partially located inside the chip without penetrating it. This disclosure does not limit the specific implementation of the embodiments.

[0051] During chip design, inter-chip interconnect structures can be placed at multiple locations on the chip. The number of inter-chip interconnect structures must be greater than or equal to the number of inter-chip interconnects to ensure that each inter-chip interconnect can be electrically connected at its start and end points through an inter-chip interconnect structure. When the number of inter-chip interconnect structures is equal to the number of inter-chip interconnects, after allocating one inter-chip interconnect structure to each inter-chip interconnect, there are no idle inter-chip interconnect structures. When the number of inter-chip interconnect structures is greater than the number of inter-chip interconnects, after allocating one inter-chip interconnect structure to each inter-chip interconnect, there will still be at least one idle inter-chip interconnect structure, which can be removed during chip design.

[0052] Step 202: Determine the cost information based on the inter-chip interconnects and inter-chip interconnect structures.

[0053] After identifying multiple inter-chip interconnects and multiple inter-chip interconnect structures, cost information can be determined based on these interconnects and structures. This cost information includes the cost of allocating different inter-chip interconnect structures to each interconnect. For example, if 5 inter-chip interconnects and 6 inter-chip interconnect structures are identified, the cost of allocating each inter-chip interconnect structure to each interconnect can be determined separately. This results in 6 costs for each interconnect, and 30 costs for 5 interconnects. These 30 costs, along with the corresponding combinations of interconnects and inter-chip interconnect structures, constitute the cost information.

[0054] The cost of combining inter-chip interconnects and inter-chip interconnect structures can be determined based on the increase in the length of the inter-chip interconnect when the inter-chip interconnect structure is allocated to it. The increase in the length of the inter-chip interconnect is relative to the straight-line distance between its start and end points. When allocating an inter-chip interconnect structure to an inter-chip interconnect, the interconnect can change from a straight line to a curve, thus increasing its length. Therefore, the increase in the length of the inter-chip interconnect can be greater than or equal to 0.

[0055] The trace distance of inter-chip interconnects affects chip reliability and increases signal transmission delay, leading to timing violations. Therefore, ideally, the trace length of each inter-chip interconnect should be minimized when allocating interconnect structures. However, since inter-chip interconnect structures are distributed across different locations on the chip, and different inter-chip interconnects cannot share the same interconnect structure, it is necessary to allocate interconnect structures reasonably to ensure chip reliability and reduce timing violations.

[0056] Since increasing the number of interconnect traces between chips can affect chip reliability and may lead to timing violations, the larger the increase in the length of the interconnect traces, the higher the cost to improve chip performance. Therefore, the cost of allocating a certain interconnect structure to the interconnect traces can be determined based on the increase in the length of the interconnect traces.

[0057] Step 203: Obtain the allocation result of the inter-chip interconnection structure based on the cost information.

[0058] The cost of inter-chip interconnects indicates the impact of allocating a certain inter-chip interconnect structure to that inter-chip interconnect on chip performance. The higher the cost, the greater the negative impact on chip performance. Therefore, based on the costs included in the cost information, the inter-chip interconnect structure allocated to each inter-chip interconnect can be determined, and the allocation result of the inter-chip interconnect structure can be obtained. When allocating inter-chip interconnect structures to each inter-chip interconnect according to the allocation result, the total cost of each inter-chip interconnect is minimized. That is, from the perspective of each inter-chip interconnect as a whole, the total negative impact of each inter-chip interconnect on chip performance is minimized, thereby ensuring chip performance.

[0059] In this embodiment, after determining multiple inter-chip interconnects and multiple inter-chip interconnect structures, cost information is determined based on these interconnects. The cost information includes the cost of allocating different inter-chip interconnect structures to the inter-chip interconnects. Then, the allocation result of the inter-chip interconnect structures is determined based on the cost information, such that the total cost of each inter-chip interconnect is minimized when allocating inter-chip interconnect structures according to the allocation result. Since the cost of an inter-chip interconnect can indicate the negative impact of the allocation of inter-chip interconnect structures on chip performance, the allocation of inter-chip interconnect structures to each inter-chip interconnect can be based on the cost information including each cost, minimizing the total negative impact on chip performance corresponding to each inter-chip interconnect and ensuring chip performance.

[0060] In one possible implementation, if the timing information of the chip cannot be obtained when allocating the inter-chip interconnect structure, when determining the cost information, the line length increment of the inter-chip interconnect when allocating an inter-chip interconnect structure to an inter-chip interconnect can be used as the cost of allocating the inter-chip interconnect structure to the inter-chip interconnect, that is, the cost is equal to the line length increment.

[0061] In one example, assigning inter-chip interconnect structure A to inter-chip interconnect 1 results in an increase of 2 in the length of inter-chip interconnect 1, meaning the length increment of inter-chip interconnect 1 is 2. Therefore, the cost of assigning inter-chip interconnect structure A to inter-chip interconnect 1 is determined to be 2. Assigning inter-chip interconnect structure B to inter-chip interconnect 1 does not increase the length of inter-chip interconnect 1, meaning the length increment of inter-chip interconnect 1 is 0. Therefore, the cost of assigning inter-chip interconnect structure B to inter-chip interconnect 1 is determined to be 0.

[0062] In this embodiment of the disclosure, when an inter-chip interconnect structure is allocated to an inter-chip interconnect, the line length increment of the inter-chip interconnect is determined as the cost of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect. This allows for the rapid acquisition of the cost of the inter-chip interconnect, improving the efficiency of cost information acquisition and thus improving the allocation efficiency of the inter-chip interconnect structure.

[0063] In one possible implementation, if the timing information of the chips can be obtained when allocating the inter-chip interconnect structure, the cost information can be determined based on the timing information, the interconnects between the chips, and the inter-chip interconnect structure.

[0064] Figure 4 This is a flowchart of a cost information determination method according to an embodiment of this disclosure. Figure 4 As shown, the method for determining cost information includes the following steps:

[0065] Step 401: Based on the timing information of the two vertically stacked chips, determine the worst-case condition for at least one inter-chip interconnect signal transmitted through the inter-chip interconnect.

[0066] After obtaining timing information, for each inter-chip interconnect, the worst-case conditions for the inter-chip interconnect signals transmitted through that inter-chip interconnect can be determined based on the timing information. The worst-case conditions can indicate the slowest or most unfavorable timing characteristics of the inter-chip interconnect under all possible operating conditions.

[0067] Inter-chip interconnects can connect multiple registers in two chips, such as... Figure 3As shown, the first chip 301 includes registers 1, 2, and 3, and the second chip 302 includes registers 4, 5, and 6. Registers 1, 2, and 3 are all connected to the starting point 313 of the inter-chip interconnect, and registers 4, 5, and 6 are all connected to the ending point 314 of the inter-chip interconnect. The signal transmission between registers 1, 2, and 3 and registers 4, 5, and 6 is all carried out through the same inter-chip interconnect. Therefore, this inter-chip interconnect serves as the common part of the nine inter-chip signal transmission paths. Thus, based on timing information, the worst-case condition of this inter-chip interconnect can be determined from the nine inter-chip signal transmission paths.

[0068] Step 402: Determine the weight of the inter-chip interconnect based on the worst-case condition corresponding to the inter-chip interconnect.

[0069] The worst-case condition for an inter-chip interconnect indicates the maximum allowable delay for signal transmission over that interconnect. The weight of the inter-chip interconnect can then be determined based on this maximum delay. The maximum delay indicated by the worst-case condition is negatively correlated with the weight of the inter-chip interconnect; that is, the smaller the maximum delay indicated by the worst-case condition, the greater the weight of the inter-chip interconnect.

[0070] The weight of an inter-chip interconnect can be a real number greater than or equal to 1. For example, if the worst-case condition indicates that the maximum allowable delay for signal transmission via the inter-chip interconnect is 2 ns (nanoseconds), then the weight of the inter-chip interconnect is determined to be 1. If the worst-case condition indicates that the maximum allowable delay for signal transmission via the inter-chip interconnect is 1 ns, then the weight of the inter-chip interconnect is determined to be 2.

[0071] Step 403: When allocating the inter-chip interconnect structure to the inter-chip interconnect, the product of the line length increment of the inter-chip interconnect and the weight corresponding to the inter-chip interconnect is determined as the cost of allocating the inter-chip interconnect structure to the inter-chip interconnect.

[0072] When an inter-chip interconnect structure is assigned to an inter-chip interconnect line, the line length increment of the inter-chip interconnect line is determined, and the product of the line length increment and the weight of the inter-chip interconnect line is used as the cost of the inter-chip interconnect line when assigning the inter-chip interconnect structure to the inter-chip interconnect line.

[0073] In one example, when inter-chip interconnect structure A is assigned to inter-chip interconnect 1, the length increment of inter-chip interconnect 1 is 2, and the weight corresponding to inter-chip interconnect 1 is 2. Therefore, the cost of inter-chip interconnect 1 when assigning inter-chip interconnect structure A to inter-chip interconnect 1 is 4. When inter-chip interconnect structure B is assigned to inter-chip interconnect 1, the length increment of inter-chip interconnect 1 is 0, and the weight corresponding to inter-chip interconnect 1 is 2. Therefore, the cost of inter-chip interconnect 1 when assigning inter-chip interconnect structure B to inter-chip interconnect 1 is 0.

[0074] Step 404: Obtain cost information including multiple costs corresponding to each inter-chip interconnect.

[0075] For each inter-chip interconnect, the cost of allocating each inter-chip interconnect structure to that inter-chip interconnect is calculated, and the calculated costs are then determined as cost information.

[0076] In this embodiment, when determining the allocation result of the inter-chip interconnect structure based on cost information, the solution condition for the allocation result is to minimize the total cost of the interconnects between all chips. The product of the weight and the line length increment is used as the cost. When allocating the inter-chip interconnect structure based on the cost information, the inter-chip interconnect structure with the larger weight is allocated to the inter-chip interconnect structure with the smaller line length increment, so as to minimize the total cost of the inter-chip interconnects. The weight of the inter-chip interconnect is determined based on the worst-case condition, and the maximum delay indicated by the worst-case condition is negatively correlated with the weight of the inter-chip interconnect. By constraining the inter-chip interconnect structure allocated to the inter-chip interconnect by the worst-case condition, other operating conditions can also meet the timing requirements, provided that the worst-case condition can meet the timing requirements. This ensures that the allocation result of the inter-chip interconnect structure can meet the various timing conditions of the chip, thereby ensuring the reliability of the chip.

[0077] In one possible implementation, when an inter-chip interconnect structure is assigned to an inter-chip interconnect, the length increment of the inter-chip interconnect is equal to L1 + L2 - L0, where L1 is the Manhattan distance between the start point of the inter-chip interconnect and the inter-chip interconnect structure, L2 is the Manhattan distance between the end point of the inter-chip interconnect and the inter-chip interconnect structure, and L0 is the Manhattan distance between the start point and the end point of the inter-chip interconnect.

[0078] In one example, such as Figure 5As shown, the Manhattan distance between the start point 313 and the end point 314 of the inter-chip interconnect is L0 = L01 + L02, the Manhattan distance between the start point 313 of the inter-chip interconnect and the inter-chip interconnect structure 303 is L1 = L11 + L12, and the Manhattan distance between the end point 314 of the inter-chip interconnect and the inter-chip interconnect structure 303 is L2 = L21 + L22. Therefore, the incremental length of the inter-chip interconnect structure 303 allocated to the inter-chip interconnect is equal to L1 + L2 - L0.

[0079] In this embodiment of the disclosure, since the calculation process of Manhattan distance is simple and fast, the Manhattan distance represents the line length increment of the interconnect between chips. When obtaining cost information, the cost of the interconnect between chips can be obtained quickly, thereby improving the efficiency of obtaining cost information and thus improving the allocation efficiency of the interconnect structure between chips.

[0080] In one possible implementation, when determining the allocation result of the inter-chip interconnect structure based on the cost information, a Boolean matrix can be constructed to indicate which inter-chip interconnect structure is allocated to which chip interconnect. The Boolean matrix is ​​then optimized based on the cost information to obtain a Boolean matrix that can indicate the allocation result of the inter-chip interconnect structure.

[0081] Figure 6 A flowchart illustrating a method for obtaining allocation results according to an embodiment of this disclosure is shown. Figure 6 As shown, the method for obtaining the allocation result includes the following steps:

[0082] Step 601: Construct a cost matrix based on the cost information.

[0083] The element in the i-th row and j-th column of the cost matrix represents the cost of the j-th inter-chip interconnect when the i-th inter-chip interconnect structure is allocated to the j-th inter-chip interconnect.

[0084] In one example, such as Figure 7As shown, the inter-chip interconnects between two vertically stacked chips include interconnects S1 to S5, and the inter-chip interconnect structures to be assigned include interconnect structures A to F. Inter-chip interconnect S1 has a starting coordinate of (0,1) and an ending coordinate of (2,0), with a Manhattan distance of 3 between the starting and ending points. Inter-chip interconnect S2 has a starting coordinate of (0,4) and an ending coordinate of (3,1), with a Manhattan distance of 6 between the starting and ending points. Inter-chip interconnect S3 has a starting coordinate of (0,0) and an ending coordinate of (3,2), with a Manhattan distance of 5 between the starting and ending points. Inter-chip interconnect S4 has a starting coordinate of (0,3) and an ending coordinate of (4,4), with a Manhattan distance of 5 between the starting and ending points. Inter-chip interconnect S5 has a starting coordinate of (0,2) and an ending coordinate of (3,5), with a Manhattan distance of 6 between the starting and ending points. The coordinates of inter-chip interconnect structure A are (1,0), the coordinates of inter-chip interconnect structure B are (1,2), the coordinates of inter-chip interconnect structure C are (1,3), the coordinates of inter-chip interconnect structure D are (1,4), the coordinates of inter-chip interconnect structure E are (1,5), and the coordinates of inter-chip interconnect structure F are (1,6).

[0085] Table 1 below shows the cost of inter-chip interconnects when each inter-chip interconnect structure is assigned to different inter-chip interconnects.

[0086] Table 1

[0087] S1 S2 S3 S4 S5 A 0 2 0 6 4 B 3 0 0 2 0 C 5 0 2 0 0 D 7 0 4 0 0 E 9 2 6 2 0 F 11 4 8 4 2

[0088] Based on the costs shown in Table 1 above, the rows of the matrix correspond to the inter-chip interconnect structure, and the columns of the matrix correspond to the inter-chip interconnect lines. The constructed cost matrix C is shown below:

[0089]

[0090] It should be noted that, Figure 7 The horizontal coordinates of the inter-chip interconnect structures A to F shown are all 1, and the vertical coordinates of the starting points of the inter-chip interconnect lines S1 to S5 are all 0. This is only an example of an embodiment of this disclosure. In actual business implementation, the starting point of the inter-chip interconnect line can be any position, and the inter-chip interconnect structure can also be any position.

[0091] Step 602: Construct a Boolean matrix.

[0092] Construct a Boolean matrix based on the number of rows and columns of the cost matrix, such that the number of rows and columns of the Boolean matrix are equal to the number of rows and columns of the cost matrix. The Boolean matrix indicates which inter-chip interconnect structure is assigned to which inter-chip interconnect. Rows in the Boolean matrix correspond to inter-chip interconnect structures, and columns correspond to inter-chip interconnects. When the i-th inter-chip interconnect structure is assigned to the j-th inter-chip interconnect, the element in the i-th row and j-th column of the Boolean matrix is ​​1. When the number of inter-chip interconnects is equal to the number of inter-chip interconnect structures, each row and each column of the Boolean matrix has only one element that is 1. When the number of inter-chip interconnects is less than the number of inter-chip interconnect structures, each row of the Boolean matrix has at most one element that is 1, and each column of the Boolean matrix has one element that is 1.

[0093] In one example, the Boolean matrix X constructed based on the cost matrix C above is shown below:

[0094]

[0095] Step 603: Construct the cost function based on the cost matrix and the Boolean matrix.

[0096] The cost function constructed based on the cost matrix C and the Boolean matrix X is as follows:

[0097]

[0098] Among them, C i,j The element X in the i-th row and j-th column of the cost matrix C. i,j The element in the i-th row and j-th column of a Boolean matrix X is defined if and only if the i-th inter-chip interconnect structure is assigned to the j-th inter-chip interconnect. i,j =1.

[0099] Step 604: Obtain the target Boolean matrix by solving the cost function.

[0100] The process of solving the cost function involves optimizing the Boolean matrix to make ∑ i ∑ j C i,j X i,j The minimum process involves adjusting the inter-chip interconnect structure allocated to each chip interconnect to minimize the total cost of the inter-chip interconnects.

[0101] In one example, the cost function is solved based on the cost matrix C and the Boolean matrix X, and the resulting target Boolean matrix is ​​shown below:

[0102]

[0103] Step 605: Determine the allocation result of the inter-chip interconnection structure based on the target Boolean matrix.

[0104] After obtaining the target Boolean matrix, for each column of the target Boolean matrix, the inter-chip interconnect structure corresponding to the element that is 1 in that column is assigned to the inter-chip interconnect line corresponding to that element.

[0105] In one example, based on the target Boolean matrix X mentioned above... ′ Inter-chip interconnect structure A is assigned to inter-chip interconnect S1, inter-chip interconnect structure C is assigned to inter-chip interconnect S2, inter-chip interconnect structure B is assigned to inter-chip interconnect S3, inter-chip interconnect structure D is assigned to inter-chip interconnect S4, inter-chip interconnect structure E is assigned to inter-chip interconnect S5, and inter-chip interconnect structure F remains unassigned. At this point, the total cost of all inter-chip interconnects is minimized. The routing of inter-chip interconnects S1 to S5 after assigning the inter-chip interconnect structures is as follows: Figure 8 As shown.

[0106] In this embodiment of the disclosure, after constructing a cost matrix based on cost information, a cost function is constructed according to the cost matrix and the Boolean matrix. The target Boolean matrix is ​​obtained by solving the cost function. The elements that are 1 in the target Boolean matrix are assigned to the inter-chip interconnects corresponding to the inter-chip interconnects structure, so that the total cost of each inter-chip interconnect after the allocation of the inter-chip interconnect structure is minimized, thereby minimizing the total negative impact on the chip performance corresponding to each inter-chip interconnect and ensuring the chip performance.

[0107] In one possible implementation, when determining inter-chip interconnects, the netlists of two vertically stacked chips can be obtained and divided into a first sub-netlist and a second sub-netlist. The first sub-netlist corresponds to the first chip, and the second sub-netlist corresponds to the second chip. Based on the first and second sub-netlists, it can be determined whether the number of inter-chip interconnects between the first and second chips is less than or equal to the number of inter-chip interconnect structures to be allocated. If the number of inter-chip interconnects between the first and second chips is greater than the number of inter-chip interconnect structures, the netlist is re-divided until the number of inter-chip interconnects between the first and second chips is less than or equal to the number of inter-chip interconnect structures. If the number of inter-chip interconnects between the first and second chips is less than or equal to the number of inter-chip interconnect structures, then the inter-chip interconnects between the first and second chips are determined as inter-chip interconnects that need to be allocated inter-chip interconnect structures.

[0108] In chip design, two vertically stacked chips are designed as a single unit, meaning they correspond to a single overall netlist. This netlist is then divided into two sub-netlists, with each chip implementing the functionality of its respective sub-netlist. There are various possible partitioning results for the netlist, leading to different numbers of inter-chip interconnects between the two chips. However, the number of inter-chip interconnect structures to be allocated is finite. If the number of inter-chip interconnects exceeds the number of inter-chip interconnect structures, the allocation of these interconnect structures cannot be completed.

[0109] In this embodiment, the netlists of two vertically stacked chips are divided to obtain a first sub-netlist corresponding to the first chip and a second sub-netlist corresponding to the second chip. The number of inter-chip interconnects between the first chip and the second chip can be determined based on the first and second sub-netlists. If the number of inter-chip interconnects between the first chip and the second chip is less than or equal to the number of inter-chip interconnect structures to be allocated, this netlist division method is adopted, and inter-chip interconnect structure allocation is performed based on the inter-chip interconnects between the first chip and the second chip under this netlist division method. If the number of inter-chip interconnects between the first chip and the second chip is greater than the number of inter-chip interconnect structures to be allocated, the netlist is re-divided until the number of inter-chip interconnects between the first chip and the second chip is less than or equal to the number of inter-chip interconnect structures to be allocated, ensuring that the inter-chip interconnect structure allocation can be completed normally.

[0110] In one possible implementation, the inter-chip interconnect structure can be a structure used for inter-chip interconnection, such as through-silicon vias, microbumps, or copper bonding, making the inter-chip interconnect structure allocation method provided in this disclosure highly applicable.

[0111] Inter-chip interconnection structure allocation device

[0112] Corresponding to the above method embodiments, Figure 9 A schematic diagram of an inter-chip interconnect structure allocation device according to an embodiment of the present disclosure is shown. Figure 9 As shown, the inter-chip interconnect structure allocation device 900 includes:

[0113] The first determining unit 901 is used to determine multiple inter-chip interconnects and multiple inter-chip interconnect structures. The start and end points of the inter-chip interconnects are located on two vertically stacked chips, and the start and end points of the inter-chip interconnects are electrically connected through the inter-chip interconnect structures.

[0114] The second determining unit 902 is used to determine cost information based on multiple inter-chip interconnects and multiple inter-chip interconnect structures. The cost information includes the cost of the inter-chip interconnect when different inter-chip interconnect structures are allocated to the inter-chip interconnect. The cost of the inter-chip interconnect is determined based on the line length increment of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect.

[0115] Allocation unit 903 is used to obtain the allocation result of the inter-chip interconnect structure based on the cost information, and the allocation result minimizes the total cost of the multiple inter-chip interconnects.

[0116] In this embodiment, after the first determining unit 901 determines multiple inter-chip interconnects and multiple inter-chip interconnect structures, the second determining unit 902 determines cost information based on the multiple inter-chip interconnects and multiple inter-chip interconnect structures. The cost information includes the cost of allocating different inter-chip interconnect structures to the inter-chip interconnects. Then, the allocation unit 903 determines the allocation result of the inter-chip interconnect structures based on the cost information, so that when allocating inter-chip interconnect structures to each inter-chip interconnect according to the allocation result, the total cost of each inter-chip interconnect is minimized. Since the cost of the inter-chip interconnect can indicate the negative impact of the allocation of inter-chip interconnect structures on chip performance, the inter-chip interconnect structures can be allocated to each inter-chip interconnect based on the cost information including each cost, so as to minimize the total negative impact on the chip performance corresponding to each inter-chip interconnect and ensure chip performance.

[0117] In one possible implementation, the second determining unit 902 is used to determine the line length increment of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect as the cost of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect.

[0118] In one possible implementation, the second determining unit 902 is configured to perform the following processing: determining the worst-case condition of at least one inter-chip interconnect signal transmitted through the inter-chip interconnect based on the timing information of the two chips; determining the weight corresponding to the inter-chip interconnect based on the worst-case condition corresponding to the inter-chip interconnect; determining the cost of the inter-chip interconnect when allocating the inter-chip interconnect structure to the inter-chip interconnect by multiplying the line length increment of the inter-chip interconnect with the weight corresponding to the inter-chip interconnect; and obtaining cost information including multiple costs corresponding to each inter-chip interconnect.

[0119] In one possible implementation, when the second determining unit 902 determines the line length increment, the line length increment of the inter-chip interconnection line when the inter-chip interconnection structure is allocated to the inter-chip interconnection line is equal to L1 + L2 - L0, where L1 is the Manhattan distance between the starting point of the inter-chip interconnection line and the inter-chip interconnection structure, L2 is the Manhattan distance between the ending point of the inter-chip interconnection line and the inter-chip interconnection structure, and L0 is the Manhattan distance between the starting point and the ending point of the inter-chip interconnection line.

[0120] In one possible implementation, the allocation unit 903 performs the following processing: constructing a cost matrix based on cost information, where the element in the i-th row and j-th column of the cost matrix represents the cost of the j-th inter-chip interconnect when the i-th inter-chip interconnect structure is allocated to the j-th inter-chip interconnect; constructing a Boolean matrix, where the number of rows in the Boolean matrix equals the number of rows in the cost matrix, and the number of columns in the Boolean matrix equals the number of columns in the cost matrix; and constructing a cost function min∑ based on the cost matrix and the Boolean matrix. i ∑ j C i, j X i,j , where C i,j The element X in the i-th row and j-th column of the cost matrix. i,j The element in the i-th row and j-th column of a Boolean matrix is ​​defined if and only if the i-th inter-chip interconnect structure is assigned to the j-th inter-chip interconnect. i,j =1; By solving the cost function, the target Boolean matrix is ​​obtained; Based on the target Boolean matrix, the allocation result of the inter-chip interconnection structure is determined.

[0121] In one possible implementation, the first determining unit 901 performs the following processing: obtaining netlists for two chips; dividing the netlists into a first subnetlist and a second subnetlist, the first subnetlist corresponding to the first chip and the second subnetlist corresponding to the second chip; determining, based on the first and second subnetlists, whether the number of inter-chip interconnects between the first and second chips is less than or equal to the number of inter-chip interconnect structures; if the number of inter-chip interconnects between the first and second chips is greater than the number of inter-chip interconnect structures, then re-dividing the netlists until the number of inter-chip interconnects between the first and second chips is less than or equal to the number of inter-chip interconnect structures; if the number of inter-chip interconnects between the first and second chips is less than or equal to the number of inter-chip interconnect structures, then determining the inter-chip interconnects between the first and second chips as multiple inter-chip interconnects.

[0122] In one possible implementation, the inter-chip interconnect structure includes through-silicon vias, microbumps, or copper bonding.

[0123] It should be noted that the inter-chip interconnect structure allocation device in this embodiment is used to implement the corresponding inter-chip interconnect structure allocation method in the aforementioned method embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0124] electronic devices

[0125] Figure 10 This is a schematic block diagram of an electronic device provided in an embodiment of this disclosure. Specific embodiments of this disclosure do not limit the specific implementation of the electronic device. Figure 10 As shown, the electronic device may include: a processor 1002, a communications interface 1004, a memory 1006, and a communication bus 1008. Wherein:

[0126] The processor 1002, communication interface 1004, and memory 1006 communicate with each other via communication bus 1008.

[0127] Communication interface 1004 is used to communicate with other electronic devices or servers.

[0128] The processor 1002 is used to execute program 1010, which can specifically execute the relevant steps in any of the aforementioned embodiments of the inter-chip interconnection structure allocation method.

[0129] Specifically, program 1010 may include program code that includes computer operation instructions.

[0130] The processor 1002 may be a CPU, an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure. The smart device may include one or more processors of the same type, such as one or more CPUs; or it may include processors of different types, such as one or more CPUs and one or more ASICs.

[0131] RISC-V is an open-source instruction set architecture based on the Reduced Instruction Set Computing (RISC) principle. It can be applied to various aspects such as microcontrollers and FPGA chips, and can be specifically applied to fields such as IoT security, industrial control, mobile phones, and personal computers. Because it was designed with small size, speed, and low power consumption in mind, it is particularly suitable for modern computing devices such as warehouse-scale cloud computers, high-end mobile phones, and tiny embedded systems.

[0132] The computer operation instructions in this embodiment can be computer operation instructions based on the RISC-V instruction set architecture. Correspondingly, the processor 1002 can be designed based on the RISC-V instruction set. Specifically, the processor chip in the electronic device provided in this embodiment can be a chip designed using the RISC-V instruction set. This chip can execute executable code based on the configured instructions, thereby implementing the inter-chip interconnect structure allocation method in the above embodiments.

[0133] Memory 1006 is used to store program 1010. Memory 1006 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0134] Specifically, program 1010 can be used to cause processor 1002 to execute the inter-chip interconnect structure allocation method in any of the foregoing embodiments.

[0135] The specific implementation of each step in program 1010 can be found in the corresponding steps and units described in the aforementioned embodiments of the inter-chip interconnection structure allocation method, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the aforementioned method embodiments, and will not be repeated here.

[0136] The electronic device according to embodiments of this disclosure determines multiple inter-chip interconnects and multiple inter-chip interconnect structures. Cost information is then determined based on these interconnects, including the cost of allocating different inter-chip interconnect structures to the interconnects. The allocation result of the inter-chip interconnect structures is then determined based on the cost information, minimizing the total cost of each interconnect when allocating inter-chip interconnect structures according to the allocation result. Since the cost of an inter-chip interconnect can indicate the negative impact of the allocation of inter-chip interconnect structures on chip performance, the allocation of inter-chip interconnect structures to each interconnect can be based on the cost information including each cost, minimizing the total negative impact on chip performance corresponding to each interconnect and ensuring chip performance.

[0137] Computer storage media

[0138] This disclosure also provides a computer-readable storage medium storing instructions for causing a machine to perform the inter-chip interconnect architecture allocation method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0139] In this case, the program code read from the storage medium can itself implement the function of any of the above embodiments, and therefore the program code and the storage medium storing the program code constitute a part of this disclosure.

[0140] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0141] Computer program products

[0142] This disclosure also provides a computer program product, including computer instructions that instruct a computing device to perform any corresponding operation in the above-described plurality of method embodiments.

[0143] It should be understood that the various embodiments in this description are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0144] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0145] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0146] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A method for allocating inter-chip interconnect structures, comprising: Multiple inter-chip interconnects and multiple inter-chip interconnect structures are defined, wherein the start and end points of the inter-chip interconnects are located on two vertically stacked chips, and the start and end points of the inter-chip interconnects are electrically connected through the inter-chip interconnect structures. Based on the plurality of inter-chip interconnects and the plurality of inter-chip interconnect structures, cost information is determined, the cost information including the cost of the inter-chip interconnect when different inter-chip interconnect structures are assigned to the inter-chip interconnect, the cost of the inter-chip interconnect being determined based on the line length increment of the inter-chip interconnect when the inter-chip interconnect structure is assigned to the inter-chip interconnect; Based on the cost information, the allocation result of the inter-chip interconnect structure is obtained, and the allocation result minimizes the total cost of the multiple inter-chip interconnects.

2. The method according to claim 1, wherein, The cost of allocating the inter-chip interconnect structure to the inter-chip interconnect line is equal to the increase in the length of the inter-chip interconnect line when the inter-chip interconnect structure is allocated to the inter-chip interconnect line.

3. The method according to claim 1, wherein, The step of determining cost information based on the plurality of inter-chip interconnects and the plurality of inter-chip interconnect structures includes: Based on the timing information of the two chips, determine the worst-case condition for at least one inter-chip interconnect signal transmitted through the inter-chip interconnect. The weight corresponding to the inter-chip interconnect is determined based on the worst-case condition corresponding to the inter-chip interconnect. The product of the incremental length of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect and the weight corresponding to the inter-chip interconnect is determined as the cost of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect. Obtain the cost information, which includes multiple costs corresponding to each of the inter-chip interconnects.

4. The method according to claim 2 or 3, wherein, When the inter-chip interconnect structure is assigned to the inter-chip interconnect line, the line length increment of the inter-chip interconnect line is equal to L1 + L2 - L0, where L1 is the Manhattan distance between the starting point of the inter-chip interconnect line and the inter-chip interconnect structure, L2 is the Manhattan distance between the ending point of the inter-chip interconnect line and the inter-chip interconnect structure, and L0 is the Manhattan distance between the starting point and the ending point of the inter-chip interconnect line.

5. The method according to claim 1, wherein, The step of obtaining the allocation result of the inter-chip interconnect structure based on the cost information includes: A cost matrix is ​​constructed based on the cost information. The element in the i-th row and j-th column of the cost matrix is ​​the cost of the j-th inter-chip interconnect when the i-th inter-chip interconnect structure is allocated to the j-th inter-chip interconnect. Construct a Boolean matrix such that the number of rows in the Boolean matrix is ​​equal to the number of rows in the cost matrix, and the number of columns in the Boolean matrix is ​​equal to the number of columns in the cost matrix; Based on the cost matrix and the Boolean matrix, construct the cost function min∑ i ∑ j C i,j X i,j , where C i,j X represents the element in the i-th row and j-th column of the cost matrix. i,j The element in the i-th row and j-th column of the Boolean matrix is ​​defined if and only if the i-th inter-chip interconnect structure is assigned to the j-th inter-chip interconnect. i,j =1; The target Boolean matrix is ​​obtained by solving the cost function. The allocation result of the inter-chip interconnect structure is determined based on the target Boolean matrix.

6. The method according to claim 1, further comprising: Obtain the netlists of the two chips; The netlist is divided into a first subnetlist and a second subnetlist, where the first subnetlist corresponds to the first chip of the two chips and the second subnetlist corresponds to the second chip of the two chips. Based on the first subnet list and the second subnet list, determine whether the number of inter-chip interconnects between the first chip and the second chip is less than or equal to the number of inter-chip interconnect structures; If the number of inter-chip interconnects between the first chip and the second chip is greater than the number of inter-chip interconnect structures, the netlist is re-divided until the number of inter-chip interconnects between the first chip and the second chip is less than or equal to the number of inter-chip interconnect structures. If the number of inter-chip interconnects between the first chip and the second chip is less than or equal to the number of inter-chip interconnect structures, then the inter-chip interconnects between the first chip and the second chip are defined as the plurality of inter-chip interconnects.

7. The method according to any one of claims 1-3 and 5-6, wherein, The inter-chip interconnect structure includes through-silicon vias, microbumps, or copper bonding.

8. An inter-chip interconnection structure allocation device, comprising: A first determining unit is used to determine multiple inter-chip interconnects and multiple inter-chip interconnect structures, wherein the starting point and the ending point of the inter-chip interconnects are respectively located on two vertically stacked chips, and the starting point and the ending point of the inter-chip interconnects are electrically connected through the inter-chip interconnect structures. The second determining unit is configured to determine cost information based on the plurality of inter-chip interconnects and the plurality of inter-chip interconnect structures. The cost information includes the cost of the inter-chip interconnect when different inter-chip interconnect structures are allocated to the inter-chip interconnect. The cost of the inter-chip interconnect is determined based on the line length increment of the inter-chip interconnect when the inter-chip interconnect structure is allocated to the inter-chip interconnect. An allocation unit is configured to obtain an allocation result of the inter-chip interconnect structure based on the cost information, wherein the allocation result minimizes the total cost of the plurality of inter-chip interconnects.

9. An electronic device, comprising: The processor, the communication interface, the memory, and the communication bus communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the inter-chip interconnect structure allocation method as described in any one of claims 1-7.

10. A computer-readable storage medium storing computer instructions that, when executed by a processor, cause the processor to perform the method of any one of claims 1-7.

11. A computer program product tangibly stored on a computer-readable medium and comprising computer-executable instructions that, when executed, cause at least one processor to perform the method according to any one of claims 1-7.

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