A memory-compute integrated circuit and coding and decoding method

Abstract

The application discloses a storage-computation integrated circuit and a coding and decoding method, and relates to the technical field of electronic circuits and signal processing, to solve the problem of high data cache energy consumption of the storage-computation integrated circuit in the prior art. The circuit at least comprises a Huffman digital-to-analog conversion unit, a storage unit and a Huffman analog-to-digital conversion unit; one end of the storage unit is connected with the Huffman digital-to-analog conversion unit, and the other end of the storage unit is connected with the Huffman analog-to-digital conversion unit; the Huffman digital-to-analog conversion unit is used for receiving first digital quantity data and converting the first digital quantity data into first analog quantity data and inputting the first analog quantity data into the storage unit; the storage unit is used for storing the weight of a neural network in the form of analog impedance and realizing the multiplication and accumulation calculation of the first analog quantity data and the weight data in a matrix; and the Huffman analog-to-digital conversion unit is used for receiving second analog quantity data and converting the second analog quantity data into second digital quantity data and outputting the second digital quantity data; and the energy consumption of data cache in the circuit array is reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic circuits and signal processing technology, and in particular to a memory computing circuit and encoding / decoding method. Background Technology

[0002] In the calculation of a circuit array structure that integrates analog and in-memory computing to realize multiplication and accumulation calculation, the weights of the neural network can be stored in the storage unit in the form of analog impedance. The input data is converted into analog voltage or current signals by a DAC (Digital to Analog Converter). According to the IV characteristics of the device, the product of the input data and the weights is obtained and expressed on the bit line in the form of voltage or current. Then, the summation in the analog domain is achieved by current convergence or charge sharing on the bit line. The result is converted into a digital signal output by an ADC (Analog to Digital Converter).

[0003] Traditional in-memory computing (CIM) chips still face several challenges in achieving high system-level energy efficiency in diverse applications such as neural networks (NNs) and recommendation systems (RecSys). For example, traditional CIM chips represent each value with the maximum bit width, resulting in large data caching overhead for the CIM array. Consequently, when the system SRAM accesses data in the array, the energy efficiency of the CIM array can be reduced to below 40%, affecting the computational efficiency of the CIM chip.

[0004] Therefore, it is urgent to design a more advanced in-memory computing circuit and encoding / decoding method to solve the problem of high energy consumption of data caching in in-memory computing circuits. Summary of the Invention

[0005] The purpose of this invention is to provide a memory computing circuit and encoding / decoding method. Based on the Huffman tree, the circuits corresponding to the Huffman digital-to-analog converter and the Huffman analog-to-digital converter are designed. In the circuit, the minimum bit width is used to represent the minimum absolute value data in the neural network parameters, which reduces the bit width ratio of the written data in the memory computing chip, thereby reducing the data buffer overhead of the memory computing circuit and solving the problem of high energy consumption of data cache in the memory computing circuit.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] In a first aspect, the present invention provides a memory computing circuit, which may include at least:

[0008] Huffman analog-to-digital converter unit, storage unit, and Huffman analog-to-digital converter unit;

[0009] One end of the storage unit is connected to the Huffman analog-to-digital converter unit, and the other end of the storage unit is connected to the Huffman analog-to-digital converter unit.

[0010] The circuit corresponding to the Huffman digital-to-analog converter unit is a Huffman tree decoding circuit; the Huffman digital-to-analog converter unit is used to receive first digital data and convert the first digital data into first analog data and input it into the storage unit.

[0011] The storage unit is used to store the weights of the neural network in the form of analog impedance, and to perform multiplication and accumulation calculation of the first analog data and the weight data within the matrix.

[0012] The circuit corresponding to the Huffman analog-to-digital converter unit is a Huffman tree encoding circuit; the Huffman analog-to-digital converter unit is used to receive the second analog data and convert the second analog data into the second digital data for output.

[0013] Preferably, the Huffman digital-to-analog converter unit may include a plurality of first Huffman digital-to-analog converter sub-units; the circuit corresponding to the plurality of first Huffman digital-to-analog converter sub-units is composed of an incomplete binary tree decoding circuit and a plurality of non-uniformly distributed resistors; the plurality of non-uniformly distributed resistors are connected in series in the leaf nodes of the incomplete binary tree decoding circuit.

[0014] The storage unit includes multiple data storage sub-paths; the input ends of the multiple data storage sub-paths are respectively connected to multiple first Huffman digital-to-analog converter sub-units.

[0015] Preferably, the Huffman analog-to-digital converter unit may include multiple Huffman analog-to-digital converter subunits;

[0016] The plurality of Huffman analog-to-digital converter subunits include at least a sample-and-hold circuit, a comparator, a second Huffman digital-to-analog converter subunit, and a Huffman tree search unit;

[0017] One end of the sample-and-hold circuit is connected to the output of the data storage sub-path, and the other end of the sample-and-hold circuit is connected to the first input of the comparator; the input of the second Huffman digital-to-analog converter sub-unit is connected to the Huffman tree search unit, and the output of the second Huffman digital-to-analog converter sub-unit is connected to the second input of the comparator; the output of the comparator is connected to the input of the Huffman tree search unit, and the Huffman tree search unit is connected to the digital output.

[0018] Preferably, the first digital data is data compressed and encoded using a preset compression method, and the preset compression method may include at least one of Huffman coding, non-uniform quantization coding, run-length encoding, and LZW coding.

[0019] Preferably, the weight data in the storage unit is uncompressed data.

[0020] Secondly, the present invention provides a memory-based encoding and decoding method, wherein the method is applied to a memory-based circuit, the circuit including at least a Huffman digital-to-analog converter unit, a storage unit, and a Huffman analog-to-digital converter unit; the method may include:

[0021] Acquire the first digital data; the first digital data is binary data.

[0022] The first digital data is decoded using the Huffman digital-to-analog converter unit to obtain the first analog data; the circuit corresponding to the Huffman digital-to-analog converter unit is a Huffman tree decoding circuit.

[0023] The storage unit is used to perform a multiplication and accumulation calculation on the first analog data and the weight data to obtain the second analog data.

[0024] The second analog data is encoded using a Huffman analog-to-digital converter to obtain the second digital data; the circuit corresponding to the analog-to-digital converter is a Huffman tree encoding circuit.

[0025] Output the second digital data.

[0026] Preferably, the step of decoding the first digital data using the Huffman digital-to-analog converter to obtain the first analog data may include:

[0027] The decoding operation begins from the root node of the Huffman digital-to-analog converter unit;

[0028] If the first digital value is 0, then search for the left subtree of the Huffman digital-to-analog converter unit;

[0029] If the first digital value is 1, then search for the right subtree of the Huffman digital-to-analog converter unit;

[0030] When the leaf node of the Huffman digital-to-analog converter is reached, the first target leaf node is obtained;

[0031] The analog signal represented by the first target leaf node is used as the first analog data.

[0032] Preferably, the step of encoding the second analog data using a Huffman analog-to-digital converter to obtain the second digital data may include:

[0033] The initial digital code for Huffman tree search in the Huffman tree search module of the Huffman analog-to-digital conversion unit is set, and the initial digital code is the code corresponding to the middle leaf node of the Huffman tree in the corresponding digital-to-analog conversion unit.

[0034] Based on the initial digital encoding, the Huffman tree search module is used to perform a data search on the second analog data to obtain the target leaf node;

[0035] The target leaf node is converted from digital to analog using the second Huffman digital-to-analog converter subunit to obtain the target feedback voltage;

[0036] The second digital data is obtained based on the analog voltage corresponding to the second analog data and the target feedback voltage.

[0037] Preferably, obtaining the second digital data based on the analog voltage corresponding to the second analog data and the target feedback voltage may include:

[0038] The analog voltage corresponding to the second analog quantity data is compared with the target feedback voltage to obtain the comparison result;

[0039] If the comparison result indicates that the analog voltage corresponding to the second analog data is equal to the target feedback voltage, then the digital data corresponding to the initial digital code is determined as the second digital data;

[0040] If the comparison result indicates that the analog voltage corresponding to the second analog data is greater than the target feedback voltage, then the search proceeds to the right subtree of the Huffman digital-to-analog converter subunit to obtain the first target digital code; if the comparison result indicates that the input voltage corresponding to the second analog data is less than the target feedback voltage, then the search proceeds to the left subtree of the Huffman digital-to-analog converter subunit to obtain the second target digital code; until the voltage corresponding to the target digital code determined by the Huffman tree search module is close to the analog voltage corresponding to the second analog data, then the digital data corresponding to the target digital code is determined as the second digital data.

[0041] Preferably, the step of using the storage unit to perform multiplication and accumulation calculations on the first analog data and the weight data to obtain the second analog data may include:

[0042] Based on the matrix circuit in the storage unit, the first analog data and the weight data are multiplied and accumulated to obtain the second analog data; the matrix circuit is a circuit that forms the weights of the neural network in the form of analog impedance.

[0043] Compared with the prior art, the present invention provides a memory-in-memory circuit, which includes at least a Huffman digital-to-analog converter (DAC), a storage unit, and a Huffman analog-to-digital converter (ADC). One end of the storage unit is connected to the Huffman DAC, and the other end of the storage unit is also connected to the Huffman ADC. The circuit corresponding to the Huffman DAC is a Huffman tree decoding circuit. The Huffman DAC receives first digital data and converts it into first analog data, which is then input to the storage unit. The storage unit stores the weights of the neural network in the form of analog impedance, and performs multiplication and accumulation calculations between the first analog data and the weight data within the matrix. The circuit corresponding to the Huffman DAC is a Huffman tree encoding circuit. The unit is used to receive the second analog data and convert it into the second digital data for output. Based on this, a Huffman digital-to-analog converter and a Huffman analog-to-digital converter designed based on a Huffman tree can be used to represent the minimum absolute value data in the neural network parameters with the minimum bit width in their corresponding circuits. This reduces the bit width ratio of the written data in the in-memory computing chip and avoids the problem of large data cache overhead of the in-memory computing array caused by representing each value with the maximum bit width. This reduces the data buffer overhead of the in-memory computing circuit and solves the problem of high energy consumption of data cache in traditional in-memory computing circuits. Furthermore, it can also avoid the problem of the in-memory computing array's energy efficiency dropping too low when the system SRAM accesses data in the array, which affects the computing efficiency of the in-memory computing chip. Attached Figure Description

[0044] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0045] Figure 1 This is a schematic diagram of a traditional analog in-memory computing circuit.

[0046] Figure 2 A schematic diagram of a memory computing circuit provided by the present invention;

[0047] Figure 3 A schematic diagram of the Huffman tree coding structure;

[0048] Figure 4 A schematic diagram of the decoding tree structure of a Huffman digital-to-analog converter subunit in a memory computing circuit provided by the present invention;

[0049] Figure 5 A schematic diagram of the decoding circuit structure of the Huffman digital-to-analog converter subunit in an in-memory computing circuit provided by the present invention;

[0050] Figure 6A schematic diagram of the circuit structure of a Huffman analog-to-digital converter subunit in a memory computing circuit provided by the present invention;

[0051] Figure 7 A schematic diagram of the main process of an in-memory computing encoding and decoding method provided by the present invention;

[0052] Figure 8 A schematic diagram illustrating the process of matrix-vector multiplication in a storage unit within a memory-computing circuit provided by this invention.

[0053] Figure 9 This is a schematic diagram illustrating the application process of the in-memory computing circuit and encoding / decoding method provided by the present invention.

[0054] Reference numerals: 210-Huffman analog-to-digital converter unit, 220-Storage unit, 230-Huffman analog-to-digital converter unit, 211-First Huffman analog-to-digital converter subunit, 231-Huffman analog-to-digital converter subunit, 2311-Sample-and-hold circuit, 2312-Comparator, 2313-Second Huffman analog-to-digital converter subunit, 2314-Huffman tree search unit. Detailed Implementation

[0055] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and the terms "first" and "second" are not necessarily different.

[0056] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0057] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0058] Existing circuit array structures for analog in-memory computing to perform multiplication and accumulation calculations, such as Figure 1 As shown, Figure 1 This is a schematic diagram of a traditional analog in-memory computing circuit. Figure 1 In this circuit, the input vectors X1, X2, and X3 are analog quantities without data compression. During computation, the weights of the neural network are stored in the storage unit in the form of analog impedance. The input data is converted into analog voltage or current signals by a DAC. Based on the IV characteristics of the device, the product of the input data and the weights is obtained and expressed as voltage or current on the bit line. Then, the analog domain is summed through current convergence or charge sharing on the bit line. Finally, the result is converted into digital signals Y1, Y2, and Y3 by an ADC for output. Similarly, because the input vector at the DAC input is an analog quantity without data compression, the digital signal output at the ADC output is also a digital quantity without data compression. This will inevitably lead to an increase in the buffer size in the circuit array.

[0059] Furthermore, in Figure 1 In the circuit array structure shown, each value is represented by the maximum bit width; for example, the value "100" is represented by a 3-bit bit width, and the value "11" is also represented by a 3-bit bit width. This results in a large amount of bit width being occupied in the computing array when writing large amounts of data, further increasing the amount of data cache. Therefore, how to reduce the amount of data cache to improve the computing efficiency of the computing array is one of the main challenges at present. Furthermore, when the system-level SRAM accesses the computing array, it will reduce its energy efficiency to below 40%, which will also seriously affect the computing efficiency of the in-memory computing chip.

[0060] In view of this, the present invention provides a memory computing circuit and encoding / decoding method. Based on the Huffman tree, the circuits corresponding to the Huffman digital-to-analog converter and the Huffman analog-to-digital converter are designed. In the circuit, the minimum bit width is used to represent the minimum absolute value data in the neural network parameters, which reduces the bit width ratio of the written data in the memory computing chip, thereby reducing the data buffering overhead of the memory computing circuit. Furthermore, the input data vector is also a compressed analog data, which reduces the size of intermediate data, thereby further reducing the data buffering overhead of the memory computing circuit. This solves the problems of large data buffering overhead and high power consumption in the existing memory computing circuits.

[0061] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings:

[0062] In one feasible embodiment, please refer to Figure 2 , Figure 2 This is a schematic diagram of a memory-based computing circuit provided by the present invention. It should be noted that, in this embodiment, the Huffman digital-to-analog converter (DAC), storage unit, and Huffman analog-to-digital converter (ADC) each include three data encoding / decoding paths. Specifically, the Huffman DAC 210 may include multiple first Huffman DAC subunits 211; the number of storage paths in its storage unit 220 and the number of Huffman ADC subunits 231 correspond to the number of first Huffman DAC subunits 211. In practical applications, the encoding / decoding paths can be set according to actual conditions; for example, the number of channels can be set to 3, 5, 8, or 10, etc.; no specific limitation is made in this invention.

[0063] exist Figure 2 In the in-memory computing circuit, at least the following can be included: Huffman digital-to-analog converter 210, storage unit 220 and Huffman analog-to-digital converter 230. Figure 2X1-C, X2-C, and X3-C are the digital data input to the Huffman analog-to-digital converter unit 210. This digital data is a compressed input vector, which is respectively input to the three first Huffman analog-to-digital converter subunits 211. X1, X2, and X3 are the analog data after analog-to-digital conversion by the three first Huffman analog-to-digital converter subunits 211. Y1, Y2, and Y3 are the output vectors after weight calculation on the three storage paths of the storage unit 220, which are respectively output to the Huffman analog-to-digital converter. The conversion unit 230 has three Huffman analog-to-digital conversion sub-units 231; Wi represents the weight corresponding to the i-th analog impedance, such as W11, W12 and W13, which are the weights corresponding to the three analog impedances in the first row; Y1-C, Y2-C and Y3-C are the digital data after analog-to-digital conversion by the Huffman analog-to-digital conversion sub-unit 231; because the input digital data is a compressed input vector, the digital data after analog-to-digital conversion by the Huffman analog-to-digital conversion sub-unit 231 is still a compressed output vector.

[0064] Specifically, one end of storage unit 220 can be connected to Huffman digital-to-analog converter unit 210, and the other end of storage unit 220 can be connected to Huffman analog-to-digital converter unit 230. The circuit corresponding to Huffman digital-to-analog converter unit 210 is a Huffman tree decoding circuit; Huffman digital-to-analog converter unit 210 is used to receive first digital data and convert it into first analog data, which is then input to storage unit 220; the first digital data is a compressed input vector. That is, the data after compression decoding by DAC is used as analog domain input data Xi, and Xi is input to storage unit 220. The multiplication and accumulation result of Xi and Wi is input to compression encoding ADC for encoding, and finally, compressed data is output. The first digital data is data compressed and encoded using a preset compression method, which includes at least one of Huffman encoding, non-uniform quantization encoding, run-length encoding, and LZW encoding.

[0065] Furthermore, the storage unit 220 is used to store the weights of the neural network in the form of analog impedance, and to perform the multiplication and accumulation calculation of the first analog data and the weight data within the matrix. Figure 2 In this context, Wi represents i resistors that represent the weights of the neural network as analog impedances. The weight data in the in-memory computing array can be uncompressed data. Preferably, the weight data in the storage unit is uncompressed data.

[0066] Furthermore, the circuit corresponding to the Huffman analog-to-digital converter unit 230 is a Huffman tree encoding circuit; the Huffman analog-to-digital converter unit 230 is used to receive the second analog data and convert the second analog data into a second digital data output; the second digital data is a compressed output vector.

[0067] It's important to explain the principle of Huffman coding: Huffman coding is an entropy coding algorithm for variable-length lossless data compression, typically used to compress character data with a high repetition rate. During communication transmission, data is represented in binary form (0s and 1s). To improve transmission speed, data compression is usually performed; simultaneously, it's crucial to ensure the encoding is unambiguous. Huffman coding meets these requirements, achieving a superior encoding method. Its principle involves constructing a Huffman tree from the bottom up based on the frequency of data occurrences.

[0068] For example, the data ABCDE and their corresponding probabilities can be represented as (A,2), (B,4), (C,3), (D,1), (E,3); using a Huffman tree for encoding, we can obtain... Figure 3 The Huffman number shown; please refer to [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of a Huffman tree encoding structure. Figure 3 In this diagram, LT represents the left subtree of the Huffman tree, RT represents the right subtree, and LN represents the leaf node of the Huffman tree. Figure 3 It can be seen that (D,1) and (A,2) occupy 3 bits of bit width, while (C,3), (E,3) and (B,4) occupy 2 bits of bit width. This shows that if Huffman tree encoding is used, the data obtained can be represented by different bit widths, which can avoid the problem of large data cache overhead in the in-memory computing array caused by representing all data with the maximum bit width in the existing technology.

[0069] Based on this, the present invention provides an in-memory computing circuit that utilizes a Huffman analog-to-digital converter (A / D) and a Huffman analog-to-digital converter (A / D) based on a Huffman tree design. In their corresponding circuits, the minimum absolute value data in the neural network parameters is represented with the minimum bit width. This reduces the bit width ratio of the written data in the in-memory computing chip, avoiding the problem of high data cache overhead in the in-memory computing array caused by representing each value with the maximum bit width. This reduces the data buffer overhead of the in-memory computing circuit and solves the problem of high energy consumption in traditional in-memory computing circuits. Furthermore, the input and output data of the in-memory computing array are compressed, reducing the amount of intermediate data compared to existing technologies, which can further reduce data cache and transmission latency. It also avoids the problem of excessively low energy efficiency of the in-memory computing array affecting the computing efficiency of the in-memory computing chip when the system SRAM accesses data in the array.

[0070] Preferably, the Huffman digital-to-analog converter unit 210 includes multiple first Huffman digital-to-analog converter sub-units 211; the circuit corresponding to the multiple first Huffman digital-to-analog converter sub-units 211 consists of an incomplete binary tree decoding circuit and multiple non-uniformly distributed resistors; the multiple non-uniformly distributed resistors are connected in series in the leaf nodes of the incomplete binary tree decoding circuit. The storage unit 220 includes multiple data storage sub-paths; the input terminals of the multiple data storage sub-paths are respectively connected to the multiple first Huffman digital-to-analog converter sub-units 211. This enables the compressed input vector to be decoded and then input to the storage unit.

[0071] In one example, please refer to Figure 4 and Figure 5 , Figure 4 A schematic diagram of the decoding tree structure of a Huffman digital-to-analog converter subunit in a memory computing circuit provided by the present invention; Figure 5 This invention provides a schematic diagram of the decoding circuit structure of a Huffman digital-to-analog converter subunit in an in-memory computing circuit.

[0072] exist Figure 4 The corresponding Huffman tree design structure is the design logic of one of the DAVs in the Huffman digital-to-analog converter (DAC), and its analog voltage data are: 0.1, 0.15, 0.22, 0.34 and 0.52; the probabilities corresponding to these analog voltage data are 4, 3, 3, 2 and 1, respectively.

[0073] The Huffman digital-to-analog converter (DAC) decodes the input data, starting from the root node. If the value is 0, it searches the left subtree; if it's 1, it searches the right subtree. When a leaf node is reached, the corresponding analog signal is output. Figure 4 The analog voltages can be obtained by searching the analog voltage data. The analog voltages 0.1, 0.15, and 0.22 occupy 2 bits each, while the analog voltages 0.34 and 0.52 occupy 3 bits each. Therefore, it is clear that the Huffman digital-to-analog converter unit provided by this invention represents small absolute value data with a small bit width and arranges the leaf nodes in numerical order. Compared to existing neural network parameter probabilities, which generally follow a bell-shaped distribution (smaller absolute values ​​have a higher probability of occurrence, while larger absolute values ​​have a lower probability), the circuit structure of the Huffman digital-to-analog converter unit provided by this invention not only reduces the data buffer overhead of the circuit but also simplifies the circuit design.

[0074] For further information, please refer to [link / reference]. Figure 5 , Figure 5 For based on Figure 4The Huffman code shown is the circuit structure corresponding to the designed Huffman digital-to-analog converter unit. This circuit consists of an incomplete binary tree decoding circuit and non-uniformly distributed series resistors, so that the binary tree decoding circuit can be controlled by the input digital signal to select the corresponding output voltage. Figure 5 In the diagram, Vout represents the output terminal of the circuit, which is the root node of the circuit corresponding to the Huffman digital-to-analog converter unit; LN represents the leaf node of the circuit corresponding to the Huffman digital-to-analog converter unit; and Ri represents multiple non-uniformly distributed resistors.

[0075] Specifically, an incomplete binary tree refers to a tree structure where each node has at most two child nodes, but not all nodes must have two child nodes. In decoding circuit design, this structure provides a more flexible implementation than a complete binary tree, allowing some nodes to have only one child node or no child nodes, thereby reducing unnecessary nodes, optimizing circuit area, and is particularly suitable for asymmetric decoding requirements; for example, the circuit corresponding to a Huffman tree structure. Compared to a complete binary tree, an incomplete binary tree can save 15-30% of the number of logic gates, has high resource efficiency, and the critical path may be shorter, increasing the operating frequency; it is also particularly suitable for non-uniformly distributed input patterns. Therefore, the circuit structure corresponding to the Huffman digital-to-analog converter unit in this invention adopts an incomplete binary tree decoding circuit and non-uniformly distributed series resistors, so that the Huffman digital-to-analog converter unit has the advantages of incomplete binary tree decoding circuits in terms of high resource efficiency, delay optimization, and design flexibility, thereby better reducing the data cache overhead of the in-memory computing chip.

[0076] Preferably, the Huffman analog-to-digital converter unit 230 may include multiple Huffman analog-to-digital converter subunits 231. See also... Figure 6 , Figure 6 This is a schematic diagram of the circuit structure of a Huffman analog-to-digital converter subunit in a memory computing circuit provided by the present invention.

[0077] exist Figure 6 In this process, each Huffman analog-to-digital converter subunit 231 may include at least a sample-and-hold circuit 2311, a comparator 2312, a second Huffman digital-to-analog converter subunit 2313, and a Huffman tree search unit 2314.

[0078] Specifically, one end of the sample-and-hold circuit 2311 can be connected to the output of the data storage sub-path, and the other end of the sample-and-hold circuit 2311 can be connected to the first input of the comparator 2312; the input of the second Huffman digital-to-analog converter sub-unit 2313 can be connected to the Huffman tree search unit 2314, and the output of the second Huffman digital-to-analog converter sub-unit 2313 can be connected to the second input of the comparator 2312; the output of the comparator 2312 can be connected to the input of the Huffman tree search unit 2314, and the Huffman tree search unit 2314 can be connected to the digital output. The circuit structure corresponding to the second Huffman digital-to-analog converter sub-unit 2313 can be the same as or different from the circuit structure corresponding to the first Huffman digital-to-analog converter sub-unit 211. The Huffman tree search unit 2314 can at least be used to search the circuit corresponding to the first Huffman digital-to-analog converter subunit 211 according to the digital code determined by the system to obtain the data stored in the leaf nodes of the Huffman tree; the second Huffman digital-to-analog converter subunit 2313 can at least be used to perform digital-to-analog conversion on the data fed back by the Huffman tree search unit 2314 and input the conversion result into the comparator; the comparator 2312 can at least be used to compare the analog data input to the second Huffman digital-to-analog converter subunit 2313 with the analog data input to the sample-and-hold circuit 2311 and output the comparison result; wherein the input data Vin of the sample-and-hold circuit 2311 is the second analog data.

[0079] Based on this, the multiple Huffman analog-to-digital converter subunits 231 in this invention can read data from the storage unit respectively, and after encoding processing, obtain a compressed output vector, and output the compressed output vector digitally; thus realizing that the input and output data of the in-memory computing array are both compressed data, reducing the amount of intermediate data, and further reducing data caching and transmission latency.

[0080] Secondly, the present invention provides a memory-based encoding and decoding method, which is applied to a memory-based circuit, the circuit including at least a Huffman analog-to-digital converter unit 210, a storage unit 220, and a Huffman analog-to-digital converter unit 230. Please refer to [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram of the main flow of an in-memory computing encoding and decoding method provided by the present invention. The execution subject of the method can be a server or an in-memory chip equipped with the in-memory computing encoding and decoding method provided by the present invention.

[0081] exist Figure 7 In this context, the method may include:

[0082] Step 710: Obtain the first digital data; the first digital data is binary data.

[0083] Step 720: Use the Huffman digital-to-analog converter unit to decode the first digital data to obtain the first analog data; the circuit corresponding to the Huffman digital-to-analog converter unit is a Huffman tree decoding circuit.

[0084] In steps 710 to 720, the first digital data is data compressed and encoded using a preset compression method. The preset compression method includes at least one of Huffman coding, non-uniform quantization coding, run-length encoding, and LZW coding; in practical applications, the specific method can be selected based on the data characteristics. Furthermore, the first digital data can be input to a Huffman digital-to-analog converter (DAC), which reduces the amount of intermediate data input to the DAC compared to existing technologies, thus lowering data buffering and data transmission latency. The Huffman DAC decodes the first digital data to obtain the first analog data, which is then input to the storage unit. Because the circuit corresponding to the Huffman DAC is a Huffman tree decoding circuit, the Huffman DAC has the advantage of representing the minimum absolute value data in the neural network parameters with the minimum bit width, reducing the bit width ratio of the written data in the memory computing chip.

[0085] Step 730: Use the storage unit to perform a multiplication and accumulation calculation on the first analog data and the weight data to obtain the second analog data.

[0086] Step 740: Encode the second analog data using a Huffman analog-to-digital converter to obtain the second digital data; the circuit corresponding to the analog-to-digital converter is a Huffman tree encoding circuit.

[0087] Step 750: Output the second digital data.

[0088] In steps 730 to 750, after receiving the first analog data, the storage unit performs multiplication and accumulation calculations on Xi and Wi in the first analog data to obtain the second analog data; finally, the second digital data is obtained by compression encoding in the Huffman analog-to-digital converter (ADC) and output. Since the first digital data is compressed, the second digital data is also compressed; and the circuit corresponding to the ADC is a Huffman tree encoding circuit, which also has the advantages of Huffman tree encoding, such as data compression, low power consumption, and fast transmission speed.

[0089] Based on this, the present invention provides an in-memory computing encoding and decoding method. Based on a Huffman tree, the invention designs circuits corresponding to both a Huffman digital-to-analog converter (DAC) and a Huffman analog-to-digital converter (ADC). The method acquires first digital data; firstly, it decodes the first digital data using the Huffman DAC to obtain first analog data; then, it uses a storage unit to perform multiplication and accumulation calculations with weight data on the first analog data to obtain second analog data; finally, it encodes the second analog data using the Huffman ADC to obtain second digital data; and finally, it outputs the second digital data. This method enables the use of Huffman DACs and ADCs designed based on Huffman trees to represent the minimum absolute value data in the neural network parameters with the minimum bit width in their corresponding circuits. This reduces the bit width ratio of written data in the in-memory computing chip, avoiding the problem of high data cache overhead in the in-memory computing array caused by representing each value with the maximum bit width. This reduces the data buffer overhead of the in-memory computing circuit and solves the problems of high data cache overhead and high power consumption in traditional in-memory computing circuits.

[0090] Preferably, in step 720, that is, decoding the first digital data using the Huffman digital-to-analog converter to obtain the first analog data, the following steps may be taken: starting the decoding operation from the root node of the Huffman digital-to-analog converter; if the first digital value is 0, then searching for the left subtree of the Huffman digital-to-analog converter; if the first digital value is 1, then searching for the right subtree of the Huffman digital-to-analog converter; when the leaf node of the Huffman digital-to-analog converter is reached, the first target leaf node is obtained; and the analog signal represented by the first target leaf node is used as the first analog data.

[0091] For details, please refer to the following: Figure 4 The Huffman DAC decodes the input data, starting from the root node. If the value is 0, it searches the left subtree; if it's 1, it searches the right subtree. When a leaf node is reached, the corresponding analog signal is output. For example, the analog voltage data retrieved from the digital value 00 is 0.1, from 01 is 0.15, from 10 is 0.22, from 110 is 0.34, and from 111 is 0.52. Therefore, the decoding process involves fewer digital values, improving decoding efficiency and reducing data buffering overhead.

[0092] Preferably, in step 730, the first analog data is multiplied and accumulated with the weight data using the storage unit to obtain the second analog data. This may include: multiplying and accumulating the first analog data with the weight data based on the matrix circuit in the storage unit to obtain the second analog data; the matrix circuit is a circuit that forms the weights of the neural network in the form of analog impedances.

[0093] For details, please refer to Figure 8 , Figure 8 This is a schematic diagram illustrating the process of matrix-vector multiplication in a storage unit within a memory-computing circuit provided by the present invention.

[0094] exist Figure 8 In this diagram, X1-C, X2-C, and X3-C represent the first digital data, which are compressed input vectors; X1, X2, and X3 represent the first analog data, which are analog data decoded by multiple Huffman analog-to-digital converter subunits; Wi (W11, W12, W13, W21, W22, W23, W31, W32, W33...) represent weight data stored in the storage unit in the form of analog impedance; Y1, Y2, and Y3 represent the second analog data, which are analog data obtained by multiplying and accumulating the first analog data with the weight data in the storage unit; and Y1-C, Y2-C, and Y3-C represent the second digital data, which are digital data obtained after encoding by multiple Huffman analog-to-digital converter subunits.

[0095] For example, the storage path of its storage unit may include a first storage path, a second storage path, and a third storage path.

[0096] The calculation processes are as follows: In the first storage path, Y1 = X1*W11 + X2*W21 + X3*W31; in the second storage path, Y2 = X1*W12 + X2*W22 + X3*W32; in the third storage path, Y3 = X1*W13 + X2*W23 + X3*W33.

[0097] Based on this, the present invention provides a storage-computing integrated encoding and decoding method that utilizes storage units to realize the storage-computing integrated matrix-vector multiplication and accumulation calculation.

[0098] Preferably, in step 740, encoding the second analog data using the Huffman analog-to-digital converter to obtain the second digital data may include: setting an initial digital code for Huffman tree search in the Huffman tree search module of the Huffman analog-to-digital converter, wherein the initial digital code is the code corresponding to the intermediate leaf node of the corresponding Huffman tree in the digital-to-analog converter; based on the initial digital code, performing a data search on the second analog data using the Huffman tree search module to obtain the target leaf node; performing digital-to-analog conversion on the target leaf node using the second Huffman digital-to-analog converter subunit to obtain the target feedback voltage; and obtaining the second digital data based on the analog voltage corresponding to the second analog data and the target feedback voltage.

[0099] Specifically, obtaining second digital data based on the analog voltage corresponding to the second analog data and the target feedback voltage may include: comparing the analog voltage corresponding to the second analog data with the target feedback voltage to obtain a comparison result.

[0100] (1) If the comparison result indicates that the analog voltage corresponding to the second analog data is equal to the target feedback voltage, then the digital data corresponding to the initial digital code is determined as the second digital data.

[0101] (2) If the comparison result indicates that the analog voltage corresponding to the second analog data is greater than the target feedback voltage, then search the right subtree of the Huffman digital-to-analog converter subunit to obtain the first target digital code; if the comparison result indicates that the input voltage corresponding to the second analog data is less than the target feedback voltage, then search the left subtree of the Huffman digital-to-analog converter subunit to obtain the second target digital code; until the voltage corresponding to the target digital code determined by the Huffman tree search module is close to the analog voltage corresponding to the second analog data, then the digital data corresponding to the target digital code is determined as the second digital data.

[0102] For examples, please refer to the following: Figure 5 , Figure 5 The output voltage terminal is the root node of the incomplete binary tree decoding circuit. Multiple resistors with non-uniform resistance values ​​are connected in series between the leaf nodes of the incomplete binary tree decoding circuit to represent different voltage values. Figure 5The direction marked by the middle arrow indicates the initial digital code for searching the first Huffman analog-to-digital converter subunit. This initial code is 1100. Based on this code, the data corresponding to the leaf node of this code is found and sent to the second Huffman analog-to-digital converter subunit for digital-to-analog conversion to obtain the target feedback voltage. Then, the analog voltage corresponding to the second analog data is compared with the target feedback voltage to obtain the second digital data. That is, Vin is compared with the output voltage Vdac of the second Huffman analog-to-digital converter subunit. If Vin equals Vdac, the digital data of the leaf node corresponding to the initial code 1100 is determined as the second digital data. If Vin is greater than Vdac, the search begins in the right subtree of the next level, and the Huffman code is set to 1111. If Vin is less than Vdac, the search begins in the left subtree of the current branch, and the Huffman code is set to 1101. This process continues until the voltage corresponding to the target digital code determined by the Huffman tree search module is close to the analog voltage corresponding to the second analog data. Then, the digital data corresponding to the target digital code is determined as the second digital data.

[0103] For example, if the digital code after the first step of the search is 10, then the size of Vin and Vdac is further compared. If Vin is greater than Vdac, the search begins in the right subtree of the next level, and the Huffman code is set to 1110. If Vin is less than Vdac, the search begins in the left subtree of the current branch, and the Huffman code is set to 00 or 01. The search continues based on the code set in the second step until the voltage corresponding to the target digital code determined by the Huffman tree search module is close to the analog voltage corresponding to the second analog data. Then, the digital data corresponding to the target digital code is determined as the second digital data.

[0104] In one example, the application of the in-memory computing circuit and encoding / decoding method provided by this invention can be based on... Figure 2 or Figure 8 The circuit shown simulates in-memory computing and can perform matrix multiplication. The compressed calculation result can be further summed, shifted, and accumulated using matrices, avoiding the need for additional encoding and decoding circuits. Please refer to the following documentation. Figure 9 , Figure 9 This is a schematic diagram illustrating the process of shifting and accumulating compressed data in a memory-based computing circuit provided by the present invention.

[0105] exist Figure 9In this approach, to achieve summation, a column in the memory array can be set to data 1. Furthermore, to achieve accumulation of different shifted data, a column in the memory array can be set to 1, 2, 4, 8, etc. (2^n). For example, OUT1 = Y1 + Y2 + Y3; OUT2 = Y1*1 + Y2*2 + Y3*4; OUT3 = Y1*2 + Y2*4 + Y3*8. This allows for improved parallelism and data reuse in on-chip computation through the array, more effectively reducing data cache overhead, data transmission power consumption, and latency in in-memory computing circuit architectures; and solving the problem of high energy consumption in traditional in-memory computing circuit data caches.

[0106] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0107] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A memory computing integrated circuit, characterized in that, At least including: Huffman analog-to-digital converter unit, storage unit, and Huffman analog-to-digital converter unit; One end of the storage unit is connected to the Huffman analog-to-digital converter unit, and the other end of the storage unit is connected to the Huffman analog-to-digital converter unit. The circuit corresponding to the Huffman digital-to-analog converter unit is a Huffman tree decoding circuit. The Huffman digital-to-analog converter unit is used to receive the first digital data and convert the first digital data into the first analog data and input it into the storage unit; The storage unit is used to store the weights of the neural network in the form of analog impedance, and to perform multiplication and accumulation calculation of the first analog data and the weight data within the matrix. The circuit corresponding to the Huffman analog-to-digital converter unit is a Huffman tree encoding circuit; the Huffman analog-to-digital converter unit is used to receive the second analog data and convert the second analog data into the second digital data for output.

2. The circuit as described in claim 1, characterized in that, The Huffman digital-to-analog converter unit includes multiple first Huffman digital-to-analog converter sub-units; the circuits corresponding to the multiple first Huffman digital-to-analog converter sub-units are composed of an incomplete binary tree decoding circuit and multiple non-uniformly distributed resistors; the multiple non-uniformly distributed resistors are connected in series in the leaf nodes of the incomplete binary tree decoding circuit. The storage unit includes multiple data storage sub-paths; the input ends of the multiple data storage sub-paths are respectively connected to multiple first Huffman digital-to-analog converter sub-units.

3. The circuit as described in claim 2, characterized in that, The Huffman analog-to-digital converter unit includes multiple Huffman analog-to-digital converter sub-units; The plurality of Huffman analog-to-digital converter subunits include at least a sample-and-hold circuit, a comparator, a second Huffman digital-to-analog converter subunit, and a Huffman tree search unit; One end of the sample-and-hold circuit is connected to the output of the data storage sub-path, and the other end of the sample-and-hold circuit is connected to the first input of the comparator; the input of the second Huffman digital-to-analog converter sub-unit is connected to the Huffman tree search unit, and the output of the second Huffman digital-to-analog converter sub-unit is connected to the second input of the comparator; the output of the comparator is connected to the input of the Huffman tree search unit, and the Huffman tree search unit is connected to the digital output.

4. The circuit as described in claim 1, characterized in that, The first digital data is data compressed and encoded using a preset compression method, which includes at least one of Huffman coding, non-uniform quantization coding, run-length encoding, and LZW coding.

5. The circuit as described in claim 1, characterized in that, The weight data in the storage unit is uncompressed data.

6. A storage-based encoding and decoding method, characterized in that, The method is applied to a memory-based computing circuit, which includes at least a Huffman analog-to-digital converter, a storage unit, and a Huffman analog-to-digital converter; the method includes: Acquire the first digital data; the first digital data is binary data. The first digital data is decoded using the Huffman digital-to-analog converter unit to obtain the first analog data; the circuit corresponding to the Huffman digital-to-analog converter unit is a Huffman tree decoding circuit. The storage unit is used to perform a multiplication and accumulation calculation on the first analog data and the weight data to obtain the second analog data. The second analog data is encoded using a Huffman analog-to-digital converter to obtain the second digital data; the circuit corresponding to the analog-to-digital converter is a Huffman tree encoding circuit. Output the second digital data.

7. The method as described in claim 6, characterized in that, The step of decoding the first digital data using the Huffman digital-to-analog converter to obtain the first analog data includes: The decoding operation begins from the root node of the Huffman digital-to-analog converter unit; If the first digital value is 0, then search for the left subtree of the Huffman digital-to-analog converter unit; If the first digital value is 1, then search for the right subtree of the Huffman digital-to-analog converter unit; When the leaf node of the Huffman digital-to-analog converter is reached, the first target leaf node is obtained; The analog signal represented by the first target leaf node is used as the first analog data.

8. The method as described in claim 6, characterized in that, The process of encoding the second analog data using a Huffman analog-to-digital converter to obtain the second digital data includes: The initial digital code for Huffman tree search in the Huffman tree search module of the Huffman analog-to-digital conversion unit is set, and the initial digital code is the code corresponding to the middle leaf node of the Huffman tree in the corresponding digital-to-analog conversion unit. Based on the initial digital encoding, the Huffman tree search module is used to perform a data search on the second analog data to obtain the target leaf node; The target leaf node is converted from digital to analog using the second Huffman digital-to-analog converter subunit to obtain the target feedback voltage; The second digital data is obtained based on the analog voltage corresponding to the second analog data and the target feedback voltage.

9. The method as described in claim 8, characterized in that, The process of obtaining the second digital data based on the analog voltage corresponding to the second analog data and the target feedback voltage includes: The analog voltage corresponding to the second analog quantity data is compared with the target feedback voltage to obtain the comparison result; If the comparison result indicates that the analog voltage corresponding to the second analog data is equal to the target feedback voltage, then the digital data corresponding to the initial digital code is determined as the second digital data; If the comparison result indicates that the analog voltage corresponding to the second analog data is greater than the target feedback voltage, then the search proceeds to the right subtree of the Huffman digital-to-analog converter subunit to obtain the first target digital code; if the comparison result indicates that the input voltage corresponding to the second analog data is less than the target feedback voltage, then the search proceeds to the left subtree of the Huffman digital-to-analog converter subunit to obtain the second target digital code; until the voltage corresponding to the target digital code determined by the Huffman tree search module is close to the analog voltage corresponding to the second analog data, then the digital data corresponding to the target digital code is determined as the second digital data.

10. The method as described in claim 6, characterized in that, The step of using the storage unit to perform multiplication and accumulation calculations on the first analog data and the weight data to obtain the second analog data includes: Based on the matrix circuit in the storage unit, the first analog data and the weight data are multiplied and accumulated to obtain the second analog data; the matrix circuit is a circuit that forms the weights of the neural network in the form of analog impedance.

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