A two-dimensional interconnection admittance matrix fast extraction method based on total charge boundary integration
Patent Information
- Application Number
- CN202611084794.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-21
- Publication Date
- 2026-10-23
AI Technical Summary
[0005]本发明的目的在于提供一种基于全电荷边界积分的二维互连导纳矩阵快速提取方法，用以解决现有技术中二维互连线导纳分布参数提取在大规模未知量下时间复杂度高、空间复杂度大等问题
[0039]1）本发明采用全电荷边界积分方法对二维互连线进行建模，仅需对导体边界和介质界面进行离散，无需对整个求解区域进行体网格剖分，能够有效降低未知量规模，特别适用于多导体、分层介质环境下二维互连线电容电导分布参数的提取；
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Abstract
Description
Technical Field
[0001] This invention belongs to the field of high-speed integrated circuit and electromagnetic parameter extraction technology, and particularly relates to the extraction of capacitance and conductance distribution parameters of two-dimensional interconnect structures. Specifically, it provides a fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integration. Background Technology
[0002] With the rapid development of high-speed integrated circuits and advanced packaging technologies, the linewidth, spacing, and dielectric layer thickness of interconnects are continuously decreasing, leading to increasingly significant electromagnetic coupling effects between conductors and at the conductor-dielectric interface. For high-speed signal transmission, the distributed parameters of interconnects, especially the capacitance and conductance matrices, directly affect key performance characteristics such as signal integrity, latency, crosstalk, and power consumption. Therefore, accurately extracting the capacitance and conductance distributed parameters of two-dimensional interconnects during the interconnect structure design phase has become a fundamental issue in high-speed circuit analysis and optimization.
[0003] Existing interconnect parameter extraction methods typically employ numerical methods such as the finite element method, finite difference method, method of moments, or boundary element method. Among these, the full charge method based on boundary integrals only requires discretization of conductor boundaries and dielectric interfaces, offering advantages such as low unknown dimensionality and suitability for handling layered dielectric structures, and is widely used in two-dimensional capacitance parameter extraction. However, for large-scale dense matrices formed under conditions of multiple conductors, multiple dielectric interfaces, and fine mesh partitioning, the traditional full matrix construction and direct solution methods lead to a rapid increase in storage overhead and solution time, making it difficult to meet the computational efficiency requirements for large-scale interconnect structure parameter extraction.
[0004] Furthermore, existing fast algorithms mostly focus on extracting resistance and inductance parameters or solving general integral equations, while research on fast, direct solutions for the joint extraction of capacitance and conductance in two-dimensional interconnects remains relatively insufficient. In particular, in unified block systems formed by full-charge boundary integration, how to combine the object characteristics of conductor boundaries and dielectric interfaces in the interconnect structure to construct a hierarchical low-rank structure suitable for fast, direct solutions, while ensuring computational accuracy and reducing time and space complexity, still requires further investigation. Based on this, this invention proposes a fast method for extracting the admittance matrix of two-dimensional interconnects based on full-charge boundary integration. Summary of the Invention
[0005] The purpose of this invention is to provide a fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral, in order to solve the problems of high time complexity and large space complexity in the extraction of two-dimensional interconnect admittance distribution parameters under large-scale unknowns in the prior art.
[0006] To achieve the above objectives, the present invention adopts the following technical solution:
[0007] A fast extraction method for two-dimensional interconnect admittance matrices based on full charge boundary integrals, characterized by the following steps:
[0008] S01: Establish a two-dimensional interconnect cross-sectional model and perform mesh generation on the conductor boundary and dielectric interface;
[0009] S02: Discretize the conductor interface and dielectric interface using the full charge boundary integral equation, and construct a unified block system matrix equation that includes the full charge unknowns of the conductor boundary and the dielectric interface.
[0010] S03: An improved stacked off-diagonal low-rank matrix hierarchical tree is established using an object-first binary search approach. Extended compatibility determination, ACA low-rank compression, and QR-SVD recompression are performed on the off-diagonal blocks. The unified block system matrix equation corresponding to multiple port excitations is solved recursively using the Woodbury formula.
[0011] S04: The material parameter matrix is used to convert the total charge at the conductor boundary into a generalized free charge, and the generalized free charge on the discrete segment is summarized into the total generalized free charge at the port through the charge summation matrix, thereby constructing the admittance matrix.
[0012] Furthermore, the specific process of step S01 is as follows:
[0013] S011: Establish a two-dimensional interconnect cross-sectional model containing multiple conductors and layered dielectric regions;
[0014] S012: Discretize the conductor boundary using line segment elements;
[0015] S013: Discretize the medium interface using line segment units.
[0016] Furthermore, the specific process of step S02 is as follows:
[0017] S021: Based on the two-dimensional electrostatic field boundary integral theory, establish the conductor boundary potential equation and the dielectric interface boundary continuity condition. The conductor boundary potential equation includes the unknown total charge of the conductor boundary, and the dielectric interface boundary continuity condition includes the unknown total charge of the dielectric interface.
[0018] S022: Discretize the unknown total charge at the conductor boundary and the unknown total charge at the dielectric interface using pulse basis functions respectively;
[0019] S023: The point matching method is used to discretize the conductor boundary potential equation and the dielectric interface boundary continuity condition to obtain the unified block system matrix equation of the coupling between the conductor boundary and the dielectric interface.
[0020] Furthermore, in step S023, the unified block system matrix equation is expressed as:
[0021] ,
[0022] in, This represents the column vector of total unknown charges on the conductor boundary. Represents the column vector of total unknown charge at the interface of the medium; This represents the potential influence of conductor boundaries on each other. This block represents the potential effect of the dielectric interface on the conductor boundary. This block represents the influence of the conductor boundary on the boundary conditions of the dielectric interface. This block represents the influence of the medium interface on the medium interface boundary conditions. This represents the diagonal matrix formed by the difference in complex permittivity on both sides of the dielectric interface and the singular transition term. The vacuum permittivity, For the port voltage column vector, This is the mapping matrix from the port voltage to the discrete segments of the conductor boundary.
[0023] Furthermore, the specific process of step S03 is as follows:
[0024] S031: Based on the geometric position and object affiliation of the conductor boundary discrete unit and the dielectric interface discrete unit, a binary tree hierarchical grouping is established using an object-first binary search method;
[0025] S032: Rearrange the unified block system matrix according to the result of binary tree hierarchical grouping to obtain a stacked off-diagonal low-rank matrix structure;
[0026] S033: Based on the extended compatibility condition, the off-diagonal matrix blocks in the stacked off-diagonal low-rank matrix are judged, and the matrix blocks that meet the condition are subjected to low-rank compression using the ACA method.
[0027] S034: Perform downlink partitioning on off-diagonal matrix blocks that do not meet the extended compatibility condition, and recursively perform judgment and low-rank compression on the partitioned sub-blocks;
[0028] S035: The uplink aggregation method is used to restore the stacked off-diagonal low-rank matrix structure of the downlink segmented matrix blocks, and the QR-SVD method is used for recompression;
[0029] S036: Perform recursive decomposition and solution on the formed stacked off-diagonal low-rank matrix. The leaf layer diagonal block is inverted by LU decomposition, and the non-leaf layer diagonal matrix is inverted by Woodbury formula.
[0030] S037: Solve the right-hand side terms corresponding to multiple port excitations to obtain the unknown total charge at the conductor boundary and the unknown total charge at the dielectric interface.
[0031] Furthermore, in step S031, the objects are first grouped according to conductor objects and dielectric interface objects; when the current group contains multiple objects, they are divided into two groups according to the type of the objects; when the current group contains only a single object, it is divided into two groups according to the geometric position within the object.
[0032] Furthermore, in step S037, a unit voltage excitation is applied sequentially to each port, while the remaining ports are grounded, thereby constructing multiple right-hand terms of the unified block system matrix equation.
[0033] Furthermore, the specific process of step S04 is as follows:
[0034] S041: Extract the total charge at the conductor boundary from the unknowns obtained in step S03;
[0035] S042: Converting the total charge at the conductor boundary into a generalized free charge using a material parameter matrix;
[0036] S043: Use the charge summation matrix to summarize the generalized free charges on each discrete unit into the total generalized free charge at the port;
[0037] S044: Construct the port admittance matrix based on the relationship between the total generalized free charge at the port and the port current, and calculate the conductance matrix and capacitance matrix of the two-dimensional interconnect.
[0038] Compared with the prior art, the beneficial effect of the present invention is that it provides a fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral, which has the following advantages:
[0039] 1) This invention uses the full charge boundary integration method to model two-dimensional interconnects. It only requires discretization of the conductor boundary and the dielectric interface, without the need to perform volume meshing of the entire solution domain. This can effectively reduce the scale of unknowns and is particularly suitable for extracting the capacitance and conductance distribution parameters of two-dimensional interconnects in multi-conductor and layered dielectric environments.
[0040] 2) This invention introduces the improved stacked off-diagonal low-rank matrix method (M-HODLR) into the extraction of capacitance and conductance parameters of two-dimensional interconnects. By prioritizing object bisection, extended compatibility determination, downlink segmentation, uplink aggregation, and QR-SVD recompression, it effectively reduces the complexity of system matrix construction, storage, and solution, improves the computational efficiency of large-scale interconnect structure parameter extraction, and reduces computational resource consumption.
[0041] 3) This invention uses a fast and direct solution method to solve the unified block system. Compared with conventional iterative methods, it is less affected by the convergence problem of ill-conditioned matrices. Furthermore, for multi-port excitation problems, it does not require repeated full matrix decomposition for each port. It can achieve efficient joint extraction of the two-dimensional interconnect admittance matrix while ensuring extraction accuracy. Attached Figure Description
[0042] Figure 1 This is a flowchart illustrating the fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral in this invention.
[0043] Figure 2 This is a schematic diagram illustrating the object-based binary search principle in this invention.
[0044] Figure 3 This is a schematic diagram illustrating the principle of off-diagonal block downlink segmentation in the fast direct solution method of this invention.
[0045] Figure 4 This is a schematic diagram illustrating the principle of the off-diagonal block up-row segmentation in the fast direct solution method of this invention.
[0046] Figure 5 This is a schematic diagram of the microstrip line model in Embodiment 1 of the present invention.
[0047] Figure 6 This is a comparison chart showing the extraction results of the interconnect conductance of the microstrip line model in Embodiment 1 of the present invention.
[0048] Figure 7 This is a comparison chart of the time complexity of the fast direct solution algorithm in Embodiment 1 of the present invention and the traditional dense method.
[0049] Figure 8 This is a comparison chart of the space complexity of the fast direct solution algorithm in Embodiment 1 of the present invention and the traditional dense method. Detailed Implementation
[0050] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the described embodiments are only used to explain this invention and are not intended to limit the scope of protection of this invention.
[0051] This embodiment provides a fast method for extracting the two-dimensional interconnect admittance matrix based on the full charge boundary integral. The process is as follows: Figure 1 As shown, the main steps include: establishing a two-dimensional interconnect cross-sectional model and discretizing the boundaries; constructing a unified block system containing unknown total charges at the conductor boundaries and dielectric interfaces; rapidly solving the linear system using the improved stacked off-diagonal low-rank matrix method (M-HODLR); and finally obtaining the admittance matrix by summing the port charges. Specifically, the steps include:
[0052] S01: First, establish a two-dimensional interconnect cross-sectional model and mesh the conductor boundary and dielectric interface; the specific process is as follows:
[0053] S011: Establish a two-dimensional interconnect cross-sectional model containing multiple conductors and layered dielectric regions;
[0054] S012: Discretize the conductor boundary using line segment elements;
[0055] S013: Discretize the medium interface using line segment units;
[0056] Specifically, with Figure 5 Taking the microstrip line model shown as an example, the air region and the dielectric layer together constitute the background dielectric environment. Three conductors are located on the surface of the upper dielectric layer or in the adjacent region. A reference ground is set below the dielectric layer. For this two-dimensional cross-sectional model, only the conductor boundary and the dielectric interface are discretized. The entire dielectric region is not meshed. The conductor boundary is discretized to characterize the unknown total charge on the conductor surface. The dielectric interface is discretized to characterize the unknown total charge at the dielectric interface.
[0057] S02: Discretize the conductor and dielectric interfaces using the full-charge boundary integral equation, and construct a unified block system matrix equation that includes the unknowns of the full charge at the conductor boundary and the full charge at the dielectric interface; the specific process is as follows:
[0058] S021: Based on the two-dimensional electrostatic field boundary integral theory, establish the conductor boundary potential equation and the dielectric interface boundary continuity condition. The conductor boundary potential equation includes the unknown total charge of the conductor boundary, and the dielectric interface boundary continuity condition includes the unknown total charge of the dielectric interface.
[0059] S022: Discretize the unknown total charge at the conductor boundary and the unknown total charge at the dielectric interface using pulse basis functions respectively;
[0060] By discretizing, the pulse basis functions on the cross section of a two-dimensional interconnect can be divided into two categories: one is the pulse basis functions on the conductor boundary, and the other is the pulse basis functions on the dielectric interface. Since this invention adopts the boundary integral modeling method, only the boundary and interface need to be discretized. Therefore, compared with the volume discretization method, it can effectively reduce the scale of unknowns.
[0061] S023: The point matching method is used to discretize the conductor boundary potential equation and the dielectric interface boundary continuity condition to obtain the unified block system matrix equation of the coupling between the conductor boundary and the dielectric interface.
[0062] After discretizing the conductor boundary potential equation and the dielectric interface boundary continuity condition, they can be written in the following unified block system form:
[0063] ,
[0064] in, This represents the column vector of total unknown charges on the conductor boundary. Represents the column vector of total unknown charge at the interface of the medium; This represents the potential influence of conductor boundaries on each other. This block represents the potential effect of the dielectric interface on the conductor boundary. This block represents the influence of the conductor boundary on the boundary conditions of the dielectric interface. This block represents the influence of the medium interface on the medium interface boundary conditions. This represents the diagonal matrix formed by the difference in complex permittivity on both sides of the dielectric interface and the singular transition term. The vacuum permittivity, For port voltage column vectors;
[0065] Let be the mapping matrix from port voltages to discrete segments of the conductor boundary. If the model has M signal ports, the total number of conductor boundaries is... If there are discrete segments of a conductor, then the mapping matrix is specifically represented as:
[0066] ,
[0067] In the above unified block system matrix equation, the left-hand matrix is a coupled system matrix composed of conductor boundaries and dielectric interfaces, which has typical dense matrix characteristics. If the traditional full matrix filling and direct solution method is used directly, the computation time and memory consumption will increase significantly when the number of conductors increases or the boundary subdivision is refined. Therefore, the present invention introduces the M-HODLR fast direct solution method in step S03.
[0068] S03: An improved hierarchical off-diagonal low-rank matrix tree is established using an object-first binary search approach. Extended compatibility determination, ACA low-rank compression, and QR-SVD recompression are performed on the off-diagonal blocks. The unified block system matrix equations corresponding to multiple port excitations are then recursively solved directly using the Woodbury formula. The specific process is as follows:
[0069] S031: Based on the geometric position and object affiliation of conductor boundary elements and dielectric interface elements, a binary tree hierarchical grouping is established using an object-first binary search method;
[0070] The object priority binary search method is as follows: Figure 2 As shown, unlike direct bisection based solely on geometric position, this invention first groups objects according to conductor objects and dielectric interface objects; when the current group contains multiple objects, it prioritizes bisection based on object type; when the current group contains only a single object, it then performs bisection within the object based on geometric position. In this way, the continuity of unknown quantities at the same conductor boundary or dielectric interface in the hierarchical structure can be maintained as much as possible while constructing the hierarchical tree, which is beneficial for the block organization of the unified block system matrix and the maintenance of the structure of the subsequent charge summary matrix Q.
[0071] S032: Rearrange the unified block system matrix according to the hierarchical grouping results to obtain a stacked off-diagonal low-rank matrix structure;
[0072] After reordering the unified block system matrix based on the binary tree grouping results, the system matrix can be reorganized into a stacked off-diagonal low-rank matrix structure. For a matrix block of a certain level, its diagonal blocks are recursively divided to form the next level structure, while the off-diagonal blocks are approximated using a low-rank form. The core feature of this structure is that the diagonal blocks of each level are retained as full blocks or continue to be recursively divided, and the off-diagonal blocks of each level are stored in the form of a low-rank matrix.
[0073] S033: Based on the extended compatibility condition, the off-diagonal matrix blocks in the stacked off-diagonal low-rank matrix are judged, and the matrix blocks that meet the condition are subjected to low-rank compression using the ACA method.
[0074] For the off-diagonal blocks corresponding to two basis function sets i and j, we first determine whether they are suitable for low-rank representation based on the extended tolerance condition, which can be written as:
[0075] ,
[0076] in, and These represent the bounding boxes that enclose the i-th and j-th basis function groups, respectively. This represents the geometric diameter of the bounding box. This represents the geometric distance between the two bounding boxes. Preset positive real numbers; and These represent subgroups of the i-th and j-th basis function groups, respectively.
[0077] For off-diagonal matrix blocks that satisfy the extended inclusiveness condition, low-rank compression is performed using the ACA method, which approximates them as: ,in, This represents the off-diagonal matrix block formed by the coupling of the i-th basis function set and the j-th basis function set. and The low-rank matrix factor obtained after compression has an approximate rank much smaller than the dimension of the matrix block itself;
[0078] S034: Perform downlink partitioning on off-diagonal matrix blocks that do not meet the extended compatibility condition, and recursively perform judgment and low-rank compression on the partitioned sub-blocks;
[0079] For off-diagonal matrix blocks that do not meet the extended compatibility condition, ACA compression is not directly applied; instead, it is performed according to... Figure 3The downlink segmentation is performed as shown; that is, a coarse off-diagonal block is further divided into four sub-blocks, and the compatibility determination and ACA compression are recursively performed on the sub-blocks until the compression condition is met or the leaf layer is reached; in this way, the direct compression of geometrically adjacent but not directly low-rank approximated coarse off-diagonal blocks can be avoided, thereby improving compression efficiency and compression accuracy.
[0080] S035: The uplink aggregation method is used to restore the stacked off-diagonal low-rank matrix structure of the matrix blocks that have been downlinked, and the QR-SVD method is used for recompression.
[0081] For the low-rank representation of the sub-blocks obtained after downlink partitioning, the original hierarchical structure needs to be restored using uplink aggregation, such as... Figure 4 As shown, suppose a coarse-level off-diagonal matrix block is divided into four sub-blocks after down-row partitioning, and their low-rank representations are denoted as:
[0082] ;
[0083] It can then be aggregated into the low-rank form of the parent block: Due to the polymerization obtained and The data often contains redundant information. To further reduce the approximate rank and improve the efficiency of subsequent decomposition, this invention uses the QR-SVD method for recompression, ultimately obtaining the low-rank matrix factor of the parent block. and ;
[0084] S036: Perform recursive decomposition and solution on the formed stacked off-diagonal low-rank matrix. The leaf layer diagonal block is inverted by LU decomposition, and the non-leaf layer diagonal matrix is inverted by Woodbury formula.
[0085] After completing the low-rank construction of each layer of off-diagonal blocks, the system matrix can be written in a stacked off-diagonal low-rank form and further decomposed into the form of a product of multiple block diagonal matrices; for the block diagonal matrix of the bottom leaf layer, LU decomposition is used to directly find the inversion; for the block diagonal matrix of the non-leaf layer, Woodbury's formula is used to find the inversion.
[0086] Using the above method, the inversion of a large-dimensional matrix block can be transformed into the inversion of a smaller-dimensional, low-rank update matrix, thereby significantly reducing the solution complexity.
[0087] S037: Solve the right-hand terms corresponding to multiple port excitations to obtain the unknown total charge at the conductor boundary and the total charge at the dielectric interface;
[0088] A unit voltage excitation is applied sequentially to each port, while the remaining ports are grounded, thereby constructing multiple right-hand terms of the unified block system matrix equation. After completing one M-HODLR decomposition, the right-hand terms of multiple ports can be solved repeatedly to obtain the corresponding unknown quantities of total charge at the conductor boundary and total charge at the dielectric interface. Due to the direct solution method, it is less susceptible to the convergence problem of ill-conditioned matrices compared to conventional iterative methods, and can effectively improve the overall solution efficiency of multi-port problems.
[0089] S04: The material parameter matrix is used to convert the total charge at the conductor boundary into a generalized free charge, and the generalized free charges on the discrete segments are summarized into the total generalized free charge at the port using a charge summation matrix, thereby constructing the admittance matrix; the specific process is as follows:
[0090] S041: Extract the total charge at the conductor boundary from the unknowns obtained in step S037;
[0091] S042: Converting the total charge at the conductor boundary into a generalized free charge using a material parameter matrix;
[0092] Let the column vector of the total charge of the conductor boundary under the excitation of the k-th port, obtained from step S037, be: Then its corresponding generalized free charge is represented as: ,in, This represents a matrix of material parameters related to the complex permittivity of the dielectric.
[0093] S043: Use the charge summation matrix to summarize the generalized free charges on each discrete unit into the total generalized free charge at the port;
[0094] The purpose of the charge summation matrix is to sum the integrals of the charge density of the line segments to obtain the total charge at the port. Let the vector of the generalized free charges on the discrete segments of the conductor be... The discrete length of the i-th conductor is Its specific form is as follows:
[0095] ,
[0096] Therefore, the total generalized free charge at the port is: ;
[0097] S044: Construct the port admittance matrix based on the relationship between the total generalized free charge at the port and the port current, thus obtaining the conductance and capacitance matrices of the two-dimensional interconnect. ;
[0098] Based on the correspondence between the quasi-electrostatic field and the macroscopic circuit, the total complex current flowing out of the port is:
[0099] ,
[0100] Meanwhile, the admittance matrix is defined in circuit theory as follows:
[0101] , Represents the conductance matrix. Represents the capacitance matrix. Represents angular frequency. The symbol represents the imaginary unit, and M represents the total number of excitation ports.
[0102] In this embodiment, the following is adopted: Figure 5 The three-conductor double-layer dielectric microstrip line model shown is used as a verification example. The relative permittivity and loss angle of the upper dielectric are 4.4 and 0.02, respectively, and the relative permittivity and loss angle of the lower dielectric are 2.5 and 0.0019, respectively.
[0103] like Figure 6 The figure shown is a comparison of the extraction results of the conductivity parameters of the microstrip line model in this embodiment. It can be seen that the extraction results of the method of the present invention are in good consistency with the benchmark results, indicating that the method can effectively achieve accurate extraction of the conductivity parameters of two-dimensional interconnects.
[0104] like Figure 7 and Figure 8 The figure shows a comparison of the complexity of the fast direct solution algorithm used in this embodiment with that of the traditional dense method. Figure 7 For comparison of time complexity, Figure 8 For comparison of storage complexity; by Figure 7 As can be seen, in the fixed geometry encryption partitioning test, the time complexity of constructing the M-HODLR in this invention is close to O(NlogN), and the time complexity of solving it is close to (NlogN). 2 N), which is significantly lower than the typical O(N) in conventional dense methods. 3 Growth trend; from Figure 8 As can be seen, the space complexity of the method of this invention is close to O(NlogN), which is significantly better than the O(N) space complexity of conventional dense methods. 2 The growth trend; in addition to the growth trend, the time and space consumption of the method of the present invention is much less than that of conventional dense methods.
[0105] Therefore, this invention can effectively reduce the computation time and memory consumption in the process of system matrix construction and solution while maintaining the extraction accuracy, and is especially suitable for extracting two-dimensional interconnect parameters with a large number of unknowns.
[0106] In addition, the results of capacitor parameter extraction in this embodiment are organized and recorded in the form shown in Table 1. As can be seen from the table, compared with the results of the electromagnetic simulation software ANSYS, the relative errors of the three capacitor parameter results are all less than 3%. After using the M-HODLR acceleration algorithm, the calculation results of the capacitor matrix can still meet a low relative error level, so as to achieve a balance between efficiency and accuracy.
[0107] Table 1 Comparison of Capacitor Matrix Extraction Results
[0108]
[0109] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.
Claims
1. A fast extraction method for two-dimensional interconnect admittance matrices based on full-charge boundary integrals, characterized in that, Includes the following steps: S01: Establish a two-dimensional interconnect cross-sectional model and perform mesh generation on the conductor boundary and dielectric interface; S02: Discretize the conductor interface and dielectric interface using the full charge boundary integral equation, and construct a unified block system matrix equation that includes the full charge unknowns of the conductor boundary and the dielectric interface. S03: An improved stacked off-diagonal low-rank matrix hierarchical tree is established using an object-first binary search approach. Extended compatibility determination, ACA low-rank compression, and QR-SVD recompression are performed on the off-diagonal blocks. The unified block system matrix equation corresponding to multiple port excitations is solved recursively using the Woodbury formula. S04: The material parameter matrix is used to convert the total charge at the conductor boundary into a generalized free charge, and the generalized free charge on the discrete segment is summarized into the total generalized free charge at the port through the charge summation matrix, thereby constructing the admittance matrix.
2. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 1, characterized in that, The specific process of step S01 is as follows: S011: Establish a two-dimensional interconnect cross-sectional model containing multiple conductors and layered dielectric regions; S012: Discretize the conductor boundary using line segment elements; S013: Discretize the medium interface using line segment units.
3. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 1, characterized in that, The specific process of step S02 is as follows: S021: Based on the two-dimensional electrostatic field boundary integral theory, establish the conductor boundary potential equation and the dielectric interface boundary continuity condition. The conductor boundary potential equation includes the unknown total charge of the conductor boundary, and the dielectric interface boundary continuity condition includes the unknown total charge of the dielectric interface. S022: Discretize the unknown total charge at the conductor boundary and the unknown total charge at the dielectric interface using pulse basis functions respectively; S023: The point matching method is used to discretize the conductor boundary potential equation and the dielectric interface boundary continuity condition to obtain the unified block system matrix equation of the coupling between the conductor boundary and the dielectric interface.
4. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 3, characterized in that, In step S023, the unified block system matrix equation is expressed as: ， in, This represents the column vector of total unknown charges on the conductor boundary. Represents the column vector of total unknown charge at the interface of the medium; This represents the potential influence of conductor boundaries on each other. This block represents the potential effect of the dielectric interface on the conductor boundary. This block represents the influence of the conductor boundary on the boundary conditions of the dielectric interface. This block represents the influence of the medium interface on the medium interface boundary conditions. This represents the diagonal matrix formed by the difference in complex permittivity on both sides of the dielectric interface and the singular transition term. The vacuum permittivity, For the port voltage column vector, This is the mapping matrix from the port voltage to the discrete segments of the conductor boundary.
5. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 1, characterized in that, The specific process of step S03 is as follows: S031: Based on the geometric position and object affiliation of the conductor boundary discrete unit and the dielectric interface discrete unit, a binary tree hierarchical grouping is established using an object-first binary search method; S032: Rearrange the unified block system matrix according to the result of binary tree hierarchical grouping to obtain a stacked off-diagonal low-rank matrix structure; S033: Based on the extended compatibility condition, the off-diagonal matrix blocks in the stacked off-diagonal low-rank matrix are judged, and the matrix blocks that meet the condition are subjected to low-rank compression using the ACA method. S034: Perform downlink partitioning on off-diagonal matrix blocks that do not meet the extended compatibility condition, and recursively perform judgment and low-rank compression on the partitioned sub-blocks; S035: The uplink aggregation method is used to recover the stacked off-diagonal low-rank matrix structure of the downlink segmented matrix blocks, and the QR-SVD method is used for recompression; S036: Perform recursive decomposition and solution on the formed stacked off-diagonal low-rank matrix. The leaf layer diagonal block is inverted by LU decomposition, and the non-leaf layer diagonal matrix is inverted by Woodbury formula. S037: Solve the right-hand side terms corresponding to multiple port excitations to obtain the unknown total charge at the conductor boundary and the unknown total charge at the dielectric interface.
6. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 5, characterized in that, In step S031, the objects are first grouped according to conductor objects and dielectric interface objects; when the current group contains multiple objects, they are divided into two groups according to the type of the objects; when the current group contains only a single object, they are divided into two groups according to the geometric position inside the object.
7. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 5, characterized in that, In step S037, a unit voltage excitation is applied sequentially to each port, while the remaining ports are grounded, thereby constructing multiple right-hand terms of the unified block system matrix equation.
8. The fast extraction method for two-dimensional interconnect admittance matrix based on full charge boundary integral according to claim 1, characterized in that, The specific process of step S04 is as follows: S041: Extract the total charge at the conductor boundary from the unknowns obtained in step S03; S042: Using the material parameter matrix to convert the total charge at the conductor boundary into a generalized free charge; S043: Use the charge summation matrix to summarize the generalized free charges on each discrete unit into the total generalized free charge at the port; S044: Construct the port admittance matrix based on the relationship between the total generalized free charge at the port and the port current, and calculate the conductance matrix and capacitance matrix of the two-dimensional interconnect.