Dependency-aware prefetch accelerator for sparse matrix factorization and its asynchronous circuit

Abstract

The application discloses a dependency-aware prefetch accelerator for sparse matrix factorization and an asynchronous circuit thereof, comprising a global control unit, a computing core, a hierarchical pivot unit, an address transformation unit and a double-buffered memory management unit. The global control unit reads node tasks and determines dependency states, controls the double-buffered memory management unit to alternately perform data prefetching and loading, and sends start and stage switching signals to the computing core. The computing core reads front data and performs computation under the support of row permutation mapping provided by the address transformation unit, and interacts with the hierarchical pivot unit to complete pivot selection. The double-buffered memory management unit is configured with at least two buffer zones, and alternately performs prefetching and execution in parallel under the control of the global control unit. The application reduces memory access delay through dependency-aware prefetching and double-buffering mechanism, and supports in-place data exchange through dynamic address transformation, thereby significantly improving the hardware execution efficiency of sparse matrix factorization.

Description

Technical Field

[0001] This invention belongs to the field of sparse matrix factorization hardware accelerator technology, specifically relating to a dependency-aware prefetch accelerator for sparse matrix factorization and its asynchronous circuit. Background Technology

[0002] Sparse linear equations are widely used in engineering and scientific computing scenarios such as circuit simulation, finite element analysis of structural mechanics, fluid and multiphysics simulation, graph optimization, and econometrics. When solving such equations, sparse direct methods have advantages over iterative methods in terms of solution stability, convergence robustness, and handling ill-conditioned problems, and are therefore widely used in computing scenarios with high reliability requirements.

[0003] Numerical decomposition processes in sparse direct methods typically involve a large number of dense linear algebra kernels, accompanied by significant overhead in processing irregular structural information and data transport. For large-scale sparse matrices, decomposition methods based on multifrontal or supernodal approaches have become an important implementation path for industrial-grade sparse solvers because they can utilize elimination trees to organize tasks and transform some sparse operations into dense block operations on the frontal matrix. From a computational perspective, multifrontal decomposition includes both dense block operations suitable for array-based implementation, such as Generalized Matrix Multiplication (GEMM) and Triangular Matrix Equation Solving (TRSM), and highly irregular control flows, such as pivot selection, row / column permutations, elimination tree dependency management, frontal task scheduling, assembly, and update write-back. Therefore, its performance is not only limited by the throughput of the underlying multiply-accumulate array but also significantly constrained by the efficiency of control logic, random memory access, and cross-layer data transport.

[0004] Existing implementations of sparse direct methods can be mainly divided into the following two categories: The first type is a hardware-software co-implementation based on CPU, GPU, or general-purpose tensor arrays. This approach typically maps dense block computations to Basic Linear Algebra Subroutines (BLAS), GPU kernel functions, or systolic arrays for execution. However, key control steps such as principal component selection, dependency analysis, wavefront scheduling, and row permutation are still primarily handled by software. The advantages of this type of scheme are mature algorithms and wide applicability. However, due to the irregular data dependencies and random memory access characteristics of sparse decomposition itself, principal component search and task management introduce a large number of branch decisions and data exchanges, making it difficult for the array core to maintain a continuously fully loaded state.

[0005] The second category is dedicated hardware or field-programmable gate array (FPGA) acceleration solutions for sparse decomposition. These solutions typically attempt to migrate dense block operations, update matrix generation, local assembly, or pipeline control in supernodes or multiple fronts to hardware implementation, providing task sequences, scheduling order, and auxiliary data through host software. While these solutions can improve throughput at specific stages, they still rely on host software for principal component policy switching, front dependency determination, or data reorganization; for row permutations, they often still employ the practice of physically moving matrix data; and for parallel front tasks, software often needs to sort the data before sending it to hardware, resulting in significant hardware-software coordination overhead.

[0006] In light of the problems to be solved by this invention, the prior art has at least the following shortcomings: 1. It is difficult to balance the flexibility of principal component selection with hardware efficiency. Existing software solvers usually execute threshold principal component selection, partial principal component selection, or related variants on the software side; even if the hardware solution implements the principal component logic, it is mostly optimized for a single scenario and it is difficult to simultaneously take into account block-level parallel principal component strategy and threshold principal component strategy, resulting in insufficient adaptability under different matrix structures and different numerical stability requirements; 2. Row permutation and address updates can still easily evolve into high-overhead data migration. If the permutation is still completed by actually swapping matrix rows or intermediate block data after the pivot is determined, it will bring additional off-chip read / write, cache mismatch and pipeline pauses, which is especially unfavorable for large-scale frontier matrices and multi-level update scenarios. 3. Frontier matrix task scheduling lacks hardware-level dependency awareness. Although multi-wavefront decomposition has elimination tree or directed acyclic graph (DAG) dependencies, existing solutions often place dependency analysis and task release on the software side. The hardware only passively executes the sorted tasks, making it difficult to dynamically launch tasks based on on-chip buffer occupancy, kernel busy / idle status, and subtask completion events. Summary of the Invention

[0007] To address the problems existing in the above-mentioned background technology, the purpose of this invention is to provide a dependency-aware prefetch accelerator and its asynchronous circuit for sparse matrix factorization, which achieves efficient pipelined execution of multiple frontier nodes through node dependency tracking, double buffer management, and intra-node stage scheduling.

[0008] To achieve the above objectives, the present invention adopts the following technical solution: A dependency-aware prefetch accelerator for sparse matrix factorization includes a global control unit, a computational core, hierarchical principal units, an address translation unit, and a double-buffered memory management unit. These modules collectively constitute a hardware acceleration system for multi-front node execution. The global control unit centrally schedules and coordinates the work of each module, the computational core is responsible for node computation, the hierarchical principal units handle principal-related control, the address translation unit maintains mapping, indexing, and address redirection information, and the double-buffered memory management unit primarily assists the global control unit in loading node tasks. This hardware acceleration system is built around the complete lifecycle of multi-front nodes, enabling node tasks to continuously execute in an overlapping manner of prefetching, loading, computation, and write-back, while satisfying parent-child dependency constraints.

[0009] Global Control Unit: Used to read node tasks from the task area of ​​external storage, determine node dependency status, and interact bidirectionally with the double-buffered storage management unit. Based on the node dependency status and buffer status, it sends node prefetching and loading control information to the double-buffered storage management unit; based on the node dependency status and buffer readiness status, it sends node start signals and stage switching signals to the computing core; responding to the node computation completion signal returned by the computing core, it sends buffer switching and release control information to the double-buffered storage management unit; it receives write-back or scattering completion feedback from the factor write-back unit or scattering assembly unit and updates the node dependency status; it controls the factor write-back unit or scattering assembly unit to complete factor write-back or update scattering with the support of the computation results output by the computing core and the row permutation mapping information provided by the address translation unit.

[0010] The computational core is used to read the leading edge data of the node from the currently executing buffer in the double-buffered storage management unit according to the node start signal and stage switching signal sent by the global control unit, and locate the data in the buffer according to the row permutation mapping information provided by the address translation unit. During the calculation process, it performs principal block LU decomposition (lower triangular-upper triangular decomposition), triangulation, and Schur update; it outputs the candidate elements of the current principal block and related calculation status to the hierarchical principal unit, and adjusts the principal block LU decomposition, triangulation, and Schur update process according to the information returned by the hierarchical principal unit; after the node calculation is completed, the computational core returns a node completion signal to the global control unit.

[0011] Hierarchical principal element unit: It is used to receive the candidate elements, candidate element position information and current decomposition stage information of the current principal element block output by the computing core, compare the candidate elements and determine the principal element, and return the principal element position, exchange control information and decomposition control information to the computing core to control the principal element block decomposition process, that is, to control the exchange semantics and data access order in the LU decomposition of the current node principal element block and subsequent triangulation and Schur update; at the same time, it sends the principal element position and exchange control information to the address translation unit.

[0012] Address Translation Unit: Used to update the local row and column mapping relationship of the current node based on the principal position and exchange control information output by the hierarchical principal unit and the current row and column access request issued by the computing core; it feeds back the generated row permutation mapping information, including the row permutation logical address, row address redirection mapping relationship and row permutation result to the computing core, so that the computing core can locate and access data in the execution buffer according to the row permutation mapping information; at the same time, it provides the updated mapping table information to the global control unit to cooperate with the data prefetching, result writing back and external storage updates of subsequent nodes.

[0013] Dual-buffered storage management unit: Configured with at least two buffers, which are alternately managed under the control of the global control unit, and are in the prefetch state and the execution state.

[0014] Furthermore, the node dependency state determination refers to determining whether all child nodes of the current node have completed the update and write-back, thereby determining the node dependency state; if all child nodes of the current node have completed the update and write-back, then the dependency state of the current node is determined to be resolved.

[0015] Furthermore, the dual-buffered storage management unit, under the control of the global control unit, manages the buffers in the prefetch and execution states alternately as follows: The dual-buffered storage management unit feeds back the status of each buffer to the global control unit. Based on the node dependency status and the buffer status, the global control unit uses the buffer that has completed data prefetching as the execution buffer, providing the computing core with the prefetched node-corresponding data and leading-edge data, and uses the other buffer as the prefetch buffer. After receiving the node computation completion information returned by the computing core, the global control unit controls the dual-buffered storage management unit to switch buffers, releasing the current execution buffer and reallocating it as the prefetch buffer, while simultaneously switching the prefetch buffer that has completed prefetching as the execution buffer, thereby achieving parallel processing of data prefetching and node computation.

[0016] Furthermore, the global control unit includes: Task Reading Submodule: Used to read and parse node tasks from the external storage task area to obtain the task description information of the current node, including the current node identifier, parent node identifier, number of child nodes, total node dimension, principal block dimension, front matrix address, mapping table address, factor write-back address, and update write-back address, and output the task description information to the Dependency Scoreboard Submodule, Buffer Management Submodule, and Micro-Scheduling Submodule. Dependency Scoreboard Module: Based on the dependency scoreboard, maintain the parent-child dependency state between nodes, and perform gating control on the prefetching, loading or execution of the current node according to the completion status of the child node update writeback. Receive the writeback or scatter completion status fed back by the micro-scheduling submodule to update the node dependency state, and send the node dependency state after the child node update writeback is completed to the buffer management submodule. The buffer management submodule is used to manage the loading and releasing of at least two buffers in the dual-buffered storage management unit during the node prefetching, node execution, and node write-back processes, based on the node dependency status and buffer status, and to feed back the buffer loading status to the micro-scheduling submodule. Micro-scheduling submodule: Based on the task description information of the current node, the buffer loading status, and the status of relevant computing units in the computing core, the micro-scheduling submodule dynamically decides the start conditions, execution order, and switching timing of each execution stage of the current node, and sends micro-scheduling instructions to the computing core according to the decision results; after the computing core completes the calculation of the current node, the micro-scheduling submodule controls the factor write-back unit or scattering assembly unit to complete the factor write-back or update the scattering, and at the same time feeds back the write-back or scattering completion status to the dependent scoreboard submodule.

[0017] Furthermore, the dependency scoring module maintains a count value for each node. After a child node completes its update and write-back, the count of the corresponding parent node is decremented. When the count reaches a predetermined value, the corresponding parent node is set to a state where prefetching or execution is allowed. For example, the predetermined value of a node is set to 0. Whether the node's count value is zero (dependency condition) is used to determine whether the node meets the execution condition. When the dependency condition is met, the corresponding parent node is set to a state where prefetching or execution is allowed.

[0018] Furthermore, the dependent scoreboard module configures a node status table, a count table of child nodes to be completed, node identifier matching and update logic, permission generation logic, and a completion return interface; The node status table is used to record the current lifecycle status of each node, including not in the scheduling state, waiting for dependencies state, allowed prefetching state, loaded state, executing state, writing back state, and completed state; The pending child node count table is used to record the number of child nodes that have not yet been written back for each node, and is maintained in the form of a count value. The node identifier matching and update logic is used to locate the corresponding parent node's entry based on the parent node identifier in the child node's write-back completion signal, and update the count value and status information of the corresponding child node to be completed by the parent node. The license generation logic is used to generate node-level prefetch license signals, load license signals, and execute license signals based on the node status table and the count table of child nodes to be completed. The completion return interface is used to receive the update write-back completion signal and release the parent node's dependencies.

[0019] Furthermore, the current node execution phase of the dynamic decision-making of the micro-scheduling submodule includes the principal component selection phase, the principal component block LU decomposition phase, the triangulation solution phase, the Schur update phase, the factor write-back phase, and the matrix update generation and assembly phase.

[0020] Furthermore, the computing core includes a RISC-V processor and multiple matrix computation units. The RISC-V processor performs principal block LU decomposition, data alignment and scaling, exponential coordination before update write-back, and low-parallel scalar operations. The matrix computation units perform high-throughput matrix multiplication and addition operations within nodes during the Schur update phase and support signed integer addition, subtraction, and multiplication combinations. The principal block decomposition results required for subsequent triangulation and Schur updates are obtained through principal block LU decomposition. After principal block decomposition, the computing core continues to perform triangulation operations on relevant sub-blocks in the current node to calculate multipliers or intermediate results required for subsequent update processes. Triangulation can correspond to the TRSM process in multiple front decomposition and is adapted to the block structure and low-precision data format of the current node. After completing triangulation, the matrix computation units perform matrix update operations based on the block data of the remaining update region in the current node. The matrix update corresponds to the Schur update process in multiple front decomposition. Its input includes intermediate results obtained through triangulation and corresponding sub-blocks to be updated, and its output is the contribution block of the current node to the parent node. The matrix core supports combined operations of signed integer addition, subtraction, and multiplication, which is suitable for performing multiply-addition accumulation on sub-block data in the frontier matrix. Through the matrix core, the Schur update part, which accounts for a high proportion in the decomposition of multiple frontier nodes, can be mapped to high-throughput matrix operations, thereby improving the efficiency of numerical computation within the node.

[0021] Furthermore, the hierarchical principal element unit adopts a tree-like comparison or hierarchical comparison structure to shorten the principal element selection path.

[0022] This invention further provides an asynchronous circuit for a dependency-aware prefetch accelerator for sparse matrix factorization. The asynchronous circuit employs an asynchronous control component to build an asynchronous micropipeline structure, the asynchronous control component comprising: Source: The starting node of the asynchronous micropipeline, used to generate the initial trigger event to drive the operation of subsequent pipelines; Trap: is the termination node of an asynchronous micropipeline, used to receive and terminate the end event at the end of the pipeline; Merge: Used to receive multiple concurrent event and data requests and aggregate them into a single event and data output; Arbiter: Used to receive multiple concurrent event and data requests, and arbitrate them according to preset priority rules, selecting the event and data with the highest priority to output; Mutex: Used to control the mutual exclusion of multiple concurrent event and data inputs, allowing only one event and data output at a time; Splitter: Used to receive one event and data input and distribute it as multiple events and data outputs; Selector: Used to receive one event and data input, and select the corresponding event and data from multiple output channels for output based on the valid selection signal of the external input; Fifo: Used to receive one event and data input, and generate multiple pulse signals in sequence during transmission to trigger combinational logic circuits, thereby realizing data buffering and one event and data output.

[0023] Compared with the shortcomings and deficiencies of existing technologies, the present invention has the following beneficial effects: 1. This invention addresses the strict dependencies between parent and child nodes in multiple frontier sparse LU decomposition by introducing node dependency state determination on the hardware side. This ensures that whether a node is allowed to enter the prefetch, loading, and execution phases is no longer solely determined by task order, but rather by whether all its child nodes have completed their write-back. This dependency-aware execution gating effectively prevents parent nodes from being preloaded and reading outdated data when dependencies are not met, thereby improving execution correctness and data consistency in the multiple frontier decomposition process. 2. This invention introduces a double-buffered storage structure into the hardware accelerator and combines it with node dependency gating, so that the prefetching and loading of the node's leading edge data can overlap with the current node's decomposition calculation process. This organizes the originally serial "data loading - node execution - result write-back" process into a node-level execution process with pipelined characteristics, thereby reducing the pauses caused by external storage access latency to the computing unit, improving the continuity of leading edge data supply and hardware resource utilization, and thus improving the overall matrix decomposition throughput. 3. This invention performs logical redirection processing on row permutation and address update through address transformation unit, transforming the process that easily evolves into a high-overhead data movement process in traditional implementation into a processing method mainly based on index update and controlled write-back, which can reduce the additional overhead caused by irregular memory access and data rearrangement, and improve the implementation efficiency of node update stage. 4. This invention adopts a low-precision / integer numerical path implemented with adapted hardware. Through a mixed block floating-point / fixed-point data organization method and corresponding scaling, alignment and write-back control, the frontier data loading, triangulation, matrix update and result write-back in the matrix decomposition process can be completed under conditions of low bandwidth and low implementation complexity. This helps to reduce hardware area and external bandwidth pressure, and improves the engineering feasibility of the system in FPGA / ASIC (Application-Specific Integrated Circuit) scenarios. Attached Figure Description

[0024] Figure 1 This is an architecture diagram of a dependency-aware prefetch accelerator for sparse matrix factorization provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the double-buffered overlapping execution timing provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the node execution data flow provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of dependency-aware prefetching and execution gating provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the asynchronous control component provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the control chain of the dependent scoreboard module provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] This invention proposes a dependency-aware prefetch accelerator for sparse matrix factorization. Its hardware system is oriented towards the direct solution process of sparse linear equations. It abstracts the node tasks in multi-front decomposition into the loading, assembly, decomposition, updating and writing back of the front. Through hardware-side dependency tracking, double buffer management, intra-node stage scheduling and low-precision / integer numerical paths, it achieves efficient pipelined execution of multi-front nodes.

[0027] This invention constructs a unified control and execution system around the complete lifecycle of multiple frontier nodes, enabling node tasks to be continuously executed in an overlapping manner of prefetching, loading, computation, and write-back, while satisfying parent-child dependency constraints. The overall architecture of the dependency-aware prefetch accelerator for sparse matrix factorization is as follows: Figure 1 As shown, the system includes a global control unit, a computing core, hierarchical principal units, an address translation unit, and a double-buffered memory management unit. These modules collectively constitute a hardware acceleration system for multi-frontal node execution. The global control unit uniformly schedules and coordinates the work of each module, the computing core is responsible for node computation, the hierarchical principal units handle principal-related control, the address translation unit maintains mapping, indexing, and address redirection information, and the double-buffered memory management unit primarily assists the global control unit in loading node tasks. This hardware acceleration system is built around the complete lifecycle of multi-frontal nodes, enabling node tasks to continuously execute in an overlapping manner of prefetching, loading, computation, and write-back, while satisfying parent-child dependency constraints. The hardware portion of this accelerator is used to read node tasks generated by the software preprocessing section, determine dependency states, load frontal data, perform numerical computation within the node, write back results, and update parent nodes, thereby achieving node-level pipelining execution for multi-frontal sparse LU decomposition.

[0028] 1. Global Control Unit The global control unit is the core control module, used to read node tasks from the external storage task area and determine node dependency status. Specifically, node dependency status determination refers to determining whether all child nodes of the current node have completed update write-back, thereby determining the node dependency status; if all child nodes of the current node have completed update write-back, the dependency status of the current node is determined to be resolved. The global control unit interacts bidirectionally with the double-buffered storage management unit, sending node prefetching and loading control information to the double-buffered storage management unit according to the node dependency status and buffer status, and sending node start signals and stage switching signals to the computing core according to the node dependency status and buffer ready status; responding to the node computation completion signal returned by the computing core, it sends buffer switching and release control information to the double-buffered storage management unit; receiving write-back or scattering completion feedback returned by the factor write-back unit or scattering assembly unit, and updating the node dependency status; controlling the factor write-back unit or scattering assembly unit to complete factor write-back or update scattering with the support of the computation results output by the computing core and the row permutation mapping information provided by the address translation unit.

[0029] The external storage portion is logically divided into the following storage areas: Task area: Used to store the queue of node task description information generated by the software preprocessing part. Each node task description information is used to describe the hardware execution context of a multi-front node. Mapping table area: Used to store the extended-accumulation mapping table generated by the software preprocessing part. This mapping table is used to describe the target position mapping relationship when the child node updates and writes to the leading edge matrix of the parent node. Its contents may include the local row and column index of the child node, the target row and column index of the parent node, the block offset address information, the description information of the sub-block boundary, or other equivalent mapping description methods. Matrix data area: Used to store the initialization data of the frontier matrix of each node, as well as the frontier matrix content that is subsequently loaded, updated, or written back during node execution; Factor area: Used to store the local L-factor and U-factor results generated during the node decomposition process. After the node is executed, the factor write-back cell writes the factor results of the current node into the factor area for subsequent solving, back-substitution or verification. Update matrix area: Used to store the update data generated by node calculations.

[0030] The global control unit connects to the external read / write interface via the control bus and uniformly schedules the leading edge loading unit, scattering assembly unit, and factor write-back unit. Each module initiates access transactions to external storage and transmits data through the data request / response interface, and reports the task completion status to the global control unit in real time through the status feedback path. Based on the feedback results of the status feedback path, the global control unit coordinates the operation and stage switching of each internal sub-module. Each sub-module includes: task reading sub-module, dependency scoreboard module, buffer management sub-module, and micro-scheduling sub-module. The functions of each sub-module are described in detail below.

[0031] 1.1 Task Reading Submodule This module is used to read and parse node tasks from the external storage task area to obtain the task description information of the current node, including the current node identifier, parent node identifier, number of child nodes, total node dimension, principal component dimension, front matrix address, mapping table address, factor write-back address, and update write-back address. The task description information is then output to the dependency scoreboard submodule, buffer management submodule, and micro-scheduling submodule to ensure that the matrix data loaded into the computing core is correct and complete. This submodule is mainly responsible for converting the node task description generated by the software preprocessing part into control information that can be directly consumed by the hardware side, thereby providing a foundation for subsequent dependency determination, buffer allocation, and node execution.

[0032] 1.2 Dependency on Scoreboard Module The dependency scoreboard maintains the parent-child dependency state between nodes, recording the number of child nodes to be completed, prefetchable status, loadable status, executable status, and completion status for each node. It gates the prefetching, loading, or execution of the current node based on the completion status of child node update write-backs. It receives write-back or scatter completion status feedback from the micro-scheduling submodule to update the node dependency state and sends the node dependency state after child node update write-back completion to the buffer management submodule. The dependency scoreboard submodule maintains a count value for each node. When a child node update write-back is completed, the count of the corresponding parent node is decremented. When the count reaches a predetermined value, the corresponding parent node is set to a prefetchable or executable state. For example, setting the predetermined value of a node to 0, the node's execution condition is determined by whether its count value is zero (dependency condition). When the dependency condition is met, the corresponding parent node is set to a prefetchable or executable state. Therefore, whether a node can enter the subsequent execution stage is determined by its dependency completion state, thus preventing parent nodes from being prematurely loaded or executed before their dependent child node updates have been completed.

[0033] The module depends on the scoreboard to configure the node status table, the count table of child nodes to be completed, the node identifier matching and update logic, the license generation logic, and the completion return interface; The node status table records the current lifecycle state of each node, including not in the scheduling state, waiting for dependencies state, allowed prefetching state, loaded state, executing state, writing back state, and completed state; the node status table provides subsequent control modules with the status basis for whether a node is allowed to be loaded and executed. The pending child node count table is used to record the number of child nodes that have not yet been written back for each node, and is maintained in the form of a count value; that is, a count value is maintained for each node. This count value can be initialized by the software preprocessing part based on the elimination tree structure and the number of child nodes, or it can be written by the task reading submodule into the corresponding table entry inside the dependent scoreboard submodule after reading the node task. The node identifier matching and update logic is used to locate the corresponding parent node's entry based on the parent node identifier in the child node's write-back completion signal, and update the count value and status information of the corresponding child node to be completed in the parent node. The license generation logic is used to generate node-level prefetch license signals, load license signals, and execute license signals based on the node status table and the count table of child nodes to be completed. The completion return interface is used to receive the update write-back completion signal and release the parent node's dependencies.

[0034] 1.3 Buffer Management Submodule This module manages the loading and releasing of at least two buffers in the dual-buffered storage management unit during node prefetching, execution, and write-back processes, based on node dependency status and buffer status, and feeds back the buffer loading status to the micro-scheduling submodule. This submodule detects the current status of each buffer, such as idle, occupied, prefetching, and loading states, and controls the dual-buffered storage management unit to allocate loading buffers to nodes that meet the conditions, based on node dependency status and buffer availability. When the dependency scoreboard submodule determines that a node meets the node dependency status and is idle, the buffer management submodule sends a loading permission signal to the leading edge loading submodule through an external read / write interface, reads the leading edge matrix data of the node, and loads it into the idle buffer; simultaneously, the other buffer prefetches the leading edge data of the next node, provided the dependency conditions are met. After the current node's execution and write-back are completed, the dual-buffered storage management unit switches buffers. The buffer management submodule, based on a dependency-aware dual-buffered execution mechanism, ensures that the current node's computation process overlaps with the next node's loading process as much as possible. This mechanism decouples data supply from numerical computation, ensuring consistency between parent and child nodes while enabling pipelined execution of node-level tasks. It effectively hides external storage access latency and improves the overall throughput of multi-front decomposition.

[0035] 1.4 Micro-scheduling submodule Based on the task description information, buffer loading status, and the status of relevant computing units in the computing core, the micro-scheduling submodule dynamically determines the start conditions, execution order, and switching timing of each execution stage of the current node, and sends micro-scheduling instructions to the computing core according to the decision results. After the computing core completes the computation of the current node, the micro-scheduling submodule controls the factor write-back unit or scattering assembly unit to complete factor write-back or update scattering, and simultaneously feeds back the write-back or scattering completion status to the dependency scoring submodule. The execution stages of the node controlled by the micro-scheduling submodule include the principal component selection stage, the principal component block LU decomposition stage, the triangulation stage, the Schur update stage, the factor write-back stage, and the matrix update generation and assembly stage. Based on the dimension information, principal component block size, buffer loading status, and busy / idle status of relevant computing units of the current node, the micro-scheduling submodule determines the start conditions, execution order, and switching timing of each stage, further refining the node-level task into multiple execution stages within the node, and realizing orderly collaboration between various computing units.

[0036] 2. Computing Core Based on the node start signal and stage switching signal (scheduling signal) sent by the global control unit, the computation core reads the leading edge data corresponding to the node from the buffer currently in execution state in the double buffer storage management unit, and locates the data in the buffer according to the row permutation mapping information provided by the address translation unit. During the calculation process, it performs principal block LU decomposition (lower triangular-upper triangular decomposition), triangulation, and Schur update; outputs the candidate elements of the current principal block and related calculation status to the hierarchical principal unit, and adjusts the principal block LU decomposition, triangulation, and Schur update process according to the information returned by the hierarchical principal unit; after the node calculation is completed, the computation core returns a node completion signal to the global control unit.

[0037] The computational core comprises a RISC-V processor and multiple matrix computation units. The RISC-V processor performs principal block LU decomposition, data alignment and scaling, exponential coordination before update write-back, and low-parallel scalar operations, implementing addition, subtraction, multiplication, division, scaling, and alignment operations in integer / fixed-point mode. The matrix computation units perform high-throughput matrix multiplication and addition operations within nodes during the Schur update phase and support combined operations of signed integer addition, subtraction, and multiplication. The matrix core supports combined operations of signed integer addition, subtraction, and multiplication, suitable for performing multiplication-addition accumulation on sub-block data in the frontier matrix. Through the matrix core, the Schur update portion, which accounts for a significant portion of the multi-frontier node decomposition, can be mapped to high-throughput matrix operations, thereby improving the numerical computation efficiency within nodes.

[0038] 3. Hierarchical principal unit The hierarchical principal element unit interacts with the computational core, receiving the candidate elements, their positions, and the current decomposition stage information of the current principal element block from the core. It executes principal element selection control during node decomposition. The unit compares candidate elements within the current principal element block and returns the selected principal's position information, exchange control information, and decomposition-related control information to the computational core. This controls the exchange semantics and data access order in the current node's principal element block LU decomposition and subsequent triangulation and Schur updates. Simultaneously, the hierarchical principal element unit sends the principal element position and exchange control information to the address translation unit. The hierarchical principal element unit can employ tree-based comparison, hierarchical comparison, or other comparison structures suitable for hardware implementation to shorten the principal element selection path and improve intra-node control efficiency.

[0039] 4. Address Translation Unit The address translation unit maintains the local row and column mapping relationship during the execution of the current node based on the information output by the hierarchical principal unit and the current row and column access request issued by the computing core. It processes row permutation logic and generates row permutation mapping information based on this relationship, including the row permutation logical address, row address redirection mapping relationship, and row permutation result. This information is then fed back to the computing core, enabling it to locate and access data within the execution buffer. Simultaneously, the updated mapping table information is provided to the global control unit to facilitate data prefetching, result write-back, and external storage updates for subsequent nodes. In this invention, row permutation and related address updates are not achieved through large-scale data migration of the underlying layers. Instead, the mapping relationship maintained by the address translation unit logically redirects subsequent accesses. When a local row swap occurs within a node due to principal selection, the address translation unit updates the corresponding row mapping table. Subsequent computing cores, scatter assembly submodules, or factor write-back submodules obtain the logical address through the mapping relationship when accessing target data, thus avoiding frequent data entity migration.

[0040] 5. Dual-buffered storage management unit The dual-buffered storage management unit is configured with at least two buffers for alternately storing node tasks and frontier data in multi-frontier matrix factorization during node execution. This structure divides the node execution process into a computation phase and a prefetch phase: while the current node occupies a buffer for numerical decomposition, the global control unit alternately manages the buffers in the prefetch and execution states. The dual-buffered storage management unit feeds back the status of each buffer (such as idle, occupied, prefetch, and loading states) to the global control unit. The buffer with completed data prefetching is used as the execution buffer, providing the computation core with the prefetched node data and frontier data. Based on the node dependency status, it determines whether the next candidate node satisfies the dependency constraints. If so, the other idle buffer is used as the prefetch buffer, and the frontier data prefetching of the next candidate node is executed in parallel. After the current node's computation is complete, the global control unit controls the dual-buffered storage management unit to switch buffers, releasing the current execution buffer and reallocating it as a prefetch buffer, while simultaneously switching the prefetch buffer with completed prefetching to the execution buffer for node loading. This architecture achieves task-level parallelism of computation and memory access by relying on gating mechanisms and coupling with a double-buffered pipeline, while ensuring data consistency.

[0041] like Figure 2As shown, the dual-buffered storage management unit consists of Buffer 1 and Buffer 2, both used to cache node tasks and their corresponding leading-edge data, serving as the task input source for the micro-scheduling submodule. Its execution flow is as follows: After system initialization, the leading-edge data of the first node is loaded into Buffer 1, and numerical decomposition is initiated; simultaneously, Buffer 2 is in an idle state. The micro-scheduling submodule queries the node dependency status. If the secondary node satisfies all parent node dependency constraints (node ​​count value is 0), then Buffer 2 is triggered to perform the prefetch operation of the secondary node's leading-edge data. When the node in Buffer 1 has finished computation, the buffer management submodule performs a context switch, transferring execution to Buffer 2 for node computation. Buffer 1 then writes back the results and resets to an idle state, preparing for the next round of prefetching. This process is iteratively executed, forming an overlapping "computation-prefetch" pipeline. Compared to traditional single-buffered serial processing, the dependency-aware gating strategy avoids invalid prefetching and data conflicts, significantly reducing the performance bottleneck caused by the storage wall.

[0042] The double-buffering mechanism of this invention is not a simple fixed rotation, but rather linked to the node dependency gating results. That is, the free buffer will only receive the leading data of the next candidate node when the next candidate node meets the dependency conditions and is determined to be allowed to load. Through this dependency-aware double-buffering structure, the correctness of parent-child dependencies can be guaranteed while making the "current node computation" and "next node prefetching" overlap as much as possible in time, thereby reducing the waiting cycle caused by external storage access.

[0043] like Figure 3 and 4 As shown, the workflow of the dependency-aware prefetch accelerator for sparse matrix factorization in this invention is as follows: S1. The node tasks generated by the software preprocessing part are written into the task area in sequence. The task reading submodule in the global control unit reads the node tasks from the externally stored task area and parses them to obtain the task description information of the current node. The task description information of the node can be put into the candidate queue and sent to the dependency scoreboard module and the buffer management submodule. S2. The dependency scoring module determines whether a node meets the execution conditions (i.e., whether the dependency conditions are met) based on the current node's count value. Assuming the node's predefined count is 0, if the count is not 0, it indicates that the node still has child nodes whose updates have not yet been written back, and the current node cannot enter the loading phase. If the count is 0, it indicates that all child nodes the node depends on have been updated and written back, and the current node can enter the subsequent loading and execution phases. When the dependency scoring module determines that a node meets the dependency conditions, and the buffer management submodule detects an idle buffer, the front-end loading unit reads the corresponding front-end data from the external storage based on the front-end matrix address information given by the current node's task description information and loads it into the target buffer. The loaded data includes at least the front-end matrix tail data, exponent data, and necessary local metadata. S3. After the current node data is loaded, the micro-scheduling submodule initiates the numerical computation process for that node. First, the hierarchical principal component unit and the computational core work together to perform principal component matrix decomposition on the current node, including principal component selection, necessary local row swapping control, and principal component block LU decomposition. After the principal component block decomposition is complete, the computational core continues to perform triangulation operations on the relevant sub-blocks in the current node to calculate the multipliers or intermediate results required for subsequent update processes. After completing the triangulation, the matrix computation unit performs GEMM update operations based on the block data of the remaining update region in the current node. The local L / U factor of the current node is written back to the factor area of ​​the external storage by the factor write-back unit; the updated data generated by the current node is written to the corresponding position of the parent node's leading edge matrix or written to the update area for subsequent parent node assembly by the scattering assembly unit, which performs address mapping, alignment, and write-back according to the mapping table. S4. After the current node update is completed and written back, the factor write-back unit and the scattering assembly unit report the write-back or scattering completion status to the micro-scheduling submodule. The micro-scheduling submodule sends a completion return signal to the dependency scoring board submodule to update the parent node's count value. The dependency scoring board submodule decrements the count value of the corresponding parent node based on the parent node identifier carried in the completion signal. If the updated count value of the parent node is still greater than zero, the parent node remains in a waiting state; if the updated count value is reduced to zero, the parent node is marked as prefetchable or executable, thus entering the subsequent scheduling link. S5. After the current node completes its execution, its own state is marked as task completed. Furthermore, as a child node of its parent node, it will continue to trigger updates to the counts of higher-level nodes. Thus, node completion information propagates upwards along the elimination tree, releasing new executable nodes layer by layer.

[0044] The asynchronous circuit of the aforementioned dependency-aware prefetch accelerator for sparse matrix factorization adopts a clockless fully asynchronous micropipeline structure. The asynchronous micropipeline structure is built through asynchronous control components, which strictly constrains the timing relationship between the data path and the corresponding control signal, effectively ensuring the timing correctness of the asynchronous circuit at the implementation level.

[0045] Asynchronous control components such as Figure 5 As shown, it includes: Source: The starting node of the asynchronous micropipeline, used to generate the initial trigger event to drive the operation of subsequent pipelines; Trap: is the termination node of an asynchronous micropipeline, used to receive and terminate the end event at the end of the pipeline; Merge: Used to receive multiple concurrent event and data requests and aggregate them into a single event and data output; Arbiter: Used to receive multiple concurrent event and data requests, and arbitrate them according to preset priority rules, selecting the event and data with the highest priority to output; Mutex: Used to control the mutual exclusion of multiple concurrent event and data inputs, allowing only one event and data output at a time; Splitter: Used to receive one event and data input and distribute it as multiple events and data outputs; Selector: Used to receive one event and data input, and select the corresponding event and data from multiple output channels for output based on the valid selection signal of the external input; Fifo: Used to receive one event and data input, and generate multiple pulse signals in sequence during transmission to trigger combinational logic circuits (CL) to achieve data buffering and output of one event and data.

[0046] In the process of building an asynchronous micropipeline structure, the appropriate asynchronous control components can be selected based on the specific input and output of events and data in the circuit. Taking the control chain dependent on the scoreboard module as an example, as follows... Figure 6 As shown, the task initialization signal and task update signal are input to the convergence structure, which converges them into a unified marker signal and then inputs it to the routing structure. The routing structure outputs three signals: initialization success signal, task ready signal, and update signal, which are input to the corresponding FIFOs respectively. The initialization success signal and task ready signal output by two of the FIFOs are input to another convergence structure, and after convergence, they are output to the start signal of the next module. The update signal output by the third FIFO is input to the trap structure and then the process ends.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dependency-aware prefetch accelerator for sparse matrix factorization, characterized in that, include: Global Control Unit: Used to read node tasks from the task area of ​​external storage, determine node dependency status, interact bidirectionally with the dual-buffered storage management unit, send node prefetching and loading control information to the dual-buffered storage management unit according to node dependency status and buffer status, and send node start signal and stage switching signal to the computing core according to node dependency status and buffer ready status; respond to the node computation completion signal returned by the computing core and send buffer switching and release control information to the dual-buffered storage management unit. The write-back or scattering completion feedback returned by the receive factor write-back unit or scattering assembly unit is used to update the node dependency state; The control factor write-back unit or scattering assembly unit, with the support of the calculation results output by the calculation core and the row permutation mapping information provided by the address transformation unit, completes the factor write-back or updates the scattering. The computational core is used to read the leading edge data of the node from the currently executing buffer in the double-buffered storage management unit according to the node start signal and stage switching signal sent by the global control unit, and locate the data in the buffer according to the row permutation mapping information provided by the address translation unit. During the computation process, it performs principal block LU decomposition, triangulation, and Schur update; outputs the candidate elements and related computation status of the current principal block to the hierarchical principal unit, and adjusts the principal block LU decomposition, triangulation, and Schur update process according to the information returned by the hierarchical principal unit; after the node computation is completed, the computational core returns a node completion signal to the global control unit. Hierarchical principal element unit: It is used to receive the candidate elements, candidate element position information and current decomposition stage information of the current principal element block output by the computing core, compare the candidate elements and determine the principal element, and return the principal element position, exchange control information and decomposition control information to the computing core; at the same time, the principal element position and exchange control information are sent to the address translation unit. Address Translation Unit: Used to update the local row and column mapping relationship of the current node based on the principal position and exchange control information output by the hierarchical principal unit and the current row and column access request issued by the computing core; feed back the generated row permutation mapping information, including the row permutation logical address, row address redirection mapping relationship and row permutation result to the computing core; at the same time, provide the updated mapping table information to the global control unit; Dual-buffered storage management unit: Configured with at least two buffers, which are alternately managed under the control of the global control unit, and are in the prefetch state and the execution state.

2. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 1, characterized in that, The node dependency state determination refers to determining whether all child nodes of the current node have completed the update and write-back, thereby determining the node dependency state; if all child nodes of the current node have completed the update and write-back, then the dependency state of the current node is determined to be resolved.

3. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 1 or 2, characterized in that, The dual-buffered storage management unit, under the control of the global control unit, manages the buffers in the prefetch and execution states alternately as follows: The dual-buffered storage management unit feeds back the status of each buffer to the global control unit. Based on the node dependency status and the buffer status, the global control unit uses the buffer that has completed data prefetching as the execution buffer, providing the computing core with the prefetched node-corresponding data and leading-edge data, and uses the other buffer as the prefetch buffer. After receiving the node computation completion information returned by the computing core, the global control unit controls the dual-buffered storage management unit to switch buffers, releasing the current execution buffer and reallocating it as the prefetch buffer, while simultaneously switching the prefetch buffer that has completed prefetching as the execution buffer, thereby achieving parallel data prefetching and node computation.

4. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 1, characterized in that, The global control unit includes: Task Reading Submodule: Used to read and parse node tasks from the external storage task area to obtain the task description information of the current node, including the current node identifier, parent node identifier, number of child nodes, total node dimension, principal block dimension, front matrix address, mapping table address, factor write-back address, and update write-back address, and output the task description information to the Dependency Scoreboard Submodule, Buffer Management Submodule, and Micro-Scheduling Submodule. Dependency Scoreboard Module: Based on the dependency scoreboard, maintain the parent-child dependency state between nodes, and perform gating control on the prefetching, loading or execution of the current node according to the completion status of the child node update writeback. Receive the writeback or scatter completion status fed back by the micro-scheduling submodule to update the node dependency state, and send the node dependency state after the child node update writeback is completed to the buffer management submodule. The buffer management submodule is used to manage the loading and releasing of at least two buffers in the dual-buffered storage management unit during the node prefetching, node execution, and node write-back processes, based on the node dependency status and buffer status, and to feed back the buffer loading status to the micro-scheduling submodule. Micro-scheduling submodule: Based on the task description information of the current node, the buffer loading status, and the status of relevant computing units in the computing core, the micro-scheduling submodule dynamically decides the start conditions, execution order, and switching timing of each execution stage of the current node, and sends micro-scheduling instructions to the computing core according to the decision results; after the computing core completes the calculation of the current node, the micro-scheduling submodule controls the factor write-back unit or scattering assembly unit to complete the factor write-back or update the scattering, and at the same time feeds back the write-back or scattering completion status to the dependent scoreboard submodule.

5. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 4, characterized in that, The dependency scoring module maintains a count value for each node. After the child node updates and writes back, the count of the corresponding parent node is decremented. When the count is reduced to a predetermined value, the corresponding parent node is set to the state of being allowed to prefetch or allowed to execute.

6. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 5, characterized in that, The dependent scoreboard module configures a node status table, a count table of child nodes to be completed, node identifier matching and update logic, license generation logic, and a completion return interface; The node status table is used to record the current lifecycle status of each node, including not in the scheduling state, waiting for dependencies state, allowed prefetching state, loaded state, executing state, writing back state, and completed state; The pending child node count table is used to record the number of child nodes that have not yet been written back for each node, and is maintained in the form of a count value. The node identifier matching and update logic is used to locate the corresponding parent node's entry based on the parent node identifier in the child node's write-back completion signal, and update the count value and status information of the corresponding child node to be completed by the parent node. The license generation logic is used to generate node-level prefetch license signals, load license signals, and execute license signals based on the node status table and the count table of child nodes to be completed. The completion return interface is used to receive the update write-back completion signal and release the parent node's dependencies.

7. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 4, characterized in that, The current node execution phase of the dynamic decision-making of the micro-scheduling submodule includes the principal component selection phase, the principal component block LU decomposition phase, the triangulation solution phase, the Schur update phase, the factor write-back phase, and the matrix update generation and assembly phase.

8. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 1, characterized in that, The computing core includes a RISC-V processor and multiple matrix computing units. The RISC-V processor is used to perform principal block LU decomposition, data alignment and scaling, exponential coordination before update write-back, and low-parallel scalar operations. The matrix computing units are used to perform high-throughput matrix multiplication and addition operations within nodes during the Schur update phase, and support signed integer addition, subtraction, and multiplication combination operations.

9. The dependency-aware prefetch accelerator for sparse matrix factorization as described in claim 1, characterized in that, The hierarchical principal unit adopts a tree-like comparison or hierarchical comparison structure.

10. An asynchronous circuit for a dependency-aware prefetch accelerator for sparse matrix factorization as described in any one of claims 1-9, characterized in that, The asynchronous circuit employs an asynchronous control component to construct an asynchronous micropipeline structure, the asynchronous control component comprising: Source: This is the starting node of the asynchronous micropipeline, used to generate the initial trigger event to drive the operation of subsequent pipelines; Sink: is the termination node of an asynchronous micropipeline, used to receive and terminate the end event at the end of the pipeline; Aggregation: Used to receive multiple concurrent event and data requests and aggregate them into a single event and data output; Arbitration: Used to receive multiple concurrent event and data requests, and to arbitrate according to preset priority rules, selecting the event and data with the highest priority for output; Mutual exclusion: Used to control the mutual exclusion of multiple concurrent event and data inputs, allowing only one event and data output at a time; Splitting: Used to receive one channel of event and data input, and then copy and distribute it into multiple channels of event and data output; Path selection: Used to receive one event and data input, and select the corresponding event and data from multiple output channels for output based on the valid selection signal of the external input; Fifo: Used to receive one event and data input, and generate multiple pulse signals in sequence during transmission to trigger combinational logic circuits, thereby realizing data buffering and one event and data output.

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