Pcie physical layer synchronization training method, electronic device, computer program product

Abstract

The application relates to a PCIe physical layer synchronization training method applied to a system comprising at least one host and a plurality of endpoint devices. After initialization and configuration, the host confirms the ready state of each endpoint device through at least one training latch signal line corresponding to each endpoint device. After confirming that all endpoint devices are ready, the host broadcasts a synchronization clock signal to the plurality of endpoint devices through a synchronization clock signal line independent of the PCIe link, so that all endpoint devices simultaneously start PCIe link training. The host configures a software polling task to poll the state of each PCIe link during PCIe link training, and performs fault tolerance processing on an abnormal link when detecting an abnormal link. The PCIe physical layer synchronization training method combines hardware signaling triggering and software state polling to realize high-precision synchronization and fault tolerance double protection.

Description

Technical Field

[0001] This application relates to the technical field of high-speed serial bus communication, and in particular to a PCIe physical layer synchronous training method, electronic device, and computer program product. Background Technology

[0002] In related technologies, a multi-channel communication architecture using a master processor and multiple slave devices via a PCIe bus has become mainstream in modern high-performance embedded systems and computing platforms. For example, in a typical application, a master control chip acts as the root complex, connected to four FPGA endpoint devices via four independent PCIe 3.0 x1 links. In this architecture, the FPGA primarily serves as a high-speed communication interface, responsible for data aggregation, conversion, and bridging with external devices, while the master control chip handles central data processing and system control.

[0003] However, according to the PCIe bus specification, the establishment process of each link (i.e., link training) is independent and asynchronous. The timing of each link completing training and entering a stable operating state (L0 state) is uncertain, resulting in significant timing skew between channels. This inherent asynchronicity constitutes a serious technical bottleneck for applications requiring strict time determinism.

[0004] Among the related technologies, there are two main schemes for link training: One method is software polling: the master control unit reads the status registers of each link through software and starts them all at once after all links have entered the L0 state. This method requires no additional hardware, but the synchronization accuracy is affected by the software scheduling delay, it cannot eliminate physical layer skew, and it consumes CPU resources.

[0005] The second method is dedicated hardware synchronization: high-precision synchronization is achieved using dedicated hardware circuits (such as the Sysref synchronization mechanism in the JESD204B standard). This method offers high synchronization accuracy, but requires dedicated chips, resulting in high costs and poor versatility.

[0006] The above technologies still cannot achieve an effective balance between synchronization accuracy, implementation cost, and versatility. Summary of the Invention

[0007] To overcome the problems existing in related technologies, this application provides a low-cost, high-precision, and highly versatile multi-channel PCIe link synchronization scheme to solve the technical problem that existing technologies cannot balance synchronization accuracy, cost, and versatility.

[0008] The first aspect of this application provides a PCIe physical layer synchronous training method, applied to a system comprising at least one master control terminal and multiple endpoint devices, characterized in that it includes: After initialization and configuration, the master control terminal confirms the ready status of each endpoint device through at least one training latch signal line corresponding to each endpoint device. After confirming that all endpoint devices are ready, the master control terminal broadcasts a synchronization clock signal to multiple endpoint devices via a synchronization clock signal line independent of the PCIe link, so that all endpoint devices can start PCIe link training simultaneously. The master control terminal is configured with a software polling task. During PCIe link training, the software polling task polls the status of each PCIe link and performs fault tolerance processing on the abnormal training link when an abnormal training link is detected.

[0009] In at least one possible implementation, when the master control terminal polls the status of each PCIe link through the software polling task, it further includes: The main control unit starts a timeout timer; When polling the status of each PCIe link, for links that successfully enter the L0 state within the timeout period, the master control terminal updates its status identifier to training complete; if there are still links that have not completed training after the timeout, a software reset command and / or re-enable command is sent to the links that have not completed training, and a pure software polling mode is entered to continuously monitor until the links that have not completed training enter the L0 state or the maximum number of retries is reached.

[0010] In at least one possible implementation, the endpoint device has a status feedback mechanism, wherein the endpoint device reserves a status register in its PCIe configuration space; the endpoint device writes its own link training status into the status register, and when the master control terminal is polling, it reads the status register to obtain the link training status of the endpoint device.

[0011] In at least one possible implementation, the synchronization clock signal can also be characterized by inserting a unique flag that distinguishes it from a normal square wave at a specific edge of a continuous square wave clock signal, and each of the endpoint devices synchronously initiates PCIe link training by detecting the flag.

[0012] In at least one possible implementation, the master control terminal is initialized and configured, including: Configure the PCIe controller to keep all links that need to be synchronized disabled or reset. The master control terminal includes general-purpose input / output pins. The master control terminal configures at least one of the general-purpose input / output pins as an output mode, serving as the synchronization clock signal line; and configures at least one of the general-purpose input / output pins as an input mode, serving as the training latch signal line corresponding to each of the endpoint devices.

[0013] In at least one possible implementation, after initializing and configuring the main control terminal, the method further includes: When the master control terminal cannot obtain the training latch signal of the endpoint device, the master control terminal can preset a fixed time delay. When the preset time delay is reached after the master control terminal is initialized, the master control terminal broadcasts a synchronization clock signal to the endpoint device.

[0014] In at least one possible implementation, the synchronization clock signal line adopts a point-to-multipoint broadcast connection topology, and one output pin of the master control terminal is simultaneously connected to the corresponding input pin of all the endpoint devices.

[0015] In at least one possible implementation, the endpoint device is configured with general-purpose input / output pins, at least one of the general-purpose input / output pins is configured in input mode for receiving a synchronization clock signal, and at least one of the general-purpose input / output pins is configured in output mode as the training latch signal line for feeding back signals to the master control terminal.

[0016] In at least one possible implementation, the training latch signal lines of each endpoint device are independent of each other, and the master control terminal accurately identifies the ready state of each endpoint device by reading each training latch signal line one by one.

[0017] In at least one possible implementation, the master control terminal maintains a 2-bit status variable for each PCIe link. The value of the 2-bit status variable corresponds to the link status as follows: 00 corresponds to the link not being initialized or in a reset state; 01 corresponds to the link being trained; 10 corresponds to the link being trained and entering the L0 state; and 11 corresponds to the link training failing or the link being disconnected.

[0018] In at least one possible implementation, the master control terminal manages the 2-bit status variables of all links in a unified manner using a link status table, with the link identifier as an index, and determines whether synchronization is complete by traversing the status table during polling.

[0019] In at least one possible implementation, after the endpoint device is configured, it sets its training latch signal line to an active level and feeds back the training latch signal to the master control terminal.

[0020] A second aspect of this application provides an electronic device including a processor and a memory coupled to the processor. The memory is used to store computer program code, the computer program code including computer instructions, which, when read from the memory by the processor, cause the processor to perform steps in any of the methods described above.

[0021] A third aspect of this application provides a computer program product comprising: computer program code that, when run on a computer, causes the computer to perform the steps of any of the methods described herein.

[0022] The technical solution provided in this application can include the following beneficial effects: This PCIe physical layer synchronous training method, combining hardware signaling triggering (synchronization clock) and software status polling, achieves both high-precision synchronization and fault tolerance. Hardware signaling ensures the real-time nature of synchronous startup, while software polling provides flexibility for anomaly recovery, which is superior to pure hardware or pure software solutions. By forcibly starting multi-link training through a dedicated synchronization clock signal, the problem of scattered link training timing in traditional solutions is solved, significantly improving the synchronization accuracy of multi-channels.

[0023] The technical solution of this application can also: 1. After hardware synchronization fails, it automatically switches to pure software polling mode, which combines the efficiency of hardware with the flexibility of software and has stronger fault tolerance.

[0024] 2. The main control unit centrally manages the status of all links, avoiding the inconsistency issues that may arise from the independent processing of individual devices in existing technologies.

[0025] 3. By using general-purpose I / O pins to replace dedicated FPGA modules, hardware dependence is reduced, making it suitable for a wider range of device scenarios.

[0026] 4. The simplified 2-bit state variable reduces the complexity of state tracking and is more suitable for large-scale multi-link scenarios.

[0027] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0028] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0029] Figure 1 This is a schematic flowchart illustrating the PCIe physical layer synchronous training method in an embodiment of this application; Figure 2 This is a flowchart illustrating the process of polling the status of each PCIe link in the PCIe physical layer synchronous training method shown in the embodiments of this application. Figure 3 This is a schematic diagram of the process with a state feedback mechanism in the PCIe physical layer synchronous training method shown in the embodiments of this application; Figure 4This is a schematic diagram of the initialization configuration process of the master control terminal in the PCIe physical layer synchronous training method shown in the embodiments of this application; Figure 5 This is a flowchart illustrating a specific embodiment of the PCIe physical layer synchronous training method shown in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of an electronic device shown in an embodiment of this application. Detailed Implementation

[0030] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0031] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0032] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0033] This application provides a multi-channel PCIe link synchronization method and system that combines hardware signaling and software polling, aiming to achieve high-precision synchronization while providing strong fault tolerance. This method achieves synchronized startup and fault recovery of all links through hardware signaling interaction between a master control terminal (root complex) and multiple endpoint devices, with a software state machine as the monitoring core.

[0034] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0035] See Figure 1The first aspect of this application provides a PCIe physical layer synchronous training method, applied to a system comprising at least one master control terminal and multiple endpoint devices, including: In step S100, the hardware signaling channel is established and ready to be confirmed: after initialization and configuration, the master control terminal confirms the ready status of each endpoint device through at least one training latch signal line corresponding to each endpoint device. In this embodiment, the synchronization clock signal line is a general purpose input / output (GPIO) pin.

[0036] In step S200, synchronization is triggered: after confirming that all endpoint devices are ready, the master control terminal broadcasts a synchronization clock signal to multiple endpoint devices via a synchronization clock signal line independent of the PCIe link, so that all endpoint devices can start PCIe link training simultaneously.

[0037] In step S300, status monitoring and fault tolerance: The master control terminal is configured with a software polling task. During PCIe link training, the software polling task polls the status of each PCIe link, and when a training abnormal link is detected, fault tolerance processing is performed on the abnormal link.

[0038] This application provides a multi-channel PCIe link synchronization method driven by a combination of hardware signaling and software polling, aiming to achieve high-precision synchronization while providing strong fault tolerance. By coordinating through GPIO hardware signaling during the startup phase, it ensures that all endpoints are ready before triggering uniformly, fundamentally avoiding the problem of "each starting independently and missing the time window." The latency of hardware signaling is much lower than that of software polling, and the synchronization trigger pulse can precisely align the startup times of multiple links to the nanosecond level, a precision that software methods cannot physically achieve. For AI computing scenarios requiring simultaneous high-speed communication from multiple GPU cards, this difference in precision directly affects interconnect performance.

[0039] Specifically, this application embodiment achieves both high-precision synchronization and fault tolerance by combining hardware signaling triggering (synchronization clock) and software status polling. Hardware signaling ensures real-time synchronization startup, while software polling provides flexibility for anomaly recovery, outperforming pure hardware or pure software solutions. By forcibly starting multi-link training through a dedicated synchronization clock signal, the problem of scattered link training timing in traditional solutions is solved, significantly improving multi-channel synchronization accuracy.

[0040] Preferably, at least one master control terminal interacts with multiple endpoint devices via hardware signaling, using a software state machine as the monitoring core to achieve synchronous startup and fault recovery of all links. System initialization involves powering on both the master control terminal and endpoint devices. The master control terminal and endpoint devices prepare synchronously, configuring GPIO pins and the PCIe controller. Endpoint devices synchronously trigger and emit a synchronization clock signal, updating the status of all links to "link training in progress." Standard GPIO pins (non-dedicated synchronization interfaces) are used as the synchronization signaling channel, replacing software polling or complex clock alignment circuits with a hardware edge-triggered mechanism. The propagation delay of the GPIO signal is typically in the nanosecond range (typically < 50ns). Combined with sampling by the FPGA's internal synchronization register, the time deviation of multiple links entering the L0 state can be controlled within 100 nanoseconds, approaching the performance of dedicated synchronization chips, but at only one-thousandth the cost. Furthermore, the GPIO synchronization signal operates independently of the PCIe link, does not occupy PCIe bus bandwidth, and does not depend on PCIe reference clock alignment.

[0041] In at least one possible implementation, see Figure 2 In step S300, when the master control terminal polls the status of each PCIe link through the software polling task, the method further includes: step S301, the master control terminal starts a timeout timer; step S302, when polling the status of each PCIe link, for links that successfully enter the L0 state within the timeout period, the master control terminal updates their status identifier to training completed; if there are still links that have not completed training after the timeout, a software reset command and / or re-enable command is sent to the links that have not completed training, and a pure software polling mode is entered to continuously monitor until the links that have not completed training enter the L0 state or the maximum number of retries is reached.

[0042] In this embodiment, the system automatically switches to a pure software polling mode after hardware synchronization failure, combining hardware efficiency with software flexibility for enhanced fault tolerance. This fault-tolerant processing employs a layered architecture of "hardware synchronization first, then degrading to software polling after timeout." Under normal circumstances, it relies on high-precision hardware triggering; in abnormal situations, it automatically degrades to software mode as a backup, achieving a delicate balance between performance and reliability.

[0043] In at least one possible implementation, see Figure 3 Step S401: The endpoint device has a status feedback mechanism, and the endpoint device reserves a status register in its PCIe configuration space; Step S402: The endpoint device writes its own link training status into the status register, and when the master control terminal is polling, it reads the status register to obtain the link training status of the endpoint device.

[0044] In this embodiment, a mechanism for proactively reporting status is provided, improving status transparency from inference to direct reading and reducing the risk of misjudgment during polling by the master control terminal. Specifically, each endpoint device reserves a status register in its PCIe configuration space. The status register is used to store the current link training status of the endpoint device. During execution, each endpoint device writes its own link training status into the status register in real time. The link training status uses the same encoding as the link status variable of the master control terminal. During polling, the master control terminal obtains the link training status of the endpoint devices by reading the status registers of each endpoint device, thereby improving the accuracy and transparency of status monitoring.

[0045] In at least one possible implementation, the synchronization clock signal can also be characterized by inserting a unique flag that distinguishes it from a normal square wave at a specific edge of a continuous square wave clock signal, and each of the endpoint devices synchronously initiates link training by detecting the flag.

[0046] In this embodiment, a continuous square wave with a special edge marker is used to change the triggering mechanism from a single pulse to a periodic square wave with embedded markers, thereby improving anti-interference performance in electromagnetic noise environments. The master control terminal generates a special marker at a specific edge of the continuous square wave clock signal, which is different from the normal square wave, to characterize the synchronous triggering action. The special marker includes at least one of pulse width abnormality or level duration deviation. Each endpoint device detects the special marker to identify the synchronous clock signal and synchronously start PCIe link training, thereby enhancing triggering reliability in electromagnetic interference environments.

[0047] In at least one possible implementation, see Figure 4 In step S100, the main control terminal is initialized and configured, including: Step S101: Configure the PCIe controller to keep all links that need to be synchronized in a disabled or reset state. Step S102, the master control terminal includes general-purpose input / output pins, the master control terminal configures at least one of the general-purpose input / output pins as output mode as the synchronization clock signal line; and configures at least one of the general-purpose input / output pins as input mode as the training latch signal line corresponding to each endpoint device.

[0048] In this embodiment, the master control terminal keeps all PCIe links in a disabled / reset state, and configures the synchronous clock signal line (output) and training latch signal line (input) through general-purpose I / O pins. In this method, the dedicated hardware signal lines include the synchronous clock signal line and training latch signal line configured by the general-purpose I / O pins, and the "dedicated hardware signal lines" are implemented at the GPIO level. Before issuing the synchronous clock signal, the master control terminal ensures that all PCIe links are in a disabled or reset-held state. The time difference between the issuance time of the synchronous clock signal and the time when each endpoint device starts PCIe link training is less than the link training time window length specified by the PCIe protocol, so as to ensure that each link completes synchronous handshake within the same training time window.

[0049] In at least one possible implementation, after initializing the master control terminal, the method further includes: when the master control terminal cannot obtain the training latch signal of the endpoint device, the master control terminal can preset a fixed delay, and when the preset delay is reached after the master control terminal is initialized, the master control terminal broadcasts a synchronization clock signal to the endpoint device.

[0050] In this embodiment of the application, after the master control terminal completes the configuration, it waits for a preset fixed delay and then directly sends a synchronization clock signal without waiting for the ready status feedback signal from each endpoint device; the length of the preset fixed delay is not less than the maximum time required for each endpoint device to complete the local initialization configuration.

[0051] In at least one possible implementation, the synchronization clock signal line adopts a point-to-multipoint broadcast connection topology, and one output pin of the master control terminal is simultaneously connected to the corresponding input pin of all the endpoint devices.

[0052] In this embodiment, the synchronization clock signal line adopts a point-to-multipoint broadcast connection topology. One output pin of the master control terminal is simultaneously connected to the corresponding input pins of all endpoint devices, so that each endpoint device can receive the same synchronization clock signal in physical parallel, eliminating timing deviations caused by different signal transmission paths.

[0053] In at least one possible implementation, the endpoint device is configured with general-purpose input / output pins, at least one of the general-purpose input / output pins is configured in input mode for receiving a synchronization clock signal, and at least one of the general-purpose input / output pins is configured in output mode as the training latch signal line for feeding back signals to the master control terminal.

[0054] In this embodiment, the endpoint device is configured with a synchronous clock receiving pin (input) and a training latch feedback pin (output). By using general-purpose I / O pins to replace dedicated hardware modules, hardware dependence is reduced, making it suitable for a wider range of device scenarios.

[0055] In at least one possible implementation, the training latch signal lines of each endpoint device are independent of each other, and the master control terminal accurately identifies the ready state of each endpoint device by reading each training latch signal line one by one.

[0056] In this embodiment, the readiness feedback signal lines of each endpoint device are independent of each other. Each endpoint device outputs its readiness status to the master control terminal through a dedicated feedback pin. The master control terminal assigns a corresponding dedicated input pin to each endpoint device. By reading the status of each independent feedback signal line one by one, the master control terminal identifies the readiness status of each endpoint device, thereby supporting the precise location and selective processing of non-ready endpoint devices. The master control terminal utilizes the status information independently fed back by each endpoint device to perform software reset only on links that have not yet completed training, without restarting links that have completed training.

[0057] In at least one possible implementation, the master control terminal maintains a 2-bit status variable for each PCIe link. The value of the 2-bit status variable corresponds to the link status as follows: 00 corresponds to the link not being initialized or in a reset state; 01 corresponds to the link being trained; 10 corresponds to the link being trained and entering the L0 state; and 11 corresponds to the link training failing or the link being disconnected.

[0058] In this embodiment, a simplified 2-bit state variable is used to reduce the complexity of state tracking, making it more suitable for large-scale multi-link scenarios. Furthermore, the 2-bit state variable (00 / 01 / 10 / 11) clearly defines the link lifecycle, and combined with software polling, it achieves fine-grained fault tolerance. This state coding system allows the master control unit to manage the parallel states of multiple links simultaneously, and accurately identify "which links are still in training (01), which have succeeded (10), and which have completely failed (11)" during timeout switching. This is the foundation for achieving multi-channel differentiated fault tolerance processing. Simultaneously, this 2-bit state variable's fine tracking of the link lifecycle is the basic data structure enabling hierarchical fault-tolerant architecture and parallel multi-link management. Specifically, when the system powers on, the 2-bit state variables of all links are initialized to 00; when a synchronization clock signal is issued, the state variables of all links are synchronously updated to 01; when a link enters the L0 state, the corresponding link's state variable is updated to 10; when a link reaches the maximum number of retries and still fails, the corresponding link's state variable is updated to 11.

[0059] In at least one possible implementation, the master control terminal manages the 2-bit status variables of all links in a unified manner using a link status table, with the link identifier as an index, and determines whether synchronization is complete by traversing the status table during polling.

[0060] In this embodiment, the status of all links is centrally managed by the master control terminal, avoiding the inconsistency issues that may arise from the autonomous processing of single devices in the prior art. The master control terminal manages the status variables of all PCIe links in the form of a link status table. The link status table is indexed by the link identifier, and each record stores the current value of the corresponding link's 2-bit status variable. During the polling process, the master control terminal traverses the link status table to determine whether all links have entered the training completion state in a single query, and updates the corresponding record in the link status table in real time when the link status changes.

[0061] In at least one possible implementation, after the endpoint device is configured, its training latch signal line is set to an active level, and a training latch signal is fed back to the master control terminal.

[0062] In this embodiment, after each endpoint device completes its local configuration, it sets the training latch signal line to an active level, notifying the master control terminal that it is ready (ready state handshake). The master control terminal continuously monitors all training latch signal lines, and once it confirms that all endpoint devices are ready, it sends a signal via the synchronization clock signal line. Simultaneously, the master control terminal updates the status variables of all links to 01. The signal sent via the synchronization clock signal line actively triggers synchronization, and hardware signaling ensures the real-time nature of the synchronization startup. By uniformly triggering the "synchronization clock" signal through the master control terminal, global synchronization across multiple links is achieved, solving the coordination problem between distributed devices.

[0063] In this embodiment, the monitoring and synchronization trigger response of the link training completion status are completely offloaded to the hardware logic. The interaction between the master control terminal and the endpoint devices is directly completed through edge / level changes of dedicated GPIO signals, without the need for CPU polling or interrupt handling. After each endpoint device completes its PCIe physical layer training, the hardware automatically sets the status GPIO to active, without software latency jitter. After all status GPIOs are active, the master control terminal automatically issues a synchronization start GPIO pulse through a hardware timer or combinational logic, with a fixed response delay (usually 1-2 system clock cycles). The entire synchronization process is completed autonomously by the hardware state machine, with the CPU only intervening in case of timeout exceptions. From the completion of the last link training to all links entering L0, the total delay is a fixed value (GPIO transmission delay + hardware logic processing delay), suitable for hard real-time systems.

[0064] Specifically, in this embodiment, the solution can be implemented through the following process, see [link to relevant documentation]. Figure 5 : Step A, System Initialization and State Definition: The master controller powers on all endpoint devices. The master controller initializes one of the aforementioned 2-bit status variables for each PCIe link and sets its initial value to 00.

[0065] Step B, Hardware Synchronization Preparation: B1. Master Control Configuration: Configure the master control unit's PCIe controller to keep all PCIe links requiring synchronization disabled or reset. Simultaneously, configure at least one general-purpose I / O pin as an output mode, serving as a synchronization clock signal line; and configure multiple general-purpose I / O pins as input modes, serving as training latch signal lines corresponding to each endpoint device.

[0066] B2. Endpoint device configuration: Each endpoint device configures at least one general-purpose IO pin in input mode to receive the synchronization clock signal; and configures at least one general-purpose IO pin in output mode as a training latch signal to be fed back to the master control terminal.

[0067] Step C, Ready handshake: After each endpoint device completes its local configuration, it sets its training latch signal line to an active level (e.g., high level) to notify the master control terminal that it is ready.

[0068] Step D, Synchronize Triggering and Status Update: The master control unit continuously monitors all training latch signal lines. Once it confirms that all endpoint devices are ready, it sends a specific synchronization trigger pulse through the synchronization clock signal line. At the same time as sending the pulse, the master control unit updates the status variables of all links to 01 (link training in progress).

[0069] Step E, Hardware Synchronization Verification and Timeout Monitoring: The master control unit starts a timeout timer and enters a polling loop: the master control unit reads the actual PCIe protocol status register of each link. If a link has successfully entered the L0 state, the master control unit updates its corresponding status variable to 10. The master control unit checks if all link statuses are 10. If yes, synchronization is successful and the process ends. If no, synchronization is unsuccessful, and the master control unit checks if a timeout has occurred. If no timeout has occurred, the loop continues; if a timeout has occurred, it proceeds to step F.

[0070] Step F: Fault tolerance and forced software synchronization: When step E exits due to timeout, the master control unit identifies all links whose status is still 01 (training) and determines that hardware synchronization has failed. At this point, the system activates its fault tolerance mechanism: The master control unit executes software reset or re-enable commands for these unready links.

[0071] The master control unit enters a pure software polling mode to continuously monitor the status of these links until they all enter the L0 state (status updated to 10) or eventually fail (status updated to 11).

[0072] Step G: Complete synchronously: When the process ends, all link states are 10, and the system enters a defined synchronous communication state; or at least one link state is 11, and the system reports an error.

[0073] Furthermore, step C above can be omitted: in scenarios where the synchronization accuracy requirement is not extreme or the system behavior is fixed, the training latch handshake can be omitted. After completing its own configuration, the master control unit waits for a preset fixed delay and directly executes step D to send a synchronization trigger pulse.

[0074] The synchronization clock signal line in steps B1 and B2 above can also be replaced by a continuous square wave clock: the master control terminal outputs a continuous square wave and generates a unique flag (such as pulse width abnormality) on a specific edge as a synchronization clock signal. The endpoint device detects this flag to start training synchronously, which enhances the anti-interference capability.

[0075] A mechanism for endpoint devices to proactively report their status can also be added: In step B2, the endpoint device can reserve a status register in its PCIe configuration space. In steps D and E, the endpoint device writes its own link training status (mapped to 00, 01, 10, 11) into this status register. When the master control terminal polls, it can directly read this status register to obtain the status, instead of relying on inference, thereby improving the accuracy and transparency of status monitoring.

[0076] This PCIe physical layer synchronous training method combines hardware signaling triggering (synchronization clock) with software status polling to achieve both high-precision synchronization and fault tolerance. Hardware signaling ensures real-time synchronization startup, while software polling provides flexibility for anomaly recovery, outperforming pure hardware or pure software solutions. By forcibly starting multi-link training through a dedicated synchronization clock signal, the problem of scattered training timing in traditional solutions is solved, significantly improving multi-channel synchronization accuracy.

[0077] The specific beneficial effects can be: 1. Combining high precision and robustness: Compared to software polling, this application achieves nanosecond-level precise synchronization through hardware signaling, completely eliminating the uncertainty of software latency and achieving a qualitative leap in performance. Compared to dedicated hardware solutions, the unique software fault-tolerant mechanism of this application ensures that the system can gracefully degrade in the event of hardware synchronization anomalies, avoiding system paralysis caused by single points of failure, and its reliability far exceeds that of existing technologies.

[0078] 2. Achieving low cost and high versatility: Compared to dedicated hardware solutions, this application only utilizes general-purpose I / O, eliminating the need for expensive dedicated chips and significantly reducing material costs and design complexity. Compared to dedicated hardware solutions, this application does not rely on specific synchronous interfaces and can be widely applied to various commercial standard devices, exhibiting extremely high versatility.

[0079] In summary, this application achieves near-dedicated hardware synchronization performance at a cost close to that of a software solution, and provides fault tolerance capabilities that neither of them possesses. It is a high-performance, high-reliability system-level solution that is unmatched by existing technologies.

[0080] Furthermore, 1. The simplified 2-bit state variable reduces the complexity of state tracking and is more suitable for large-scale multi-link scenarios.

[0081] 2. After hardware synchronization fails, it automatically switches to pure software polling mode, which combines the efficiency of hardware with the flexibility of software and has stronger fault tolerance.

[0082] 3. The main control unit centrally manages the status of all links, avoiding the inconsistency issues that may arise from the independent processing of individual devices in existing technologies.

[0083] 4. By using general-purpose I / O pins to replace dedicated FPGA modules, hardware dependence is reduced, making it suitable for a wider range of device scenarios.

[0084] Corresponding to the aforementioned application function implementation method embodiments, this application also provides a system, electronic device, and corresponding embodiments for PCIe physical layer synchronous training.

[0085] This application provides a system for synchronous training of the PCIe physical layer, comprising: a master control terminal, wherein the master control terminal is provided with a PCIe controller and a general-purpose I / O unit, and the PCIe controller is provided with multiple ports; multiple endpoint devices, wherein the endpoint devices are provided with a PCIe core and general-purpose I / O pins, and the PCIe core is connected to the ports via a PCIe link; the general-purpose I / O unit sends a synchronization clock signal to the general-purpose I / O pin, and the general-purpose I / O pin feeds back a training latch signal to the general-purpose I / O unit.

[0086] At the center is the root complex, which connects to the peripheral endpoint devices via multiple PCIe links and GPIO signal lines. Key elements include: a link status table maintained by the root complex; a sync clock output line serving as a "broadcast" signal; training latch input lines used by each endpoint device to provide feedback on its readiness status; and multiple independent PCIe data links.

[0087] Specifically, the functional modules of the main control terminal include a software state machine, which is connected to the link state management module, the PCIe control and polling module, and the synchronization signaling control module. The software state machine is the control core, the link state management module is used to maintain the state table, the PCIe control and polling module is used to configure and / or read the state register, and the synchronization signaling control module is used to generate a synchronization clock signal and read the training latch signal.

[0088] Specifically, the endpoint device's functional modules include a local link control module, which is connected to a synchronization signaling detection module and a latch driver module. The local link control module is used to control the start of PCIe training, the synchronization signaling detection module is used to detect the synchronization clock signal, and the latch driver module is used to drive the training latch signal. Furthermore, the endpoint device's functional modules also include a status reporting register, used to store the endpoint device's status.

[0089] Regarding the system in the above embodiments, the specific ways in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0090] Additionally, see Figure 6 This application also provides an electronic device including a processor and a memory, the memory being coupled to the processor, the memory being used to store computer program code, the computer program code including computer instructions, and when the processor reads the computer instructions from the memory, causing the processor to perform the steps in the method described in any at least one of the foregoing embodiments.

[0091] In addition, this application also provides a computer program product, which includes computer program code that, when run on a computer, causes the computer to perform the steps of the method as described in any at least one embodiment.

[0092] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A PCIe physical layer synchronous training method, applied to a system comprising at least one master control terminal and multiple endpoint devices, characterized in that, include: After initialization and configuration, the main control terminal confirms the ready status of each endpoint device through at least one training latch signal line corresponding to each endpoint device. After confirming that all endpoint devices are ready, the master control terminal broadcasts a synchronization clock signal to multiple endpoint devices via a synchronization clock signal line independent of the PCIe link, so that all endpoint devices can start PCIe link training simultaneously. The master control terminal is configured with a software polling task. During PCIe link training, the software polling task polls the status of each PCIe link and performs fault tolerance processing on the abnormal training link when an abnormal training link is detected.

2. The PCIe physical layer synchronous training method according to claim 1, characterized in that, When the master control terminal polls the status of each PCIe link through the software polling task, it also includes: The main control unit starts a timeout timer; When polling the status of each PCIe link, for links that successfully enter the L0 state within the timeout period, the master control terminal updates its status identifier to training complete; if there are still links that have not completed training after the timeout, a software reset command and / or re-enable command is sent to the links that have not completed training, and a pure software polling mode is entered to continuously monitor until the links that have not completed training enter the L0 state or the maximum number of retries is reached.

3. The PCIe physical layer synchronous training method according to claim 2, characterized in that, The endpoint device has a status feedback mechanism. The endpoint device reserves a status register in its PCIe configuration space. The endpoint device writes its own link training status into the status register. When the master control terminal is polling, it reads the status register to obtain the link training status of the endpoint device.

4. The PCIe physical layer synchronous training method according to claim 1, characterized in that, The synchronization clock signal can also be characterized by inserting a unique flag that differs from a normal square wave at a specific edge of the continuous square wave clock signal, and each endpoint device synchronously starts PCIe link training by detecting the flag.

5. The PCIe link physical layer synchronous training method according to claim 1, characterized in that, The main control terminal is initialized and configured, including: Configure the PCIe controller to keep all links that need to be synchronized disabled or reset. The master control terminal includes general-purpose input / output pins. The master control terminal configures at least one of the general-purpose input / output pins as an output mode, serving as the synchronization clock signal line; and configures at least one of the general-purpose input / output pins as an input mode, serving as the training latch signal line corresponding to each of the endpoint devices.

6. The PCIe physical layer synchronous training method according to claim 5, characterized in that, After initializing and configuring the main control terminal, the following is also included: When the master control terminal cannot obtain the training latch signal of the endpoint device, the master control terminal can preset a fixed time delay. When the preset time delay is reached after the master control terminal is initialized, the master control terminal broadcasts a synchronization clock signal to the endpoint device.

7. The PCIe physical layer synchronous training method according to claim 5, characterized in that, The synchronization clock signal line adopts a point-to-multipoint broadcast connection topology, and one output pin of the master control terminal is simultaneously connected to the corresponding input pin of all the endpoint devices.

8. The PCIe physical layer synchronous training method according to claim 5, characterized in that, The endpoint device is configured with general-purpose input / output pins, at least one of the general-purpose input / output pins is configured as an input mode for receiving a synchronization clock signal; and at least one of the general-purpose input / output pins is configured as an output mode for serving as the training latch signal line for feeding back signals to the master control terminal.

9. The PCIe physical layer synchronous training method according to claim 8, characterized in that, The training latch signal lines of each endpoint device are independent of each other, and the master control terminal accurately identifies the ready state of each endpoint device by reading each training latch signal line one by one.

10. The PCIe physical layer synchronous training method according to claim 1, characterized in that, The master control terminal maintains a 2-bit status variable for each PCIe link. The value of the 2-bit status variable corresponds to the link status as follows: 00 corresponds to the link being uninitialized or in a reset state; 01 corresponds to the link being in training. 10 corresponds to the link training being completed and entering the L0 state; 11 corresponds to the link training failing or the link being disconnected.

11. The PCIe physical layer synchronous training method according to claim 10, characterized in that, The master control terminal uses a link status table to uniformly manage the 2-bit status variables of all links, using the link identifier as an index. During polling, it traverses the status table to determine whether synchronization is complete.

12. The PCIe physical layer synchronous training method according to claim 8, characterized in that: After the endpoint device is configured, its training latch signal line is set to an active level, and the training latch signal is fed back to the master control terminal.

13. An electronic device, characterized in that, The method includes a processor and a memory coupled to the processor. The memory is used to store computer program code, which includes computer instructions that, when the processor reads the computer instructions from the memory, cause the processor to perform the steps of the method as described in any one of claims 1-12.

14. A computer program product, characterized in that, The computer program product includes: computer program code that, when the computer program product is run on a computer, causes the computer to perform the steps of the method as described in any one of claims 1-12.

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