A data encryption method, system, computer device and storage medium

Abstract

The application discloses a data encryption method and system, computer equipment and a storage medium, and relates to the technical field of information security. The method comprises the following steps: inputting to-be-encrypted data into an S box; performing isomorphic mapping on the to-be-encrypted data by using an isomorphic matrix; performing inverse operation on the data generated by the isomorphic mapping on a composite field, performing inverse isomorphic mapping on the operation result by using an inverse matrix of the isomorphic matrix; performing affine transformation on the result of the inverse isomorphic mapping, and outputting encrypted data by the S box; controlling random negation and correction of S box output by setting a linear feedback shift register; and sending n-bit random numbers generated by the linear feedback shift register into n+1-bit right shift registers X and Y after right padding 0 and left padding 0, so as to realize random negation and correction of the S box output. The method controls random negation and correction in the S box encryption process by setting the linear feedback shift register, thereby affecting side channel information of the encryption result, and further realizing anti-side channel attack.

Description

Technical Field

[0001] This invention relates to the field of information security technology, specifically to a data encryption method, system, computer device, and storage medium. Background Technology

[0002] Currently, there are three hardware implementation methods for S-boxes: implementation based on direct mapping (lookup table, LUT), implementation based on combinational logic algorithms, and implementation based on composite field algorithms. ROM-based LUTs require a large amount of memory, increasing circuit area overhead, and the fixed access time of the ROM leads to high latency. In contrast, S-boxes based on combinational logic are implemented using logical expressions directly derived from truth tables. However, due to the complexity of these logical expressions, a large number of logic gates are required, resulting in significant resource overhead. In this context, the composite field-based S-box implementation significantly optimizes S-box design. It decomposes computation into lower-order domains and performs inversion operations in these lower-order domains, effectively reducing the area overhead in S-box implementation.

[0003] Research on composite S-boxes primarily focuses on improving performance by selecting different fields and representation bases, employing an exhaustive strategy to choose the optimal generator polynomial and corresponding transformation matrix. In 2015, Ueno et al. from Tohoku University in Japan constructed a top-performing S-box in GF(2πf) using a hybrid approach of normal bases, redundant representation bases, and polynomial rings. 4 The most efficient composite domain S-box in the domain; for resisting side-channel attacks on composite domain S-boxes, a common solution is the composite domain masking scheme, the specific process of which is as follows: Figure 1 As shown, this scheme first adds a mask to the input (by XORing the plaintext with the mask), then performs a composite field inversion and affine transformation on the masked input, and finally compensates the masked encrypted data using a mask correction module, thus restoring the output to its unmasked state. The principle of the masking scheme is to protect data security by shielding the encrypted data. Meanwhile, Jiang Jiuxing et al. proposed a general high-order masking scheme based on a composite field S-box, which significantly reduces the complexity of the masking scheme through extensive module reuse. However, this scheme is based on a polynomial basis, making it difficult to apply to composite field S-boxes with other representation bases. Furthermore, once the masking scheme is determined, the S-box construction is fixed, which to some extent reduces the overall resistance to side-channel attacks.

[0004] In summary, most data encryption technologies currently in use fix the generator polynomial for the composite field S-box structure, which fixes the inversion operation in the composite field, resulting in their inadequacy in resisting side-channel attacks. Summary of the Invention

[0005] Considering that existing technologies fix the generator polynomial for the composite domain S-box structure, thus fixing the inversion operation in the composite domain and leading to its inadequacy in resisting side-channel attacks, this invention proposes a data encryption method, system, computer device, and storage medium. Starting from the construction of the composite domain S-box, the properties of the transformation matrix are studied. Utilizing the transformation relationship between adjacent rounds in the encryption algorithm, a method is proposed that, without changing the inversion operation, the output of the S-box can be randomly inverted during the encryption process, thereby affecting the side-channel information of the encryption result. This achieves a secure structure resistant to side-channel attacks, thus solving the problem that existing technologies fix the generator polynomial, resulting in a fixed inversion operation in the composite domain and thus insufficient resistance to side-channel attacks.

[0006] A data encryption method includes the following steps:

[0007] Input the data to be encrypted into the S box;

[0008] Use isomorphic matrices to perform isomorphic mapping on the data to be encrypted;

[0009] The data generated by the isomorphism mapping is placed in the composite domain GF(2). 4 ) and GF(2 2 Perform the inverse operation on );

[0010] The operation result is inversely mapped using the inverse of the isomorphic matrix. A first data selector is set after the XOR operation following the isomorphic mapping, and a second data selector is set after the XOR operation before the inverse isomorphic mapping. A linear feedback shift register (LFSR) is used to control the random inversion and correction of the S-box output data. Right shift registers X and Y are respectively set between the first and second data selectors and the LFSR. The control of the random inversion and correction of the S-box output through the LFSR specifically includes: generating an n-bit random number using the LFSR, padding the n-bit random number with 0 on the right and left, and then feeding it into the (n+1)-bit right shift registers X and Y. These registers control whether the XOR operation corresponding to each of the two data selectors is performed, thereby achieving the random inversion and correction of the S-box output data.

[0011] The result of the inverse isomorphic mapping is subjected to an affine transformation, and then encrypted data is output.

[0012] Furthermore, the method of using isomorphic matrices to perform isomorphic mapping on the data to be encrypted, transforming the elements in the finite field from the standard representation to the composite field representation.

[0013] Furthermore, the inverse matrix of the isomorphic matrix is ​​used to perform an inverse isomorphic mapping on the operation result, converting the operation result from the representation in the composite field to the standard representation in the finite field.

[0014] Furthermore, the output inversion and correction operations of the S-box are performed in two adjacent rounds.

[0015] Furthermore, the synchronization between the inversion operation and the correction operation is achieved by the misalignment pairing of the n+1 bit right shift registers X and Y. Specifically, in the i-th encryption round, the same number generated by the linear feedback shift register LFSR is padded with 0 on the right and 0 on the left to ensure that the control signal X[i] of the i-th round and the control signal Y[i+1] of the i+1-th round are always equal.

[0016] Furthermore, the affine transformation operation includes a multiplication matrix and a constant 8'h63.

[0017] Furthermore, the result of the inverse isomorphic mapping is subjected to an affine transformation to obtain the encrypted data output by the S-box; specifically, the result of the inverse isomorphic mapping is multiplied by a constant matrix on the left and then XORed with the constant 8'h63 to obtain the output result of the S-box.

[0018] Furthermore, a data encryption system includes:

[0019] The data input module is used to input the data to be encrypted into the S-box;

[0020] The inverse module is used to perform isomorphic mapping on the data to be encrypted using isomorphic matrices, and to convert the data generated by the isomorphic mapping into the composite field GF(2). 4 ) and GF(2 2 Perform the inverse operation on );

[0021] The inverse isomorphism module is used to perform inverse isomorphic mapping on the operation result using the inverse matrix of the isomorphic matrix. A first data selector is set after the XOR operation following the isomorphic mapping, and a second data selector is set after the XOR operation before the inverse isomorphic mapping. A linear feedback shift register (LFSR) is also provided to control the random inversion and correction of the S-box output data. Right shift registers X and Y are respectively set between the first and second data selectors and the LFSR. The control of the random inversion and correction of the S-box output through the LFSR specifically includes: generating an n-bit random number using the LFSR, padding the n-bit random number with 0 on the right and left, and then feeding it into the (n+1)-bit right shift registers X and Y. These registers control whether the XOR operation corresponding to each of the two data selectors is performed, thereby achieving the random inversion and correction of the S-box output data.

[0022] The data output module is used to output encrypted data after performing an affine transformation on the result of the inverse isomorphic mapping.

[0023] Furthermore, a data encryption computer device includes: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the data encryption method.

[0024] Furthermore, a readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, are used to perform the steps of the data encryption method.

[0025] This invention provides a data encryption method, system, computer device, and storage medium, which have the following beneficial effects:

[0026] This invention starts from the construction of the composite field S-box, studies the properties of isomorphic and inverse isomorphic matrices, and utilizes the transformation relationship between adjacent rounds in the encryption algorithm. It proposes a method that, without changing the inversion operation, uses a linear feedback shift register (LFSR) to generate n-bit random numbers, which are then padded with zeros on the right and left respectively before being fed into n+1-bit right shift registers X and Y. These registers control whether the XOR operation of the two data selectors is performed, thereby randomly inverting and correcting the S-box output data. This affects the side-channel information of the encryption result, thus achieving resistance to side-channel attacks and improving the security of data encryption. Attached Figure Description

[0027] Figure 1 A flowchart illustrating the composite field masking scheme used in existing technologies;

[0028] Figure 2 This is a flowchart illustrating a method for implementing a composite domain S-box to resist side-channel attacks according to the present invention. Detailed Implementation

[0029] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0030] This invention proposes a data encryption method that provides protection against the hardware implementation of block cipher algorithms (AES, SM4, etc.). Starting from the construction of the composite domain S-box, this scheme studies the properties of transformation matrices (isomorphic and inverse isomorphic matrices). Utilizing the transformation relationship between adjacent rounds in the encryption algorithm, it proposes a method that, without altering the inversion operation, randomly inverts the output of the S-box during the encryption process, thereby affecting the side-channel information of the encryption result and thus achieving resistance to side-channel attacks. Specifically, it includes the following steps:

[0031] Input the data to be encrypted into the S box.

[0032] Isomorphic matrices are used to perform isomorphic mapping on the data to be encrypted.

[0033] The data generated by the isomorphism mapping is placed in the composite domain GF(2). 4 ) and GF(2 2 Perform the inverse operation on ).

[0034] The operation result is inversely mapped using the inverse of the isomorphic matrix. A first data selector is set after the XOR operation following the isomorphic mapping, and a second data selector is set after the XOR operation before the inverse isomorphic mapping. A linear feedback shift register (LFSR) is used to control the random inversion and correction of the S-box output data. Right shift registers X and Y are respectively set between the first and second data selectors and the LFSR. The control of the random inversion and correction of the S-box output through the LFSR specifically includes: generating an n-bit random number using the LFSR, padding the n-bit random number with 0 on the right and left, and then feeding it into the (n+1)-bit right shift registers X and Y. These registers control whether the XOR operation corresponding to each of the two data selectors is performed, thereby achieving the random inversion and correction of the S-box output data.

[0035] The result of the inverse isomorphic mapping is subjected to an affine transformation, and then encrypted data is output.

[0036] like Figure 2 As shown, the encryption method is constructed using a composite field S-box implementation structure, a linear feedback shift register, a right shift register, and a multiplexer. The composite field S-box implementation structure performs the S-box transformation function and mainly consists of an isomorphic matrix, a multiplexer, an XOR operation, a composite field inversion transformation, an inverse isomorphic matrix, an affine transformation, a right shift register, and a linear feedback shift register. The functions of each part are as follows:

[0037] Isomorphic matrix: Constructs an isomorphic mapping between two fields. Here, we mainly map the elements of a finite field isomorphically to a composite field.

[0038] XOR operation: The XOR operation with the constant λ can invert and correct encrypted data.

[0039] Multiplexer: The 1-bit bits obtained by left shifting X and Y control the corresponding selector to select one of the two inputs as the output. That is, the control signal determines whether to perform inversion or correction operation on the S-box result in the current encryption process.

[0040] Inverse transformation of a composite field: In the composite field GF(2 4 ) and GF(2 2 Perform the inverse operation on ).

[0041] Inverse isomorphism transformation: Maps the elements of a composite field back to a finite field isomorphically.

[0042] Affine Transformation: The inverse affine transformation consists of a multiplication matrix and a constant (8'h63). The structure of the inverse operation is multiplied by the constant matrix on the left, and then XORed with the constant (8'h63) to obtain the S-box output.

[0043] Linear Feedback Shift Register (LFSR): Generates an n-bit random number to determine the number of encryption rounds for random inversion, where n = number of encryption rounds - 1.

[0044] Right shift registers: The n-bit random number generated by the LFSR is padded with 0 on the left and right respectively and then sent to the (n+1)-bit right shift registers Y and X to control the random inversion and correction operations in the encryption round. Specifically, in the i-th round, X[i] and Y[i] are shifted out by the right shift registers and used to control the two-to-one operation of the two multiplexers respectively, thereby achieving the purpose of random inversion.

[0045] Figure 2 The linear feedback shift register (LFSR), right shift register, and multiplexer control the random inversion of the S-box output to enhance its resistance to DPA attacks. This module primarily consists of an LFSR module, an XOR operation module after isomorphic transformation, an XOR operation module before inverse isomorphic transformation, two 2-to-1 data selectors, and two right shift registers. The XOR operations after isomorphic transformation and before inverse isomorphic transformation work together to achieve random inversion and correction of the S-box output during encryption. The LFSR is used to generate random numbers to control the randomness of the S-box output inversion operation.

[0046] Taking the 10-round AES encryption algorithm as an example, an LFSR random number generator can be designed to generate a 9-bit random number. Then, by padding the number with 0 on the right and left, two 10-bit control signals, X and Y, are generated and stored in the shift register.

[0047] In the 10-round encryption process of AES, the XOR operation after isomorphic transformation and before inverse isomorphic transformation is controlled according to the value of the 10-bit number pair of X and Y, so as to realize the random inversion and correction operation of the S-box output, thereby achieving the purpose of resisting side-channel attacks.

[0048] Taking the X control signal as an example, if X[i] is 1, it means that an XOR operation with λ needs to be performed after the inverse isomorphic transformation in this round; otherwise, it is not necessary (selected by a two-to-one data selector). The Y control signal is similar. It should be noted that the output inversion operation of the S-box (controlled by X[i]) and the correction operation (controlled by Y[i]) are not completed in the same round, but in two adjacent rounds, that is, the inversion is performed in the previous round and the correction is performed in the next round. This synchronization between the two rounds is achieved by the misalignment pairing of X and Y. That is, when constructing X and Y, the control signal X[i] of the i-th round and the control signal Y[i+1] of the (i+1)-th round are always equal by padding the same number with 0 on the right and left, thus ensuring that the S-box inversion operation of the previous round can be corrected in the next round.

[0049] Based on the same inventive concept, this invention proposes a data encryption system, comprising:

[0050] The data input module is used to input the data to be encrypted into the S box.

[0051] The inverse module is used to perform isomorphic mapping on the data to be encrypted using isomorphic matrices, and to convert the data generated by the isomorphic mapping into the composite field GF(2). 4 ) and GF(2 2 Perform the inverse operation on ).

[0052] The inverse isomorphism module is used to perform inverse isomorphic mapping on the operation result using the inverse matrix of the isomorphic matrix. Specifically, a first data selector is set after the XOR operation following the isomorphic mapping, and a second data selector is set after the XOR operation before the inverse isomorphic mapping. A linear feedback shift register (LFSR) is also included to control the random inversion and correction of the S-box output data. Right shift registers X and Y are respectively set between the first and second data selectors and the LFSR. The control of the random inversion and correction of the S-box output through the LFSR specifically includes: generating an n-bit random number using the LFSR, padding the n-bit random number with 0 on the right and left, and then feeding it into the (n+1)-bit right shift registers X and Y. These registers control whether the XOR operation corresponding to each of the two data selectors is performed, thereby achieving the random inversion and correction of the S-box output data.

[0053] The data output module is used to output encrypted data after performing an affine transformation on the result of the inverse isomorphic mapping.

[0054] Based on the same inventive concept, the present invention also proposes a data encryption computer device, comprising: a storage device, a processor, and a computer program stored in the storage device, wherein the processor executes the computer program to implement the steps of a data encryption method.

[0055] Based on the same inventive concept, the present invention also proposes a readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, are used to perform steps of a data encryption method.

[0056] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A data encryption method, characterized in that, include: Input the data to be encrypted into the S box; Using an isomorphic matrix, isomorphic mapping is performed on the data to be encrypted, and the data generated by the isomorphic mapping is placed in the composite field GF(2). 4 ) and GF(2 2 Perform the inverse operation on ); The operation result is inversely mapped using the inverse of the isomorphic matrix. A first data selector is set after the XOR operation following the isomorphic mapping, and a second data selector is set after the XOR operation before the inverse isomorphic mapping. A linear feedback shift register (LFSR) is used to control the random inversion and correction of the S-box output data. Right shift registers X and Y are respectively set between the first and second data selectors and the LFSR. The control of the random inversion and correction of the S-box output through the LFSR specifically includes: generating an n-bit random number using the LFSR, padding the n-bit random number with 0 on the right and left, and then feeding it into the (n+1)-bit right shift registers X and Y. These registers control whether the XOR operation corresponding to each of the two data selectors is performed, thereby achieving the random inversion and correction of the S-box output data. The result of the inverse isomorphic mapping is subjected to an affine transformation, and then encrypted data is output.

2. The data encryption method according to claim 1, characterized in that, The method described above utilizes isomorphic matrices to perform isomorphic mapping on the data to be encrypted, transforming elements in a finite field from a standard representation to a composite field.

3. The data encryption method according to claim 1, characterized in that, The method involves using the inverse of the isomorphic matrix to perform an inverse isomorphic mapping on the operation result, converting the operation result from its representation in the composite field to its standard representation in the finite field.

4. The method for implementing a composite domain S-box anti-side-channel attack according to claim 1, characterized in that, The output inversion and correction operations of the S-box are completed in two adjacent rounds.

5. The data encryption method according to claim 1, characterized in that, The synchronization between the inversion operation and the correction operation is achieved by the misalignment pairing of the n+1 bit right shift registers X and Y. Specifically, in the i-th encryption round, the same number generated by the linear feedback shift register LFSR is padded with 0 on the right and 0 on the left to ensure that the control signal X[i] of the i-th round and the control signal Y[i+1] of the i+1-th round are always equal.

6. The data encryption method according to claim 1, characterized in that, The affine transformation operation includes a multiplication matrix and a constant 8'h63.

7. A data encryption method according to claim 6, characterized in that, The result of the inverse isomorphic mapping is subjected to an affine transformation to obtain the encrypted data output by the S-box; specifically, the result of the inverse isomorphic mapping is multiplied by a constant matrix on the left and then XORed with the constant 8'h63 to obtain the output result of the S-box.

8. A data encryption system, characterized in that, include: The data input module is used to input the data to be encrypted into the S-box; The inverse module is used to perform isomorphic mapping on the data to be encrypted using isomorphic matrices, and to convert the data generated by the isomorphic mapping into the composite field GF(2). 4 ) and GF(2 2 Perform the inverse operation on ); The inverse isomorphism module is used to perform inverse isomorphic mapping on the operation result using the inverse matrix of the isomorphic matrix. A first data selector is set after the XOR operation following the isomorphic mapping, and a second data selector is set after the XOR operation before the inverse isomorphic mapping. A linear feedback shift register (LFSR) is also set to control the random inversion and correction of the S-box output data. Right shift registers X and Y are respectively set between the first and second data selectors and the LFSR. Specifically, controlling the random inversion and correction of the S-box output through the LFSR involves generating an n-bit random number, padding it with 0 on the right and left, and then feeding it into the (n+1)-bit right shift registers X and Y. These registers control whether the XOR operation corresponding to each of the two data selectors is performed, thereby achieving the random inversion and correction of the S-box output data. The data output module is used to output encrypted data after performing an affine transformation on the result of the inverse isomorphic mapping.

9. A data encryption computer device, characterized in that, include: A memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the data encryption method according to any one of claims 1-7.

10. A readable storage medium, characterized in that, The readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, are used to perform the steps of the data encryption method according to any one of claims 1-7.

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