Partially assembled spmv and spmm parallel processing method, system, medium and processor

Abstract

The application provides a partially assembled SpMV and SpMM parallel processing method, system, medium and processor, and is applied to the technical field of computers. In the application, a plurality of grid units are subjected to data blocking to obtain blocked units for a CPU finite element analysis task, each blocked unit is provided with a corresponding restriction operator, a base calculation operator and a weight operator. Through multi-thread parallel calculation, the input matrix of each thread is determined, and the blocked units are subjected to operator fusion and nonlinear transformation in the respective intervals. In the thread, the operators of the blocked units are further accumulated to obtain a processing result. Finally, the processing results of all threads are globally reduced through thread synchronization, and the overall result is output. Through the blocking and multi-thread independent processing, the operator fusion and the intermediate result accumulation of the application significantly reduce the number of global read-write and synchronization operations, reduce the read-write and synchronization overhead, optimize the storage and calculation complexity, and improve the parallel computing efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and more particularly to partially assembled SpMV and SpMM parallel processing methods, systems, media, and processors. Background Technology

[0002] The finite element method (FEM), based on the Galerkin approximation, transforms the weak form of partial differential equations (PDEs) into a system of algebraic equations by choosing a basis function space of finite dimensions. The solution accuracy can be improved by reducing the mesh scale and increasing the order of the basis functions. The discontinuous finite element method relaxes the continuity requirements between elements and reduces element degree-of-freedom coupling, making it widely applicable to various PDE problems.

[0003] However, existing finite element method libraries MFEM and libCEED primarily support sparse matrix-vector multiplication (SpMV), with limited support for sparse matrix-matrix multiplication (SpMM). libCEED stores operators in function form, using both matrix and array representations. The computation process is implemented in multiple steps, relying on atomic operations to avoid write conflicts, resulting in significant memory access overhead. MFEM stores operators in sparse matrix form and utilizes SpMV operators to avoid parallel write conflicts, but this increases storage and computational overhead.

[0004] Therefore, current technical solutions suffer from problems such as numerous read / write operations, high synchronization overhead, or high storage computational complexity. There is an urgent need for a partially assembled SpMV and SpMM parallel processing method that balances memory access efficiency and performance. Summary of the Invention

[0005] In view of the above problems, the present invention provides a partially assembled SpMV and SpMM parallel processing method, system, medium, and processor that overcomes or at least partially solves the above problems. The technical solution is as follows:

[0006] A partially assembled parallel processing method for SpMV and SpMM includes:

[0007] In the finite element analysis task of the CPU, multiple mesh elements are divided into data blocks to obtain block elements. Each block element corresponds to a specific element constraint operator, basis calculation operator, and weight operator.

[0008] A multi-threaded parallel computing approach is adopted. The input matrix corresponding to each thread is determined. For any block unit within the interval corresponding to each thread: the input matrix is ​​fused using the unit restriction operator and the basis computation operator corresponding to the block unit to obtain the first processing result of the block unit. The weight operator corresponding to the block unit and the first processing result are used to perform a nonlinear transformation to obtain the second processing result of the block unit.

[0009] For any of the aforementioned threads: using the unit restriction operator and the base computation operator corresponding to each of the block units within the thread, the second processing result of each of the block units within the thread is accumulated to obtain the third processing result of the thread;

[0010] By synchronizing threads, the third processing result of each thread is globally reduced, and the fourth processing result is output.

[0011] Optionally, the unit constraint operator is stored in function form, the basis calculation operator is stored in matrix form, and the weight operator is stored in array form.

[0012] Optionally, the accumulation operation uses bit-field encoding to record the state of the matrix unit update. When the corresponding bit is 0, it indicates that it has not been initialized, and when the corresponding bit is 1, it indicates that it has been initialized.

[0013] Optionally, the step of dividing multiple grid cells into data blocks to obtain block units includes:

[0014] According to preset network segmentation parameters, multiple grid cells are divided into multiple segmentation cells, wherein the preset network segmentation parameters are related to the parameters of the CPU.

[0015] Optionally, the process of determining the interval corresponding to the thread includes:

[0016] Based on the minimum storage unit of the CPU cache, the memory access overhead of each block unit is obtained according to the unit restriction operator corresponding to each block unit.

[0017] Based on the memory access overhead of each of the aforementioned block units, the total memory access overhead is calculated.

[0018] Based on the total number of threads, the total number of grid cells, and the total memory access overhead, each block cell is assigned to the corresponding thread, and the index array corresponding to each thread is calculated;

[0019] Based on the index array corresponding to each thread, the interval corresponding to each thread is determined.

[0020] Optionally, the minimum storage unit of the CPU cache is used to obtain the memory access overhead of each block unit according to the unit restriction operator corresponding to each block unit, including:

[0021] Construct basis vectors;

[0022] The unit constraint operator corresponding to each block unit is simulated to act on the basis vector, and the number of cross-cache line accesses corresponding to each unit constraint operator is counted.

[0023] The memory access overhead of each block unit is calculated based on the number of cross-cache line accesses corresponding to each unit restriction operator.

[0024] A computing system includes: a data partitioning module, a multi-threaded parallel computing module, and a result aggregation module.

[0025] The data segmentation module is used to segment multiple mesh elements into blocks in the finite element analysis task of the CPU to obtain segmented units. Each segmented unit has a corresponding element constraint operator, basis calculation operator and weight operator.

[0026] The multi-threaded parallel computing module is used to determine the input matrix corresponding to each thread using a multi-threaded parallel computing method. For any block unit within the interval corresponding to each thread: the input matrix is ​​fused using the unit restriction operator and the basis computation operator corresponding to the block unit to obtain a first processing result of the block unit; a nonlinear transformation is performed using the weight operator corresponding to the block unit and the first processing result to obtain a second processing result of the block unit; for any thread: the second processing result of each block unit within the thread is accumulated using the unit restriction operator and the basis computation operator corresponding to each block unit within the thread to obtain a third processing result of the thread.

[0027] The result aggregation module is used to globally reduce the third processing result of each thread through thread synchronization and output the fourth processing result.

[0028] Optionally, the computing system may further include a storage module.

[0029] The storage module is used to store the unit restriction operator, basis calculation operator and weight operator corresponding to each block unit, and restricts the unit restriction operator to be stored in function form, the basis calculation operator to be stored in matrix form, and the weight operator to be stored in array form.

[0030] A computer-readable storage medium having a program stored thereon that, when executed by a central processing unit, implements the partially assembled SpMV and SpMM parallel processing method.

[0031] A central processing unit (CPU) for running a program, wherein the program executes the partially assembled SpMV and SpMM parallel processing method during runtime.

[0032] Using the above technical solution, the partially assembled SpMV and SpMM parallel processing method, system, medium, and processor provided by this invention, in the finite element analysis task of the CPU, divides multiple mesh elements into data blocks to obtain block elements. Each block element corresponds to a specific element constraint operator, basis calculation operator, and weight operator. Employing a multi-threaded parallel computing approach, the input matrix corresponding to each thread is determined. For any block element within the interval corresponding to each thread: the element constraint operator and basis calculation operator corresponding to the block element are used to perform operator fusion calculation on the input matrix to obtain the first processing result of the block element. A nonlinear transformation is then performed using the weight operator corresponding to the block element and the first processing result to obtain the second processing result of the block element. For any thread: the element constraint operator and basis calculation operator corresponding to each block element within the thread are used to accumulate the second processing results of each block element within the thread to obtain the third processing result of the thread. Through thread synchronization, the third processing result of each thread is globally reduced to output the fourth processing result. This invention achieves operator fusion and accumulation of intermediate results by dividing multiple grid cell data into blocks and distributing them to multiple threads for independent processing. This reduces the number of global read / write and synchronization operations, thereby effectively reducing the number of read / write operations and synchronization overhead. At the same time, the localized computation process also optimizes storage and computational complexity and improves overall parallel efficiency.

[0033] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0034] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0035] Figure 1 A flowchart illustrating one embodiment of the partially assembled SpMV and SpMM parallel processing method provided by an embodiment of the present invention is shown.

[0036] Figure 2 This is a flowchart illustrating one implementation of the process for determining the thread-corresponding interval provided in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of a computing system provided in an embodiment of the present invention is shown. Detailed Implementation

[0038] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0039] The Finite Element Method (FEM) is a classic numerical method for solving Partial Differential Equations (PDEs) based on the Galerkin approximation method. This method constructs a finite-dimensional basis function space by selecting a set of basis functions to approximate the solution of the PDE. Specifically, the FEM selects a series of trial functions in a finite-dimensional trial function space and, based on the weak form of the PDE, transforms the continuous PDE problem into a system of algebraic equations. The mesh scale is usually represented by h, and the polynomial order of the basis functions is represented by p. The FEM can expand the basis function space by decreasing the mesh scale h (refining the mesh) and increasing the order p of the basis functions (raising the order), thereby improving the solution accuracy. The Discontinuous Galerkin Method (DG) relaxes the continuity requirement of the interface functions across elements, thus weakening the coupling relationship between the degrees of freedom of each element. This makes the Discontinuous Galerkin Method widely used in various PDE solution fields. Taking the Poisson equation as an example, the computational domain is designed as... ( (where dimensionality is a factor)

[0040]

[0041] here and Assuming It is a closed set. Let it be an open set. Multiply the test function on the left side of equation (1) After integration, we obtain the weak form:

[0042]

[0043] set up yes A discrete grid has N elements, and the set of elements is... ,but .exist Related finite element space Choose a set of basis functions ,right Expand , ,get:

[0044] (2)

[0045] Right now ,in , , , , Thus, solving the Poisson equation is transformed into solving a system of sparse linear equations.

[0046] The computation of sparse matrices suffers from problems such as irregular memory access and low computational density. The coefficient matrix of the finite element method... Computational efficiency is improved by using matrix-free techniques. Let the order of the finite element be... The order of the numerical integral is Let the number of non-zero basis functions in each unit be . (Generally speaking,) Considering ,set up k represents the matrix The size. Therefore, due to... , It is a local basis function, when , exist When it is not zero, Non-zero. Because The number of nonzero basis functions is , The number of non-zero elements is ,set up Composed of non-zero elements The element stiffness matrix is ,set up .set up express My heart is The column index in, therefore Related to grid indexes, then ,set up Make . express It only needs to be calculated based on the grid cell index. That's it; no explicit storage is required. (Hereinafter referred to as...) Matrix-free storage for individual cells. Sparse matrix-vector multiplication (SpMV). This is thus transformed into general matrix-vector multiplication (GEMV). In the finite element method, this is used... replace This helps improve the spatial locality and computational efficiency of memory access, effectively accelerating SpMV.

[0047] While improving computational efficiency, it did not reduce the space complexity of storing the coefficient matrix. and The space complexity is As the order increases With the increase in size, the storage overhead of high-order finite element methods is relatively large. Let the actual element... The isoparametric unit is (For example, the isoparametric element of a hexahedral mesh element is) ), vector arrive vector The Jacobi transformation matrix is In equation (2), , , .

[0048] set up The number of integration points is The integration points are The integral weight is Therefore, let's set , ,but ,set up , Then note that if the finite element shape functions and numerical integration methods are the same for different actual elements, then Same. Therefore, by ,get:

[0049]

[0050] The partial assembly method saves... Replace sparse matrices. It only relates to the grid and the numerical integration method. Number of integration points. , The space complexity is Calculation of SpMV In other words, SpMV calculations can be transformed into batch tensor shrinking. Partial assembly in the finite element method replaces matrix storage with storage grids and integration weights, reducing memory consumption and communication overhead.

[0051] In finite element numerical computation, sparse matrix-vector multiplication (SpMV) and sparse matrix-matrix multiplication (SpMM) are core computational operations. While some existing high-performance finite element mathematical libraries, such as MFEM and libCEED, primarily support SpMV operations, their support for SpMM is insufficient, limiting their parallel computational performance for certain multi-right-end vector problems.

[0052] The libCEED computation framework employs the following storage and computation scheme: operator G is stored in function form, basis computation operator B is stored in matrix form, and weight operator D is stored in array form. During computation, the expression is: Its multi-threaded scheme breaks down the overall computation into multiple steps: multi-threaded computation of y=Gx, multi-threaded computation of y=By, multi-threaded computation of y=f(D,y), and multi-threaded computation of... Multi-threaded computing .in Atomic operations are used to resolve multi-threaded write conflicts, but this results in significant memory access and synchronization overhead.

[0053] In MFEM's storage scheme, operator G is stored in sparse matrix form, while the storage forms of B and D are similar to those in libCEED. The computation expression is... In its multi-threaded solution, z=Gx is first calculated using the SpMV operator, and then... Finally, the SpMV operator is used to calculate... z. This scheme avoids the parallel write conflict problem by using the SpMV operator of sparse matrices, but increases storage and computational overhead.

[0054] In summary, the libCEED multithreaded solution involves up to 10 read / write operations on the vector dimension m, and atomic operations incur additional overhead. The MFEM solution reduces the number of read / write operations to 6, but sacrifices storage efficiency and increases computational complexity.

[0055] Based on this, the present invention designs a partially assembled SpMV and SpMM parallel processing scheme that balances memory access efficiency, parallel performance, and storage overhead. By using a segmented summation method, the overall computation task is divided into multiple subtasks, with each thread possessing a private matrix. The mesh is then divided and assigned to different threads. Within each thread, calculations are performed on its assigned mesh portion. Then, the private results of all threads are aggregated to obtain the final result. During this process, by analyzing and controlling the amount of computation and memory access, load balancing among threads is ensured, thereby improving computational efficiency and resource utilization.

[0056] like Figure 1 The diagram shows a flowchart of one embodiment of the partially assembled SpMV and SpMM parallel processing method provided by this invention. The method may include:

[0057] S100. In the finite element analysis task of the CPU, multiple mesh elements are divided into data blocks to obtain block elements. Each block element has a corresponding element constraint operator, basis calculation operator and weight operator.

[0058] To facilitate accurate understanding and clear description of the calculation process and implementation details in the technical solution, the following symbol descriptions are provided in this embodiment of the invention: The coefficient matrix formed by the finite element method. : The matrix. : The matrix, . [i,:]: matrix The i-th row. [:,j]: matrix The j-th column. [i,j]: matrix The element in the i-th row and j-th column. G: Element constraint operator, which transforms the global degrees of freedom and the element degrees of freedom. B: Element constraint operator for the e-th element. B: Basis computation operator, which transforms the element degrees of freedom and integration points. The basis computation operator for the e-th unit: In this invention, it is assumed that the basis of each unit is the same and the basis computation operator is the same. Weight operators are stored in partial aggregation forms. : The weight operator for the e-th unit. f: A user-defined function used in weight-related calculations. The total number of cells in the grid. : The total number of threads in the program. start: An index array, where the j-th thread is responsible for calculating the grid cells in the interval [start[j], start[j+1]-1]. : Mesh partitioning parameters, Each grid cell forms a block, used to improve memory access efficiency. flag(y): an array indicating y; the i-th bit of flag is used to represent the matrix. Whether the i-th row is initialized or not, the i-th bit is 0. [i,:] is not initialized; a value of 1 indicates that... [i,:] has been initialized.

[0059] Optionally, the unit constraint operator is stored in function form, the basis calculation operator is stored in matrix form, and the weight operator is stored in array form.

[0060] The unit constraint operators provided in this embodiment of the invention are stored in function form, that is, the values ​​of the constraint operators are dynamically calculated or obtained by defining corresponding functions, instead of storing all their data in memory in advance, thus saving storage space and providing greater flexibility. The basis calculation operators provided in this embodiment of the invention are stored in matrix form, meaning that the basis calculation operators shared by all units are stored completely in matrix form, facilitating efficient matrix operations and access. The weight operators provided in this embodiment of the invention are stored in array form, that is, the weight data corresponding to each unit is stored sequentially in an array to achieve fast indexing and processing. Overall, different storage methods optimize computational efficiency and memory usage.

[0061] The embodiments of the present invention can be applied to operators G, B, and Batch processing: In the libCEED framework, operators G and B support operations on vectors, but do not directly support batch operations on matrices. Considering that each unit of the operator acts on a matrix, the matrix can be viewed as a set of its column vectors. Specifically, for operators... The input matrix x is denoted as: =[ x[:,1], x[:,2],..., x[:,n]], similarly, the operator The effect on matrix x is: =[ x[:,1], x[:,2],..., x[:,n]]. Therefore, the number of columns n of the matrix can be regarded as a batch parameter, and operator operations can be performed on each column vector of the matrix sequentially, thereby utilizing the existing libCEED vector operators to realize the function of matrix operations. Since a single unit corresponds to Since the data size of x is relatively small, all n column vector operations can be completed within the cache, ensuring computational efficiency. For example, for the interpolation process y=Bx of a hexahedral mesh element, the application of the basis operator B satisfies the tensor computation formula: Where J is the interpolation operator. For the SpMM case, the tensor calculation formula corresponding to y=Bx is: By increasing the batch processing dimension n, the density and efficiency of tensor computation are improved.

[0062] The embodiments of the present invention can be applied to the transpose operator. Batch processing and optimization: for the transpose operator This is also implemented using batch processing. However, to reduce the initialization overhead of matrix y during each calculation, this invention designs a complex strategy based on the indicator array flag(y). Specifically, for the operation: ,when When the i-th bit is 0, execute: = and will The i-th bit is set to 1; when the i-th bit in flag(y) is 1, execute: =y+ This design effectively avoids the overhead of repeatedly initializing the matrix y, thus improving overall computational efficiency.

[0063] Based on the above design, the overall calculation process can be expressed as follows:

[0064]

[0065] Optionally, embodiments of the present invention can be performed according to preset network segmentation parameters. This divides multiple grid cells into multiple block cells, where the preset network block parameters are related to the CPU parameters.

[0066] Among them, the preset network block parameters This indicates the number of grid cells contained in each block. Choosing an appropriate... The following two conditions must be met: 1. Cache adaptability: It is necessary to ensure that all relevant data within the block, such as radix operators, are cached. Weighting operators And all accessed elements of the input vector x can be loaded into the processor's cache, reducing access to main memory and improving data access efficiency. 2. Maximizing computational performance: Block size It should be large enough to fully utilize the basis computation operators. While offering significant computational performance advantages, excessively small blocks may lead to underutilization of computing resources, impacting the acceleration effect.

[0067] Due to the specific optimal block parameters The value varies depending on the processor's cache size, number of computing units, memory bandwidth, and other hardware characteristics. It is closely dependent on the CPU hardware characteristics, so this parameter is usually adjusted and set by the user according to the CPU architecture and actual application scenario to achieve the best computing performance and resource utilization efficiency.

[0068] It is important to note that the finite element analysis task in this embodiment of the invention employs a partial assembly or matrix-free storage method, which differs from the traditional sparse matrix storage format. This embodiment divides multiple mesh elements into blocks, resulting in several sub-blocks. Each sub-block does not store complete sparse matrix row and column index information; instead, each sub-block corresponds to a locally dense operator (such as element constraint operators, basis calculation operators, and weight operators). This avoids the indexing overhead and assembly process inherent in sparse matrix storage formats, significantly reducing memory usage and computational costs. This embodiment utilizes this partially assembled data structure, combined with multi-threaded parallel computation, to reduce thread conflicts and achieve efficient SpMV and SpMM operations, making it suitable for high-performance computing needs in large-scale finite element analysis.

[0069] S110. Using a multi-threaded parallel computing method, the input matrix corresponding to each thread is determined. For any block unit within the interval corresponding to each thread: the unit constraint operator and basis computation operator corresponding to the block unit are used to perform operator fusion computation on the input matrix to obtain the first processing result of the block unit. The weight operator corresponding to the block unit and the first processing result are used to perform nonlinear transformation to obtain the second processing result of the block unit.

[0070] Specifically, embodiments of the present invention can employ a batch processing method for input matrices or vectors x, utilizing... and The operator operates on each column or batch of data in x, calculating the first processing result z= For each block unit, the array Using the intermediate result z as input, the data is processed by the function f to obtain the second processed result f( ,z).

[0071] like Figure 2 The diagram illustrates a flowchart of one embodiment of the process for determining the thread-corresponding interval provided in this invention. The process for determining the thread-corresponding interval may include:

[0072] S200, based on the CPU's smallest cache storage unit, obtains the memory access overhead of each block unit according to the unit limit operator corresponding to each block unit.

[0073] Since CPU caches use cache lines as the basic unit of storage and management, accessing data across multiple cache lines will incur multiple memory accesses, impacting performance. Therefore, estimating whether data access in a block spans cache lines is crucial for assessing memory access overhead.

[0074] Specifically, in this embodiment of the invention, a basis vector can be constructed; the unit constraint operator corresponding to each block unit can be simulated to act on the basis vector, and the number of cross-cache line accesses corresponding to each unit constraint operator can be counted; based on the number of cross-cache line accesses corresponding to each unit constraint operator, the memory access overhead of each block unit can be calculated.

[0075] S210. Based on the memory access cost of each block unit, calculate the total memory access cost.

[0076] Specifically, in this embodiment of the invention, the memory access overhead of all block units is accumulated or summarized to obtain the total memory access overhead of the entire computing task. The total memory access overhead reflects the overall memory access overhead and serves as the basis for subsequent load balancing allocation.

[0077] S220. Based on the total number of threads, the total number of grid cells, and the total memory access overhead, allocate each block cell to the corresponding thread and calculate the index array corresponding to each thread.

[0078] Specifically, in this embodiment of the invention, the block units can be reasonably divided and allocated to each thread according to the total number of threads, the total number of grid units, and the total memory access overhead, based on the memory access overhead weight. This allows for a reasonable division of computational tasks in a multi-threaded environment, ensuring that the workload allocated to each thread is roughly balanced in terms of memory access overhead, thus preventing certain threads from becoming bottlenecks. Then, the index range corresponding to each thread is calculated, i.e., the index array [start[j], start[j+1]-1], which clearly identifies the block unit range that the thread is responsible for processing.

[0079] S230. Based on the index array corresponding to each thread, determine the corresponding interval for each thread.

[0080] Specifically, in this embodiment of the invention, the grid cell block range responsible for each thread is clearly defined by the index array, ensuring that the computing tasks between threads are clearly divided, which facilitates scheduling and execution, so as to achieve memory access load balancing and maximize computing parallelism, thereby improving the overall computing performance.

[0081] When allocating index ranges for each thread, the memory access overhead involved in the SpMV process needs to be evaluated to ensure load balancing across threads. Since the memory access overhead for reading input vector x and writing output vector y is equivalent during computation, we only need to focus on estimating the memory access overhead for reading x.

[0082] Assuming that during memory access, the cache line containing the previously accessed data is retained in the cache. If the currently accessed element is outside this cache line, a new cache line needs to be loaded. This assumption simplifies the memory access model, making the calculation of the read overhead for a column of the input vector x more intuitive and feasible. The specific memory access overhead estimation process is as follows: Input: matrix G and cache line size s, Output: memory access overhead Q generated by the action of matrix G, Algorithm steps: Construct a basis vector v←{0,1,2,…,n-1}, where n is the vector length. Calculate z=Gv to obtain the access index sequence for elements of x. Initialize the counter count←0 and set the position of the previously accessed element to pre←z[0]. Traverse the index array z: for the current element index cur←z[i], determine whether its cache line number is the same as the previous one, i.e., compare cur / s with pre / s. If they are different, it means that a new cache line has been accessed, the counter count is incremented, and pre=cur is updated. Calculate the read overhead Q = count × s, which is the number of cross-cache line accesses multiplied by the cache line size.

[0083] After obtaining the read overhead Q of a single column vector x, considering that the weight matrix D is read only once, its memory access overhead is equal to its storage space size, denoted as s(D). Therefore, the total memory access overhead is 2Qn+s(D), where the memory access overhead for reading and writing x and the output vector y is equal, so it is multiplied by 2; n represents the number of columns or the batch size. Based on this total memory access overhead, combined with the number of threads and the grid cell division, the index interval [start[j], start[j+1]-1] corresponding to each thread is calculated, thereby achieving a balanced distribution of memory access load.

[0084] This invention, through simulation of the cache access characteristics of the unit-limiting operator, accurately estimates the memory access overhead of each block unit, and then combines the number of threads and the grid size to achieve a reasonable division of tasks. This design not only ensures load balancing but also makes full use of CPU cache characteristics, reduces memory access bottlenecks, and improves the overall efficiency of parallel computing.

[0085] S120. For any thread: using the unit constraint operator and base calculation operator corresponding to each block unit within the thread, perform an accumulation operation on the second processing result of each block unit within the thread to obtain the third processing result of the thread.

[0086] Specifically, in this embodiment of the invention, a multi-threaded parallel computing method of segmented summation can be adopted. The second processing result of each block unit in the corresponding interval [start[j], start[j+1]-1] of each thread is calculated and accumulated to obtain the third processing result of the thread.

[0087] Optionally, the accumulation operation uses bit-field encoding to record the update state of the matrix unit. When the corresponding bit is 0, it indicates that it has not been initialized, and when the corresponding bit is 1, it indicates that it has been initialized.

[0088] S130. Through thread synchronization, the third processing result of each thread is globally reduced, and the fourth processing result is output.

[0089] The input to the piecewise summation algorithm for SpMV / SpMM provided in this embodiment of the invention includes: , , , (e=1,2,…, ), number of threads and block parameters The output is a matrix y. For the j-th thread The matrix. The j-th thread is responsible for calculating the grid cells in the interval [start[j], start[j+1]-1]. This represents the total number of grid cells. The algorithm steps include: 1. Based on... , , 1. Calculate the index array start. 2. Perform the following operations in parallel (each thread runs independently): Obtain the thread number j. Divide the grid cell interval [start[j], start[j+1]-1] responsible for the thread into blocks, with the processing range determined by the block size. Convert to block index: i←start[j] / to(start[j+1]-1) / For each block i: for each unit e within the block (from...) To (i+1) -1) Perform matrix multiplication: z x, perform a nonlinear transformation on each element e within the same interval: z For each cell e within the same interval, calculate a partial result and accumulate it to the thread's local result. middle: x, flag( 3. Synchronize between threads to ensure all threads complete their respective tasks. 4. Merge the results of each thread and calculate the global result y: For each index i in y (evenly divided by thread) and each column h: y[i,h]←y[i,h]+ [i,h], where k is 0 to [i,h]. .

[0090] This invention provides a partially assembled parallel processing method for SpMV and SpMM. The method includes: in a CPU finite element analysis task, dividing multiple mesh elements into data blocks to obtain block elements, each block element corresponding to a specific element constraint operator, basis operation operator, and weight operator; employing a multi-threaded parallel computing approach, determining the input matrix corresponding to each thread; for any block element within the interval corresponding to each thread: using the element constraint operator and basis operation operator corresponding to the block element to perform operator fusion calculation on the input matrix to obtain a first processing result for the block element; using the weight operator corresponding to the block element and the first processing result to perform a nonlinear transformation to obtain a second processing result for the block element; for any thread: using the element constraint operator and basis operation operator corresponding to each block element within the thread to perform an accumulation operation on the second processing results of each block element within the thread to obtain a third processing result for the thread; through thread synchronization, globally reducing the third processing result of each thread to output a fourth processing result. This invention achieves operator fusion and accumulation of intermediate results by dividing multiple grid cell data into blocks and distributing them to multiple threads for independent processing. This reduces the number of global read / write and synchronization operations, thereby effectively reducing the number of read / write operations and synchronization overhead. At the same time, the localized computation process also optimizes storage and computational complexity and improves overall parallel efficiency.

[0091] Although the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous.

[0092] It should be understood that the various steps described in the method embodiments of the present invention may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of the present invention is not limited in this respect.

[0093] Corresponding to the above method embodiments, this invention also provides a computing system, the structure of which is as follows: Figure 3 As shown, it may include: a data segmentation module 10, a multi-threaded parallel computing module 20, and a result summarization module 30.

[0094] The data segmentation module 10 is used to segment multiple mesh elements into blocks in the finite element analysis task of the CPU to obtain segmented elements. Each segmented element has a corresponding element constraint operator, basis calculation operator and weight operator.

[0095] The multi-threaded parallel computing module 20 is used to determine the input matrix corresponding to each thread using a multi-threaded parallel computing approach. For any block unit within the interval corresponding to each thread: the input matrix is ​​fused using the unit restriction operator and basis operation operator corresponding to the block unit to obtain the first processing result of the block unit. The first processing result is then transformed using the weight operator corresponding to the block unit to obtain the second processing result of the block unit. For any thread: the second processing result of each block unit within the thread is accumulated using the unit restriction operator and basis operation operator corresponding to each block unit within the thread to obtain the third processing result of the thread.

[0096] The result summarization module 30 is used to globally reduce the third processing result of each thread through thread synchronization and output the fourth processing result.

[0097] Optionally, the computing system may also include a storage module.

[0098] The storage module is used to store the cell restriction operator, basis calculation operator and weight operator corresponding to each block unit. The cell restriction operator is stored in function form, the basis calculation operator is stored in matrix form, and the weight operator is stored in array form.

[0099] Optionally, the multi-threaded parallel computing module 20 can be specifically used to record the update state of matrix units using bit field encoding. When the corresponding bit is 0, it indicates that it has not been initialized, and when the corresponding bit is 1, it indicates that it has been initialized.

[0100] Optional, data segmentation module 10. Specifically, it can be used to divide multiple grid cells into multiple segmentation cells according to preset network segmentation parameters, wherein the preset network segmentation parameters are related to the CPU parameters.

[0101] Optionally, the computing system may also include a thread range allocation module.

[0102] The thread interval allocation module is used to determine the interval corresponding to a thread: based on the smallest storage unit of the CPU cache, the memory access overhead of each block unit is obtained according to the unit limit operator corresponding to each block unit; based on the memory access overhead of each block unit, the total memory access overhead is calculated; based on the total number of threads, the total number of grid units, and the total memory access overhead, each block unit is allocated to the corresponding thread, and the index array corresponding to each thread is calculated; based on the index array corresponding to each thread, the interval corresponding to each thread is determined.

[0103] Optionally, the thread interval allocation module can be specifically used to construct the basis vector; simulate the operation of the unit constraint operator corresponding to each block unit on the basis vector, and count the number of cross-cache line accesses corresponding to each unit constraint operator; and calculate the memory access overhead of each block unit based on the number of cross-cache line accesses corresponding to each unit constraint operator.

[0104] The computing system provided by this invention, in the finite element analysis task of the CPU, divides multiple mesh elements into data blocks to obtain block elements. Each block element corresponds to a specific element constraint operator, basis calculation operator, and weight operator. Employing a multi-threaded parallel computing approach, the system determines the input matrix for each thread. For any block element within the interval corresponding to each thread: the element constraint operator and basis calculation operator corresponding to the block element are used to perform operator fusion calculation on the input matrix to obtain the first processing result of the block element. Then, the weight operator corresponding to the block element and the first processing result are used to perform a nonlinear transformation to obtain the second processing result of the block element. For any thread: the element constraint operator and basis calculation operator corresponding to each block element within the thread are used to accumulate the second processing results of each block element within the thread to obtain the third processing result of the thread. Through thread synchronization, the third processing result of each thread is globally reduced to output the fourth processing result. This invention achieves operator fusion and accumulation of intermediate results by dividing multiple grid cell data into blocks and distributing them to multiple threads for independent processing. This reduces the number of global read / write and synchronization operations, thereby effectively reducing the number of read / write operations and synchronization overhead. At the same time, the localized computation process also optimizes storage and computational complexity and improves overall parallel efficiency.

[0105] Regarding the computing system in the above embodiments, the specific ways in which each module performs operations have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0106] The computing system includes a central processing unit (CPU) and a memory. The data partitioning module, multi-threaded parallel computing module, and result aggregation module are all stored as program units in the memory. The CPU executes these program units to achieve their respective functions. The CPU contains a kernel, which retrieves the corresponding program units from memory. One or more kernels can be configured. By adjusting kernel parameters, multiple grid cell data can be partitioned and distributed to multiple threads for independent processing. This enables operator fusion and accumulation of intermediate results, reducing the number of global read / write operations and synchronization overhead. Simultaneously, it optimizes the storage and computational complexity of the localized computation process, improving overall parallel efficiency.

[0107] This invention provides a computer-readable storage medium storing a program that, when executed by a central processing unit, implements the SpMV and SpMM parallel processing method of the partially assembled components.

[0108] This invention provides a central processing unit (CPU) for running a program, wherein the program executes the partially assembled SpMV and SpMM parallel processing method during runtime.

[0109] This invention provides an electronic device, which includes at least one central processing unit (CPU), at least one memory connected to the CPU, and a bus. The CPU and memory communicate with each other via the bus. The CPU is used to call program instructions from the memory to execute the partially assembled SpMV and SpMM parallel processing methods described above. The electronic device described herein can be a server, PC, PAD, mobile phone, etc.

[0110] The present invention also provides a computer program product that, when executed on an electronic device, is adapted to perform the steps of initializing a partially assembled SpMV and SpMM parallel processing method.

[0111] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, computing systems, central processing units, electronic devices, and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0112] In a typical configuration, an electronic device includes one or more processors (CPUs), memory, and a bus. The electronic device may also include input / output interfaces, network interfaces, etc.

[0113] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, like read-only memory (ROM) or flash RAM, and memory includes at least one memory chip. Memory is an example of computer-readable media.

[0114] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0115] In the description of this invention, it should be understood that if the terms "upper", "lower", "front", "rear", "left" and "right" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the position or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0116] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0117] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0118] The above are merely embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the present invention.

Claims

1. A method for parallel processing of partially assembled SpMV and SpMM processes, characterized in that, include: In the finite element analysis task of the CPU, multiple mesh elements are divided into data blocks to obtain block elements. Each block element corresponds to a specific element constraint operator, basis calculation operator, and weight operator. A multi-threaded parallel computing approach is adopted. The input matrix corresponding to each thread is determined. For any block unit within the interval corresponding to each thread: the input matrix is ​​fused using the unit restriction operator and the basis computation operator corresponding to the block unit to obtain the first processing result of the block unit. The weight operator corresponding to the block unit and the first processing result are used to perform a nonlinear transformation to obtain the second processing result of the block unit. For any of the aforementioned threads: using the unit restriction operator and the base computation operator corresponding to each of the block units within the thread, the second processing result of each of the block units within the thread is accumulated to obtain the third processing result of the thread; By synchronizing threads, the third processing result of each thread is globally reduced, and the fourth processing result is output.

2. The method according to claim 1, characterized in that, The unit constraint operator is stored in function form, the basis calculation operator is stored in matrix form, and the weight operator is stored in array form.

3. The method according to claim 1, characterized in that, The accumulation operation uses bit-field encoding to record the state of the matrix unit update. When the corresponding bit is 0, it indicates that it has not been initialized, and when the corresponding bit is 1, it indicates that it has been initialized.

4. The method according to claim 1, characterized in that, The step of dividing multiple grid cells into data blocks to obtain block units includes: According to preset network segmentation parameters, multiple grid cells are divided into multiple segmentation cells, wherein the preset network segmentation parameters are related to the parameters of the CPU.

5. The method according to claim 4, characterized in that, The process of determining the interval corresponding to the thread includes: Based on the minimum storage unit of the CPU cache, the memory access overhead of each block unit is obtained according to the unit restriction operator corresponding to each block unit. Based on the memory access overhead of each of the aforementioned block units, the total memory access overhead is calculated. Based on the total number of threads, the total number of grid cells, and the total memory access overhead, each block cell is assigned to the corresponding thread, and the index array corresponding to each thread is calculated; Based on the index array corresponding to each thread, the interval corresponding to each thread is determined.

6. The method according to claim 5, characterized in that, The minimum storage unit of the CPU-based cache is used to obtain the memory access overhead of each block unit according to the unit restriction operator corresponding to each block unit, including: Construct basis vectors; The unit constraint operator corresponding to each block unit is simulated to act on the basis vector, and the number of cross-cache line accesses corresponding to each unit constraint operator is counted. The memory access overhead of each block unit is calculated based on the number of cross-cache line accesses corresponding to each unit restriction operator.

7. A computing system, characterized in that, include: The module consists of a data partitioning module, a multi-threaded parallel computing module, and a result aggregation module. The data segmentation module is used to segment multiple mesh elements into blocks in the finite element analysis task of the CPU to obtain segmented units. Each segmented unit has a corresponding element constraint operator, basis calculation operator and weight operator. The multi-threaded parallel computing module is used to determine the input matrix corresponding to each thread using a multi-threaded parallel computing method. For any block unit within the interval corresponding to each thread: the input matrix is ​​fused using the unit restriction operator and the basis computation operator corresponding to the block unit to obtain a first processing result of the block unit; a nonlinear transformation is performed using the weight operator corresponding to the block unit and the first processing result to obtain a second processing result of the block unit; for any thread: the second processing result of each block unit within the thread is accumulated using the unit restriction operator and the basis computation operator corresponding to each block unit within the thread to obtain a third processing result of the thread. The result aggregation module is used to globally reduce the third processing result of each thread through thread synchronization and output the fourth processing result.

8. The computing system according to claim 7, characterized in that, Also includes: Storage module, The storage module is used to store the unit restriction operator, basis calculation operator and weight operator corresponding to each block unit, and restricts the unit restriction operator to be stored in function form, the basis calculation operator to be stored in matrix form, and the weight operator to be stored in array form.

9. A computer-readable storage medium having a program stored thereon, characterized in that, When the program is executed by the central processing unit, it implements the partially assembled SpMV and SpMM parallel processing method as described in any one of claims 1 to 6.

10. A central processing unit, characterized in that, The central processing unit is used to run a program, wherein the program executes the partially assembled SpMV and SpMM parallel processing method according to any one of claims 1 to 6.

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