A simulation method for processing uncertain states and a flip-flop
Patent Information
- Application Number
- CN202510492794.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-18
- Publication Date
- 2026-10-23
AI Technical Summary
[0007](3)第三类是该触发器本身导致的不确定状态，即：后仿真中，时序不满足的时候，该触发器会输出不确定态
[0056](1)提高芯片质量：只要发生时序不满足，仿真一定是失败的，一定可以在仿真阶段发现芯片的问题，保证设计的芯片时序和功能都是正确的。(2)及时发现问题，及时投片：只要发生时序不满足，只需要仿真一次，所有时序不满足的触发器都可以一次性的全部暴露出来，可以在前期及时发现问题，不会影响投片的进度，节省时间和人力成本。
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Figure CN122965383A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of simulation and verification technology of digital circuit chips, and specifically relates to a simulation method and trigger for handling uncertain states. Background Technology
[0002] In existing technologies, errors caused by uncertainties are frequently encountered during simulation verification. Furthermore, these uncertainties within the chip can spread throughout the chip, significantly increasing debugging difficulty. Therefore, it is necessary to eliminate uncertainties in the simulation verification environment to reduce debugging difficulty and improve debugging speed.
[0003] The operating environment of a real chip differs from the virtual environment used in simulation verification: a real chip has no uncertain states; in a real chip, the uncertain state value is a random 0 or 1. In a simulation verification environment, uncertain states, denoted by x, exist. These uncertain states propagate and spread, leading to an increasing number of uncertain states within the chip. Uncertain state x can cause simulation failures, making debugging extremely difficult.
[0004] There are three sources of uncertain states in the triggers of a chip:
[0005] (1) The first type is that when the chip is just started up, there are no flip-flops with asynchronous reset pins. They will remain in an uncertain state. After several clock cycles, the data is slowly transmitted to these flip-flops and the uncertain state disappears.
[0006] (2) The second type is the uncertain state passed from the previous level of the trigger.
[0007] (3) The third type is the uncertain state caused by the trigger itself, that is: in the post-simulation, when the timing is not satisfied, the trigger will output an uncertain state.
[0008] The commonly used method to remove uncertainties is to randomly assign a value of 0 or 1 when encountering an uncertain state during simulation.
[0009] Currently, commonly used methods for removing uncertainties are effective in solving (1) and (2) of the above classification, but they are not effective in solving (3), and sometimes even have negative effects, increasing the difficulty of debugging. For example, if the expected correct value of the flip-flop is 1, the timing may not be met, causing the flip-flop output to become an uncertain state x. After randomization, it may become 1, thus the simulation will succeed, and the hidden problems in the chip cannot be detected in time, resulting in the defective chip being released.
[0010] In other words, the shortcomings of existing technology are:
[0011] (1) Impact on chip quality: Because a random method is used, sometimes even after many simulations, the value that causes the simulation error cannot be found. This leads us to mistakenly believe that the simulation is successful, and we cannot find the chip problem during the simulation stage, resulting in defective chips being released and causing losses to customers. (2) Impact on wafer fabrication schedule: Because a random method is used, sometimes many simulations are required to find the value that causes the simulation error. If the problem is found in the later stages, just before wafer fabrication, a lot of work needs to be redone, which greatly delays the wafer fabrication schedule and increases the workload, wasting a lot of time and manpower. Summary of the Invention
[0012] To address the aforementioned issues, this application aims to resolve the uncertainties arising from timing discrepancies in post-simulation. Post-simulation runtime is significantly longer than pre-simulation, and it uses netlists, whose language is difficult for humans to understand, making debugging extremely challenging. Therefore, eliminating these uncertainties in post-simulation is crucial. Post-simulation refers not only to verifying the correctness of the function but also to back-annotating timing delay information and verifying the correctness of the timing itself. Timing discrepancies result in the trigger, which should output a definite value, producing an uncertain output that could be either 0 or 1 due to timing inconsistencies.
[0013] Specifically, the present invention provides a simulation method for handling uncertainties, comprising the following steps: S1, determining whether the simulation can succeed if the uncertainties are not handled;
[0014] If so, end the simulation;
[0015] If not, proceed to the next steps;
[0016] S2, determine whether the output of the trigger is in an uncertain state;
[0017] If not, then set the final output of the model to equal the output of the trigger;
[0018] If so, proceed to the next steps;
[0019] S3, determine whether the input data of the trigger is not in an uncertain state a moment before the rising edge of the clock arrives; if not, set the final output of the model to a random value;
[0020] If so, proceed to the next steps;
[0021] S4, determine whether the input data of the trigger is 0 a moment before the rising edge of the clock arrives;
[0022] If not, then set the final output of the model to 0;
[0023] If so, then set the final output of the model to 1.
[0024] The method described above is a method for removing trigger uncertainties in a simulation verification environment, and further includes the following steps:
[0025] S1: Set remove_x = 0 to perform the first simulation. If the simulation is successful, the process ends; if the simulation fails, proceed to step S2. Here, remove_x = 0 means that the uncertain state x is not processed.
[0026] S2: Set remove_x = 1, where remove_x = 1 indicates that the uncertain state x needs to be removed, and check whether the output signal q_tmp of the trigger is the uncertain state x:
[0027] If q_tmp is not x, then let the final output of the model be q = q_tmp, and end the process;
[0028] If q_tmp is x, then proceed to step S3;
[0029] S3: Determine if the input data terminal d_last is NOT x just before the rising edge of the clock:
[0030] If d_last is x, then let q = rand_val, where rand_val is a random value generated by the code rand_val = $random(); that is, the random value rand_val is either 0 or 1, and is dynamically assigned by the pseudo-random number generation function $random().
[0031] If d_last is not x, then proceed to step S4;
[0032] S4: The remove_x operation to remove uncertainties includes:
[0033] When the input data d_last is 0, the output of the trigger is forced to be 0;
[0034] When the input data d_last is 1, the output of the trigger is forced to be 1;
[0035] That is, determine the value of d_last:
[0036] If d_last = 1, then let q = 0;
[0037] If d_last = 0, then let q = 1.
[0038] The trigger includes a clock pin clk, a data pin d, and an output pin q, and the value of d_last is obtained through the following code:
[0039] always@(posedge clk)begin
[0040] d_last <= d;
[0041] end
[0042] Where d_last is the value of the input data of the flip-flop one moment before the clock edge arrives.
[0043] Step S3 further includes:
[0044] S3.1, detect the input status of clock signal clk and data signal d;
[0045] S3.2, when triggered by the rising edge of the clock, determine whether the input data d_last is in a deterministic state, i.e., a non-x state;
[0046] If the input data d_last is deterministic and equal to logic 0, then the removal_x operation in step S4 is executed to remove the uncertain state.
[0047] If the input data is still in an uncertain state, then continue randomization or the default output strategy.
[0048] S3.3, Check whether the temporary output q_tmp of the trigger is in an uncertain state;
[0049] If q_tmp is in an uncertain state, then select one from the preset candidate values, i.e., random values, 0, and 1, as the final output;
[0050] The priority order of the preset candidate values is: random value > 0 > 1.
[0051] The method is implemented using a modified trigger equivalence model, wherein:
[0052] When remove_x = 1, the modified model ensures that the output q is a deterministic or random value by logically covering the uncertain state x in steps S2 to S4.
[0053] The method is applicable to hardware description language (HDL) simulation environments, and removes the influence of uncertainties on simulation results through conditional branching and state coverage.
[0054] The present invention also relates to a trigger for a chip, wherein the internal model of the trigger is applicable to any of the methods described above, and the trigger is used in the simulation verification stage to perform verification and debugging more quickly and accurately.
[0055] Therefore, the advantage of this solution is:
[0056] (1) Improve chip quality: If timing discrepancies occur, simulation will definitely fail. Chip problems can be detected during the simulation stage, ensuring that the timing and function of the designed chip are correct. (2) Timely problem detection and timely wafer fabrication: If timing discrepancies occur, only one simulation is needed to expose all timing-disagreeing triggers at once. Problems can be detected in the early stages without affecting the wafer fabrication schedule, saving time and manpower costs. Attached Figure Description
[0057] The accompanying drawings, which are provided to further illustrate the invention and form part of this application, are not intended to limit the scope of the invention.
[0058] Figure 1 This is a flowchart illustrating the method used in this application.
[0059] Figure 2 This is a schematic diagram of the original trigger before the modification in this application.
[0060] Figure 3 This is a schematic diagram of the modified model equivalent to a trigger in this application.
[0061] Figure 4 This is the complete Verilog code for the modified model equivalent to triggers in this application. Detailed Implementation
[0062] To better understand the technical content and advantages of the present invention, the present invention will now be described in further detail with reference to the accompanying drawings.
[0063] like Figure 2 As shown, the flip-flop is the smallest unit in the chip. A flip-flop usually has three ports: input clock clk, input data d, and output data q. The function of the flip-flop is to transmit the value of input d to output q only when the clock edge arrives.
[0064] The original Verilog code for the trigger before modification is as follows:
[0065] tsmc_dff(q,d,clk);
[0066] like Figure 4 The image shows the Verilog code for the modified model that is functionally equivalent to the original trigger:
[0067] The first line of code defines the name of the trigger model: tsmc_dff. The name of the model is the same as the original trigger before the modification.
[0068] Lines 2 and 3 of the code are the input ports d and clk of the trigger model, and the output port q. The names of the input and output ports are the same as the original trigger before the modification.
[0069] Lines 4 through 8 are declarations of intermediate process variables;
[0070] Lines 11-13 assign a value to `remove_x`. In this example, the simulation is run using Synopsys' VCS software. To assign `remove_x` a value of 0, the command is: `vcs + remove_x = 0 - full64 - Rl log`. To assign `remove_x` a value of 1, the command is: `vcs + remove_x = 1`.
[0071] -full64-Rl log;
[0072] Lines 15 to 17 of the code obtain the input data values of the flip-flop before the rising edge of the clock arrives;
[0073] Lines 19-21 of the code obtain a random value;
[0074] Lines 23 to 39 contain the entire process of removing uncertainties through conditional judgments;
[0075] Line 41 is the original trigger model before modification: smc_dff_org(q_tmp,d,clk);
[0076] Change the original trigger name from tsmc_dff to tsmc_dff_org, change the output from q to q_tmp, and keep the inputs d and clk unchanged.
[0077] This application relates to a method for handling uncertainties, the idea of which includes:
[0078] 1. Set remove_x = 0 and run the simulation once. If the simulation is successful, then end. If the simulation fails, then proceed to step 2.
[0079] remove_x = 0: means that the uncertain state x is not processed;
[0080] remove_x = 1: This means that the uncertain state x needs to be removed;
[0081] 2. The processing method for the internal flip-flop of the chip is as follows: Set remove_x = 1, and determine whether the value of the flip-flop's output signal q_tmp is indeterminate x:
[0082] If q_tmp is not an uncertain state x, then let the final output of the model be q = q_tmp, and the process ends.
[0083] If q_tmp is an uncertain state x, then proceed to step 3;
[0084] 3. Determine if the input data terminal d_last before the rising edge of the clock is not in an uncertain state x: If the input data terminal d_last is in an uncertain state, then let q = rand_val, where rand_val is a random value. The code to obtain the random value is as follows: rand_val = $random();
[0085] If the input data terminal d_last is not in an uncertain state, then proceed to step 4;
[0086] The original flip-flop has three pins: clock pin clk; data pin d; and output pin q, as shown below. Figure 2 The diagram shown is a schematic of the original flip-flop before modification in this application, where the input data is d, the input clock is clk, and the output is q. The modified flip-flop equivalent model in this invention is shown below. Figure 3 As shown;
[0087] d_last is the value of the input data of the flip-flop one moment before the clock edge arrives. The code to obtain the value of d_last is as follows:
[0088] always@(posedge clk)
[0089] d_last <= d;
[0090] 4. Determine if the value of the input data terminal d_last is 1 before the rising edge of the clock arrives: If the value of d_last is 1, then set q = 0;
[0091] If the value of d_last is 0, then let q = 1.
[0092] In summary, such as Figure 1 As shown, this invention is a simulation method for handling uncertainties, comprising the following steps:
[0093] S1, determine whether the simulation can succeed if no treatment is done on the uncertainty;
[0094] If so, end the simulation;
[0095] If not, proceed to the next steps;
[0096] S2, determine whether the output of the trigger is in an uncertain state;
[0097] If not, then set the final output of the model to equal the output of the trigger;
[0098] If so, proceed to the next steps;
[0099] S3, determine whether the input data of the trigger is not in an uncertain state a moment before the rising edge of the clock arrives; if not, set the final output of the model to a random value;
[0100] If so, proceed to the next steps;
[0101] S4, determine whether the input data of the trigger is 0 a moment before the rising edge of the clock arrives;
[0102] If not, then set the final output of the model to 0;
[0103] If so, then set the final output of the model to 1.
[0104] The random value is generated by a random number generator.
[0105] The final output of the model is used for subsequent simulation calculations.
[0106] The uncertainty refers to the situation where the output state is unclear during the simulation process due to certain conditions not being met.
[0107] The rising edge of the clock refers to the moment when the clock signal changes from a low level to a high level.
[0108] Furthermore, the present invention is able to achieve:
[0109] S1: Set remove_x = 0 to perform the first simulation. If the simulation is successful, the process ends; if the simulation fails, proceed to step S2. Here, remove_x = 0 means that the uncertain state x is not processed.
[0110] S2: Set remove_x = 1, where remove_x = 1 indicates that the uncertain state x needs to be removed, and check whether the output signal q_tmp of the trigger is the uncertain state x:
[0111] If q_tmp is not x, then let the final output of the model be q = q_tmp, and end the process;
[0112] If q_tmp is x, then proceed to step S3;
[0113] S3: Determine if the input data terminal d_last is NOT x just before the rising edge of the clock:
[0114] If d_last is x, then let q = rand_val, where rand_val is a random value generated by the code rand_val = $random(); that is, the random value rand_val is either 0 or 1, and is dynamically assigned by the pseudo-random number generation function $random().
[0115] If d_last is not x, then proceed to step S4;
[0116] Step S3 further includes:
[0117] S3.1, detect the input status of clock signal clk and data signal d;
[0118] S3.2, when triggered by the rising edge of the clock, determine whether the input data d_last is in a deterministic state, i.e., a non-x state;
[0119] If the input data d_last is deterministic and equal to logic 0, then the removal_x operation in step S4 is executed to remove the uncertain state.
[0120] If the input data is still in an uncertain state, then continue randomization or the default output strategy.
[0121] S3.3, Check whether the temporary output q_tmp of the trigger is in an uncertain state;
[0122] If q_tmp is in an uncertain state, then select one from the preset candidate values, i.e., random values, 0, and 1, as the final output;
[0123] The priority order of the preset candidate values is: random value > 0 > 1;
[0124] S4: The remove_x operation to remove uncertainties includes:
[0125] When the input data d_last is 0, the output of the trigger is forced to be 0;
[0126] When the input data d_last is 1, the output of the trigger is forced to be 1;
[0127] That is, determine the value of d_last:
[0128] If d_last = 1, then let q = 0;
[0129] If d_last = 0, then let q = 1.
[0130] The method is implemented using a modified trigger equivalence model, wherein:
[0131] When remove_x = 1, the modified model ensures that the output q is a deterministic or random value by logically covering the uncertain state x in steps S2 to S4.
[0132] The method is applicable to hardware description language (HDL) simulation environments, and removes the influence of uncertainties on simulation results through conditional branching and state coverage.
[0133] The present invention also relates to a trigger for a chip, wherein the internal model of the trigger is applicable to any of the methods described above. In other processes of the chip's front-end and back-end design, the original trigger model provided by TSMC is still used. In the simulation and verification stage, using this trigger model can enable faster and more accurate verification and debugging.
[0134] This technical solution can be applied to all series of chips from Ingenic Semiconductor and similar chips.
[0135] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A simulation method for handling uncertainties, characterized in that, The method Includes the following steps: S1, determine whether the simulation can succeed if no treatment is done on the uncertainty; If so, end the simulation; If not, proceed to the next steps; S2, determine whether the output of the trigger is in an uncertain state; If not, then set the final output of the model to equal the output of the trigger; If so, proceed to the next steps; S3, determine whether the input data of the trigger is not in an uncertain state a moment before the rising edge of the clock arrives; if not, set the final output of the model to a random value; If so, proceed to the next steps; S4, determine whether the input data of the trigger is 0 a moment before the rising edge of the clock arrives; If not, then set the final output of the model to 0; If so, then set the final output of the model to 1.
2. The method according to claim 1, characterized in that, The method described above is a method for removing trigger uncertainties in a simulation verification environment, and further includes the following steps: S1: Set remove_x = 0 to perform the first simulation. If the simulation is successful, the process ends; if the simulation fails, proceed to step S2. Here, remove_x = 0 means that the uncertain state x is not processed. S2: Set remove_x = 1, where remove_x = 1 indicates that the uncertain state x needs to be removed, and check whether the output signal q_tmp of the trigger is the uncertain state x: If q_tmp is not x, then let the final output of the model be q = q_tmp, and end the process; If q_tmp is x, then proceed to step S3; S3: Determine if the input data terminal d_last is NOT x just before the rising edge of the clock: If d_last is x, then let q = rand_val, where rand_val is a random value generated by the code rand_val = $random(); that is, the random value rand_val is either 0 or 1, and is dynamically assigned by the pseudo-random number generation function $random(). If d_last is not x, then proceed to step S4; S4: The remove_x operation to remove uncertainties includes: When the input data d_last is 0, the output of the trigger is forced to be 0; When the input data d_last is 1, the output of the trigger is forced to be 1; That is, determine the value of d_last: If d_last = 1, then let q = 0; If d_last = 0, then let q = 1.
3. The method according to claim 1, characterized in that, The trigger includes a clock pin clk, a data pin d, and an output pin q, and the value of d_last is obtained through the following code: always@(posedge clk)begin d_last <= d; end Where d_last is the value of the input data of the flip-flop one moment before the clock edge arrives.
4. The method according to claim 1, characterized in that, Step S3 further includes: S3.1, detect the input status of clock signal clk and data signal d; S3.2, when triggered by the rising edge of the clock, determine whether the input data d_last is in a deterministic state, i.e., a non-x state; if the input data d_last is in a deterministic state and equal to logic 0, then perform the removal of the uncertain state, i.e., the remove_x operation in step S4. If the input data is still in an uncertain state, then continue randomization or the default output strategy. S3.3, check if the temporary output q_tmp of the trigger is indeterminate; if q_tmp is indeterminate, select one from the preset candidate values, i.e., random value, 0, 1, as the final output; The priority order of the preset candidate values is: random value > 0 > 1.
5. The method according to claim 2, characterized in that, The method is implemented using a modified trigger equivalence model, wherein: When remove_x = 1, the modified model ensures that the output q is a deterministic or random value by logically covering the uncertain state x in steps S2 to S4.
6. The method according to claim 1, characterized in that, The method is applicable to hardware description language (HDL) simulation environments, and removes the influence of uncertainties on simulation results through conditional branching and state coverage.
7. A trigger for a chip, characterized in that, The internal model of the trigger is adapted to the method described in any one of claims 1-6. The trigger is used in the simulation verification stage to perform verification and debugging more quickly and accurately.