Watchdog-based verification method, verification platform, electronic device and storage medium

Abstract

The application aims to provide a watchdog-based verification method, a verification platform, an electronic device and a storage medium. The watchdog-based verification method is applied to a verification platform, and the verification platform comprises a watchdog model. The watchdog-based simulation verification method comprises the following steps: running a verification case; monitoring a plurality of preset events of the verification case in a running process based on the watchdog model; wherein the watchdog model comprises a plurality of dog feeding trigger sources, different dog feeding trigger sources correspond to different preset events; the watchdog model is used for feeding dogs through the respective corresponding dog feeding trigger sources based on the normal running of each preset event; and the watchdog model triggers timeout in the case that all the preset events are abnormal, causing each dog feeding trigger source not to feed dogs; and in response to the timeout of the watchdog model, a preset abnormal handling mechanism is executed. The method can meet the monitoring requirements of multiple cause abnormalities of a chip during simulation verification.

Description

Technical Field

[0001] This application relates to the field of chip simulation, and specifically, provides a watchdog-based verification method, verification platform, electronic device, and storage medium. Background Technology

[0002] During chip simulation and verification, abnormal situations may occur, such as bus jamming or no output from the computing module. To handle these situations, a timeout mechanism is typically used to trigger the exception handling process, releasing occupied resources after a certain duration has elapsed since the exception occurred. However, conventional timeout mechanisms usually have a long timeout period for triggering the exception handling logic. If simulation and verification continue until the exception handling logic is triggered, it leads to a waste of time and computing resources.

[0003] Therefore, in some simulation verification processes, a watchdog timer is used to monitor for anomalies. The watchdog timer executes in parallel with the test cases. If the simulation verification proceeds normally, the watchdog timer will be fed normally. However, if an anomaly occurs, the watchdog timer will fail to be fed due to a timeout, thus triggering the exception handling process. Compared to conventional timeout mechanisms, watchdog timeouts can be set to shorter durations, triggering the exception handling process earlier.

[0004] However, current watchdogs can only monitor a single parameter. As chip functions become more diverse, some functions may have multiple inputs and outputs, leading to various causes of anomalies. Therefore, watchdogs triggered by a single parameter cannot meet the monitoring needs for multiple causes of chip anomalies during simulation verification. Summary of the Invention

[0005] In view of this, this application aims to provide a watchdog-based verification method, verification platform, electronic device and storage medium to meet the monitoring needs of multi-cause anomalies of chips during simulation verification.

[0006] In a first aspect, embodiments of this application provide a watchdog-based verification method, comprising: applying to a verification platform, the verification platform including a watchdog model, the watchdog-based simulation verification method comprising: running verification test cases; monitoring multiple preset events of the verification test cases during operation based on the watchdog model; wherein, the watchdog model includes multiple watchdog feeding trigger sources, different watchdog feeding trigger sources corresponding to different preset events; the watchdog model is used to feed the watchdog through its corresponding watchdog feeding trigger source based on the normal operation of each preset event; and, the watchdog model triggers a timeout when all preset events are abnormal, causing each watchdog feeding trigger source to fail to feed the watchdog; in response to the watchdog model timeout, executing a preset exception handling mechanism.

[0007] This application provides a watchdog model that supports multiple feed trigger sources. Multiple preset events during the simulation verification process can be configured as feed trigger sources. Feeding is triggered based on whether each preset event runs correctly. This method can monitor multiple preset events simultaneously, meeting the monitoring requirements for multi-cause anomalies in the chip. Compared to watchdogs that can only monitor a single event, this method reduces the need for repeatedly modifying the object monitored by the watchdog and recompiling code, thereby helping to reduce time and resource waste and improve verification efficiency and resource utilization.

[0008] In one embodiment, before monitoring multiple preset events of the verification test case during its operation based on the watchdog model, the method further includes: determining multiple preset events to be monitored in the verification test case; and configuring each preset event as a different watchdog trigger source for the watchdog model.

[0009] In this embodiment, the watchdog model supports multiple dog-feeding trigger sources to monitor different preset events, which can meet the monitoring needs of multi-cause anomalies in large-scale chip design simulation verification.

[0010] In one embodiment, the watchdog model includes a feeding interface, which includes multiple data bits; configuring each of the preset events as different feeding trigger sources for the watchdog model includes: for any preset event, selecting any target data bit, and configuring the normal operation of the preset event to trigger the modification of the value of the target data bit from a first value to a second value.

[0011] In this embodiment, the watchdog interface uses multiple data bits to monitor different preset events. The correctness of an event is determined by the value of a data bit (either a first or second value). This method effectively simplifies monitoring complexity and helps reduce the watchdog model's resource consumption. Furthermore, each data bit corresponds to a preset event. Based on this, the state of a preset event can be determined according to the correspondence between data bits and preset events, and the value of the data bits. This facilitates user monitoring of the watchdog's operational status and debugging / verification of the environment.

[0012] In one embodiment, monitoring multiple preset events of the verification test case during operation based on the watchdog model includes: traversing each data bit of the watchdog interface through the watchdog interface; and triggering the watchdog feed when any of the data bits is the second value.

[0013] In this embodiment, the watchdog feeding interface configures the watchdog trigger source through multiple data bits. Then, when determining whether the watchdog is being fed normally, it only needs to iterate through the values ​​of each data bit to check for changes. This method effectively improves the efficiency of statistically analyzing whether each preset event is running normally, eliminating the need to judge each preset event individually; instead, it only requires iterating through the multiple data bits of the watchdog feeding interface. This method effectively simplifies the structural complexity of the watchdog model, while also helping to improve the real-time performance and accuracy of monitoring, and reducing the watchdog model's consumption of computer resources.

[0014] In one embodiment, the watchdog model further includes a timer, and the watchdog model is configured with a preset timeout duration; before traversing each data bit of the feeding interface through the feeding interface, the method further includes: timing based on the timer; after traversing each data bit of the feeding interface, the method further includes: determining that the watchdog model triggers a timeout when the timer's timing duration reaches the preset timeout duration and each data bit is the first value; and after the feeding interface triggers feeding, the method further includes: resetting the timer's timing duration to zero.

[0015] In this embodiment, each data bit is a first value, indicating that a pre-set event has not run normally and triggers a watchdog timer. Based on this, if the timer's duration reaches a pre-set timeout duration, it indicates that the simulation verification of the test case may encounter an anomaly, such as an infinite loop or lag. In this case, it can be determined that the watchdog model has timed out, thus triggering the exception handling mechanism and reducing the resource consumption of the verification test case. Simultaneously, if a watchdog timer is triggered, the timer can be reset to avoid accidental triggering of exception handling.

[0016] In one embodiment, before determining that the watchdog model triggers a timeout when the timer's duration reaches the preset timeout duration and all data bits are the first value, the method further includes: the watchdog model triggering an alert in response to the timer's duration reaching a preset warning interval; and the method further includes: triggering a reset when the number of warnings reaches a reset threshold, the reset being used to trigger the execution of the preset exception handling mechanism.

[0017] In this embodiment of the application, an early warning function can also be configured as needed to meet the needs of prompting some time relationships, timing requirements, etc. during the verification process, and to assist in analyzing the causes of anomalies and problems.

[0018] In one embodiment, before running the verification test case, the method further includes: instantiating the pre-stored watchdog model in response to the startup of the verification environment of the verification platform; initializing the instantiated watchdog model; the initialization configuration is used to configure at least the enable state of the watchdog model and the preset timeout duration; the initialization configuration includes: configuring each of the preset events as different watchdog feeding trigger sources for the watchdog model.

[0019] In this embodiment of the application, preset events and watchdog trigger sources can be configured during the instantiation and initialization phase after the verification environment is started, so that the watchdog model can directly monitor after the verification starts, effectively simplifying the configuration process, reducing time waste, and improving verification efficiency.

[0020] In one embodiment, instantiating the pre-stored watchdog model includes: instantiating multiple watchdog models based on the code of the pre-stored watchdog model; initializing the instantiated watchdog models includes: configuring the same or different preset timeout durations for different watchdog models.

[0021] Currently, watchdog timers only allow configuration of one timeout duration for each verification test case. Once set, any subsequent modifications require code recompilation. However, in large-scale chip verification, timeout durations are typically set based on test case type. For example, different functional modules have different latency requirements, and consequently, their respective latency settings differ. Furthermore, multiple timeout durations may exist within the same verification test case. A single watchdog cannot meet the verification needs. In this embodiment, multiple watchdog models can be instantiated simultaneously. Different watchdog models can be configured with different timeout settings to meet the different timeout duration requirements for different functions within the same verification test case. This reduces the time spent repeatedly modifying timeout parameters and recompiling code, reduces resource consumption, and improves efficiency.

[0022] In one embodiment, the preset event includes at least one of the following: the control path of the design under test is in a working state; the verification test case is used to perform simulation verification on the design under test; the data path of the design under test transmits a handshake signal; the computing module of the design under test inputs or outputs data; and the preset custom event in the verification platform is completed.

[0023] If the control path is not in operation, the data path is not transmitting a handshake signal, or the arithmetic module is not inputting or outputting data, it indicates that the verification test case is malfunctioning. Therefore, in this embodiment, preset events can be set based on the input and output of the control path, data path, and arithmetic module, and used as watchdog trigger sources to monitor whether the verification test case is running correctly. Simultaneously, this watchdog also supports setting other custom events to meet testing requirements.

[0024] In one embodiment, the watchdog model is constructed based on a UVM object.

[0025] UVM is a general verification methodology that provides a standardized verification platform architecture and component library for chip verification. Currently, UVM is the mainstream verification methodology, offering advantages such as randomness, reusability, and integration. `uvm_object` (UVM object) is a mainstream and fundamental component within UVM. Based on the current development trend of mainstream verification methodologies, verification environments built using UVM are typically employed. Therefore, in the embodiments of this application, the watchdog model built based on the UVM object enables its use in more verification projects and environments, facilitating reuse, reducing the time required for subsequent project development and verification, and improving efficiency.

[0026] In one embodiment, the watchdog model further includes a parameter passing interface, and the method further includes: sending a parameter modification instruction to the watchdog model through the parameter passing interface; modifying the configuration parameters of the watchdog model based on the parameter modification instruction; the configuration parameters include at least one of the following: a preset timeout duration of the timer in the watchdog model; and the enabled state of the watchdog model.

[0027] In this embodiment, the watchdog model also includes a parameter passing interface, which can receive parameter modification instructions to dynamically adjust the watchdog's configuration parameters during its use. For example, the watchdog model's enable state and the timer's preset timeout duration can be adjusted. This method does not require the watchdog model to stop working and be recompiled, effectively reducing the complexity of modifying the watchdog model's configuration parameters and reducing time and resource consumption.

[0028] In one embodiment, the parameter passing interface is a command-line parameter passing interface, and sending parameter modification instructions to the watchdog model through the parameter passing interface includes: sending parameter modification instructions to the watchdog model through the command line.

[0029] In this embodiment, the parameter passing interface is a command-line parameter passing interface. This interface supports command-line parsing, thus enabling it to receive parameter modification commands in command-line form. Compared to other types of commands, the command line is compatible with more verification platforms. Therefore, the watchdog model's function of receiving parameter modification commands via the parameter passing interface can be implemented in more projects, making the watchdog model more reusable.

[0030] Secondly, embodiments of this application provide a verification platform, comprising: a verification module for running verification test cases; a watchdog module for running a watchdog model and monitoring various preset events during the execution of the verification test cases based on the watchdog model; wherein the watchdog model includes multiple watchdog feeding trigger sources, and different watchdog feeding trigger sources correspond to different preset events; the watchdog model feeds the watchdog through its respective corresponding watchdog feeding trigger source based on the normal operation of each preset event; and the watchdog model triggers a timeout if all preset events are abnormal, causing each watchdog feeding trigger source to fail to feed the watchdog; and an exception handling module for executing a preset exception handling mechanism in response to the watchdog model timeout.

[0031] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor is configured as a verification platform and performs a watchdog-based simulation verification method as described in any of the first aspects.

[0032] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the watchdog-based simulation verification method as described in any of the first aspects. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 A flowchart illustrating a delayed output method provided in an embodiment of this application; Figure 2 A schematic diagram of a watchdog model provided in this application embodiment; Figure 3A schematic diagram of the operation of a multi-watchdog model provided in this application embodiment; Figure 4 A schematic diagram of a verification platform provided in an embodiment of this application; Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of this application.

[0035] Icons: Verification Platform 400; Verification Module 410; Watchdog Module 420; Exception Handling Module 430; Electronic Device 500; Processor 510; Memory 530. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0037] First, this application provides a watchdog-based simulation verification method that can be applied to a verification platform.

[0038] When simulating and verifying integrated circuits, a verification platform is used to simulate and verify the code and software functions of the integrated circuit. The verification platform builds a verification environment and abstracts the hardware functions of the integrated circuit into software code, so as to simulate the behavior of the hardware through software code, thereby realizing the simulation and verification of the integrated circuit.

[0039] In the embodiments of this application, the verification platform includes a watchdog model, which is an independently running process within the verification platform. The watchdog model can run in parallel with the process of the verification test cases, and it can also monitor the operation of the verification test cases to determine whether any abnormalities occur.

[0040] In the embodiments of this application, the verification platform is used to simulate and verify the code of integrated circuit functions, including but not limited to circuit functions and interactions between modules. The verification platform is a software platform, and correspondingly, the watchdog model provided in the embodiments of this application is also a program module.

[0041] In the embodiments of this application, the watchdog model described above is constructed based on a UVM (Universal Verification Methodology) object.

[0042] UVM is a mainstream verification methodology with advantages such as randomness, reusability, and integration. The uvm_object (UVM object) is a mainstream and fundamental component of UVM. Based on the current development trend of mainstream verification methodologies, UVM is typically used to build verification environments with different buses. Therefore, in the embodiments of this application, the watchdog model built based on the UVM object enables its use in more verification projects, reducing the time required for subsequent project development and verification, and improving efficiency.

[0043] In embodiments of this application, the watchdog model includes: a dog feeding interface, a dog feeder, and a watchdog.

[0044] The watchdog feeder interface, which can be represented as wdt_feeder_if, is used to define the basic signals and operation interface of the watchdog, as well as to define the enable signal, the feeder function, and the feeder trigger source.

[0045] In the embodiments of this application, the watchdog model may include multiple watchdog feeding trigger sources, and different watchdog feeding trigger sources correspond to different preset events in the execution of verification test cases.

[0046] In the embodiments of this application, the watchdog model is used to feed the dog through the corresponding feeding trigger source based on the normal operation of each preset event; and the watchdog model triggers a timeout when all preset events are abnormal, causing each feeding trigger source to fail to feed the dog.

[0047] Based on this, if all functions of the verification test case are running normally, all preset events will run normally and occur, and the watchdog will be continuously fed. If the function of the verification test case is abnormal, the function of the verification test case will not be able to run, which will prevent all preset events from being fed to the watchdog, and the watchdog will time out because it has not been fed.

[0048] The dog feeder, which can be represented as wdt_feeder, is set within or connected to the dog feeding interface. It is used to perform specific operations such as raising and feeding the dog, and to manage the state of the watchdog, including instantiating the watchdog internally.

[0049] A watchdog timer, also known as a watchdog body or watchdog data structure, is used to implement the basic functions of a watchdog timer. For example, it can store the watchdog's configuration information and operating status, including enable status, timeout duration, timers, and watchdog feeding history.

[0050] In embodiments of this application, the watchdog model may further include a parameter passing interface, which can receive configuration parameters for each part of the watchdog model, including the dog feeding interface, the dog feeder, and the main body of the watchdog.

[0051] Next, we will elaborate on the relevant content of the watchdog model based on the method provided in this application, without going into too much detail here.

[0052] Please see Figure 1 , Figure 1 The flowchart illustrates a watchdog-based simulation verification method according to an embodiment of this application. The watchdog-based simulation verification method includes: S110, Run the verification test case.

[0053] Verification test cases are used to test DUT (Device Under Test, or the object to be verified by the chip). The DUT includes, but is not limited to, various functions of the chip. The method provided in this application can be used when verifying different DUTs using a verification platform. No restrictions are placed on the specific types and contents of verification test cases and DUTs.

[0054] In embodiments of this application, before running the verification test case, the method may further include: instantiating a pre-stored watchdog model in response to the startup of the verification environment of the verification platform; and initializing the instantiated watchdog model.

[0055] In this embodiment of the application, the verification platform can call the code file of the pre-stored watchdog model and instantiate the watchdog model through the code file, thereby simulating the watchdog model to run the watchdog model to monitor the verification test cases.

[0056] The instantiated watchdog model has not yet been configured, such as the monitored objects and timer durations. Therefore, in the embodiments of this application, the watchdog model can also be initialized and configured for verification test cases to meet the monitoring requirements of verification test cases.

[0057] For example, the initialization configuration is used to at least configure the watchdog model's enable state and preset timeout duration. The enable state is used to enable or disable the watchdog model; during initialization, the watchdog model's enable state can be changed from disabled to enabled. The preset timeout duration can be configured according to the timeout mechanism's duration requirements; the specific duration is not limited here. The watchdog model also has default parameters; if not configured during the initialization phase, the watchdog model will monitor based on these default parameters. Furthermore, other configuration parameters for the watchdog interface, watchdog feeder, and other watchdog parameters can be adaptively configured based on verification requirements; these are not limited here.

[0058] In embodiments of this application, the initialization configuration further includes: configuring each preset event as a different watchdog trigger source for the watchdog model. That is, in embodiments of this application, before monitoring multiple preset events of the verification test case during operation based on the watchdog model in S120, multiple preset events to be monitored in the verification test case can be determined, and each preset event can be configured as a different watchdog trigger source for the watchdog model.

[0059] During the simulation and verification of the chip, there are many reasons why the same functional module may produce anomalies, which means that there are also many parameters that need to be monitored.

[0060] For example, a functional module may have multiple data input or output channels. During verification or use, one or more of these channels may not work for an extended period while other channels are functioning normally. In this case, the functional module is still within the normal range. If the watchdog only monitors one of these channels, there is a high probability that it will falsely trigger a timeout, affecting the accuracy of the monitoring.

[0061] For example, a functional module may need to interact with multiple other modules. During the verification or use process, some interactions may not be triggered for a long time. If the watchdog monitors the signals of such interactions, timeouts are more likely to occur.

[0062] Therefore, in the embodiments of this application, it is necessary to enable the watchdog model to monitor multiple preset events in order to more comprehensively determine whether the verification test cases are running correctly. These multiple preset events can be different signals or events from the same module or different modules. The multiple preset events configured in the same watchdog model can be different events that independently determine anomalies, or they can be different events that cause anomalies in the same module and have a certain correlation.

[0063] Please see Figure 2 , Figure 2 This is a schematic diagram of a watchdog model provided in an embodiment of this application. In this example, the design under test (DUT) runs in the verification environment of the verification platform and operates through an externally provided clock source. At the same time, the verification platform can also run a watchdog model and configure various preset events of the DUT as different watchdog trigger sources, such as watchdog trigger sources 1, 2...N, so as to realize the watchdog model's monitoring of different preset events of the DUT during the simulation verification process.

[0064] In the embodiments of this application, the type of preset event can be selected according to the verification requirements, and the engineer can define the dog-feeding trigger source during the initialization phase. In the embodiments of this application, the preset event includes, but is not limited to, at least one of the following: the control path of the design under test is in a working state, for example, monitoring signals such as busy or not_idle indicating whether the control path is in a working state; the data path of the design under test transmits a handshake signal, for example, monitoring whether the valid or read channel transmits a handshake signal; the computing module of the design under test inputs or outputs data, for example, monitoring whether the valid channel inputs or outputs data; and the preset custom event in the verification platform is completed.

[0065] If the control path is not in operation, the data path does not transmit a handshake signal, or the arithmetic module does not input or output data, it indicates that the execution of the verification test case is abnormal, thus preventing the watchdog timer from being triggered. The watchdog model will time out if it is not fed for an extended period. In the embodiments of this application, the watchdog timer can be triggered by starting or ending the aforementioned preset events; no restrictions are imposed.

[0066] The preset events in this application can be customized by engineers according to their needs, including but not limited to triggering a dog feed when some simulation tasks or monitoring tasks are completed within the verification platform, such as triggering a dog feed when the "done" or "finish" fields are detected.

[0067] In the embodiments of this application, each preset event is configured as a different watchdog trigger source in the watchdog model. This can be achieved by connecting the watchdog to the watchdog trigger source inside the watchdog interface, so that the signal of the preset event can be output to the watchdog inside the watchdog interface for triggering.

[0068] In the embodiments of this application, the watchdog interface includes multiple data bits, each corresponding to a watchdog trigger source. Each data bit is connected to a different preset event, and the value of the data bit is modified based on whether the preset event is executed correctly. For example, configuring each preset event as a different watchdog trigger source for the watchdog model includes: for any preset event, selecting any target data bit, and configuring the normal operation of the preset event to trigger a modification of the target data bit's value from a first value to a second value. The normal operation of the preset event can be an output signal indicating correct execution, such as a handshake signal, a busy signal, or a not_idle signal.

[0069] During the verification process, although the preset event may run normally and trigger the dog feeding, some functions have certain requirements on timing and time relationships. Therefore, in the embodiments of this application, the watchdog model can also be configured with an early warning function, that is, a dog bark, so as to provide a time-based prompt through the early warning function to assist in the analysis of the cause of anomalies and problems. Accordingly, the early warning interval corresponding to the dog bark can also be configured during the initial configuration.

[0070] In the embodiments of this application, the aforementioned preset timeout duration can also be configured as the number of warnings, that is, when the number of warnings reaches a threshold, it is determined that the dog feeding timeout has expired, or it is called triggering a dog bite.

[0071] If the dog is fed for too long or bitten, the watchdog model will trigger a reset operation. In the embodiments of this application, the reset operation can be configured to trigger a preset exception handling mechanism, including but not limited to timeout exit, error reporting, resource release, output log recording, etc. The corresponding method can be configured according to the actual verification requirements, and no restrictions are imposed here.

[0072] Currently, watchdog timers only allow configuration of one timeout duration for each verification test case. Once set, any subsequent modifications require code recompilation. However, in large-scale chip verification, timeout durations are typically configured based on test case type. For example, different functional modules have different latency requirements, and consequently, their respective latency settings also differ. Furthermore, multiple timeout durations may exist within the same verification test case. A single watchdog timer cannot meet the verification needs.

[0073] Therefore, in the embodiments of this application, when instantiating the pre-stored watchdog model, multiple watchdog models can be instantiated based on the code of the pre-stored watchdog model. Accordingly, when initializing and configuring the instantiated watchdog models, the same or different preset timeout durations can be configured for different watchdog models.

[0074] Please see Figure 3 , Figure 3 This is a schematic diagram illustrating the operation of a multi-watchdog model provided in an embodiment of this application. Figure 3 As shown in the example, the verification platform runs two designs under test, A and B. A and B can be different functional modules of the same verification test case, or designs in different verification test cases, which is not restricted here.

[0075] In the verification environment, designs under test (DUTs) A and B are run separately, using clock sources A and B respectively. Watchdog timers A and B are used for monitoring DUTs A and B respectively. Watchdog model A can configure feed trigger sources A1 and A2 based on different events related to DUT A, while watchdog model B can configure feed trigger sources B1 and B2 based on different events related to DUT B. Watchdog models A and B can use different timeout durations.

[0076] Therefore, by using different watchdog models, different timeout durations can be set to meet the different timeout duration requirements in the same verification test case, reducing the time spent on repeatedly modifying timeout duration parameters and recompiling code, reducing resource consumption, and improving efficiency.

[0077] Other functions and principles related to watchdogs can be found in existing technologies and will not be elaborated here.

[0078] S120 monitors and verifies various preset events during the execution of test cases based on a watchdog model.

[0079] In the embodiments of this application, since each preset event is configured as a watchdog trigger source, each preset event will trigger the watchdog to feed through a signal when it runs correctly. Thus, the watchdog model can monitor multiple preset events of the verification test case during the running process.

[0080] In embodiments of this application, feeding the dog includes multiple data bits, each data bit being connected to a preset event. The normal operation of each data bit triggers a modification of its value based on the preset event, changing it from a first value to a second value, where the first value can be 0 and the second value can be 1, or vice versa.

[0081] Therefore, if the watchdog is fed normally, at least one of the multiple data bits will have the second value. Based on this, in the embodiments of this application, the various preset events of the watchdog model monitoring and verification test case during operation may include: traversing each data bit of the watchdog feeding interface through the watchdog feeding interface; and triggering the watchdog feeding interface when any data bit has the second value.

[0082] In this embodiment, by traversing each data bit, it is possible to quickly count whether multiple events have been triggered, which can effectively improve the statistical efficiency.

[0083] In the embodiments of this application, the watchdog also includes a timer. Accordingly, after the watchdog is fed by the watchdog interface, the time recorded by the timer is also cleared and a new round of timing begins.

[0084] In the embodiments of this application, the watchdog timer starts timing based on a preset clock after initial configuration or each reset. The time recorded by the timer triggers an alert or determines whether a timeout has occurred. The preset clock can be provided internally by the watchdog model or provided by the verification test case, and is not limited here.

[0085] In this embodiment, after traversing each data bit of the watchdog interface through the watchdog interface, if the timer duration reaches the preset timeout duration and each data bit is the first value, it can be determined that the watchdog model has triggered a timeout.

[0086] If none of the preset events have been triggered and the dog feeding has continued for a certain period of time, i.e., the preset timeout period has been extended, it indicates that the preset events have not been running correctly for a long time. For example, the verification test case may be due to an infinite loop or lag. In this case, if all data bits remain at the first value, it can be determined that there is an anomaly and the corresponding anomaly handling logic needs to be triggered.

[0087] In the embodiments of this application, before determining that the watchdog model triggers a timeout when the timer's duration reaches a preset timeout duration and all data bits are the first value, the method may further include: the watchdog model triggering a warning in response to the timer's duration reaching a preset warning interval.

[0088] In some embodiments of this application, a reset may be triggered when the number of warnings reaches a reset threshold, thereby triggering the execution of a preset exception handling mechanism. This reset may include, but is not limited to, using functions such as uvm_fatal or $finish() to trigger a simulator termination signal, thus exiting the simulation.

[0089] The early warning function can output early warning signals, logs, prompts, etc., and can be configured according to actual verification needs. No restrictions are imposed here.

[0090] S130, in response to a watchdog model timeout, executes a pre-defined exception handling mechanism.

[0091] In this embodiment, the exception handling mechanism includes, but is not limited to, timeout exit, error reporting, and release of occupied resources. The specific method can be configured according to specific needs and is not limited here.

[0092] In some embodiments of this application, the verification platform can record and output runtime information about verification test cases and watchdog models to assist engineers in anomaly analysis.

[0093] In the embodiments of this application, the watchdog model may further include a parameter passing interface. Accordingly, the simulation verification method based on the watchdog may further include: sending a parameter modification command to the watchdog model through the parameter passing interface; and modifying the configuration parameters of the watchdog model based on the parameter modification command.

[0094] In the embodiments of this application, the parameter modification instructions received via the parameter passing interface can be received at any time after initialization configuration. That is, during the verification process, the parameters of the watchdog model can be adjusted dynamically and in real time according to the problems and requirements that arise during verification. This method eliminates the need to wait for the verification test cases to complete their full execution before making unified adjustments. Furthermore, adjusting the watchdog model parameters does not require recompiling the watchdog, effectively reducing the time required for parameter adjustment and verification, and improving verification efficiency.

[0095] In some embodiments of this application, the configuration parameters modified based on the parameter modification instruction include, but are not limited to, at least one of the following: the preset timeout duration of the timer in the watchdog model; and the enable state of the watchdog model.

[0096] In other embodiments of this application, the configuration parameters modified based on the parameter modification command may also include the relationship between a preset event and a dog-feeding trigger source. For example, establishing a relationship between a new preset event and a new dog-feeding trigger source, or replacing the current preset event corresponding to the current dog-feeding trigger source with a new preset event.

[0097] In some embodiments of this application, the configuration parameters modified based on the parameter modification command may also include the warning interval, the reset threshold for triggering a reset, etc.

[0098] In this embodiment, by configuring a parameter passing interface in the watchdog model, the watchdog model provides independent parameter configuration capabilities, allowing engineers to flexibly set parameters such as watchdog timeout and enable status as needed. This enables modification of watchdog model parameters without recompiling the code, effectively reducing the time required for verification.

[0099] In embodiments of this application, multiple watchdog models may be instantiated, and each watchdog model may include a parameter passing interface to modify configuration parameters based on parameter modification instructions. The parameter passing interfaces between different watchdog models can be represented by different strings for differentiation.

[0100] In the embodiments of this application, the parameter passing interface of the watchdog model is a command-line parameter passing interface. Accordingly, sending parameter modification instructions to the watchdog model through the parameter passing interface may include sending parameter modification instructions to the watchdog model through the command line.

[0101] UVM has functions for parsing command lines. In the embodiments of this application, the watchdog model is built based on uvm_object (UVM object). On this basis, the watchdog model integrates command line parameter parsing functions based on UVM, thereby realizing the transmission and parsing of parameter modification instructions based on command lines, and configuring the watchdog model based on the parsed content.

[0102] Compared to other types of instructions, command lines are more commonly used in verification platforms. Configuring a command-line parameter passing interface in the watchdog model allows it to adapt to more scenarios and projects. Furthermore, the watchdog model can be separated into a standalone module for use in different projects, meeting the needs of more projects.

[0103] Based on the same inventive concept, this application also provides a verification platform. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of a verification platform provided in an embodiment of this application. The verification platform 400 includes: a verification module 410, a watchdog module 420, and an exception handling module 430.

[0104] Verification module 410 is used to run verification test cases.

[0105] The watchdog module 420 is used to run a watchdog model and monitor various preset events during the execution of verification test cases based on the watchdog model. The watchdog model includes multiple watchdog-feeding trigger sources, each corresponding to a different preset event. The watchdog model feeds the watchdog through its corresponding watchdog-feeding trigger source based on the normal operation of each preset event. Furthermore, the watchdog model triggers a timeout if all preset events fail to occur, resulting in the watchdog-feeding trigger sources not feeding the watchdog. The exception handling module 430 is used to execute a preset exception handling mechanism in response to a watchdog model timeout.

[0106] In one embodiment, the watchdog module 420 is further configured to determine the various preset events to be monitored in the verification case before monitoring the various preset events in the operation of the verification case based on the watchdog model; and to configure each preset event as a different watchdog trigger source of the watchdog model.

[0107] In one embodiment, the watchdog model includes a feeding interface, which includes multiple data bits. The watchdog module 420 is further configured to select any target data bit for any preset event and configure the normal operation of the preset event to trigger the modification of the value of the target data bit from a first value to a second value.

[0108] In one embodiment, the watchdog model is further configured to: traverse each of the data bits of the watchdog feeding interface through the watchdog feeding interface; and trigger the watchdog feeding interface when any of the data bits is the second value.

[0109] In one embodiment, the watchdog model further includes a timer, and the watchdog model is configured with a preset timeout duration. The watchdog module 420 is further configured to start timing based on the timer before traversing each data bit of the feeding interface through the feeding interface. The watchdog module is also configured to determine that the watchdog model triggers a timeout after traversing each data bit of the feeding interface through the feeding interface, when the timer's duration reaches the preset timeout duration and each data bit is the first value. The watchdog module is further configured to reset the timer's duration to zero after the feeding interface triggers the feeding.

[0110] In one embodiment, the watchdog module 420 is further configured to: instantiate the pre-stored watchdog model in response to the startup of the verification environment of the verification platform before running the verification test case; and initialize the instantiated watchdog model. The initialization configuration is used to configure at least the enable state of the watchdog model and the preset timeout duration; the initialization configuration also includes: configuring each preset event as a different watchdog-feeding trigger source for the watchdog model.

[0111] In one embodiment, the watchdog module 420 is further configured to: instantiate multiple watchdog models based on pre-stored watchdog model code. Additionally, the watchdog module is further configured to: configure the same or different preset timeout durations for different watchdog models.

[0112] In some embodiments of this application, the watchdog module 420 is also configured to configure at least one of the following preset events: the control path of the design under test is in a working state; the verification test case is used to perform simulation verification on the design under test; the data path of the design under test transmits a handshake signal; the computing module of the design under test inputs or outputs data; and a preset custom event in the verification platform is completed.

[0113] In one embodiment, the watchdog model within the watchdog module 420 is constructed based on a UVM object.

[0114] In one embodiment, the watchdog model within the watchdog module 420 further includes a parameter passing interface. The watchdog module is used to send a parameter modification instruction to the watchdog model through the parameter passing interface; and modify the configuration parameters of the watchdog model based on the parameter modification instruction. The configuration parameters include at least one of the following: the preset timeout duration of the timer in the watchdog model; and the enabled state of the watchdog model.

[0115] In one embodiment, the parameter passing interface of the watchdog model within the watchdog module 420 is a command-line parameter passing interface, and the watchdog module is used to send parameter modification instructions to the watchdog model via the command line.

[0116] The functions implemented by the verification platform provided in this application can be described in the delayed output method provided in the foregoing embodiments. Other modules and functions of the verification platform can be referred to the prior art, and will not be elaborated here.

[0117] Please refer to point 5. Figure 5 This application also provides a schematic diagram of an electronic device 500, which can serve as the execution subject of the aforementioned watchdog-based simulation verification method, including: a processor 510 and a memory 520, wherein the processor 510 and the memory 520 are communicatively connected.

[0118] The electronic device 500 can be configured as a verification platform, and the memory 520 stores computer-readable instructions that can be executed by the processor 510, so that the processor 510 can execute the watchdog-based simulation verification method in the aforementioned embodiments.

[0119] The processor 510 and memory 520 are connected, but are not limited to, via a communication bus.

[0120] Processor 510 can be an integrated circuit chip with signal processing capabilities. Processor 510 can be a general-purpose processor, including a CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be a digital signal processor, application-specific integrated circuit, off-the-shelf programmable gate array, or other programmable logic device or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor.

[0121] The memory 520 may include, but is not limited to, RAM (Random Access Memory), ROM (Read Only Memory), PROM (Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0122] It is understood that the electronic device 500 may also include more general modules required by itself, which will not be described one by one in the embodiments of this application.

[0123] Based on the same inventive concept, embodiments of this application also provide a readable storage medium storing a program thereon. When the computer program runs on a processor, it causes the processor to execute the watchdog-based simulation verification method provided in the above embodiments.

[0124] The readable storage medium can be any available medium that the processor can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs (digital video discs)), or semiconductor media (e.g., SSDs (solid state disks)).

[0125] If the method is implemented as a software functional module and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0126] In the embodiments provided in this application, it should be understood that the disclosed methods and apparatus can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. The functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0127] The above embodiments can be freely combined without conflict, and the resulting embodiments are covered within the protection scope of this application.

[0128] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0129] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A simulation verification method based on a watchdog timer, characterized in that, The method is applied to a verification platform, which includes a watchdog model, and the watchdog-based simulation verification method includes: Run the verification test cases; The watchdog model monitors various preset events during the execution of the verification test case; wherein, the watchdog model includes multiple watchdog feeding trigger sources, and different watchdog feeding trigger sources correspond to different preset events; the watchdog model is used to feed the watchdog through its corresponding watchdog feeding trigger source based on the normal operation of each preset event; and, the watchdog model triggers a timeout if all preset events are abnormal, causing each watchdog feeding trigger source to fail to feed the watchdog. In response to the watchdog model timeout, a preset exception handling mechanism is executed.

2. The simulation verification method based on a watchdog timer according to claim 1, characterized in that, Before monitoring various preset events during the execution of the verification test case based on the watchdog model, the method further includes: Identify the various preset events to be monitored in the verification test cases; Each of the preset events is configured as a different dog-feeding trigger source for the watchdog model.

3. The simulation verification method based on a watchdog timer according to claim 2, characterized in that, The watchdog model includes a dog-feeding interface, which includes multiple data bits; The step of configuring each of the preset events as a different dog-feeding trigger source for the watchdog model includes: For any of the preset events, select any target data bit and configure the normal operation of the preset event to trigger the modification of the value of the target data bit from a first value to a second value.

4. The simulation verification method based on a watchdog timer according to claim 3, characterized in that, The monitoring of various preset events during the execution of the verification test cases based on the watchdog model includes: Iterate through each data bit of the dog feeding interface; When any of the data bits is the second value, the dog-feeding interface triggers the dog-feeding process.

5. The simulation verification method based on a watchdog timer according to claim 3, characterized in that, The watchdog model also includes a timer, and the watchdog model is also configured with a preset timeout duration; Before traversing each data bit of the dog-feeding interface through the dog-feeding interface, the method further includes: timing based on the timer; After traversing each of the data bits of the dog-feeding interface, the method further includes: When the timer reaches the preset timeout duration and all data bits are at the first value, the watchdog model is determined to have triggered a timeout. Furthermore, after the dog-feeding interface triggers the dog-feeding process, the method further includes: resetting the timer's duration to zero.

6. The simulation verification method based on a watchdog timer according to claim 5, characterized in that, Before the watchdog model triggers a timeout, and all data bits are at the first value when the timer's duration reaches the preset timeout duration, the method further includes: When the timer reaches a preset warning interval, the watchdog model triggers a warning. Furthermore, the method further includes: triggering a reset when the number of warnings reaches a reset threshold, wherein the reset is used to trigger the execution of the preset exception handling mechanism.

7. The simulation verification method based on a watchdog timer according to claim 5, characterized in that, Before running the verification test cases, the method further includes: In response to the startup of the verification environment of the verification platform, the pre-stored watchdog model is instantiated; The instantiated watchdog model is initialized and configured. The initialization configuration is used to configure at least the enable state of the watchdog model and the preset timeout duration; The initialization configuration also includes: configuring each of the preset events as a different dog-feeding trigger source for the watchdog model.

8. The simulation verification method based on a watchdog timer according to claim 7, characterized in that, The instantiation of the pre-stored watchdog model includes: Based on the pre-stored code of the watchdog model, instantiate multiple watchdog models; The initialization configuration of the instantiated watchdog model includes: Configure the same or different preset timeout durations for different watchdog models.

9. The simulation verification method based on a watchdog timer according to claim 1, characterized in that, The preset event includes at least one of the following: The control path of the design under test is in operation; the verification test case is used to perform simulation verification on the design under test. The data path of the design under test transmits handshake signals; The computation module of the design under test inputs or outputs data; The verification platform has completed the execution of a preset custom event.

10. The simulation verification method based on a watchdog timer according to any one of claims 1-9, characterized in that, The watchdog model is built based on UVM objects.

11. The simulation verification method based on a watchdog timer according to claim 10, characterized in that, The watchdog model also includes a parameter passing interface, and the watchdog-based simulation verification method further includes: Send parameter modification instructions to the watchdog model through the parameter transmission interface; The watchdog model's configuration parameters are modified based on the parameter modification command; the configuration parameters include at least one of the following: the preset timeout duration of the timer in the watchdog model; and the enable state of the watchdog model.

12. The simulation verification method based on a watchdog timer according to claim 11, characterized in that, The parameter passing interface is a command-line parameter passing interface. Sending parameter modification instructions to the watchdog model through the parameter passing interface includes sending parameter modification instructions to the watchdog model via the command line.

13. A verification platform, characterized in that, include: The verification module is used to run verification test cases; A watchdog module is used to run a watchdog model and monitor various preset events during the execution of the verification test case based on the watchdog model. The watchdog model includes multiple watchdog trigger sources, each corresponding to a different preset event. The watchdog model feeds the watchdog through its corresponding trigger source based on the normal operation of each preset event. Furthermore, the watchdog model triggers a timeout if all preset events fail to trigger a watchdog, resulting in the trigger source not feeding the watchdog. An exception handling module is used to execute a preset exception handling mechanism in response to a timeout in the watchdog model.

14. An electronic device, characterized in that, include: A memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, cause the processor to be configured as a verification platform and to perform the watchdog-based simulation verification method as described in any one of claims 1-12.

15. A computer-readable storage medium, characterized in that, The readable storage medium stores a computer program that, when run on a computer, causes the computer to perform the watchdog-based simulation verification method as described in any one of claims 1-12.

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