Dual-scale concurrent timing optimization method for asic global placement critical path

Abstract

The present disclosure provides a kind of ASIC Global layout critical path double-scale collaborative timing optimization method, comprising: first complete initial layout, adopt report_timing_type(n,c) Screening timing violation critical path, then update the weight of key pin by logarithmic dynamic weight, build double-scale loss function iterative optimization layout containing pin and path two-level constraints, and output the layout after convergence legalization.The present disclosure solves the defects that the existing timing layout is difficult to balance STA overhead and timing accuracy, TNS / WNS Optimization is insufficient, path extraction is simplified to reduce timing analysis time, logarithmic weight strengthens optimization priority of severe violation path, double-scale mechanism cooperates with control local interconnection and global path distribution, significantly improves the timing convergence effect of super large scale ASIC With a small increase in computational complexity.

Description

Technical Field

[0001] This disclosure relates to the field of digital integrated circuit electronic design automation (EDA) technology, and in particular to a critical path-based dual-scale collaborative timing optimization method for ASIC global layout. Background Technology

[0002] With the evolution of very large-scale integrated circuit (VLSI) technology, the scale and complexity of ASIC chip design have increased exponentially, placing stringent demands on electronic design automation (EDA) technology. Placement and routing, which connect logic design and physical implementation in the physical design flow, occupy the majority of the design cycle. Placement determines the coordinates of millions of logic cells in the chip, and its quality directly determines subsequent routing difficulty, bus length, congestion, power consumption, critical path delay, and other chip performance indicators. Accurate prediction and optimization of physical indicators during the placement stage are key to overcoming design bottlenecks.

[0003] Traditional physical design processes suffer from significant lag: conventional placement algorithms focus on minimizing bus length and optimizing density, without directly introducing timing constraints; after placement, the cell space distribution is uniform but the electrical performance is unreasonable, the spacing between critical path cells is too large, and the lack of timing awareness in the global placement stage causes line length delays and interconnection congestion that are difficult to repair through routing and buffer insertion, resulting in repeated iterative placement modifications and rerouting, increasing the risk and time cost of tape-out.

[0004] Timing-Driven Placement (TDP) bridges the gap between geometry optimization and timing analysis. It incorporates timing information such as critical path delay and slack from static timing analysis (STA) into the global placement objective function, shortening the critical path in the early stages of placement, improving timing convergence, and reducing the number of timing violation iterations. It is a core technology for improving ASIC design quality and adapting to advanced process timing constraints.

[0005] Nonlinear analytical layouts offer excellent solution quality. Existing solutions like ePlace are based on electrostatic potential energy models, fast Fourier transforms, and Nesterov momentum methods with the goal of minimizing line length and using penalty functions to transform constraints for optimization. RePlAce adds adaptive parameter adjustment and a cell expansion mechanism to alleviate local congestion, but both only focus on geometric optimization and cannot adapt to stringent temporal constraints.

[0006] Existing analytical timing-driven placement technologies include Differentiable-TDP, DistributionTDP, ElectrostaticsTDP, HybridModeling-TDP, NadamHybrid-TDP, DREAMPlace 4.0, and Efficient-TDP. These solutions integrate static timing analysis into the analytical placement framework. However, the STA coupling accuracy and timeliness of static timing analysis directly determine the placement optimization effect. Existing differentiable and hybrid modeling solutions need to make trade-offs between computational overhead and timing prediction accuracy, making it difficult to simultaneously consider line length and density optimization and continuously map path timing information into an optimizable objective function. At the same time, timing-driven placement is difficult to accurately locate timing bottleneck paths, and the improvement of TNS and WNS optimization is limited. This results in huge STA computational overhead caused by traditional critical path extraction, making it impossible to simultaneously balance timing optimization effect and overall operating efficiency, and making it difficult to adapt to VLSI design.

[0007] Therefore, a collaborative timing optimization method that can solve the problem that existing parsing timing-driven layout schemes cannot simultaneously take into account STA coupling accuracy, computational overhead, and timing performance optimization effects, and is adapted to ultra-large-scale ASIC designs, urgently needs to be developed. Summary of the Invention

[0008] The purpose of this disclosure is to construct a dual-scale collaborative optimization mechanism at the pin level and path level, and to implement a static timing analysis path selection and logarithmic dynamic weight update strategy. This will shorten critical path latency and improve total negative relaxation and worst-case negative relaxation timing metrics while significantly reducing the computational overhead of static timing analysis, providing a complete technical solution with low overhead and high timing optimization effect for global layout of ultra-large-scale ASICs.

[0009] The technical solution disclosed herein is:

[0010] A dual-scale collaborative timing optimization method for critical paths in ASIC global layout, comprising:

[0011] Input the ASIC circuit netlist and layout constraint parameters, and perform initial global layout;

[0012] Static timing analysis is performed, and the critical paths for timing violations are extracted using the report_timing_type (n,c) strategy, resulting in a set of critical paths. ;

[0013] Based on the set of critical paths A logarithmic dynamic weight update strategy is used to update each pin pair within the critical path. The corresponding optimization weights;

[0014] A dual-scale collaborative loss function, which includes both pin-level optimization terms and path-level diffusion constraint terms, is constructed as the layout optimization objective. The optimal coordinates of each logic unit are iteratively solved and the layout results are updated.

[0015] Under the premise that the layout optimization converges, the layout legalization process is performed, and the final ASIC global layout result is output.

[0016] In the report_timing_type (n,c) strategy, parameter n is the number of time endpoints to be extracted, and parameter c is the target type of time violation; and time endpoints are filtered according to the time violation type c, retaining only the time endpoints of the corresponding violation type.

[0017] The report_timing_type (n,c) strategy filters each time-series endpoint after filtering, obtains candidate paths with negative relaxation, and sorts them according to relaxation values.

[0018] Extract the worst-case path for each endpoint relaxation and output it. The critical path set consists of several paths. .

[0019] The set of critical paths A logarithmic dynamic weight update strategy is used to update each pin pair within the critical path. The corresponding optimization weights include:

[0020] ;

[0021] in, For pin pairs Optimize the weights; Basic weights; slack is the weight scaling factor; slack is the path timing margin. It is a minimal constant used to eliminate the zeros of the logarithmic domain; This is the set of critical paths.

[0022] The expression for the dual-scale collaborative loss function is as follows:

[0023] ;

[0024] in, These are the coordinates of the logical unit's location. It is a function of the length of the smoothed half-circumference; For density measurement; Density penalty factor; , For hyperparameters; For pin-level function terms; This is a path-level item.

[0025] The pin-level function satisfy:

[0026] ;

[0027] in, The square of the Euclidean distance between the pin pairs; For pin pairs Optimize the weights; This is the set of critical paths.

[0028] The pin is at a squared Euclidean distance. satisfy:

[0029] ;

[0030] in, For pins The coordinates; For pins The coordinates.

[0031] The path-level item satisfy:

[0032] ;

[0033] in, For the set of all critical paths; For path The corresponding dynamic path weights; It is the square of the half perimeter of the rectangle enclosed by all the cells of a single path.

[0034] The square of the half perimeter of the rectangle enclosed by all units of the single path Represented as:

[0035] ;

[0036] in, These represent the maximum and minimum x-coordinates of all cells along a single path, respectively. These represent the maximum and minimum ordinate values ​​of all cells along a single path.

[0037] The path weight The update formula is:

[0038] ;

[0039] in, This represents the worst-case negative timing margin. This is for timing margin.

[0040] Worst-case negative timing margin With total negative timing margin Represented as:

[0041] ;

[0042] ;

[0043] in, set of critical paths Any path within; Representing a path The timing margin.

[0044] The beneficial effects of this disclosure include at least the following:

[0045] This disclosure addresses multiple shortcomings of existing analytical timing-driven layout schemes, such as the need to compromise between STA computational overhead and timing prediction accuracy, the inability to accurately locate timing bottleneck paths, the limited optimization range of TNS and WNS, and the difficulty in adapting to ultra-large-scale circuits. It can significantly reduce the time consumption of static timing analysis by relying on a simplified path selection mechanism, and can amplify the optimization priority of severely violated paths by leveraging a logarithmic weight strategy. At the same time, it can realize local pin distance constraints and global critical path space control by relying on dual-scale loss synchronization. It can significantly improve the overall timing convergence performance with a slight increase in computation, and balance the optimization quality of bus length and layout density with algorithm running efficiency. Attached Figure Description

[0046] Figure 1 This is a flowchart of the complete system framework for global layout timing iteration of ASIC disclosed in this paper.

[0047] Figure 2 This diagram illustrates a comparison between the logarithmic dynamic weight update strategy of this disclosure and the traditional linear weight update strategy.

[0048] Figure 3 The graph shows a comparison between the critical path extraction strategy disclosed herein and existing extraction schemes such as Efficient-TDP and OpenTimer in terms of the number of extracted paths and the cumulative time spent on static time series analysis. Detailed Implementation

[0049] The technical solutions of the embodiments of this disclosure will be clearly and thoroughly described below with reference to the accompanying drawings. The described embodiments are merely some embodiments of this disclosure. Specific Implementation Example 1:

[0051] In this embodiment, as Figure 1 As shown, a dual-scale collaborative timing optimization method for critical paths in ASIC global placement includes: inputting the ASIC circuit netlist and placement constraint parameters, performing initial global placement; performing static timing analysis, and using the report_timing_type (n,c) strategy to extract timing violation critical paths, thus obtaining a set of critical paths. Based on the set of critical paths A logarithmic dynamic weight update strategy is used to update each pin pair within the critical path. The corresponding optimization weights are determined; a dual-scale collaborative loss function containing both pin-level optimization terms and path-level diffusion constraint terms is constructed as the layout optimization objective, and the optimal coordinates of each logic unit are iteratively solved and the layout results are updated; under the premise of layout optimization convergence, layout legalization processing is performed, and the final ASIC global layout result is output; in the report_timing_type (n,c) strategy, parameter n is the number of timing endpoints to be extracted, and parameter c is the timing violation target type; and timing endpoints are filtered according to timing violation type c, retaining only timing endpoints of the corresponding violation type.

[0052] In the iterative optimization phase driven by timing in ASIC global layout, this embodiment includes: critical path extraction, weight update, and pin-path dual-scale collaborative optimization. Through the coordinated work of these three core steps, the key information feedback from timing analysis can be fully utilized, thereby effectively solving the timing convergence problem.

[0053] Regarding critical path extraction strategies:

[0054] The effectiveness and efficiency of time series optimization largely depend on the rationality and accuracy of the critical path extraction strategy, as the design of this strategy directly affects the quality and speed of time series convergence.

[0055] To address this core issue, this embodiment proposes a critical path extraction strategy, `report_timing_type(n, c)`, specifically tailored for accurate timing repair. This strategy achieves a good balance between path representativeness and computational efficiency. The parameter `n` specifies the number of timing endpoints to be extracted (main output port, data input pins of timing units, pins with specified output delays), while the parameter `c` precisely constrains the target type of timing violation (setup time or hold time).

[0056] The `report_timing_type` strategy first distinguishes endpoints based on violation type and then extracts paths only for endpoints corresponding to the specified violation category. For each timing endpoint, the system first filters out paths with negative relaxation as candidate paths and sorts them by priority according to their relaxation values. Then, it extracts the path with the worst relaxation (i.e., the worst timing) from each endpoint. This method returns n paths, ensuring that each mentioned endpoint is properly covered, thus comprehensively reflecting the timing issues of the entire chip and directly targeting the TNS metric.

[0057] By employing a two-stage mechanism—first filtering by violation type and then sorting endpoint paths based on priority—this method can return the worst-case timing path for a specified violation type for each target endpoint and directly output the core violation path. This design effectively eliminates redundant paths, ensuring that all extracted paths are highly aligned with the timing repair target, thereby significantly improving the focus and execution efficiency of timing optimization.

[0058] Regarding the logarithmic dynamic weight update strategy:

[0059] The weight update mechanism plays a crucial role in bridging static timing analysis and layout optimization. Because timing constraints are inherently discrete and non-differentiable, the layout optimization process cannot directly use path-level timing violations as optimization targets. Therefore, weight updates are needed to transform critical paths and their timing margin information into continuous, optimizable cost terms.

[0060] (1)

[0061] Equation (1) uses a linear mapping to quantify the severity of timing violations. However, this linear transformation reduces the weight difference between severe violation paths and minor violation paths, thus weakening the weight's ability to distinguish high-priority paths. To amplify the weight proportion of severe violation paths, this paper introduces a logarithmic function to perform a nonlinear mapping of violation severity and proposes an improved weight update formula:

[0062] (2)

[0063] Timing margin (slack) represents the timing relaxation value of a path, where the constant is a constant. This is to avoid hour A small quantity introduced when it is undefined. Parameter Set the base weight to 10. The weight scaling factor is set to 0.2 to control the contribution of the logarithmic term to the final weight.

[0064] The improved logarithmic weight update formula utilizes the non-linear properties of the logarithmic function—monotonically increasing with a decreasing growth rate—to achieve precise priority differentiation of temporal violation paths. On one hand, its monotonicity ensures a positive correlation between the severity of the violation (i.e., the absolute value of the negative temporal margin) and the weight increment, conforming to the temporal optimization principle that higher weights should be given to more severe violations. On the other hand, its decreasing growth rate effectively amplifies the weight difference between paths with severe and minor violations. This characteristic allows temporal optimization resources to be selectively allocated to the most critical and most severely violated paths, improving both the differentiation capability of the weight mechanism and the accuracy of resource allocation during the temporal repair phase. Therefore, this method improves overall optimization efficiency and provides more reasonable weight guidance for subsequent temporal optimization iterations.

[0065] As shown in Figure 2, the comparison between linear and logarithmic weight update methods visually illustrates this effect: the green, blue, and orange curves correspond to the three timing paths, respectively. Under the traditional linear weight method, the weight difference between pin pairs is mainly dominated by the number of their shared paths; even if the negative timing margin of a path becomes more severe, the weight increase is very gradual, resulting in insufficient differentiation of extreme violation paths and weakening the impact of severe violation paths on pin importance. In contrast, the logarithmic weight update strategy breaks through the limitation of relying solely on shared path counts, dynamically adjusting the weights according to the severity of timing violations for each path. Through logarithmic transformation, this method amplifies the weight proportion corresponding to severe violation paths, thus more accurately meeting the actual need for timing optimization to prioritize the repair of critical violation paths.

[0066] Regarding the time-based dual-scale loss function:

[0067] This work explicitly introduces a pin-path dual-scale optimization term into the objective function to enhance the ability of the placement optimization process to capture the geometric features of critical timing paths. This constraint term not only optimizes the distance between highly shared pins and pin pairs but also limits the physical dispersion of critical paths in the placement space, guiding the cells associated with the critical paths to be more spatially compact, thereby enhancing the optimizer's direct control over paths with severe timing violations.

[0068] The more concentrated the cell distribution along the critical timing path, the shorter the interconnect length and the corresponding RC delay. This not only makes the path delay easier to compress but also increases the likelihood of satisfying timing relaxation constraints. The extended objective function formula is as follows:

[0069] (3)

[0070] In the formula, x and y are the cell position coordinates, WL is the smoothed half-perimeter length (HPWL) function (e.g., weighted average model), and D is the density metric. This is the density penalty factor. , These are hyperparameters. The expression for the pin-level function term is as follows:

[0071] (4)

[0072] Selective constraints are applied based on the independent timing slack of each pin pair on the critical path, thereby precisely reducing the distance between highly shared critical pins to decrease line latency. This not only avoids degrading the line length of other networks or creating new violation paths, but also achieves finer timing control by accurately calculating the cumulative impact of path sharing. This significantly improves timing performance while effectively maintaining global line length quality. During the optimization process, the weights corresponding to each pin pair on the critical path are dynamically updated. This dynamic weight update uses the logarithmic dynamic weight update strategy mentioned above, which further enhances the sensitivity to temporal changes caused by the shared path structure. This is the square of the Euclidean distance. This loss term is modeled based on the quadratic growth characteristic of the RC delay, which, compared to linear distance, shows a higher degree of fit with actual time series models. The expression for this distance is as follows:

[0073] (5)

[0074] Path-level items The expression is as follows:

[0075] (6)

[0076] For a set of paths. Path weights. The update expression is as follows:

[0077] (7)

[0078] Representing the square of the half-circle length, this indicator uses a model that more closely reflects the actual physical layout characteristics and can characterize the growth trend of RC delay as a function of line length, thus more accurately reflecting timing characteristics. Its specific form is as follows:

[0079] (8)

[0080] and These represent the leftmost and rightmost positions of all points contained in a path, respectively. and These represent the top and bottom positions. In this formula, each path is mapped as a weight factor, enabling the model to optimize temporal behavior from a global path-level perspective. The new objective function, while retaining the fine-grained ability to decompose the critical path into pin-pair cost terms, further enhances the path-level temporal driving effect, achieving coordinated control of the critical path at both the local connectivity and global path scales.

[0081] Through this dual-scale optimization mechanism, the proposed method can simultaneously handle local delay optimization and global path structure adjustment in timing-sensitive regions, achieving more efficient and stable timing repair. As shown in Figure 2, in addition to pin-level local optimization, this framework also introduces a global control mechanism for each path, enabling more effective and targeted adjustments to the entire path during the layout optimization process.

[0082] Verification process:

[0083] The method described in this embodiment has been verified on the open-source and industry-authoritative timing benchmark, ICCAD2015. All test cases are large in scale, with the vast majority containing a large number of cells and nets, and none of the benchmarks contain movable macrocells. Specific information is as follows:

[0084] Table 1: ICCAD 2015 Competition Design Data

[0085]

[0086] All experiments were conducted on a Linux platform. The algorithm presented in this disclosure was implemented using Python and C++ and run on a workstation with an Intel i7-10700 CPU, 64GB of RAM, and an NVIDIA GeForce RTX 2060 graphics card.

[0087] Regarding hyperparameter settings, Values , Values The timing optimization phase is activated starting from the 500th iteration, at which point the cell distribution has basically stabilized.

[0088] Worst Negative Timing Margin (WNS) is the smallest timing margin value among all paths with timing violations, representing the most severe timing violation in the circuit and corresponding to the highest priority critical path. Total Negative Timing Margin (TNS) is the sum of the timing margins of all timing violation paths, reflecting the overall degree of timing violations in the circuit and corresponding to all critical paths.

[0089] set up Let p be a set of time-series paths, where p is any path within the set. This represents the timing margin of path p. The worst-case negative timing margin and the total negative timing margin are calculated as follows:

[0090] (9)

[0091] (10)

[0092] Commonly used line length estimation models include the half-perimeter line length model, the star model, and the Steiner tree model. Among them, the half-perimeter line length model is the simplest in form and the most widely used. For a net e, first select the smallest rectangle that can enclose all the pins of the net, and then use half the perimeter of this rectangle as the estimated line length. Let x and y be the coordinates of the pins within the net, and their mathematical expressions are as follows:

[0093] (11)

[0094] I. Layout performance:

[0095] Table 2 is from TNS (unit: ×10) 5 ps), WNS (unit: ×10³ ps), HPWL (unit: ×10) 6 The proposed time-driven layouter was comprehensively compared with the latest authoritative layouters DREAMPlace 4.0 and Efficient-TDP mentioned in the background section above, based on four metrics: time, execution time (in seconds), and performance. The best results for each metric are marked in bold, and the second-best results are marked in brown. All results were validated using the official ICCAD 2015 competition evaluation kit to ensure the fairness and consistency of the comparison. Experimental results show that the overall performance of the proposed method is significantly better than Efficient-TDP and DREAMPlace 4.0.

[0096] Table 2: Performance Comparison

[0097]

[0098] As shown in Table 2, the method described in this embodiment achieves best or near-best timing performance on all test benchmarks. Compared to Efficient-TDP, it achieves average improvements of 18.3% and 4.4% on TNS and WNS, respectively, effectively reducing total negative relaxation and worst-case critical path latency. Regarding HPWL, the proposed method performs comparably to Efficient-TDP, indicating that timing optimization does not introduce additional line length overhead, thus maintaining a good balance between timing and line length objectives. In terms of runtime, the total runtime of the proposed method increases by approximately 5% compared to Efficient-TDP, with comparable computational cost. These results confirm that the proposed method maintains good scalability while providing excellent timing quality.

[0099] Overall, the experimental results clearly demonstrate that the method described in this embodiment, which combines pin-pair-level local modeling with path-level global timing optimization, can achieve more efficient timing-driven global layout without significantly increasing computational complexity.

[0100] II. Experimental Results of Different Path Extraction Strategies

[0101] like Figure 3 The experimental results verified the findings proposed in this embodiment. The strategy demonstrates a significant advantage in path extraction efficiency. This is comparable to the strategy used in Efficient-TDP. Compared to the native critical path extraction strategy of OpenTimer (an open-source academic static time series analysis tool), the method described in this embodiment extracts significantly fewer critical paths in each iteration (e.g., ...). Figure 3 (a)). As the number of STA iterations increases, the number of paths extracted by the method described in this embodiment remains at a relatively low level, while Efficient-TDP and OpenTimer continuously extract approximately There are several paths. This clearly shows that... It is more targeted and effective in selecting representative routes for each region.

[0102] In addition, regarding STA runtime (e.g.) Figure 3 (b) The total runtime of the method described in this embodiment is only 50% of that of Efficient-TDP and 25% of that of OpenTimer. These results show that by consistently extracting fewer critical paths, the proposed strategy significantly reduces the overall STA computation while maintaining meaningful timing optimization guidance accuracy, thereby greatly improving the efficiency of overall timing optimization.

[0103] As can be seen, this embodiment proposes a dual-scale collaborative optimization mechanism at the pin level and path level. At the pin level, it retains the fine-grained optimization capability of decomposing critical paths into pin-pair cost terms, enabling refined control of local connection delays. Simultaneously, at the path level, it introduces a global timing regulation mechanism. By filtering critical violation paths through static timing analysis and employing a logarithmic dynamic weight update strategy, the severity of pin-level timing violations is mapped to optimizable weight terms, amplifying the priority differences of severely violation paths. This dual-scale collaborative optimization architecture overcomes the limitation of traditional single linear weight methods in their insufficient differentiation of extreme timing violation paths. It achieves collaborative control of local pin connection optimization and global critical path timing repair, more accurately guiding layout optimization resources towards high-priority timing-sensitive areas, significantly improving overall timing optimization efficiency.

[0104] It should be clarified that the path-level timing optimization method used in this embodiment updates weights and distinguishes priorities on a pin-pair and path-by-path basis, thereby achieving timing-driven layout optimization. In addition, those skilled in the art can also achieve the same timing optimization effect using other technical solutions. For example, by assigning differentiated weights to different nets, layout optimization can be guided to prioritize critical nets, thereby improving overall timing performance. Timing optimization methods combining artificial intelligence, such as intelligent timing-driven layout methods based on reinforcement learning and graph neural networks, can also achieve the goal of timing repair and optimization of critical paths by dynamically adjusting the layout strategy by learning the timing characteristics of the circuit. Specific Implementation Example 2:

[0106] This disclosure also provides an embodiment:

[0107] An electronic device includes: a storage medium and a processing unit; wherein the storage medium is used to store a computer program, and the processing unit exchanges data with the storage medium for executing the computer program through the processing unit during timing-driven layout optimization to perform the steps of the method as described in Specific Embodiment 1. Specific Implementation Example 3:

[0109] A computer-readable storage medium storing a computer program; when the computer program is run, it performs the steps of the method described in Specific Embodiment 1.

[0110] In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0111] The above disclosures only cover a few specific implementation scenarios. However, this disclosure is not limited to these, and any variations that can be conceived by those skilled in the art should fall within the protection scope of this disclosure. The serial numbers in this disclosure are for descriptive purposes only and do not represent the superiority or inferiority of the implementation scenarios.

Claims

1. A dual-scale collaborative timing optimization method for critical paths in ASIC global layout, characterized in that, include: Input the ASIC circuit netlist and layout constraint parameters, and perform initial global layout; Static timing analysis is performed, and the critical paths for timing violations are extracted using the report_timing_type (n,c) strategy, resulting in a set of critical paths. ; Based on the set of critical paths A logarithmic dynamic weight update strategy is used to update each pin pair within the critical path. The corresponding optimization weights; A dual-scale collaborative loss function, which includes both pin-level optimization terms and path-level diffusion constraint terms, is constructed as the layout optimization objective. The optimal coordinates of each logic unit are iteratively solved and the layout results are updated. Under the premise that the layout optimization converges, perform layout legalization processing and output the final ASIC global layout result; In the report_timing_type (n,c) strategy, parameter n is the number of time-series endpoints to be extracted, and parameter c is the target type of time-series violation; And filter the timing endpoints according to the timing violation type c, keeping only the timing endpoints of the corresponding violation type.

2. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 1, characterized in that, include: The report_timing_type (n,c) strategy filters each time-series endpoint after filtering, obtains candidate paths with negative relaxation, and sorts them according to relaxation values. Extract the worst-case relaxation path for each endpoint and output it. The critical path set consists of several paths. .

3. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 1, characterized in that, The set of critical paths A logarithmic dynamic weight update strategy is used to update each pin pair within the critical path. The corresponding optimization weights include: ； in, For pin pairs Optimize the weights; Basic weights; slack is the weight scaling factor; slack is the path timing margin. It is a minimal constant used to eliminate the zeros of the logarithmic domain; This is the set of critical paths.

4. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 1, characterized in that, The expression for the dual-scale collaborative loss function is as follows: ； in, These are the coordinates of the logical unit's location. It is a function of the length of the smoothed half-circumference; For density measurement; Density penalty factor; , For hyperparameters; For pin-level function terms; This is a path-level item.

5. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 4, characterized in that, The pin-level function satisfy: ； in, The square of the Euclidean distance between the pin pairs; For pin pairs Optimize the weights; This is the set of critical paths.

6. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 5, characterized in that, The pin is at a squared Euclidean distance. satisfy: ； in, For pins The coordinates; For pins The coordinates.

7. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 4, characterized in that, The path-level item satisfy: ； in, For the set of all critical paths; For path The corresponding dynamic path weights; It is the square of the half perimeter of the rectangle enclosed by all the cells of a single path.

8. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 7, characterized in that, The square of the half perimeter of the rectangle enclosed by all units of the single path Represented as: ； in, These represent the maximum and minimum x-coordinates of all cells along a single path, respectively. These represent the maximum and minimum ordinate values ​​of all cells along a single path.

9. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 7, characterized in that, The path weight The update formula is: ； in, This represents the worst-case negative timing margin. This is for timing margin.

10. The dual-scale collaborative timing optimization method for critical paths in ASIC global layout according to claim 9, characterized in that: Worst-case negative timing margin With total negative timing margin Represented as: ； ； in, set of critical paths Any path within; Representing a path Timing margin.

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