A hardware description generation method based on high-level synthesis of channelization algorithm

Abstract

The application discloses a channelization algorithm hardware description generation method based on high-level synthesis, which comprises the following steps: S1, in a high-level synthesis tool, a high-level language description program for generating a channelization algorithm is written, and FPGA hardware specification parameters are configured; S2, compiling and function testing are completed through the high-level synthesis tool; S3, hardware settings and targets of the channelization algorithm are set in the high-level synthesis tool; S4, the high-level synthesis tool converts and generates a corresponding channelization algorithm hardware language description program; S5, a joint simulation test file is written, and the high-level language description program and the hardware language description program of the channelization algorithm are jointly simulated and verified; and S6, the channelization algorithm hardware language description program is packaged in the high-level synthesis tool, and a reused channelization algorithm IP core is obtained. The application automatically generates the hardware description of the algorithm by applying the high-level synthesis technology, greatly shortens the channelization hardware design flow cycle, and improves the flexibility and maintainability of the program.

Description

Technical Field

[0001] This invention relates to the field of signal processing, and in particular to a method for generating a channelized hardware description of real-number signals based on high-level synthesis technology for programmable logic devices. This method enables the automated generation of hardware description languages ​​and IP cores from high-level languages, providing support for the parameterized implementation of radar detection channelization algorithms of different scales. Background Technology

[0002] Signal sampling preprocessing is widely used in communications, signal detection, and other fields. These signals are characterized by their wide frequency domain and large bandwidth, allowing for the differentiation and processing of mixed signals in the frequency domain. Signal sampling converts the analog signal received by the antenna into a high-speed digital signal through analog-to-digital conversion. Preprocessing then converts the high-speed serial signal into a low-speed parallel signal with a large bit width, facilitating subsequent signal processing. Polyphase filtering is a commonly used channelization algorithm for signal preprocessing. It features good parallelism and simple structure, making it suitable for implementation in programmable logic devices and custom circuits.

[0003] High-level synthesis (HLS) is a tool for automatically generating custom circuits. Compared to writing hardware description languages, HLS tools can automatically convert high-level languages ​​into hardware description languages, significantly reducing circuit design and development time.

[0004] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention

[0005] Addressing the technical challenges of writing hardware description languages ​​for channelized algorithms, including difficulties, long development cycles, and poor code versatility, this invention aims to automate the generation of hardware description languages ​​from high-level languages ​​by introducing high-level synthesis technology, thus adapting to the deployment of channelized algorithm hardware of different scales and devices.

[0006] To achieve the above objectives, this invention provides a method for generating hardware descriptions of channelization algorithms based on high-level synthesis, comprising the following steps: Step S1: In the high-level synthesis tool, write a high-level language description program to generate the channelization algorithm. Configure the FPGA hardware specification parameters, including the number of sub-channels and the number of parallel input signals, in the header file of the high-level language description program to obtain the high-level language description program of the channelization algorithm containing the FPGA hardware specification parameters. The channelization algorithm uniformly divides the signal sampled by the external analog-to-digital converter into multiple parallel sub-channel signals. Each sub-channel signal is subjected to filtering calculations and time-frequency domain transformation operations. Finally, the channelization algorithm calculation results of each sub-channel are output for the external data processing unit to perform subsequent signal processing according to the sub-channel. Step S2: For the received high-level language description program of the channelization algorithm containing FPGA hardware specifications, complete the compilation and functional testing using high-level synthesis tools; Step S3: In the high-level synthesis tool, further refine the hardware settings and objectives of the channelization algorithm: specify the type of FPGA hardware platform for the channelization algorithm, and set the high-level synthesis objectives and high-level synthesis optimization instructions. The high-level integration objectives include: timing objectives, namely the expected operating clock frequency of the channelization algorithm on a specified FPGA hardware platform; and pipeline objectives, namely the clock cycle interval between the execution of the channelization algorithm once and the next execution of the channelization algorithm. Step S4: The high-level synthesis tool automatically converts and generates the corresponding channelization algorithm hardware language description program for the refined hardware settings and target channelization algorithm. Step S5: Compile a joint simulation test file for generating the channelization algorithm, and perform joint simulation verification on the high-level language description program of the channelization algorithm and the corresponding generated hardware language description program to ensure that the execution result of the hardware language description program of the channelization algorithm is consistent with the output result of its high-level language description program. Step S6: Using high-level synthesis tools, the channelization algorithm hardware language description program that has passed the joint simulation verification is encapsulated into a reusable channelization algorithm IP core.

[0007] The FPGA hardware specification parameters configured in S1 include: filter order, oversampling rate, number of transform points, conjugate enabled, conjugate disabled, normalization enabled, normalization disabled, inversion enabled, and inversion disabled.

[0008] Among them, the high-level comprehensive optimization instructions mentioned in S3 include: matrix rearrangement, matrix partitioning, binding storage, specifying constants, and loop expansion.

[0009] The channelization algorithm generated in S1 is implemented through a filter bank submodule and a transform operation and inversion submodule. The filter bank submodule is connected to an external analog-to-digital converter, receives multiple parallel input signals transmitted by the external analog-to-digital converter, stores the multiple parallel input signals and divides them into sub-channels, and performs filtering calculations on the input signals of each sub-channel in combination with filter coefficients, and outputs the intermediate filtering results of multiple sub-channels. The transformation operation and inversion submodule is connected to the filter bank submodule, receives the intermediate filtering results of multiple sub-channels from the filter bank submodule, performs transformation operations and inversion operations on each sub-channel, and finally outputs the calculation results of the channelization algorithm. The FPGA hardware specifications configured for the filter bank submodule include: number of sub-channels, total filter order, number of parallel input signals, and oversampling rate. The FPGA hardware specifications for the transformation and inversion submodules include: number of transformation points, conjugate enabled, conjugate disabled, normalization enabled, normalization disabled, inversion enabled, and inversion disabled.

[0010] The channelization algorithm generated in S1 has two working modes: polyphase filtering channelization mode and STFT mode.

[0011] Specifically, when S1 writes the channelization algorithm for generating the polyphase filter channelization mode, it generates the filter coefficients of the channelization algorithm for the polyphase filter channelization mode and stores them in header file format for the filter bank submodule to call.

[0012] In S1, when writing the channelization algorithm to generate the multiphase filter channelization mode, the FPGA hardware specifications are set as follows: conjugate enable, normalization enable, and inversion enable.

[0013] Specifically, when S1 writes the channelization algorithm for generating the STFT mode, it generates the filter coefficients of the channelization algorithm for the STFT mode and stores them in header file format for the filter bank submodule to call.

[0014] When S1 writes the channelization algorithm to generate the STFT mode, the FPGA hardware specifications are set as follows: conjugate is disabled and inversion is disabled. If data calculation overflows, normalization is enabled; otherwise, normalization is disabled.

[0015] Among them, the channelization algorithm IP core described in S6 is encapsulated by the filter bank submodule and the transform operation and inversion submodule of the channelization algorithm, respectively.

[0016] Compared with the prior art, the present invention has the following advantages: 1) This invention innovatively applies high-level synthesis technology in the hardware design process of channelization algorithms, which can significantly improve the automation level from top-level requirements to hardware implementation, greatly shorten the hardware design process cycle of channelization algorithms, unify top-level requirements, design input and output, and testing and verification processes, and realize the automatic generation of adapted hardware in different scenarios through configurable hardware specification parameters, thereby improving resource utilization.

[0017] 2) This invention divides the hardware design of the channelization algorithm into two sub-modules, and achieves automated hardware design generation through high-level synthesis, reducing the number of modules compared to manual hardware module design. The code of the hardware module written in a high-level language is reduced from tens of thousands of lines to hundreds of lines, significantly improving maintainability and readability. Attached Figure Description

[0018] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the drawings in the following description are one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 This is a schematic diagram illustrating the hardware description generation process of the channelization algorithm of the present invention; Figure 2 This is a schematic diagram of the multi-way shift register cache structure of the present invention; Figure 3 This is a schematic diagram of the multiply-accumulate operation of an instantiated DSP unit of the present invention; Figure 4 This is a schematic diagram illustrating the usage configuration of the multiphase filtering mode and STFT mode of the transformation operation and inversion submodule of the present invention. Figure 5 This is a schematic diagram of the butterfly operation unit of the transformation operation and inversion submodule of the present invention with different instantiation structures. Detailed Implementation

[0019] The following is in conjunction with the appendix Figures 1-5 The following detailed description further illustrates the hardware description generation method for channelization algorithms based on high-level synthesis proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0020] like Figure 1 As shown, this invention discloses a method for generating hardware descriptions of channelization algorithms based on high-level synthesis, the specific steps of which include: S1. In the high-level synthesis tool, write a high-level language description program to generate the channelization algorithm, and configure the FPGA hardware specification parameters, including the number of sub-channels and the number of parallel input signals, in the header file of the high-level language description program according to the channelization requirements, so as to finally obtain a high-level language description program of the channelization algorithm containing the FPGA hardware specification parameters. The channelization algorithm divides the signal sampled by the external analog-to-digital converter into multiple parallel sub-channel signals. Each sub-channel signal is subjected to filtering calculations and time-frequency domain transformation operations. Finally, the channelization algorithm calculation results of each sub-channel are output, which are then used by the external data processing unit for subsequent signal processing according to the sub-channel, thereby improving the parallel utilization of the FPGA.

[0021] S2. For the received high-level language description program of the channelization algorithm containing FPGA hardware specifications, complete the compilation and functional testing using high-level synthesis tools. S3. In the high-level synthesis tool, further refine the hardware settings and objectives of the channelization algorithm: specify the type of FPGA hardware platform for the channelization algorithm, and set the high-level synthesis objectives and high-level synthesis optimization instructions. The high-level integration objectives include: timing objectives, namely the expected operating clock frequency of the channelization algorithm on the currently specified FPGA hardware platform; and pipeline objectives, namely the clock cycle interval between the execution of the channelization algorithm once and the next execution of the channelization algorithm. S4. For the refined hardware settings and objectives of the channelization algorithm, the high-level synthesis tool automatically converts and generates the corresponding channelization algorithm hardware language description program, which conforms to the constraints of the corresponding high-level language description, high-level synthesis objectives, high-level synthesis optimization instructions and FPGA hardware platform. S5. Write a joint simulation test file to generate the channelization algorithm, and perform joint simulation verification on the high-level language description program of the channelization algorithm and the corresponding generated hardware language description program to ensure that the execution result of the hardware language description program of the channelization algorithm is consistent with the output result of its high-level language description program. S6. Using high-level synthesis tools, the channelization algorithm hardware language description program that has passed the joint simulation verification is encapsulated into a reusable channelization algorithm IP (intellectual property) core for use in subsequent projects.

[0022] The FPGA hardware specifications configured in S1 include: filter order, oversampling rate, number of transform points, conjugate enable / disable, normalization enable / disable, and inversion enable / disable.

[0023] The present invention can generate channelization algorithms in multiple operating modes, including: polyphase filtering channelization mode and STFT (Short Time Fourier Transform) mode.

[0024] When S1 writes and generates a channelization algorithm for a certain working mode, it generates the filter coefficients of the channelization algorithm for the corresponding working mode and stores them in header file format for the channelization algorithm to call in that corresponding working mode.

[0025] Among them, the high-level comprehensive optimization instructions described in S3 are used to guide the optimization operation of the channelization algorithm hardware architecture. The high-level comprehensive optimization instructions include: matrix rearrangement, matrix partitioning, binding storage, specifying constants, loop expansion, etc.

[0026] Specifically, S2 describes using high-level synthesis tools to complete compilation and functional testing, which includes: S21. For the high-level language description program of the channelization algorithm containing FPGA hardware specifications, compile it using the high-level synthesis tool. If the compilation fails, return to S1, modify the high-level language description program and recompile. If the compilation succeeds, the high-level language description program has no logical or syntactic errors, and continue with functional testing. S22. Run the functional test cases using the high-level synthesis tool. If the output results are consistent with expectations, it indicates that the high-level language description program is functionally correct, and continue to S3; otherwise, return to S1, modify the corresponding functional program, and re-execute S2.

[0027] The core algorithm of this invention is the channelization algorithm, which can be implemented through two sub-modules: a filter bank sub-module and a transform operation and inversion sub-module. The filter bank sub-module is connected to an external analog-to-digital converter (ADC), receives multiple parallel input signals transmitted from the ADC, stores and divides these signals into sub-channels, and then, using the generated filter coefficients of the channelization algorithm for the corresponding operating mode, performs filtering calculations on the input signals of each sub-channel, outputting intermediate filtering results for multiple sub-channels. The transform operation and inversion sub-module is connected to the filter bank sub-module, receives the intermediate filtering results from the multiple sub-channels of the filter bank sub-module, performs transform operations and inversion operations on each sub-channel for the corresponding operating mode, and finally outputs the calculation results of the channelization algorithm for the corresponding operating mode.

[0028] Among them, the channelization algorithm IP core described in S6 is encapsulated in units of each sub-module (i.e., filter bank sub-module and transform operation and inversion sub-module).

[0029] Specifically, the FPGA hardware specifications configured in the filter bank submodule include: number of sub-channels M, total filter order L, number of parallel input signals N, and oversampling rate K. The filter bank submodule mainly includes: a multiplexer register and an instantiated DSP (Digital Signal Processing) unit. The multiplexer register is connected to an external analog-to-digital converter and the instantiated DSP unit. It operates according to the clock frequency set in S3 to obtain a clock cycle. Within each clock cycle (per clock cycle), the multiplexer register is set on each input signal path. That is, a shift register is set on each input signal path in each clock cycle. Each shift register receives one input signal corresponding to the current clock cycle. Therefore, the multiplexer register receives N parallel input signals in the current clock cycle, and each shift register stores the corresponding input signal path for the current clock cycle. The N parallel input signals are then distributed to M sub-channels. Finally, the input signals of the M sub-channels in the current clock cycle are transmitted to the instantiated DSP unit for filtering calculations. The instantiated DSP units are connected to the transform operation and inversion submodule. One instantiated DSP unit is set on each subchannel, for a total of M units. When the input signals of the current M subchannels are received, the M instantiated DSP units synchronously perform multiplication and accumulation operations on the corresponding subchannel input signals in each cycle. Each instantiated DSP unit outputs an operation result, i.e., a filtering intermediate result. Finally, the filtering intermediate results of the M subchannels are output in each cycle and passed to the transform operation and inversion submodule.

[0030] Furthermore, such as Figure 2 The diagram shows the overall structure of a multi-channel shift register. N shift registers, each storing N input signals, form a parallel shift register array. This array stores the N parallel input signals within the same time period as buffered data. The total number of stages equals the filter order of each channel, L / N. The N parallel input signals are first stored in the first-stage shift register array. After each clock cycle, the buffered data of all N shift registers is synchronously shifted to the right to the next stage. Where Z... -1 This indicates that one time period has elapsed. The cached data is in the format of a fixed-point signed number, and its decimal places and total bit width can be specified in the header file.

[0031] Furthermore, such as Figure 3As shown, the multiply-accumulate operation process of each instantiated DSP unit is as follows: First, the input signal allocated to the sub-channel is horizontally expanded. The instantiated DSP unit of the sub-channel performs multiply-accumulate operations according to the comb structure, where the number of comb teeth is the filter order L / M, and the comb tooth interval is the oversampling rate K. The input signal of the sub-channel is sampled according to the comb tooth interval. The sampled data is multiplied by the corresponding multiplication coefficients in sequence to obtain the corresponding multiplication results. All multiplication results are added together, and finally, a calculation result is output. The number of multiply-accumulate operations is the filter order L / M of the sub-channel. The multiplication coefficients in the multiply-accumulate operation are the filter coefficients of the channelization algorithm in the corresponding working mode, stored in header file format. Finally, each instantiated DSP unit performs pipelined operation, outputting a calculation result per cycle.

[0032] Specifically, the transformation operation and inversion submodule mainly includes a transformation operation unit and a data inversion unit. The transformation operation unit is connected to the instantiated DSP unit and the data inversion unit. First, it receives the intermediate filtering results of M sub-channels output by the instantiated DSP unit in each frame, confirms the working mode of the channelization algorithm to be used, and configures the FPGA hardware specifications of the transformation operation and inversion submodule according to the working mode. According to the configured FPGA hardware specifications, it performs transformation operations on the intermediate filtering results of each sub-channel in each frame according to the corresponding working mode, and finally outputs the transformation operation results of M sub-channels in each frame and transmits them to the data inversion unit. The data inversion unit is connected to an external data processing unit and receives the transformation operation results of M sub-channels per cycle. Based on the FPGA hardware specifications in the corresponding operating mode, it determines whether to enable or disable the data inversion unit: if enabled, the data inversion unit inverts the transformation operation results of the received M sub-channels per cycle, where the number of sub-channels is odd and the transformation operation results for odd-numbered cycles are inverted, while the remaining transformation operation results remain unchanged; if disabled, the received transformation operation results of the received M sub-channels per cycle are directly output without any operation. This enables the calculation of the channelization algorithm in this operating mode and outputs the channelization algorithm calculation results for the M sub-channels per cycle.

[0033] The FPGA hardware specifications for the transformation and inversion submodule configuration include: number of transformation points (equal to the number of sub-channels), conjugate enabled / disabled, normalization enabled / disabled, and inversion enabled / disabled.

[0034] Furthermore, enabling / disabling conjugate determines the corresponding transformation operation in different working modes, i.e., enabling and disabling conjugate correspond to the transformation operations IFFT (Inverse Fast Fourier Transform) and FFT (Fast Fourier Transform); enabling / disabling inversion determines the opening and closing of the data inversion unit.

[0035] Specifically, such as Figure 4As shown, the FPGA hardware specifications and configuration methods for the two operating modes of the transformation operation and inversion submodules are as follows: (1) Multiphase filtering mode: set to conjugate enable, normalization enable and inversion enable; (2) STFT mode: Set to enable conjugate and disable invert. The normalization enable is determined by whether the data calculation overflows. If the data calculation overflows, normalization is enabled; otherwise, normalization is disabled.

[0036] Furthermore, the transformation operation unit uses Radix-22 (base-22) calculation to save computational resources, including first-level bit reversal and log2(M) level butterfly operations, where the butterfly operations have normalized shift functionality. For example... Figure 5 As shown, the butterfly operation has two input ports and two output ports. Each butterfly operation inputs intermediate filtering results from two sub-channels selected according to the radix-22 rule. Assuming the intermediate filtering results A and B are input to the butterfly operation, the first step involves addition and subtraction to obtain two intermediate results: C1 = A + B, C2 = AB. The second step multiplies these two intermediate results by the corresponding rotatable factors of radix-22 to obtain the final two butterfly operation results: D1 = C1 * Wn1, D2 = C2 * Wn2. The rotatable factors in Radix-22 include four special rotatable factor values ​​and other common rotatable factor values. The special rotatable factor values ​​are 1, -1, j, and -j. Complex multiplication calculations for special rotatable factor values ​​can be implemented using adders and hardwired connections to save hardware resources. Complex multiplication calculations for common rotatable factor values ​​are implemented using a hardware architecture of 3 multipliers and 5 adders, requiring three calculation cycles to complete. To synchronize the calculation time of special rotation factor values ​​with that of ordinary rotation factor values, a delay register is used to synchronize the calculation results of complex multiplication. Finally, after a log2(M) level butterfly operation, the butterfly operation results of M sub-channels are output; then, according to the set transformation operation and inversion sub-module FPGA hardware specifications, the transformation operation results of M sub-channels in the corresponding working mode are calculated.

[0037] The following examples illustrate several channelization processing embodiments implemented by the present invention. The parameter settings in the following examples are only for better demonstrating the applicable scenarios of the invention and should not be construed as limiting the present invention: All embodiments shown in this invention specify the type of FPGA hardware platform as Xilinx XCVU3P series FPGA.

[0038] 1) 8-input 16-channel double oversampling polyphase filter channelization mode: The input signal parallelism was set to 8, the filter order to 112, and the number of sub-channels and transform points to 16. A prototype filter coefficient file with 16 channels and 2x decimation was generated, and compilation and high-level language functional testing were completed. The high-level synthesis objectives were set as follows: the timing objective for the filter bank submodule was 320MHz, and the pipeline objective was 1 clock cycle; the timing objective for the transform operation and inversion submodule was 375MHz, and the pipeline objective was 1 clock cycle. The high-level synthesis optimization instructions used in the filter bank submodule were matrix rearrangement, matrix partitioning, constant specification, and loop expansion; the high-level synthesis optimization instructions used in the transform operation and inversion submodule were matrix rearrangement, matrix partitioning, bound storage, constant specification, and loop expansion. Running the high-level synthesis tool refined the high-level language description program with the settings and objectives, generating the corresponding hardware language description program. Co-simulation verification passed, and the channelization algorithm hardware language description program was encapsulated as an IP core. The IP core was imported into the FPGA project, and during use, it was set to conjugate enable, normalization enable, and inversion enable, outputting the channelization algorithm calculation results. After synthesis and placement and routing, the actual operating clock frequencies of the filter bank submodule and the transform operation and inversion submodule reached 321MHz and 393MHz respectively, meeting the design requirements.

[0039] 2) 8-input 64-channel non-oversampling polyphase filtering channelization mode: The input signal parallelism was set to 8, the filter order to 448, and the number of sub-channels and transform points to 64. A prototype filter coefficient file with 64 channels and 1x decimation was generated, and compilation and high-level language functional testing were completed. The high-level synthesis objectives were set as follows: the timing objective for the filter bank submodule was 320MHz, and the pipeline objective was 1 clock cycle; the timing objective for the transform operation and inversion submodule was 375MHz, and the pipeline objective was 4 clock cycles. The high-level synthesis optimization instructions used in the filter bank submodule were matrix rearrangement, matrix partitioning, constant specification, and loop expansion; the high-level synthesis optimization instructions used in the transform operation and inversion submodule were matrix rearrangement, matrix partitioning, bound storage, constant specification, and loop expansion. Running the high-level synthesis tool refined the high-level language description program with the settings and objectives, generating the corresponding hardware language description program. Co-simulation verification passed, and the channelization algorithm hardware language description program was encapsulated as an IP core. The IP core was imported into the FPGA project, and during use, it was set to conjugate enable, normalization enable, and inversion enable, outputting the channelization algorithm calculation results. After synthesis and placement and routing, the actual operating clock frequencies of the filter bank submodule and the transform operation and inversion submodule reached 324MHz and 381MHz respectively, meeting the design requirements.

[0040] 3) 8-input 16-channel low-pass filter STFT mode: The input signal parallelism is set to 8, the filter order to 112, and the number of sub-channels and transform points to 16, generating a 16-channel low-pass filter coefficient file. Compilation and high-level language function testing are then completed. The high-level synthesis objectives are set as follows: the timing objective for the filter bank submodule is 320MHz, and the pipeline objective is 1 clock cycle; the timing objective for the transform operation and inversion submodule is 375MHz, and the pipeline objective is 1 clock cycle. The high-level synthesis optimization instructions used in the filter bank submodule are matrix rearrangement, matrix partitioning, constant specification, and loop expansion; the high-level synthesis optimization instructions used in the transform operation and inversion submodule are matrix rearrangement, matrix partitioning, bound storage, constant specification, and loop expansion. Running the high-level synthesis tool refines the high-level language description program with the settings and objectives, generating the corresponding hardware language description program. Co-simulation verification is successful, and the channelization algorithm hardware language description program is encapsulated as an IP core. The IP core is imported into the FPGA project. During use, conjugation and inversion are disabled, and the low-pass filter STFT calculation results are output. After synthesis and placement and routing, the actual operating clock frequencies of the filter bank submodule and the transform operation and inversion submodule reached 321MHz and 393MHz respectively, meeting the design requirements.

[0041] The data collection, storage, and processing involved in this application strictly comply with current laws and regulations. Specifically, all user-related data to be processed in this solution originates from legal channels, and explicit authorization and consent from the data subjects have been obtained through user agreements or privacy policies during the data collection phase. For cases involving sensitive personal information, separate consent from the users has been further obtained, strictly adhering to the principle of informed consent. In the actual data processing process, if identity-identifying information is involved, this solution employs anonymization or de-identification techniques to ensure that the processed data cannot identify any specific natural person and cannot be restored. The data processing activities do not infringe upon personal privacy rights and comply with the provisions of the "Personal Information Protection Law of the People's Republic of China," the "Cybersecurity Law of the People's Republic of China," and other relevant laws. If this solution involves collecting information in public places, the purpose of collection is limited to maintaining public safety or specific scenarios with explicit user authorization, and does not exceed the necessary limits.

[0042] In summary, the technical solution claimed in this application ensures its legality, compliance, and ethics through technical means throughout the entire chain of data acquisition, data processing, and result output, and there is no situation that violates the law, social morality, or harms the public interest.

[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] In the description of this invention, it should be understood that the terms "center," "height," "thickness," "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0045] In the description of this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0046] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0047] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A method for generating hardware descriptions of channelization algorithms based on high-level synthesis, characterized in that, include: Step S1: In the high-level synthesis tool, write a high-level language description program to generate the channelization algorithm. Configure the FPGA hardware specification parameters, including the number of sub-channels and the number of parallel input signals, in the header file of the high-level language description program to obtain the high-level language description program of the channelization algorithm containing the FPGA hardware specification parameters. The channelization algorithm uniformly divides the signal sampled by the external analog-to-digital converter into multiple parallel sub-channel signals. Each sub-channel signal is subjected to filtering calculations and time-frequency domain transformation operations. Finally, the channelization algorithm calculation results of each sub-channel are output for the external data processing unit to perform subsequent signal processing according to the sub-channel. Step S2: For the received high-level language description program of the channelization algorithm containing FPGA hardware specifications, complete the compilation and functional testing using high-level synthesis tools; Step S3: In the high-level synthesis tool, further refine the hardware settings and objectives of the channelization algorithm: specify the type of FPGA hardware platform for the channelization algorithm, and set the high-level synthesis objectives and high-level synthesis optimization instructions. The high-level integration objectives include: timing objectives, namely the expected operating clock frequency of the channelization algorithm on a specified FPGA hardware platform; and pipeline objectives, namely the clock cycle interval between the execution of the channelization algorithm once and the next execution of the channelization algorithm. Step S4: The high-level synthesis tool automatically converts and generates the corresponding channelization algorithm hardware language description program for the refined hardware settings and target channelization algorithm. Step S5: Compile a joint simulation test file for generating the channelization algorithm, and perform joint simulation verification on the high-level language description program of the channelization algorithm and the corresponding generated hardware language description program to ensure that the execution result of the hardware language description program of the channelization algorithm is consistent with the output result of its high-level language description program. Step S6: Using high-level synthesis tools, the channelization algorithm hardware language description program that has passed the joint simulation verification is encapsulated into a reusable channelization algorithm IP core.

2. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 1, characterized in that, The FPGA hardware specification parameters configured in S1 also include: filter order, oversampling rate, number of transform points, conjugate enabled, conjugate disabled, normalization enabled, normalization disabled, inversion enabled, and inversion disabled.

3. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 2, characterized in that, The high-level comprehensive optimization instructions described in S3 include: matrix rearrangement, matrix partitioning, binding storage, specifying constants, and loop expansion.

4. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 3, characterized in that, The channelization algorithm generated in S1 is implemented through a filter bank submodule and a transform operation and inversion submodule. The filter bank submodule is connected to an external analog-to-digital converter, receives multiple parallel input signals transmitted by the external analog-to-digital converter, stores the multiple parallel input signals and divides them into sub-channels, and performs filtering calculations on the input signals of each sub-channel in combination with filter coefficients, and outputs the intermediate filtering results of multiple sub-channels. The transformation operation and inversion submodule is connected to the filter bank submodule, receives the intermediate filtering results of multiple sub-channels from the filter bank submodule, performs transformation operations and inversion operations on each sub-channel, and finally outputs the calculation results of the channelization algorithm. The FPGA hardware specifications configured for the filter bank submodule include: number of sub-channels, total filter order, number of parallel input signals, and oversampling rate. The FPGA hardware specifications for the transformation and inversion submodules include: number of transformation points, conjugate enabled, conjugate disabled, normalization enabled, normalization disabled, inversion enabled, and inversion disabled.

5. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 4, characterized in that, The channelization algorithm generated in S1 has two operating modes: polyphase filtering channelization mode and STFT mode.

6. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 5, characterized in that, When S1 writes the channelization algorithm for generating the polyphase filter channelization mode, it generates the filter coefficients of the channelization algorithm for the polyphase filter channelization mode and stores them in header file format for the filter bank submodule to call.

7. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 6, characterized in that, When S1 writes the channelization algorithm to generate the multiphase filter channelization mode, the FPGA hardware specifications are set as follows: conjugate enable, normalization enable, and inversion enable.

8. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 5, characterized in that, When S1 writes the channelization algorithm for generating the STFT mode, it generates the filter coefficients of the channelization algorithm for the STFT mode and stores them in header file format for the filter bank submodule to call.

9. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 8, characterized in that, When S1 writes the channelization algorithm to generate the STFT mode, the FPGA hardware specifications are set as follows: conjugate is disabled and inversion is disabled. If data calculation overflows, normalization is enabled; otherwise, normalization is disabled.

10. The method for generating hardware descriptions of channelization algorithms based on high-level synthesis according to claim 4, characterized in that, The channelization algorithm IP core described in S6 is encapsulated in the filter bank submodule and the transform operation and inversion submodule of the channelization algorithm, respectively.

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