Analog integrated circuit performance optimization method based on circuit simulation data

Abstract

The present application belongs to the technical field of analog integrated circuit design automation, and relates to an analog integrated circuit performance optimization method based on circuit simulation data. The present application generates an initial sampling point set by matching historical cases through a graph neural network, extracts parameter sensitivity coefficients and implicit rules into structured constraint conditions by using a large language model, and constructs a Gaussian process prior mean function. The candidate sampling points are selected and iteratively updated by combining the Gaussian process surrogate model and the acquisition function value containing a penalty term. The problems of traditional optimization leading to excessive simulation calls, the limited prediction accuracy caused by the zero-mean prior of the surrogate model, the failure to convert empirical knowledge into computable constraints, and the limited reuse of historical simulation data are solved. The method narrows down the optimization interval, reduces the dependence on simulation data, converges quickly under fewer simulation times, improves the overall efficiency of analog integrated circuit performance optimization, and outputs the optimized circuit parameters.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit design automation technology, and relates to a method for optimizing the performance of analog integrated circuits based on circuit simulation data. Background Technology

[0002] Analog integrated circuits are core circuit modules in fields such as communications, industrial control, and consumer electronics. Optimizing their performance indicators, such as gain, bandwidth, phase margin, and power consumption, depends on precise adjustment of design parameters, and each parameter change must be verified through circuit simulation data. In traditional design, parameter adjustments mainly rely on manual iteration based on engineers' experience, resulting in long iteration cycles and a high correlation between design quality and engineers' experience.

[0003] To improve optimization efficiency, metaheuristic algorithms such as genetic algorithms and particle swarm optimization have been introduced into the parameter search process for analog circuits. However, these methods have limited convergence speed in high-dimensional parameter spaces, require numerous simulation calls, and accumulate significant computational overhead. Furthermore, they typically treat each parameter as an independent variable during the search process, neglecting the interaction effects between parameters.

[0004] To reduce simulation overhead, some studies have introduced statistical surrogate models to approximate direct simulation. However, existing surrogate models often employ zero-mean or constant-mean prior assumptions during construction, making limited use of prior information regarding the direction and extent of parameter influence from design experience. This results in limited prediction accuracy during the initial sampling phase, often requiring substantial circuit simulation data to achieve a usable approximation level. Furthermore, empirical knowledge such as parameter variation trends, component ratios, and numerical ranges recorded in process design documents and design manuals exists primarily as manual experience in current optimization processes and has not yet been systematically transformed into computable constraint expressions. Consequently, the limiting effect of constraint information on the search range of feasible solutions is not fully realized.

[0005] On the other hand, designers have accumulated a large amount of circuit simulation data and corresponding design parameters in completed projects, which contain design experience related to circuit structure. Existing methods usually restart the search process in new circuit scenarios, which limits the reuse of historical simulation data and its associated topology information, and the related characterization and utilization methods are also insufficient, affecting the overall efficiency of analog integrated circuit performance optimization. Summary of the Invention

[0006] In view of this, in order to solve the problems mentioned in the background technology, a method for optimizing the performance of analog integrated circuits based on circuit simulation data is proposed.

[0007] The objective of this invention can be achieved through the following technical solution: a method for optimizing the performance of analog integrated circuits based on circuit simulation data, comprising: S1, parsing and encoding the target circuit netlist into device nodes and connection edges, inputting it into a graph neural network for aggregation and pooling to obtain a topological embedding vector, retrieving historical cases according to similarity, and mapping historical design parameters to a unified variable space according to the mapping relationship to generate an initial set of sampling points.

[0008] S2. Extract parameter sensitivity coefficients and implicit rules from device nodes and connection edges using the large language model, convert them into structured constraints, and map them to a unified variable space. Substitute the parameter sensitivity coefficients as linear coefficients into the initial sampling point set to construct the Gaussian process prior mean function.

[0009] S3. Construct a Gaussian process surrogate model based on the prior mean function of the Gaussian process and the initial sampling point set. Input candidate variable values ​​and output performance prediction mean and uncertainty. Calculate penalty values ​​based on structured constraints to generate acquisition function values ​​with penalty terms and select candidate sampling points.

[0010] S4. Back-map the candidate sampling points to the netlist parameters, perform circuit simulation to obtain simulation performance data, and incorporate them into the updated sampling point set to update the Gaussian process surrogate model. Based on the trace convergence of the posterior covariance function, map and output the optimized circuit parameters.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention outputs the mean and uncertainty of performance prediction by constructing a Gaussian process proxy model, and selects candidate sampling points for iterative updates based on the acquisition function value containing the penalty term. This method avoids the blind optimization in the high-dimensional parameter space and the disturbance operation of treating each parameter as an independent variable in the metaheuristic algorithm, and solves the problem of many simulation calls and significant cumulative computational overhead in the traditional optimization process, thereby achieving rapid convergence with fewer simulations and accurately obtaining the optimized circuit parameters.

[0012] (2) This invention constructs a Gaussian process prior mean function by substituting the parameter sensitivity coefficients extracted from the large language model as linear term coefficients into the initial sampling point set. This method differs from the zero-mean or constant-mean prior assumptions used by existing surrogate models, and solves the problem of limited prediction accuracy caused by the limited use of prior information on the direction and degree of parameter influence in design experience during the initial sampling stage. It effectively reduces the dependence on circuit simulation data and accelerates the surrogate model to reach a usable approximation level.

[0013] (3) This invention extracts implicit rules from device nodes and connecting edges using a large language model, transforms them into structured constraints, and maps them to a unified variable space to calculate penalty values ​​and generate acquisition function values. This method transforms parameter variation trends, device ratios, and numerical ranges in process design documents and design manuals into computable constraint expressions, solving the problem that constraint information does not fully limit the search range of feasible solutions, narrowing the optimization interval, and improving the effectiveness of candidate sampling points.

[0014] (4) This invention obtains the topology embedding vector by parsing and encoding the target circuit netlist into the input graph of device nodes and connection edges using neural network aggregation pooling, and generates an initial sampling point set by retrieving historical case mappings based on similarity. This method changes the conventional operation of restarting the search process under new circuit scenarios, solves the problem of limited reuse of historical simulation data and its associated topology information, enables the rapid location of effective initial design parameters under new topology structures, and thus improves the overall optimization efficiency. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a method for optimizing the performance of analog integrated circuits based on circuit simulation data, as described in this invention.

[0017] Figure 2 This is a comparison diagram of the initial sampling point distribution and optimization trajectory in this invention;

[0018] Figure 3 This is a comparison graph showing the variation of prediction error of the surrogate model in this invention with the number of simulations;

[0019] Figure 4 The graph shows a comparison of the convergence results of the circuit performance index optimization of this invention and traditional optimization methods. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0022] The following description, in conjunction with the accompanying drawings, details a specific scheme for a method to optimize the performance of analog integrated circuits based on circuit simulation data, provided by the present invention.

[0023] Please see Figure 1 As shown, the implementation steps of the present invention include S1 to S4.

[0024] To address the problems in existing analog integrated circuit optimization, such as blind cold-start search of new topologies, limited prediction accuracy due to zero-mean priors of surrogate models, and failure to transform process experience knowledge into computable constraints, this invention uses a collaborative processing method of graph neural networks and large language models to perform circuit netlist parsing and structured processing of experience knowledge, thereby combining design prior information with the optimization process.

[0025] First, a graph neural network is used to extract topological features and match historical cases to generate an initial set of sampling points. A large language model extracts parameter sensitivity coefficients and implicit rules, transforming them into structured constraints. These sensitivity coefficients are then used as linear term coefficients to construct a Gaussian process prior mean function. Based on this, a Gaussian process surrogate model is constructed using this prior mean function and the initial set of sampling points. This model outputs the performance prediction mean and uncertainty. Penalty values ​​are calculated based on the structured constraints to generate a sampling function value containing a penalty term, selecting candidate sampling points. Finally, the candidate sampling points are back-mapped to a netlist to perform circuit simulation and obtain performance data. The sampling point set and surrogate model are updated, and the optimized circuit parameters are output after convergence, determined by the trace of the posterior covariance function. This mechanism avoids blind exploration in high-dimensional space, narrows the search interval for feasible solutions, and reduces the number of circuit simulation calls, thus enabling rapid convergence and output of optimized circuit parameters.

[0026] S1. Parse and encode the target circuit netlist into device nodes and connection edges, input the graph neural network into aggregation pooling to obtain the topological embedding vector, retrieve historical cases according to similarity, and map the historical design parameters to a unified variable space according to the mapping relationship to generate an initial sampling point set.

[0027] The topology of analog circuits determines the parameter coupling relationships between devices, resulting in independent parameter spaces for different circuits. Existing optimization processes often disregard historical design data when facing new topologies, directly using random sampling to construct initial samples. This approach lacks structural prior guidance, easily leading to ineffective exploration in high-dimensional spaces and increasing early simulation overhead. To establish an experience transfer channel across topologies, this step extracts the graph structure features of the target circuit for similarity matching, thereby locating the historical parameter distribution as the starting benchmark for subsequent searches.

[0028] In one specific embodiment, firstly, the target circuit netlist is read. The target circuit netlist is a text file in SPICE format. The first character of each line of text is parsed to identify the device type keyword. The first character is M, which indicates a MOSFET device; the first character is R, which indicates a resistor device; the first character is C, which indicates a capacitor device; and the first character is L, which indicates an inductor device. According to the SPICE syntax rules, the remaining fields of each line are separated by spaces, and the device instance name, the circuit node number connected to the device port, the device parameter name, and the device parameter value are extracted in sequence.

[0029] Then, each device instance is treated as a device node. The circuit node numbers connected to the ports of all device nodes are traversed. When two device nodes share the same circuit node number, a connection edge is established between the two device nodes. All device nodes constitute a device node set, and all connection edges constitute a connection edge set.

[0030] Next, the device type is converted into a type vector using one-hot encoding. The device parameter values ​​are converted into numerical vectors by performing maximum-minimum normalization based on the upper and lower limits of each parameter value recorded in the process design manual. The type vector and the numerical vector are concatenated to form the initial feature vector of the node. The set of connecting edges is encoded into an adjacency matrix. The row index and column index of the adjacency matrix correspond to the serial number of the device node in the set of device nodes, respectively. A matrix element value of 1 indicates that there is a connecting edge between two corresponding device nodes, and a value of 0 indicates that there is no connecting edge.

[0031] Subsequently, a two-layer GraphSAGE neural network is used as an example, with the initial feature vectors of the nodes and the adjacency matrix input into the network for forward propagation. The message passing operation at each layer is as follows: for each device node, the element-wise mean of the current layer feature vectors of all its neighboring nodes is calculated as an aggregate vector. The current layer feature vector of the device node itself is concatenated with the aggregate vector along the feature dimension. This concatenation is then linearly transformed by the weight matrix and processed by the ReLU activation function to obtain the node feature vector output by that layer. The implementer can determine the dimension of the initial feature vector of the node based on the number of device types and the number of parameter types for each type of device in the target circuit, and set the output dimension of each layer's weight matrix accordingly. For example, the output dimension of the first layer can be set to 64, and the output dimension of the second layer to 32. After two layers of message passing, the node embedding vector is output.

[0032] The GraphSAGE neural network employs the following training configuration: mean squared error loss as the loss function, Adam as the optimizer, a learning rate of 0.001, a batch size of 32, and 200 training epochs. The weight matrices of each layer are initialized using Xavier uniform initialization. The neural network is pre-trained on a dataset containing no fewer than 1000 analog circuit examples with different topologies, using predicted circuit performance metrics as supervisory signals.

[0033] Pooling is performed on the arithmetic mean of the node embedding vectors of all device nodes to obtain a topology embedding vector with dimension 32.

[0034] Furthermore, the cosine similarity between the topology embedding vector and each historical topology embedding vector in the historical circuit case library is calculated and sorted in descending order. Historical circuit cases are read from the sorting results, and the historical design parameter names and values ​​of each historical circuit case are read.

[0035] A unified variable space is constructed, which is a standardized parameter space with variables x1 to xn as variable names and each variable taking values ​​from 0 to 1, where n is the total number of device parameter types in the target circuit. The variable names x1 to xn are mapped one by one to the device parameter names in the target circuit netlist obtained by the previous analysis, and a mapping table between the unified variable space and the circuit netlist parameter space is constructed. Historical design parameter names are mapped to variable names x1 to xn according to the same parameter type. According to this mapping relationship, each historical design parameter value is subtracted from the lower limit of the parameter value recorded in the process design manual, and then divided by the difference between the upper and lower limits of the parameter value to obtain the unified variable space variable value with a value range from 0 to 1. All the variable values ​​of each historical circuit case constitute an initial sampling point.

[0036] All initial sampling points are combined into an initial sampling point set. The initial sampling point set is a set of sampling points generated by mapping all historical circuit cases to a unified variable space after topological similarity matching. Each initial sampling point is a set of variable value vectors in the unified variable space, and each initial sampling point carries the historical simulation performance data of the corresponding historical circuit case, which serves as the initial training data for subsequently constructing the Gaussian process surrogate model.

[0037] For example, please refer to Figure 2 As shown in the figure, the normalized channel width W and channel length L of the MOSFET device are used as the horizontal and vertical coordinates to illustrate the spatial distribution of the initial sampling points and the optimization trajectory. The circular markers represent the initial sampling points generated by the traditional random sampling method, uniformly distributed throughout the variable space [0, 1] × [0, 1]. The triangular markers represent the initial sampling points generated by the present invention through historical case retrieval and mapping using a graph neural network, clustered in the upper right corner region where the optimal solution is located. The star markers represent the location of the optimal solution. The dashed lines represent the optimization trajectory of the traditional method, starting from the dispersed initial points in the lower left corner, gradually approaching the optimal solution in the upper right corner through multiple directional adjustments and iterations; the path is long and involves many turns. The solid lines represent the optimization trajectory of the present invention, starting from the initial points clustered near the optimal solution, reaching the optimal solution with only a few iterations; the path is short and involves fewer turns.

[0038] S2. Extract parameter sensitivity coefficients and implicit rules from device nodes and connection edges using the large language model, convert them into structured constraints, and map them to a unified variable space. Substitute the parameter sensitivity coefficients as linear coefficients into the initial sampling point set to construct the Gaussian process prior mean function.

[0039] Conventional Gaussian process models often employ zero-mean priors, resulting in initial prediction surfaces lacking physical trend guidance. Approximating the true response requires a large number of simulation samples. Furthermore, the parameter variation trends and proportional constraints recorded in process documentation are mostly unstructured text, making them difficult to translate into mathematical boundaries that can be executed by the algorithm. Therefore, this step utilizes a large language model to analyze the circuit topology to extract parameter sensitivity coefficients and implicit rules, transforming them into structured constraints. The sensitivity coefficients are then embedded into the prior mean function, providing the surrogate model with an initial prediction benchmark that conforms to physical laws.

[0040] In one specific embodiment, firstly, the device type of each device node in the device node set, the device node number pairs connected by each connection edge in the connection edge set, and all device parameter names are arranged in a structured text format and concatenated into a text prompt. This text prompt instructs the large language model to output a description of the influence trend of each device parameter on the circuit performance index in a format containing keywords such as "positive correlation", "negative correlation", "high sensitivity", and "low sensitivity" based on circuit design knowledge; to output a description of the numerical range of each device parameter in a format of "parameter name value range is from the lower bound value to the upper bound value"; and to output a description of the relationship between devices in a format of "parameter name 1 is a proportional coefficient multiple of parameter name 2" and "parameter name 1 is equal to parameter name 2".

[0041] For example, this embodiment uses DeepSeek-V3.2 as the large language model. Implementers can choose other publicly available large language models to replace it based on actual deployment conditions and inference cost requirements.

[0042] Then, the system receives the natural language text output by the large language model and uses regular expressions to match sentences containing keywords such as "positive correlation," "negative correlation," "high sensitivity," and "low sensitivity" as text segments influencing trends. Sentences containing numerical values ​​and unit symbols, or containing the multiple relation word "times" and the equality relation word "equal," are matched as text segments representing numerical ranges.

[0043] Next, the text fragments influencing the trend are analyzed. For each device parameter, the relationship between it and the circuit performance index is determined. If the text description is positively correlated, it is mapped to +1; if the text description is negatively correlated, it is mapped to -1. The sensitivity in the text description is determined. If it contains high sensitivity, it is mapped to 1.0; if it contains low sensitivity, it is mapped to 0.5. Here, 1.0 indicates that the parameter has a complete influence on the performance index, and 0.5 indicates that the parameter has a half influence on the performance index. The correlation direction value is multiplied by the sensitivity value to generate a parameter sensitivity coefficient. All parameter sensitivity coefficients are arranged by device parameter name to generate a parameter sensitivity list. The parameter sensitivity list is a one-dimensional list indexed by device parameter name and containing parameter sensitivity coefficients as elements, representing a quantitative representation of the direction and degree of influence of each device parameter on the circuit performance index.

[0044] Subsequently, the text fragments containing numerical ranges are parsed. When the text fragment contains descriptions like "parameter name takes values ​​from the lower bound to the upper bound," such as "W takes values ​​from 1μm to 100μm," regular expressions are used to match the numerical values ​​and dimensions. The first matched value is taken as the minimum boundary value, and the last matched value is taken as the maximum boundary value, serving as the lower and upper bounds of the parameter's value range, respectively. This constructs an inequality constraint of the form "parameter name ≥ lower bound value and parameter name ≤ upper bound value," i.e., "W ≥ 1μm and W ≤ 100μm." When the text fragment contains descriptions like "parameter name 1 is a proportionality coefficient,"... When describing "parameter name 2", such as "W is 10 times L", the parameter name and proportional coefficient are extracted to construct a mathematical expression "W=10L" containing an equal sign as an equality constraint. When the text fragment contains a description of the form "parameter name 1 is equal to parameter name 2", such as "W is equal to L", the parameter name is extracted to construct a mathematical expression "W=L" containing an equal sign as an equality constraint. Inequality constraints and equality constraints are used as implicit rules. The implicit rules are a set of mathematical expressions composed of inequality constraints and equality constraints, which represent the computable constraint expression of the boundary of device parameter values ​​and the proportional relationship between devices.

[0045] The parameter sensitivity list and implicit rules are combined into structured constraints. The device parameter names in the constraints are replaced with variable names x1 to xn in the unified variable space according to the parameter type correspondence. The boundary values ​​in the inequality constraints are normalized to the range of 0 to 1 according to the lower and upper limits of the parameter values ​​in the process design manual. The proportional relationships between parameters in the equality constraints are converted into linear equality constraints between variables in the unified variable space according to the upper and lower limits of each parameter value.

[0046] Based on this, since the parameter sensitivity coefficients characterize the direction and degree of influence of each variable on the circuit performance indicators, variables x1 to xn in the unified variable space are used as independent variables, and the parameter sensitivity coefficients in the parameter sensitivity list are used as the coefficients of the first-order terms of their respective variables to construct a linear function of the first-order terms: ,in Let i be the sensitivity coefficient of the i-th parameter in the parameter sensitivity list. Let i be the i-th variable in the unified variable space.

[0047] Substituting the variable value of each initial sampling point in the initial sampling point set into a linear function, calculating the product of each independent variable and its corresponding linear coefficient, and summing the products, we obtain the prior mean of each initial sampling point. The mapping relationship between the independent variable, the linear coefficient, and the prior mean constitutes the Gaussian process prior mean function with embedded parameter sensitivity: .

[0048] For example, please refer to Figure 3 As shown in the figure, the horizontal axis represents the number of circuit simulation calls, and the vertical axis represents the root mean square error of the surrogate model's prediction. The dashed line represents the prediction error descent curve of the traditional surrogate model using the zero-mean prior assumption; the error decreases slowly with a small number of simulations, requiring a significant accumulation of simulation data before gradually decreasing. The solid line represents the prediction error descent curve of the surrogate model using the embedded parameter sensitivity coefficients to construct the prior mean function according to this invention. Because the prior mean function incorporates prior information about the direction and degree of parameter influence, it exhibits a lower prediction error initially, and then rapidly approaches stability with increasing simulation data. With the same number of simulations, the prediction error of the method described in this invention is lower than that of the traditional method, and the number of circuit simulations required to reach a usable approximation level is approximately one-third that of the traditional method.

[0049] S3. Construct a Gaussian process surrogate model based on the prior mean function of the Gaussian process and the initial sampling point set. Input candidate variable values ​​and output performance prediction mean and uncertainty. Calculate penalty values ​​based on structured constraints to generate acquisition function values ​​with penalty terms and select candidate sampling points.

[0050] The time taken for a single call to an analog circuit simulator ranges from seconds to minutes. During optimization, repeated executions are required to evaluate the performance response under different parameter combinations. This computational overhead accumulates with the number of iterations, becoming a major bottleneck limiting efficiency. If simulation results are used as the sole basis for parameter selection, sampling efficiency is limited by simulation throughput, making it difficult to cover key regions in high-dimensional space within a limited number of iterations. Furthermore, determining the feasible region boundary defined by structured constraints only after simulation consumes additional simulation resources. Therefore, this step constructs a Gaussian process surrogate model to output the predicted mean and uncertainty, and generates a sampling function value with a penalty term based on the structured constraints to select candidate sampling points.

[0051] In one specific embodiment, firstly, the historical simulation performance data carried by each initial sampling point in the initial sampling point set is obtained, and the variable value vector of each initial sampling point is... Corresponding historical simulation performance data The training data is composed of the simulated output values ​​of a single performance index of the circuit. ,in, , This represents the total number of sampling points in the initial set of sampling points.

[0052] Then, the radial basis function value between two sampling points in the initial sampling point set is calculated, as shown below: .

[0053] in, For signal variance, The length scale is determined by maximizing the log-marginal likelihood function based on the training data, and all pairwise kernel function values ​​are arranged into an m×m covariance matrix. .

[0054] training data, covariance matrix and the prior mean function of Gaussian process Input a Gaussian process regression model and calculate the posterior mean function equation, as shown below: .

[0055] The posterior covariance function equation is shown below: .

[0056] in, The candidate variable values ​​to be predicted, This is a vector of kernel function values ​​between candidate variable values ​​and all training data. To simulate noise variance, tolerance settings are determined based on numerical solutions obtained from the circuit simulator. The posterior mean function equation and the posterior covariance function equation are combined as a Gaussian process surrogate model.

[0057] Subsequently, 500 candidate variable values ​​were generated in the unified variable space using the Latin hypercube sampling method. The number 500 was determined based on engineering experience that ensures sufficient sampling levels for each dimension when the typical dimensions of the unified variable space are 3 to 5. The performance prediction mean was calculated by inputting each candidate variable value into the posterior mean function equation. The diagonal elements of each candidate variable value were extracted as the posterior variance, and the square root of the variance was taken as the uncertainty.

[0058] Substituting candidate variable values ​​into the inequality constraints in the structured constraints, if the candidate variable value falls between the lower and upper bounds, the violation degree of the inequality constraint is zero; if the candidate variable value is less than the lower bound, the violation degree is the difference between the lower bound value and the candidate variable value; if the candidate variable value is greater than the upper bound, the violation degree is the difference between the candidate variable value and the upper bound value. Substituting candidate variable values ​​into the equality constraints, if both sides of the equation are equal, the violation degree is zero; if they are unequal, the violation degree is the absolute value of the difference between the two sides of the equation. Summing the violation degrees of all inequality constraints and equality constraints and multiplying by a weight coefficient of 1.0, the weight coefficient 1.0 is determined based on the balance requirement that the penalty term and the expected value of the exploration remain at the same order of magnitude, to obtain the penalty value.

[0059] The desired improvement in the acquisition function is constructed as shown in the following formula: .

[0060] in, This represents the optimal value of the simulation performance data within the current set of sampling points. Given the standard normal probability density function, the performance prediction mean is... minus The improvement increment is obtained, and the improvement increment is combined with the uncertainty. Calculate the expected value of exploration .

[0061] The difference between the expected value and the penalty value is calculated as the acquisition function value including the penalty term. All 500 candidate variable values ​​are traversed, and the candidate variable value with the largest acquisition function value including the penalty term is selected as the candidate sampling point. The candidate sampling point is the variable vector corresponding to the candidate variable value with the largest acquisition function value including the penalty term in a unified variable space, which is used for subsequent inverse mapping to the circuit netlist parameter space to perform circuit simulation.

[0062] S4. Back-map the candidate sampling points to the netlist parameters, perform circuit simulation to obtain simulation performance data, and incorporate them into the updated sampling point set to update the Gaussian process surrogate model. Based on the trace convergence of the posterior covariance function, map and output the optimized circuit parameters.

[0063] Candidate sampling points are generated by the surrogate model's predictions, and their actual performance needs to be verified through circuit simulation. The surrogate model is built based on a finite initial sample set, and the prediction bias increases with distance from known data points. Without continuous correction through simulation feedback, the accumulated error in subsequent iterations will cause the optimization direction to deviate. If the iteration termination condition directly relies on a preset number of steps, it cannot guarantee convergence and wastes resources; therefore, the model's own stability should be used as the stopping criterion. Thus, this step performs iterative updates, incorporates simulation results into the training set to reconstruct the surrogate model, and terminates the iteration after convergence based on the change in the posterior covariance function trace, mapping the optimized circuit parameters to the output.

[0064] In one specific embodiment, firstly, the mapping table between the unified variable space and the circuit netlist parameter space constructed in S1 is read, and the mapping table is used to find the value of each variable in the candidate sampling point. The corresponding circuit netlist parameter name is based on the lower limit of the parameter value in the process design manual. and upper limit , the variable values ​​in the candidate sampling points according to The inverse mapping is performed to the actual parameter values ​​in the circuit netlist parameter space. The original values ​​of the corresponding parameter names in the target circuit netlist are replaced with the inversely mapped actual parameter values ​​to generate an updated circuit netlist.

[0065] Then, the circuit simulator is invoked to run the updated circuit netlist and read the simulation performance data output by the circuit simulator. The candidate sampling points and simulation performance data are used as new samples and incorporated into the initial sampling point set to form the updated sampling point set. At this time, the total number of sampling points in the updated sampling point set is updated from m to m+1.

[0066] Subsequently, the radial basis function values ​​between the two sampling points are recalculated using the updated sampling point set to construct the updated covariance matrix. The updated covariance matrix, the training data of the updated sampling point set, and the Gaussian process prior mean function are then re-input into the Gaussian process regression model to calculate the updated posterior mean function equation and posterior covariance function equation, thus overriding the original Gaussian process surrogate model and completing the model update.

[0067] Based on this, since the trace of the posterior covariance function represents the overall prediction uncertainty of the surrogate model for the updated sample point set, when the uncertainty changes gradually, it indicates that the model has converged. Therefore, the sum of the diagonal elements of the updated posterior covariance function equation at all m+1 sample points on the updated sample point set is calculated to obtain the trace of the current posterior covariance function.

[0068] The iteration stops when the trace of the current posterior covariance function is less than the trace calculated in the previous iteration, and the absolute value of the difference between the trace of the current posterior covariance function and the trace calculated in the previous iteration is less than the absolute value of the difference calculated in the adjacent previous iteration. This criterion indicates that the trace continues to decrease and the rate of decrease has narrowed, and the change in the prediction uncertainty of the surrogate model tends to converge. When the number of iterations is less than three, the stopping condition is not met because the trace difference between two adjacent iterations cannot be obtained yet. The iteration continues to return to S3 to reselect candidate sampling points based on the updated Gaussian process surrogate model and execute the next simulation and model update.

[0069] Read and sort all simulation performance data in the updated sampling point set, extract the variable value of the sampling point corresponding to the first simulation performance data, use the mapping table to find the circuit netlist parameter name corresponding to the variable value, and output it as the optimized circuit parameter.

[0070] For example, please refer to Figure 4 As shown in the figure, the horizontal axis represents the number of circuit simulation calls, and the vertical axis represents the circuit performance index value. The dashed line represents the optimization convergence curve of the traditional metaheuristic algorithm. Due to the use of random sampling to construct initial samples and the lack of constraint guidance, the starting point is low and the rise is gradual, requiring many simulations before the performance index stabilizes. The solid line represents the optimization convergence curve of the method of this invention. Because it generates initial sampling points clustered in excellent regions by matching historical cases through graph neural networks and narrows the search range of feasible solutions through structured constraints, the starting point is high and the convergence is fast, requiring only a few simulations to achieve high performance index and stabilize. To achieve the same target performance index, the number of simulation calls required by this invention is approximately half that of the traditional method, and the final converged circuit performance index is superior to that of the traditional method.

[0071] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0072] Those skilled in the art will recognize that the algorithmic steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0073] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0074] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0075] Finally, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for optimizing the performance of analog integrated circuits based on circuit simulation data, characterized in that, include: S1. Parse and encode the target circuit netlist into device nodes and connection edges, input the graph neural network into aggregation pooling to obtain the topology embedding vector, retrieve historical cases according to similarity, and map the historical design parameters to a unified variable space according to the mapping relationship to generate an initial sampling point set; S2. Extract parameter sensitivity coefficients and implicit rules from device nodes and connecting edges using a large language model, convert them into structured constraints, and map them to a unified variable space; substitute the parameter sensitivity coefficients as linear term coefficients into the initial sampling point set to construct the Gaussian process prior mean function; S3. Construct a Gaussian process surrogate model based on the prior mean function of the Gaussian process and the initial sampling point set, and output the performance prediction mean and uncertainty by inputting candidate variable values. Based on the structured constraints, the penalty value is calculated to generate the acquisition function value containing the penalty term, and candidate sampling points are selected. S4. Back-map the candidate sampling points to the netlist parameters, perform circuit simulation to obtain simulation performance data, and incorporate them into the updated sampling point set to update the Gaussian process surrogate model. Based on the trace convergence of the posterior covariance function, map and output the optimized circuit parameters.

2. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 1, characterized in that, The acquisition of the topological embedding vector includes: Read the target circuit netlist to identify device types, device port connections, device parameter names, and device parameter values; Each device is treated as a device node, and the device port connection relationships are treated as connection edges, generating a set of device nodes and a set of connection edges; The device type and device parameter values ​​are encoded into node initial feature vectors, and the set of connecting edges is encoded into an adjacency matrix; The initial feature vector of a node and its adjacency matrix are input into a graph neural network. The features of neighboring nodes are aggregated through a message passing layer to update the node embedding vector. Pooling is performed on the node embedding vectors of all device nodes to obtain the topology embedding vector.

3. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 1, characterized in that, The acquisition of the initial sampling point set includes: Calculate the cosine similarity between the topology embedding vector and each historical topology embedding vector in the historical circuit case library, sort them in descending order, and read the historical circuit cases in the sorting results; Read the historical design parameter names and values ​​for each historical circuit case. Based on the mapping relationship between variable names in the unified variable space and historical design parameter names, the historical design parameter values ​​are mapped to variable values ​​in the unified variable space to obtain the initial sampling points; All initial sampling points are combined into an initial sampling point set.

4. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 1, characterized in that, The acquisition of the structured constraints includes: Format the device node set, connection edge set, and device parameter name as text prompts and input them into the large language model; Receive natural language text output from a large language model, use regular expressions to extract text fragments describing the influence trends and numerical ranges of device parameters, and generate a parameter sensitivity list and implicit rules; The parameter sensitivity list and implicit rules are combined into structured constraints, and the device parameter names in them are replaced with variable names in a unified variable space.

5. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 4, characterized in that, The acquisition of the parameter sensitivity list and implicit rules includes: The algorithm analyzes text fragments that influence trends, identifies text descriptions that show a positive or negative correlation between parameters and circuit performance indicators, maps positive correlation to +1 and negative correlation to -1; identifies text descriptions containing high or low sensitivity, maps high sensitivity to a first value and low sensitivity to a second value; multiplies the +1 or -1 with the first or second value to generate a parameter sensitivity coefficient, and arranges all parameter sensitivity coefficients by device parameter name to generate a parameter sensitivity list. Parse the text fragments of numerical ranges, extract the minimum and maximum boundary values ​​of device parameters, and convert the minimum and maximum boundary values ​​into inequality constraints containing greater than or equal to and less than or equal to signs; extract the text descriptions of the multiple or equality relationships between device parameters, convert the multiple or equality relationships into mathematical expressions containing equal signs as equality constraints, and use the inequality constraints and equality constraints as implicit rules.

6. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 4, characterized in that, The construction of the prior mean function of the Gaussian process includes: Using variables in the unified variable space as independent variables and parameter sensitivity coefficients in the parameter sensitivity list as coefficients of the first-order terms of the independent variables, a linear function of the first-order terms is constructed. Substitute the variable value of each initial sampling point in the initial sampling point set into a linear function of the first term, calculate the product of each term and sum them to obtain the prior mean of each initial sampling point. The mapping relationship between the independent variable, the coefficient of the first term and the prior mean constitutes the Gaussian process prior mean function with embedded parameter sensitivity.

7. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 1, characterized in that, The acquisition of the performance prediction mean and uncertainty includes: Obtain historical circuit simulation performance data corresponding to the initial sampling point set, and combine it with variable values ​​to form training data; Calculate the radial basis kernel function values ​​between two sampling points in the initial sampling point set to construct the covariance matrix; The training data, covariance matrix, and Gaussian process prior mean function are input into the Gaussian process regression model, and the posterior mean function equation and posterior covariance function equation are output. The two are combined as the Gaussian process surrogate model. A set of candidate variable values ​​is generated in a unified variable space. The candidate variable values ​​are input into the posterior mean function equation to calculate the performance prediction mean. The candidate variable values ​​are input into the posterior covariance function equation to extract the variance term corresponding to the candidate variable value itself. The square root of the variance term is used as the uncertainty.

8. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 1, characterized in that, The selection of candidate sampling points includes: Substitute the candidate variable values ​​into the structured constraints. If the inequality and equality constraints are satisfied, the penalty value is zero. Otherwise, calculate the difference between the excess or non-satisfied parts as the degree of violation, and multiply it by the weight coefficient to obtain the penalty value. Construct an expected improvement acquisition function, input the performance prediction mean and the optimal value of the simulation performance data in the current sampling point set into the expected improvement acquisition function to calculate the improvement increment, and combine the improvement increment with uncertainty to calculate the expected value; The difference between the expected value and the penalty value is calculated as the acquisition function value including the penalty term; Traverse the set of candidate variable values ​​and select the candidate variable value with the largest value of the sampling function containing the penalty term as the candidate sampling point.

9. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 1, characterized in that, The updated Gaussian process proxy model specifically includes: Read the mapping table between the unified variable space and the circuit netlist parameter space, use the mapping table to find the circuit netlist parameter name corresponding to the variable value in the candidate sampling point, reverse map the variable value in the candidate sampling point to the actual parameter value in the circuit netlist parameter space, replace the original value of the corresponding parameter name in the target circuit netlist with the actual parameter value, and generate the updated circuit netlist. Call the circuit simulator to run the updated circuit netlist and read the simulation performance data output by the circuit simulator; The candidate sampling points and simulation performance data are incorporated as new samples into the initial sampling point set to form an updated sampling point set. The radial basis function, posterior mean function equation, and posterior covariance function equation are recalculated using the updated sample point set, thus covering the original Gaussian process surrogate model and completing the model update.

10. The method for optimizing the performance of analog integrated circuits based on circuit simulation data as described in claim 9, characterized in that, The acquisition of the optimized circuit parameters includes: The trace of the current posterior covariance function is obtained by summing the diagonal elements of the updated posterior covariance function equation over the updated sample point set. The iteration stops when the trace of the current posterior covariance function is less than the trace calculated in the previous iteration, and the absolute value of the difference between the trace of the current posterior covariance function and the trace calculated in the previous iteration is less than the absolute value of the difference calculated in the adjacent previous iteration. Read and sort all simulation performance data in the updated sampling point set, and extract the variable value of the sampling point corresponding to the first and first simulation performance data. Use the mapping table to find the circuit netlist parameter name corresponding to the variable value, and output it as the optimized circuit parameter.

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