Address configuration method and server system

Abstract

The present invention provides an address configuration method, which is suitable for a server system. The server system includes a mainboard and a backplane. The mainboard includes a control circuit. The backplane includes a logic circuit, a shift register and a plurality of devices. The address configuration method includes: (a) the control circuit reads internal data stored in the logic circuit to learn the number of the plurality of devices included in the backplane; (b) the control circuit provides a corresponding number of device addresses to the logic circuit according to the number of the plurality of devices included in the backplane; (c) the logic circuit transmits a first signal to the shift register according to the plurality of device addresses; (d) the shift register transmits a plurality of second signals to the plurality of devices according to the first signal; and (e) each device sets its own address according to its corresponding second signal.

Description

Technical Field

[0001] This case concerns address configuration technology, and in particular an address configuration method applicable to server systems. Background Technology

[0002] In server systems, a motherboard typically consists of several backplanes. These backplanes house multiple devices and connect to a Baseboard Management Controller (BMC). Because backplanes can connect to the motherboard in different combinations, multiple backplanes with the same design may exist in the system. This requires design engineers to carefully consider the SMBus state after system connection to avoid address conflicts between devices on different backplanes. Traditionally, device addresses are set via voltage values ​​on the address pins of the device's IC, usually fixed during PCB design using resistor connections. Subsequent modifications require cumbersome desoldering and resoldering, resulting in insufficient flexibility. Furthermore, when system users install backplanes not considered in the initial design, it can also lead to address conflicts between devices on different backplanes, further limiting backplane portability and system scalability.

[0003] To resolve the address conflicts between devices on different backplanes, prior art primarily employed two methods: one was to add I2C multiplexers to divide the SMBus into multiple sub-SMBus. For details, please refer to [link to relevant documentation]. Figure 1 , Figure 1 The server system 1 includes a motherboard 10 and multiple backplanes 20, each backplane 20 containing multiple devices 22. Each backplane 20 is connected to the motherboard 10 via a connector 30. The motherboard 10 includes an I2C multiplexer 13. The motherboard 10 switches the I2C multiplexer 13 so that it connects to only one backplane 20 during server system 1 operation, thus isolating the backplanes 20 during operation and avoiding address conflicts between devices 22 on different backplanes 20. Alternatively, the Address Resolution Protocol (ARP) in the SMBus specification can be used to dynamically allocate I2C addresses to ARP-enabled devices. However, currently, only a minority of devices support ARP, and the above method still has many limitations and inconveniences in practical applications. Therefore, most devices on the backplane still rely on address pin voltage values ​​to set their addresses. Summary of the Invention

[0004] To address the aforementioned problems, this invention provides an address configuration method applicable to a server system. The server system includes a motherboard and a backplane. The motherboard is connected to the backplane via a connector. The motherboard includes control circuitry. The backplane includes logic circuitry, a shift register, and multiple devices. The shift register is coupled to the logic circuitry and the multiple devices. The address configuration method includes: (a) the control circuitry reading internal data stored in the logic circuitry to determine the number of devices included in the backplane; (b) the control circuitry providing a corresponding number of device addresses to the logic circuitry based on the number of devices included in the backplane; (c) the logic circuitry transmitting a first signal to the shift register based on the multiple device addresses; (d) the shift register transmitting multiple second signals to the multiple devices based on the first signal, each second signal corresponding to a specific device; and (e) each device setting its own address based on its corresponding second signal.

[0005] Preferably, the address configuration method further includes: (f) the control circuit provides a logic circuit address to the logic circuit; and (g) the logic circuit sets its own address based on the logic circuit address.

[0006] Preferably, the backplane further includes a switching circuit. The switching circuit is coupled to the connector, logic circuit, and multiple devices. The switching circuit is used to disconnect the multiple devices from the motherboard before step e. After step e, the address configuration method further includes: (h) the logic circuit providing an enable signal to the switching circuit; and (i) the switching circuit turning on the multiple devices and the motherboard according to the enable signal.

[0007] Preferably, the logic circuit supports ARP. In step f, the control circuit provides the logic circuit address to the logic circuit via ARP.

[0008] Preferably, the first signal is a serial signal. The second signal is a parallel signal.

[0009] Preferably, the shift register includes an input pin and multiple output pins. The input pin is coupled to a logic circuit, and the multiple output pins are coupled to multiple devices. The shift register is used to receive a first signal through the input pin. The shift register is used to control the voltage level of the multiple output pins according to the first signal, so as to transmit multiple second signals to the multiple devices.

[0010] In some embodiments, a server system includes a backplane and a motherboard. The backplane includes logic circuitry, multiple devices, and a shift register. The logic circuitry stores internal data. The shift register is coupled to the logic circuitry and the multiple devices. The motherboard is connected to the backplane via a connector. The motherboard includes control circuitry. The control circuitry is configured to: read the internal data to determine the number of control circuitry devices included in the backplane; and provide a corresponding number of device addresses to the logic circuitry based on the number of control circuitry devices included in the backplane. The logic circuitry transmits a first signal to the shift register based on the multiple device addresses. The shift register transmits multiple second signals to the multiple devices based on the first signal, each second signal corresponding to a specific device. Each device sets its own address based on its corresponding second signal.

[0011] Preferably, the control circuit is further configured to provide a logic circuit address to the logic circuit, and the logic circuit is further configured to set its own address according to the logic circuit address.

[0012] Preferably, the backplane further includes a switching circuit coupled to the connector, the logic circuit, and the plurality of devices. The switching circuit is used to disconnect the plurality of devices from the motherboard before each device sets its address according to its corresponding second signal. After each device sets its address according to its corresponding second signal, the logic circuit is further used to provide a consistent enable signal to the switching circuit, and the switching circuit is further used to connect the plurality of devices to the motherboard according to the enable signal.

[0013] Preferably, the first signal is a series signal and the second signal is a parallel signal.

[0014] Preferably, the shift register includes: an input pin coupled to the logic circuit, the shift register being used to receive the first signal through the input pin; and a plurality of output pins coupled to a plurality of the devices, the shift register being used to control the voltage level of the plurality of output pins according to the first signal, so as to transmit a plurality of second signals to the plurality of the devices.

[0015] The following detailed description of the features and advantages of this invention is sufficient to enable anyone skilled in the art to understand the technical content of this invention and implement it accordingly. Furthermore, based on the content disclosed in this specification, the scope of the patent application, and the drawings, anyone skilled in the art can easily understand the relevant purpose and advantages of this invention. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a server system based on prior art.

[0017] Figure 2This is a schematic diagram of one embodiment of a server system;

[0018] Figure 3 A flowchart of one embodiment of an address configuration method;

[0019] Figure 4 This is a schematic diagram of one embodiment of a connector and a backplane. Detailed Implementation

[0020] Figure 2 This is a schematic diagram of one embodiment of server system 2. Please refer to [link / reference]. Figure 2 Server system 2 includes a motherboard 10 and a backplane 40. In some embodiments, there may be multiple backplanes 40. The motherboard 10 is connected to each backplane 40 via connectors 30. The motherboard 10 includes control circuitry 11. Each backplane 40 includes logic circuitry 21, devices 22, and shift registers 41. Shift registers 41 are coupled to the logic circuitry 21 and the devices 22. In some embodiments, each backplane 40 may include multiple devices 22.

[0021] In some embodiments, the control circuit 11 may be, but is not limited to, a programmable controller such as a Baseboard Management Controller (BMC), a Microcontroller Unit (MCU), or a Field-Programmable Gate Array (FPGA).

[0022] In some embodiments, connector 30 may be, but is not limited to, multichannel I / O connector (MCIO), serial Attached SCSI connector (SAS), RAID Card, serial Advanced Technology Attachment connector (SATA), small computer system interface connector (SCSI), PCIe connector, M.2 connector, and other types of connectors suitable for server systems or electronic devices.

[0023] In some embodiments, the backplane 40 may be, but is not limited to, a hot-swap backplane (HSBP). That is, in some embodiments, each backplane 40 establishes or disconnects its connection with each connector 30 in a hot-swap manner, but this invention is not limited thereto. In some embodiments, depending on design requirements, the backplane 40 may also be connected in a non-hot-swap manner, for example, after the server system 2 is shut down or powered off, the backplane 40 may be replaced or removed and reconnected to the connector 30 after restarting.

[0024] In some embodiments, the logic circuit 21 may be, but is not limited to, combinational logic circuits, sequential logic circuits, programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), application-specific integrated circuits (ASICs), and other logic circuits suitable for server systems or electronic devices.

[0025] In some embodiments, the server system 2 includes a plurality of connectors 30 in a number greater than or equal to the plurality of backplanes 40. For example, see [link to relevant documentation]. Figure 2 . Figure 2 The server system 2 shown includes a plurality of connectors 30, corresponding to a plurality of backplanes 40, both of which are two. Figure 2 In the original document, server system 2 includes two connectors 30 and two backplanes 40, but this is not a limitation. The number of connectors 30 and backplanes 40 included in server system 2 can be any positive integer.

[0026] At Figure 2 In this embodiment, each backplate 40 includes three devices 22 (i.e., device 221, device 222, and device 223), but this is not a limitation. The number of devices 22 included in each backplate 40 can be zero or any positive integer. That is, in some embodiments, the backplate 40 does not include any device 22, includes more than one device 22, or includes only one device 22.

[0027] In some embodiments, the motherboard 10 and the backplane 40 may be interconnected via, but not limited to, a System Management Bus (SMBus). Specifically, in some embodiments, the motherboard 10 is interconnected with the connector 30, the connector 30 with the logic circuit 21, and the connector 30 with multiple devices 22 via SMBus, but this is not a limitation of the present invention. In some embodiments, the motherboard 10 and the backplane 40 may also be interconnected via a Serial Peripheral Device Bus (SPI), a high-speed data transmission line, a PCIe bus, an I2C bus, a SATA cable, a SAS cable, a Multichannel I / O connection line (MCIO), a disk array card connection line, and other transmission lines or buses suitable for server systems or electronic devices.

[0028] In some embodiments, logic circuit 21 stores internal data. In some embodiments, the internal data includes the number of multiple devices 22 included in the backplane 40 where logic circuit 21 is located. In some embodiments, the internal data further includes the version of the backplane 40 where logic circuit 21 is located.

[0029] Figure 3 A flowchart illustrating one embodiment of an address configuration method. Please refer to... Figure 2 and Figure 3First, the control circuit 11 reads the internal data stored in the logic circuit 21 to determine the number of multiple devices 22 included in the backplane 40 (step S01). Next, the control circuit 11 provides the logic circuit 21 with a corresponding number of device addresses based on the number of multiple devices 22 included in the backplane 40 (step S02).

[0030] In some embodiments, before step S02, the control circuit 11 provides a logic circuit address to the logic circuit 21, and the logic circuit 21 sets its own address based on this logic circuit address after receiving it. In some embodiments, the motherboard 10 further includes a plurality of motherboard devices 12. In some embodiments, the number of the plurality of motherboard devices 12 may be zero or any positive integer. That is, in some embodiments, the motherboard 10 may not contain any motherboard devices 12, may contain more than one motherboard device 12, or may contain only one motherboard device 12. Each motherboard device 12 has its corresponding motherboard address. In some embodiments, in step S02, the control circuit 11 provides a device address different from the logic circuit address and the corresponding motherboard addresses of the plurality of motherboard devices 12 to the logic circuit 21 based on the logic circuit address and the corresponding motherboard addresses of the plurality of motherboard devices 12, in order to avoid conflicts between the addresses of the plurality of devices 22 and the addresses of the plurality of motherboard devices 12 and the logic circuit 21.

[0031] Next, logic circuit 21 transmits a first signal S1 to shift register 41 according to the addresses of multiple devices (step S03). Then, shift register 41 transmits multiple second signals S2 to multiple devices 22 according to the first signal S1 (step S04), each second signal S2 corresponding to a specific device 22. Figure 2 For example, the second signal S21 corresponds to device 221, the second signal S22 corresponds to device 222, and the second signal S23 corresponds to device 223.

[0032] Finally, each device 22 sets its own address according to its corresponding second signal S2 (step S05). Figure 2 For example, device 221 sets its own address according to the second signal S21, device 222 sets its own address according to the second signal S22, and device 223 sets its own address according to the second signal S23.

[0033] In some embodiments, the first signal S1 is a serial signal and the second signal S2 is a parallel signal. Figure 4 This is a schematic diagram of one embodiment of connector 30 and backplane 40. Please refer to [link / reference]. Figures 2 to 4In some embodiments, the shift register 41 includes an input pin 1 and a plurality of output pins D. The input pin 1 is coupled to logic circuit 21, and the plurality of output pins D are coupled to a plurality of devices 22. In some embodiments, the shift register 41 is used to receive a first signal S1 as a serial signal through the input pin 1. In some embodiments, the shift register 41 controls the voltage preset of the plurality of output pins D according to the first signal S1 to transmit a plurality of second signals S2 to the plurality of devices 22. In some embodiments, the device 22 includes a plurality of address pins A, which are coupled to the plurality of output pins D and are used to receive the second signal S2. Figure 4 For example, Figure 4 The shift register 41 includes an input pin I and multiple output pins D (i.e., output pins D0 to D7). Figure 4 The device 22 includes multiple address pins A (i.e., address pins A0~A2), and output pins D0~D2 are coupled to address pins A0~A2. Figure 4 The shift register 41 receives the first signal S1 through the input pin I and controls the voltage level of the output pins D0 to D7 according to the first signal S1. Figure 4 Device 22 receives the voltage thresholds of output pins D0-D2 via address pins A0-A2 coupled to output pins D0-D2. At this time, the voltage thresholds of output pins D0-D2 are the second signal S2, which is a parallel signal, received by device 22. Figure 4 In the diagram, only one device 22 is drawn. If the backplane 40 contains another device 22, the multiple address pins A of this other device 22 are coupled to the remaining output pins D (i.e., output pins D3~D7) of the shift register 41. In this case, as described above, the shift register 41 can transmit multiple second signals S2 to multiple devices 22.

[0034] In some embodiments, the number of address pins A included in device 22 is as follows: Figure 4 Three examples are shown, but this case is not limited to these. It is hereby specifically stated that... Figure 4 In this example, shift register 41 is an 8-bit shift register (i.e., containing 8 output pins D). If the backplane 40 contains more than 3 devices 22, and each device 22 contains 3 address pins A, the 8 output pins D of this 8-bit shift register 41 will be insufficient, requiring a more bit shift register 41 (e.g., a 16-bit shift register) to meet the needs of the backplane 40. In other words, in some embodiments, the number of bits in the shift register 41 is determined based on the number of devices 22 contained in the backplane 40 and the number of address pins A contained in each device 22.

[0035] In some embodiments, the number of bits in the address of device 22 may be, but is not limited to, 7 or 10, but this invention is not limited thereto. In some embodiments, the address of device 22 includes the device type identifier of device 22 and the voltage thresholds (i.e., the second signal S2) received by the plurality of address pins A of device 22. In some embodiments, in the address of device 22, the device type identifier of device 22 and the voltage thresholds of the plurality of output pins D received by the plurality of address pins A of device 22 respectively correspond to different bits of the address of device 22. For example, with Figure 4 For example, if the address of device 22 has 7 bits, the device type identification code of device 22 is 1010, and the voltage threshold of output pins D0-D2 received by address pins A0-A2 is 111, then the address of device 22 is 1010111 (i.e., 0x57). In other words, in some embodiments, the second signal S2 only determines a portion of the address of device 22.

[0036] Please see Figures 2 to 4 In some embodiments, the backplane 40 further includes a switching circuit 42. The switching circuit 42 is coupled to the connector 30, the logic circuit 21, and multiple devices 22. Before step S05, the switching circuit 42 disconnects the multiple devices 22 from the motherboard 10 to ensure that the motherboard 10 does not read devices 22 that have not yet been addressed, thereby preventing the motherboard 10 from reading incorrect address information and ensuring the stable operation of the server system 2. Furthermore, an excessively long bus may affect signal integrity; the switching circuit 42 can segment the bus, reducing the number of devices on a single bus and improving the communication stability of the server system 2.

[0037] In some embodiments, after step S05 (i.e. after the address setting of the plurality of devices 22 is completed), the logic circuit 21 is further used to provide an enable signal EN to the switching circuit 42, and the switching circuit 42 is further used to turn on the plurality of devices 22 and the motherboard 10 according to the enable signal EN.

[0038] In some embodiments, the switching circuit 42 may be, but is not limited to, a repeater.

[0039] In some embodiments, logic circuit 21 supports ARP. In some embodiments, when control circuit 11 provides logic circuit address to logic circuit 21, control circuit 11 provides logic circuit address to logic circuit 21 via ARP.

[0040] In some embodiments, the logic circuit 21 can directly set the initial voltage threshold of the multiple output pins D of the shift register 41 so that the multiple devices 22 can still have an initial static address when the control circuit 11 does not support the dynamic address configuration method described above.

[0041] In summary, in some embodiments, the server system 2 utilizes the control circuit 11 to provide multiple device addresses to the logic circuit 21. The logic circuit 21 then uses a first signal S1 to control the voltage settings of multiple output pins D of the shift register 41 to set the addresses of multiple devices 22, thereby achieving dynamic address allocation for the multiple devices 22. The control circuit 11 can dynamically allocate appropriate addresses based on the number and topology of the multiple devices 22 within the server system 2, allowing the server system 2 to flexibly adapt to different hardware configurations without requiring manual address setting, thus improving management convenience and flexibility.

[0042] Furthermore, in some embodiments, compared to prior art, server system 2 only requires the addition of two components: shift register 41 and switching circuit 42, to enable server system 2 to dynamically allocate addresses to multiple devices 22. This reduces modification costs and ensures compatibility with existing server systems. In other words, the applicability of server system 2 can be determined by whether control circuit 11 supports dynamic address allocation in existing server systems. When control circuit 11 does not support dynamic allocation, logic circuit 21 can still directly set the initial voltage thresholds of multiple output pins D of shift register 41, ensuring that multiple devices 22 still have initial static addresses and guaranteeing normal operation of server system 2. Additionally, the switching circuit 42 can isolate devices 22 without set addresses before address setting is complete, thereby avoiding interference with motherboard 10 and preventing system anomalies caused by address identification errors. Furthermore, motherboard 10 does not require an additional I2C multiplexer, simplifying the design of server system 2, reducing hardware costs, and significantly improving the flexibility of device 22 management and the stability of server system 2.

[0043] Although the technical content of this case has been disclosed above with reference to preferred embodiments, it is not intended to limit this case. Any modifications and refinements made by those skilled in the art without departing from the spirit of this case should be included within the scope of this case. Therefore, the scope of protection of this case shall be determined by the appended claims.

Claims

1. An address configuration method applicable to a server system, the server system comprising a motherboard and a backplane, the motherboard being connected to the backplane via a connector, the motherboard comprising a control circuit, the backplane comprising a logic circuit, a shift register, and a plurality of devices, the shift register being coupled to the logic circuit and the plurality of devices, characterized in that, The address configuration method includes: (a) The control circuit reads internal data stored in the logic circuit to determine the number of the plurality of devices contained in the backplane; (b) The control circuit provides a corresponding number of device addresses to the logic circuit based on the number of the plurality of devices contained in the backplane; (c) The logic circuit transmits a first signal to the shift register based on the plurality of device addresses; (d) The shift register transmits a plurality of second signals to a plurality of the devices according to the first signal, and each of the second signals corresponds to a respective device; and (e) Each of the devices sets its own address according to the second signal corresponding to it.

2. The address configuration method according to claim 1, characterized in that, It also includes: (f) The control circuit provides a logic circuit address to the logic circuit; and (g) The logic circuit sets its own address according to the logic circuit address.

3. The address configuration method according to claim 1, characterized in that, The backplane further includes a switching circuit coupled to the connector, the logic circuit, and the plurality of devices. The switching circuit is used to disconnect the plurality of devices from the motherboard before step e, and after step e, the address configuration method further includes: (h) The logic circuit provides a consistent signal to the switching circuit; and (i) The switching circuit connects the plurality of the devices to the motherboard according to the enable signal.

4. The address configuration method according to claim 1, characterized in that, The first signal is a series signal, and the second signal is a parallel signal.

5. The address configuration method according to claim 4, characterized in that, The shift register includes an input pin and multiple output pins. The input pin is coupled to the logic circuit, and the multiple output pins are coupled to multiple devices. The shift register is used to receive the first signal through the input pin, and the shift register is used to control the voltage level of the multiple output pins according to the first signal, so as to transmit multiple second signals to the multiple devices.

6. A server system comprising: A backplane includes: a logic circuit storing internal data; a plurality of devices; and a shift register coupled to the logic circuit and the plurality of devices; and A motherboard, connected to the backplane via a connector, includes: a control circuit for: Read the internal data to determine the number of the plurality of devices contained in the backplane; and Provide a corresponding number of device addresses to the logic circuit based on the number of the plurality of devices included in the backplane; in, The logic circuit transmits a first signal to the shift register based on the addresses of the plurality of devices. The shift register transmits a plurality of second signals to the plurality of devices based on the first signal. Each second signal corresponds to a device. Each device sets its own address based on its corresponding second signal.

7. The server system according to claim 6, characterized in that, The control circuit is further configured to provide a logic circuit address to the logic circuit, and the logic circuit is further configured to set its own address according to the logic circuit address.

8. The server system according to claim 6, characterized in that, The backplane further includes a switching circuit coupled to the connector, the logic circuit, and the plurality of devices. The switching circuit is used to disconnect the plurality of devices from the motherboard before each device sets its address according to its corresponding second signal. After each device sets its address according to its corresponding second signal, the logic circuit is further used to provide a consistent enable signal to the switching circuit, and the switching circuit is further used to connect the plurality of devices to the motherboard according to the enable signal.

9. The server system according to claim 6, characterized in that, The first signal is a series signal, and the second signal is a parallel signal.

10. The server system according to claim 9, characterized in that, The shift register includes: An input pin is coupled to the logic circuit, and the shift register is used to receive the first signal through the input pin; and Multiple output pins are coupled to multiple of the aforementioned devices. The shift register is used to control the voltage level of the multiple output pins according to the first signal, so as to transmit multiple second signals to the multiple of the aforementioned devices.

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