A clock layout winding method, layout, clock system

Abstract

The embodiment of the present disclosure provides a clock layout winding method, a layout and a clock system, the method comprising: reducing the number of clock leaf nodes in a clock tree, the clock tree being a topology structure branching out from the center to the periphery; making the same number of parameterized units called by the winding to be matched in the clock tree, the parameterized unit being a single module made by the winding; and the winding before the grid using a top metal and the winding after the grid using a sub-top metal. The embodiment of the present disclosure reduces the problem of output signal mismatch, ensures the consistency of the winding length, minimizes the resistance and signal loss, optimizes the layout of the grid while ensuring the signal transmission quality.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a winding method, layout, and clock system for a clock layout. Background Technology

[0002] In integrated circuit design, the physical implementation of high-speed clock signal transmission is typically achieved using tree topologies (h-tree), fishbone topologies, or mesh topologies, such as... Figures 1-3 As shown.

[0003] However, the parasitic capacitance and trace resistance of the long traces in the above topology will affect the frequency, making it difficult to achieve the expected performance. And matching the signals of multiple high-speed clocks is even more difficult in terms of physical implementation.

[0004] Therefore, how to achieve clock-matched layout routing has become a pressing technical problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a winding method, layout, and clock system for a clock layout, in order to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a winding method for a clock layout is provided, the method comprising: reducing the number of clock leaf nodes in a clock tree, the clock tree being a topology branching outwards from the center; causing the windings to be matched in the clock tree to call the same number of parameterized units, the parameterized units being individual modules made of the windings; the windings before the mesh using top-layer metal, and the windings after the mesh using second-top-layer metal.

[0007] According to a second aspect of the present disclosure, a clock layout is provided, wherein the number of clock leaf nodes in the clock tree of the layout is reduced, and the clock tree is a topology that branches outward from the center; the windings that need to be matched in the clock tree call the same number of parameterized units, and the parameterized units are individual modules made of windings; the windings before the grid use top-layer metal, and the windings after the grid use second-layer metal.

[0008] According to a third aspect of the present disclosure, a clock system is provided, the clock system including the plurality of clock layouts described in the second aspect.

[0009] According to the clock matching layout routing scheme provided in this disclosure, the clock tree adopts a topology that branches outwards from the center, and reduces the number of clock leaf nodes in the clock tree, thereby reducing the problem of output signal mismatch. In this disclosure, the parameterized unit is a single module made of routing. Routes requiring matching in the clock tree call the same number of parameterized units, thus ensuring consistent routing lengths. For long-distance clock signal transmission, this disclosure uses top-layer metal for routing before the grid to minimize resistance and signal loss; considering the complexity of layout and design, routing after the grid uses second-layer metal, which can optimize the grid layout while ensuring signal transmission quality. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0011] Figure 1 This is a schematic diagram of the clock tree topology;

[0012] Figure 2 This is a schematic diagram of a clock tree fishbone topology;

[0013] Figure 3 This is a schematic diagram of the clock tree grid topology;

[0014] Figure 4 This is a flowchart of a layout routing method for clock matching according to an embodiment of the present disclosure;

[0015] Figure 5 This is a schematic diagram of the principle of a clock tree according to an embodiment of this disclosure;

[0016] Figure 6 This is a public announcement Figure 5 A schematic diagram of the clock tree layout in the Chinese embodiment;

[0017] Figure 7 This is a schematic diagram of the layout routing for clock matching according to another embodiment of this disclosure;

[0018] Figure 8a —— Figure 8c as well as Figure 9 This is a schematic diagram of the parameterized units of the top metal layer;

[0019] Figure 10a —— Figure 10e This is a schematic diagram of the parameterized unit layout of the second-to-top metal.

[0020] Figure 11 This is a schematic diagram of the layout routing for clock matching in another embodiment of the present disclosure;

[0021] Figure 12 This is a schematic diagram of the layout routing for clock matching according to yet another embodiment of this disclosure. Detailed Implementation

[0022] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0023] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0024] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0025] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0026] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0027] Some of the nouns or terms that appear in the description of the embodiments of this disclosure are to be interpreted as follows.

[0028] Mesh: A structure used for chip clock distribution. It divides the entire chip into a mesh, distributing the clock signal first to each mesh node, and then from each node to the corresponding clock leaf node.

[0029] Mtop (Medium Top): The Mtop is the highest metal layer in chip design, typically used for long-distance signal transmission, power supply, and ground distribution within the chip. It plays a crucial role in the chip's interconnect structure, ensuring efficient signal transmission between different parts of the chip.

[0030] The second-to-last metal layer (Myy) is the second-to-last metal layer in a chip metal stack, located below the top metal layer (Mtop). It is typically used to assist the top metal layer in implementing signal transmission, power distribution, and complex interconnect structures.

[0031] The layout routing scheme for clock matching provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Map winding method

[0033] This disclosure provides a clock-matched layout routing method, see [link to relevant documentation]. Figure 4 The method includes:

[0034] Step 101: Reduce the number of clock leaf nodes in the clock tree, which is a topology structure that branches outward from the center.

[0035] The more leaf nodes there are, the greater the difference in delay (often called clock skew) between the clock signals arriving at different leaf nodes. The greater the clock skew, the higher the risk of output signal mismatch. Furthermore, the more leaf nodes there are, the more complex the topology of the clock tree, the longer the clock tree, and the more severe the output signal mismatch problem caused by the clock tree.

[0036] Figure 5 This is a schematic diagram of the clock tree in an embodiment of this disclosure. Figure 6 This is a schematic diagram of the clock tree layout according to an embodiment of this disclosure.

[0037] according to Figure 5 and Figure 6 As can be seen, the clock tree topology that branches outwards from the center in this embodiment minimizes the number of clock leaf nodes in the clock tree, which can solve part of the clock tree output signal mismatch problem.

[0038] Step 102: Make the same number of parameterized cells (PCELLs) called for the windings that need to be matched in the clock tree. A parameterized cell is a single module made of a winding.

[0039] During the transmission of clock signals, the electrical characteristics of the winding (such as resistance and capacitance) need to remain consistent, so precise matching of the winding is usually required.

[0040] This disclosure uses EDA tools to create parameterized cells and define the basic geometry and parameters of the winding, including the length, width, and spacing of the winding.

[0041] For example, in the creation of parameterized units, the length of the winding is defined parametrically. For instance, it can be set that all windings requiring matching call 5 parameterized units, thus ensuring that the lengths of the matching windings are consistent.

[0042] See Figure 7 In order to ensure the matching of windings in the clock tree, the windings are made into parameterized units of individual modules. The windings that need to be matched in the clock tree call the same number of parameterized units, thereby ensuring that the winding lengths are consistent.

[0043] This disclosure embodiment, through parametric design in the parametric unit, can quickly generate windings with different configurations, reducing the workload of repetitive design. If it is necessary to adjust the winding length or other parameters, only the parameters in the parametric unit need to be modified, without redesigning each winding. The parametric unit not only improves the flexibility and efficiency of the design but also ensures the accuracy and consistency of winding matching.

[0044] Step 103: The winding before the mesh uses the top layer metal (Mtop), and the winding after the mesh uses the second-to-top layer metal (Myy).

[0045] Because the top layer metal is typically thick and undergoes advanced process optimization, it usually has the lowest possible resistance. In clock signal transmission, lower resistance reduces signal transmission delay and attenuation, thereby improving the stability and accuracy of the clock signal. In this embodiment, the winding before the grid uses the top layer metal, thus reducing the resistance of the winding before the grid. Clock signals typically have high frequencies, and higher resistance leads to increased signal reflection and loss, affecting signal integrity. The use of the top layer metal for the winding before the grid in this embodiment effectively reduces the adverse effects of winding resistance, ensuring that the clock signal maintains good quality during long-distance transmission.

[0046] The traces following the mesh are primarily used to construct the mesh, and their main function is to provide a stable clock for the load devices. Using the top metal (the metal with the lowest resistance) for the traces following the mesh, while further reducing resistance, will significantly impact the mesh layout and design. The mesh layout needs to consider uniform distribution and stability; using the top metal may increase the spacing between traces, thus affecting routing density and efficiency. The trace lengths following the mesh are relatively short, so the resistance has a relatively small impact on signal transmission. In this case, using the second-highest metal (Myy) can reduce interference with the mesh layout while ensuring signal transmission quality. Although the resistance of the second-highest metal is slightly higher than that of the top metal, its impact on signal transmission remains within acceptable limits due to the shorter trace length.

[0047] Figure 8a —— Figure 8c This is a schematic diagram of the parameterized cells of the top-layer metal. Among them, Figure 8a This is a schematic diagram of the Mtop layer (first layer) layout in the parameterized unit of the top metal; Figure 8b This is a schematic diagram of the layout of the Mtop-1 layer (the next layer) in the parameterized unit of the top metal. Figure 8c This is a schematic diagram of the layout of the Mtop-2 layer (the two layers below) in the parameterized unit of the top metal.

[0048] See Figure 8a , Figure 8b , Figure 8c The parameterized units of the top metal include: Mtop routing, Mtop blockage, Mtop-1 blockage, Mtop-2 shielding, and Mtop-2 blockage.

[0049] In specific implementations of some embodiments of this disclosure, see [link to relevant documentation]. Figure 8cThe reason for using layer Mtop-2 as the shielding layer is that its parasitic capacitance to layer Mtop is smaller than that of layer Mtop-1 to layer Mtop. This is because the distance between layer Mtop-2 and layer Mtop is greater, resulting in smaller parasitic capacitance. Furthermore, considering the winding resources and the proportion of reduction in parasitic capacitance, the benefits of using metal layers below layer Mtop-3 as shielding layers are minimal; therefore, lower metal layers were not used as shielding layers.

[0050] To effectively reduce parasitic capacitance and electromagnetic interference, while optimizing signal integrity and power supply stability, the shielding layer is uniformly connected to ground potential (GND, not shown in the figure). Connecting the shielding layer to ground potential provides a stable reference potential, thereby reducing parasitic capacitance between signal lines or power lines and the surrounding environment. A grounded shielding layer can effectively absorb and disperse external electromagnetic interference, while reducing coupling between signal lines, improving signal integrity and stability.

[0051] Specifically, see Figure 8c The shielding layer has a mesh structure, which is created by hollowing out the corresponding metal sections to form a grid pattern. This design significantly reduces the direct contact area between the metal layer and the signal lines, thereby reducing parasitic capacitance. Furthermore, the mesh structure effectively reduces crosstalk between signal lines, improving signal integrity.

[0052] In addition, see Figure 8c The shielding portion above the Mtop trace in the shielding layer is cut off, which further reduces the parasitic capacitance on the Mtop trace. This is because the distance between the shielding portion and the Mtop trace is relatively short, resulting in a large parasitic capacitance; cutting off the shielding portion reduces this effect. Therefore, reducing parasitic capacitance can lower signal delay and distortion, and improve the signal quality of the Mtop trace.

[0053] Dummy insertion is a common design technique used to add virtual metal lines or fillers to empty areas of a chip to improve the uniformity of the lithography process, reduce stress effects, or balance the density of different areas. Dummy insertion may introduce additional parasitic capacitance, especially in areas near signal or power lines.

[0054] See Figure 8b To avoid introducing additional parasitic capacitance between the Mtop-1 layer and the Mtop-2 layer and the Mtop-1 layer during virtual filling, Mtop-1 blocking needs to be added at critical locations on the metal of the Mtop, Mtop-1, and Mtop-2 layers. These critical locations are directly below or around the signal or power lines of the Mtop traces to protect these critical lines from parasitic capacitance.

[0055] The embodiments disclosed herein can effectively reduce the parasitic capacitance introduced by virtual fill by adding Mtop-1 blocking in the Mtop-1 layer of the parameterized unit of the top metal, thereby optimizing signal integrity and power supply stability and improving overall performance.

[0056] To ensure a consistent winding environment, especially in parametric unit design of the top metal layer, all unnecessary top metal windings, including unnecessary power and signal lines, must be cut off. This ensures that critical power and / or signal lines operate in the same electrical environment, avoiding the introduction of additional parasitic effects or interference due to the presence of other windings.

[0057] Figure 9 This is a layout diagram illustrating dummy AP filling for the pin-wrap metal layer (AP RDL, Al Redistribution layer). See also... Figure 9 When the pin winding metal layer passes through the Mtop trace, in order to ensure the consistency of parasitic parameters, the same matching fill needs to be added to the matching path corresponding to the trace, thereby reducing the difference in parasitic effects and optimizing signal integrity and circuit performance.

[0058] Figure 10a —— Figure 10e This is a schematic diagram of the parameterized unit layout for the second-to-top layer metal. Figure 10a This is a schematic diagram of the Myy layer (first layer). Figure 10b This is a schematic diagram of the layout of layer Myy-1 (the next layer). Figure 10c This is a schematic diagram of the Myy-2 layer (the two layers below). Figure 10d This is a schematic diagram of the Myy+1 layer (the layer above). Figure 10e This is a schematic diagram of the Myy+2 layer (the two layers above).

[0059] See Figures 10a-10e The parameterized units of the second-to-top layer metal include: Myy routing, Myy blockage, Myy shielding, Myy-1 blockage, Myy-1 dummy, Myy-2 shielding, Myy-2 blockage, Myy+1 blockage, Myy+1 dummy, Myy+2 shielding, and Myy+2 blockage.

[0060] In some specific implementations of this disclosure, Myy-2 and Myy+2 layers are used as shielding layers. The reason for choosing Myy-2 and Myy+2 layers as shielding layers is that their parasitic capacitance to the Myy layer is smaller than that of Myy-1 and Myy+1 layers. This is because the distance between Myy-2 and Myy+2 layers and the Myy layer is greater, resulting in smaller parasitic capacitance. Furthermore, considering the reduction in winding resources and parasitic capacitance, the benefits of using Myy-3 and Myy+3 layers and lower metal layers as shielding layers are relatively small; therefore, lower metal layers are not used as shielding layers.

[0061] To effectively reduce parasitic capacitance and electromagnetic interference, while optimizing signal integrity and power supply stability, the shielding layer is uniformly connected to ground (GND). Connecting the shielding layer to ground provides a stable reference potential, thereby reducing parasitic capacitance between signal lines or power lines and the surrounding environment. A grounded shielding layer can effectively absorb and disperse external electromagnetic interference, while reducing coupling between signal lines, improving signal integrity and stability.

[0062] Specifically, see Figure 10c The shielding layer has a mesh structure, which is created by hollowing out the metal of the second-layer metal layer to form a grid pattern. This design significantly reduces the direct contact area between the metal layer and the signal lines, thereby reducing parasitic capacitance. The mesh structure effectively reduces crosstalk between signal lines and improves signal integrity.

[0063] In addition, see Figure 10c The shielding portion above the Myy trace in the shielding layer is cut off, which further reduces the parasitic capacitance on the Myy trace. This is because the distance between the shielding portion and the Myy trace is relatively short, resulting in a large parasitic capacitance; cutting off the shielding portion reduces this effect. Therefore, reducing parasitic capacitance can lower signal delay and distortion, and improve the signal quality of the Myy trace.

[0064] To further reduce the parasitic capacitance of the shielding layer to the Myy traces, the shielding layer needs to be designed in segments, and the spacing between the shielding layer and the Myy traces should use the maximum spacing allowed by the Design Rules Check (DRC).

[0065] Specifically, the formula for calculating parasitic capacitance is Formula 1:

[0066] Where C is the parasitic capacitance, ∈ 0 ∈ r Where is the dielectric factor, S is the area between the shielding layer and the signal line (Myy trace), and d is the spacing between the shielding layer and the Myy trace.

[0067] Therefore, the smaller the area S between the shielding layer and the signal line (Myy trace), the larger the spacing d, and the smaller the parasitic capacitance. In this embodiment, the shielding layer is designed in segments, and the spacing between it and the Myy trace uses the maximum spacing allowed by the Design Rule Check (DRC), which minimizes parasitic capacitance.

[0068] Adding dummy fill above Myy traces increases parasitic capacitance between the Myy trace and the dummy fill. This parasitic capacitance degrades signal integrity, leading to signal delay and distortion. To avoid this parasitic effect, design guidelines prohibit adding dummy fill to the Myy trace areas on Myy-1 and Myy+1 layers. This minimizes the impact of parasitic capacitance and optimizes signal integrity and power stability.

[0069] In multilayer metal designs, virtual fill between different metal layers can introduce parasitic capacitance into the Myy trace, affecting signal integrity and power supply stability. To avoid introducing additional parasitic capacitance through virtual fill, blocking is added to specific metal layers (Myy, Myy-1, Myy-2, Myy+1, Myy+2) around the Myy trace. The blocking area corresponds to the virtual fill area around the trace of the next-highest metal layer. Adding Myy blocking, Myy-1 blocking, Myy-2 blocking, Myy+1 blocking, and Myy+2 blocking is to prevent the introduction of additional parasitic capacitance during virtual fill.

[0070] Taking the N5 process as an example, the maximum gap (empty space) between the Myy layer, Myy-1 layer, and Myy+1 layer is 1 micrometer.

[0071] In some specific implementations of this disclosure, if the number of clock leaf nodes of the last-stage clock inverter in the clock tree is inconsistent, dummy loading is added to the clock inverter with fewer clock leaf nodes to balance the load of the last-stage clock inverter.

[0072] See Figure 11 The final stage of the clock tree, the clock inverter, typically drives multiple clock leaf nodes, which are connected to the actual load devices. To achieve load matching, the load characteristics of each clock inverter must be consistent. If there is an inconsistency in the number of clock leaf nodes among the clock inverters, virtual loads need to be added to the clock inverters with fewer clock leaf nodes to ensure load balance.

[0073] Clock map

[0074] Corresponding to the above method, this disclosure also provides a clock layout in which the number of clock leaf nodes in the clock tree of the layout is reduced, and the clock tree is a topology structure that branches out from the center; the windings that need to be matched in the clock tree call the same number of parameterized units, and the parameterized units are individual modules made of windings; the windings before the mesh use top-layer metal, and the windings after the mesh use second-top-layer metal.

[0075] The more leaf nodes there are, the greater the difference in delay (often called clock skew) between the clock signals arriving at different leaf nodes. The greater the clock skew, the higher the risk of output signal mismatch. Furthermore, the more leaf nodes there are, the more complex the topology of the clock tree, the longer the clock tree, and the more severe the output signal mismatch problem caused by the clock tree.

[0076] Figure 5 This is a schematic diagram of the clock tree in an embodiment of this disclosure. Figure 6 This is a schematic diagram of the clock tree layout according to an embodiment of this disclosure.

[0077] according to Figure 5 and Figure 6 As can be seen, the clock tree topology that branches outwards from the center in this embodiment minimizes the number of clock leaf nodes in the clock tree, which can solve part of the clock tree output signal mismatch problem.

[0078] During the transmission of clock signals, the electrical characteristics of the winding (such as resistance and capacitance) need to remain consistent, so precise matching of the winding is usually required.

[0079] This disclosure uses EDA tools to create parameterized cells and define the basic geometry and parameters of the winding, including the length, width, and spacing of the winding.

[0080] For example, in the creation of parameterized units, the length of the winding is defined parametrically. For instance, it can be set that all windings requiring matching call 5 parameterized units, thus ensuring that the lengths of the matching windings are consistent.

[0081] See Figure 7 In order to ensure the matching of windings in the clock tree, the windings are made into parameterized units of individual modules. The windings that need to be matched in the clock tree call the same number of parameterized units, thereby ensuring that the winding lengths are consistent.

[0082] This disclosure embodiment, through parametric design in the parametric unit, can quickly generate windings with different configurations, reducing the workload of repetitive design. If it is necessary to adjust the winding length or other parameters, only the parameters in the parametric unit need to be modified, without redesigning each winding. The parametric unit not only improves the flexibility and efficiency of the design but also ensures the accuracy and consistency of winding matching.

[0083] Because the top layer metal is typically thick and undergoes advanced process optimization, it usually has the lowest possible resistance. In clock signal transmission, lower resistance reduces signal transmission delay and attenuation, thereby improving the stability and accuracy of the clock signal. In this embodiment, the winding before the grid uses the top layer metal, thus reducing the resistance of the winding before the grid. Clock signals typically have high frequencies, and higher resistance leads to increased signal reflection and loss, affecting signal integrity. The use of the top layer metal for the winding before the grid in this embodiment effectively reduces the adverse effects of winding resistance, ensuring that the clock signal maintains good quality during long-distance transmission.

[0084] The traces following the mesh are primarily used to construct the mesh, and their main function is to provide a stable clock for the load devices. Using the top metal (the metal with the lowest resistance) for the traces following the mesh, while further reducing resistance, will significantly impact the mesh layout and design. The mesh layout needs to consider uniform distribution and stability; using the top metal may increase the spacing between traces, thus affecting routing density and efficiency. The trace lengths following the mesh are relatively short, so the resistance has a relatively small impact on signal transmission. In this case, using the second-highest metal (Myy) can reduce interference with the mesh layout while ensuring signal transmission quality. Although the resistance of the second-highest metal is slightly higher than that of the top metal, its impact on signal transmission remains within acceptable limits due to the shorter trace length.

[0085] Figure 8a —— Figure 8c This is a schematic diagram of the parameterized cells of the top-layer metal. Among them, Figure 8a This is a schematic diagram of the Mtop layer (first layer) layout in the parameterized unit of the top metal; Figure 8b This is a schematic diagram of the layout of the Mtop-1 layer (the next layer) in the parameterized unit of the top metal. Figure 8c This is a schematic diagram of the layout of the Mtop-2 layer (the two layers below) in the parameterized unit of the top metal.

[0086] See Figure 8a , Figure 8b , Figure 8c The parameterized units of the top metal include: Mtop routing, Mtop blockage, Mtop-1 blockage, Mtop-2 shielding, and Mtop-2 blockage.

[0087] In specific implementations of some embodiments of this disclosure, see [link to relevant documentation]. Figure 8cThe reason for using layer Mtop-2 as the shielding layer is that its parasitic capacitance to layer Mtop is smaller than that of layer Mtop-1 to layer Mtop. This is because the distance between layer Mtop-2 and layer Mtop is greater, resulting in smaller parasitic capacitance. Furthermore, considering the winding resources and the proportion of reduction in parasitic capacitance, the benefits of using metal layers below layer Mtop-3 as shielding layers are minimal; therefore, lower metal layers were not used as shielding layers.

[0088] To effectively reduce parasitic capacitance and electromagnetic interference, while optimizing signal integrity and power supply stability, the shielding layer is uniformly connected to ground potential (GND, not shown in the figure). Connecting the shielding layer to ground potential provides a stable reference potential, thereby reducing parasitic capacitance between signal lines or power lines and the surrounding environment. A grounded shielding layer can effectively absorb and disperse external electromagnetic interference, while reducing coupling between signal lines, improving signal integrity and stability.

[0089] Specifically, see Figure 8c The shielding layer has a mesh structure, which is created by hollowing out the corresponding metal sections to form a grid pattern. This design significantly reduces the direct contact area between the metal layer and the signal lines, thereby reducing parasitic capacitance. Furthermore, the mesh structure effectively reduces crosstalk between signal lines, improving signal integrity.

[0090] In addition, see Figure 8c The shielding portion above the Mtop trace in the shielding layer is cut off, which further reduces the parasitic capacitance on the Mtop trace. This is because the distance between the shielding portion and the Mtop trace is relatively short, resulting in a large parasitic capacitance; cutting off the shielding portion reduces this effect. Therefore, reducing parasitic capacitance can lower signal delay and distortion, and improve the signal quality of the Mtop trace.

[0091] Dummy insertion is a common design technique used to add virtual metal lines or fillers to empty areas of a chip to improve the uniformity of the lithography process, reduce stress effects, or balance the density of different areas. Dummy insertion may introduce additional parasitic capacitance, especially in areas near signal or power lines.

[0092] See Figure 8b To avoid introducing additional parasitic capacitance between the Mtop-1 layer and the Mtop-2 layer and the Mtop-1 layer during virtual filling, Mtop-1 blocking needs to be added at critical locations on the metal of the Mtop, Mtop-1, and Mtop-2 layers. These critical locations are directly below or around the signal or power lines of the Mtop traces to protect these critical lines from parasitic capacitance.

[0093] The embodiments disclosed herein can effectively reduce the parasitic capacitance introduced by virtual fill by adding Mtop-1 blocking in the Mtop-1 layer of the parameterized unit of the top metal, thereby optimizing signal integrity and power supply stability and improving overall performance.

[0094] To ensure a consistent winding environment, especially in parametric unit design of the top metal layer, all unnecessary top metal windings, including unnecessary power and signal lines, must be cut off. This ensures that critical power and / or signal lines operate in the same electrical environment, avoiding the introduction of additional parasitic effects or interference due to the presence of other windings.

[0095] Figure 9 This is a layout diagram illustrating dummy AP filling for the pin-wrap metal layer (AP RDL, Al Redistribution layer). See also... Figure 9 When the pin winding metal layer passes through the Mtop trace, in order to ensure the consistency of parasitic parameters, the same matching fill needs to be added to the matching path corresponding to the trace, thereby reducing the difference in parasitic effects and optimizing signal integrity and circuit performance.

[0096] Figure 10a —— Figure 10e This is a schematic diagram of the parameterized unit layout for the second-to-top layer metal. Figure 10a This is a schematic diagram of the Myy layer (first layer). Figure 10b This is a schematic diagram of the layout of layer Myy-1 (the next layer). Figure 10c This is a schematic diagram of the Myy-2 layer (the two layers below). Figure 10d This is a schematic diagram of the Myy+1 layer (the layer above). Figure 10e This is a schematic diagram of the Myy+2 layer (the two layers above).

[0097] See Figures 10a-10e The parameterized units of the second-to-top layer metal include: Myy routing, Myy blockage, Myy shielding, Myy-1 blockage, Myy-1 dummy, Myy-2 shielding, Myy-2 blockage, Myy+1 blockage, Myy+1 dummy, Myy+2 shielding, and Myy+2 blockage.

[0098] In some specific implementations of this disclosure, Myy-2 and Myy+2 layers are used as shielding layers. The reason for choosing Myy-2 and Myy+2 layers as shielding layers is that their parasitic capacitance to the Myy layer is smaller than that of Myy-1 and Myy+1 layers. This is because the distance between Myy-2 and Myy+2 layers and the Myy layer is greater, resulting in smaller parasitic capacitance. Furthermore, considering the reduction in winding resources and parasitic capacitance, the benefits of using Myy-3 and Myy+3 layers and lower metal layers as shielding layers are relatively small; therefore, lower metal layers are not used as shielding layers.

[0099] To effectively reduce parasitic capacitance and electromagnetic interference, while optimizing signal integrity and power supply stability, the shielding layer is uniformly connected to ground (GND). Connecting the shielding layer to ground provides a stable reference potential, thereby reducing parasitic capacitance between signal lines or power lines and the surrounding environment. A grounded shielding layer can effectively absorb and disperse external electromagnetic interference, while reducing coupling between signal lines, improving signal integrity and stability.

[0100] Specifically, see Figure 10c The shielding layer has a mesh structure, which is created by hollowing out the metal of the second-layer metal layer to form a grid pattern. This design significantly reduces the direct contact area between the metal layer and the signal lines, thereby reducing parasitic capacitance. The mesh structure effectively reduces crosstalk between signal lines and improves signal integrity.

[0101] In addition, see Figure 10c The shielding portion above the Myy trace in the shielding layer is cut off, which further reduces the parasitic capacitance on the Myy trace. This is because the distance between the shielding portion and the Myy trace is relatively short, resulting in a large parasitic capacitance; cutting off the shielding portion reduces this effect. Therefore, reducing parasitic capacitance can lower signal delay and distortion, and improve the signal quality of the Myy trace.

[0102] To further reduce the parasitic capacitance of the shielding layer to the Myy traces, the shielding layer needs to be designed in segments, and the spacing between the shielding layer and the Myy traces should use the maximum spacing allowed by the Design Rules Check (DRC).

[0103] Specifically, the formula for calculating parasitic capacitance is Formula 1:

[0104] Where C is the parasitic capacitance, ∈ 0 ∈ r Where is the dielectric factor, S is the area between the shielding layer and the signal line (Myy trace), and d is the spacing between the shielding layer and the Myy trace.

[0105] Therefore, the smaller the area S between the shielding layer and the signal line (Myy trace), the larger the spacing d, and the smaller the parasitic capacitance. In this embodiment, the shielding layer is designed in segments, and the spacing between it and the Myy trace uses the maximum spacing allowed by the Design Rule Check (DRC), which minimizes parasitic capacitance.

[0106] Adding dummy fill above Myy traces increases parasitic capacitance between the Myy trace and the dummy fill. This parasitic capacitance degrades signal integrity, leading to signal delay and distortion. To avoid this parasitic effect, design guidelines prohibit adding dummy fill to the Myy trace areas on Myy-1 and Myy+1 layers. This minimizes the impact of parasitic capacitance and optimizes signal integrity and power stability.

[0107] In multilayer metal designs, virtual fill between different metal layers can introduce parasitic capacitance into the Myy trace, affecting signal integrity and power supply stability. To avoid introducing additional parasitic capacitance through virtual fill, blocking is added to specific metal layers (Myy, Myy-1, Myy-2, Myy+1, Myy+2) around the Myy trace. The blocking area corresponds to the virtual fill area around the trace of the next-highest metal layer. Adding Myy blocking, Myy-1 blocking, Myy-2 blocking, Myy+1 blocking, and Myy+2 blocking is to prevent the introduction of additional parasitic capacitance during virtual fill.

[0108] Taking the N5 process as an example, the maximum gap (empty space) between the Myy layer, Myy-1 layer, and Myy+1 layer is 1 micrometer.

[0109] In some specific implementations of this disclosure, if the number of clock leaf nodes of the last-stage clock inverter in the clock tree is inconsistent, dummy loading is added to the clock inverter with fewer clock leaf nodes to balance the load of the last-stage clock inverter.

[0110] See Figure 11 The final-level clock inverters in the clock tree typically drive multiple clock leaf nodes, which are connected to the actual load devices. To achieve load matching, the load characteristics of each clock inverter must be consistent. If there is an inconsistency in the number of clock leaf nodes among the clock inverters, dummy loads need to be added to the clock inverters with fewer leaf nodes to ensure load balance. The layout after adding dummy loads, with a missing 1 as an example... Figure 12 As shown.

[0111] Clock system

[0112] This disclosure also provides a clock system, which includes multiple clock layouts from the above embodiments.

[0113] This disclosure provides a clock system with a clock tree that branches outwards from the center, reducing the number of clock leaf nodes and minimizing output signal mismatch. The parameterized units are individual modules made of wire wound, and the same number of parameterized units are used for matching wires in the clock tree, ensuring consistent wire lengths. For long-distance clock signal transmission, the wires before the grid use top-layer metal to minimize resistance and signal loss; considering layout and design complexity, the wires after the grid use second-layer metal, optimizing the power grid layout while maintaining signal transmission quality.

[0114] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0115] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0116] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0117] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A method for winding a clock layout, the method comprising: Reduce the number of clock leaf nodes in the clock tree, which is a topology that branches outward from the center; The clock tree calls the same number of parameterized units for each wire that needs to be matched, where each parameterized unit is a single module made of wire. The winding before the grid uses the top layer metal, and the winding after the grid uses the second-to-top layer metal.

2. The method according to claim 1, wherein, The Mtop-2 layer is selected as the shielding layer in the parameterization unit of the top metal.

3. The method according to claim 2, wherein, The shielding layers are all connected to ground potential.

4. The method according to claim 3, wherein, The shielding layer has a mesh structure, which is formed by hollowing out the top layer of metal.

5. The method according to claim 4, wherein, The shielding portion in the shielding layer corresponding to the trace above the top metal layer is cut off.

6. The method according to claim 5, wherein, Add blocking at key locations in the Mtop, Mtop-1, and Mtop-2 layers of the parameterized unit of the top metal layer. The key locations are directly below or around the signal lines or power lines of the top metal traces.

7. The method according to claim 5, wherein the top metal windings other than the critical power lines and signal lines in the parameterization unit of the top metal are cut off.

8. The method according to claim 6, wherein, If the pin winding metal layer passes through the Mtop layer trace in the parameterized unit of the top layer metal, the same matching fill is added to the matching path corresponding to the trace.

9. The method according to claim 1, wherein, The parameterization unit of the second-top metal is selected as Myy-2 layer and Myy+2 layer as shielding layer.

10. The method according to claim 9, wherein, The shielding layers are all connected to ground potential.

11. The method according to claim 10, wherein, The shielding layer has a mesh structure, which is formed by hollowing out the second-layer metal.

12. The method according to claim 11, wherein, The shielding portion above the trace of the second-layer metal in the shielding layer is cut off.

13. The method according to claim 12, wherein, The shielding layer is segmented, and the spacing between the traces of the shielding layer and the second-layer metal is checked using design rules to ensure the maximum allowable spacing.

14. The method according to claim 12, wherein, Virtual fill is added to the area outside the traces of the second-top metal in the Myy-1 and Myy+1 layers of the parameterized unit of the second-top metal.

15. The method according to claim 12, wherein, The parameterization unit of the second-top metal adds blocking in the Myy layer, Myy-1 layer, Myy-2 layer, Myy+1 layer, and Myy+2 layer. The area where the blocking is added is the area corresponding to the virtual fill around the trace of the second-top metal.

16. The method according to claim 1, wherein if the number of clock leaf nodes of the last-stage clock inverters of the clock tree is inconsistent, virtual load is added at the clock inverters with fewer clock leaf nodes to balance the load of the last-stage clock inverters.

17. A clock layout, wherein the number of clock leaf nodes in the clock tree of the layout is reduced, and the clock tree is a topology that branches outward from the center; the windings to be matched in the clock tree call the same number of parameterized units, and the parameterized units are individual modules made of windings; the windings before the grid use top-layer metal, and the windings after the grid use second-layer metal.

18. A clock system comprising the plurality of clock layouts as described in claim 17.

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