A modular reusable core pellet thermal simulation method and system

Abstract

The application discloses a kind of modular, reusable core particle thermal simulation method and system.The method uses the idea of "lego", complex core particle heterogeneous integrated system is split into independently solvable functional module, and high-fidelity three-dimensional grid is constructed for each module, and the thermal resistance network is extracted, and then the low-order thermal module is generated by port aggregation.The final simulation is realized by using modular assembly to reconstruct different design scenarios, and the fast simulation of multi-scene thermal analysis is realized.Compared with the existing finite element method and compact thermal model, the application significantly reduces the simulation time and iteration cost while maintaining the accuracy of key hot spots, and can shorten the thermal design cycle from several weeks to half a day.The method is particularly suitable for fast thermal simulation iteration of 2.5D / 3D chip packaging structure in multiple scenarios, and can effectively cope with the thermal design and management challenges in modern integrated circuit design, providing a fast and accurate thermal simulation tool for heterogeneous integrated chip design.

Description

Technical Field

[0001] This invention relates to the field of chip packaging and heterogeneous chip integration technology, and in particular to a modular, reusable thermal simulation method and system for heterogeneous chip integrated circuits. Background Technology

[0002] As semiconductor manufacturing approaches its physical limits, heterogeneous chip integration has become a crucial approach to improving system performance and energy efficiency. This architecture integrates multiple functional chips stacked or side-by-side using advanced packaging technologies, and achieves high-speed interconnection through microscale interconnects such as through-silicon vias (TSVs), redistribution layers (RDLs), and solder joints. However, this hierarchical stacking significantly increases power density, and thermal gradients caused by localized hotspots can compromise device reliability.

[0003] Current thermal simulations primarily employ analytical and numerical methods. Analytical methods, such as variable separation and Green's functions, are only suitable for simple geometries; numerical methods, such as the finite element method (FEM), are the industry "gold standard" in terms of accuracy, but require significant computational resources for the integration of core-particle heterogeneous structures across scales. Compact thermal models (CTMs) based on finite differences simplify the problem through thermal resistance-capacitance networks, achieving a balance between efficiency and accuracy to some extent, but their ability to capture micro-interconnect details and local hotspots is limited. While deep learning methods have the potential for acceleration, the dimensionality of the feature matrix increases dramatically when dealing with cross-scale interconnects, resulting in high training costs and limited scalability. Furthermore, existing methods typically build complete models for a single configuration; design modifications require re-meshing and resolving, lacking modular reusability. Summary of the Invention

[0004] The purpose of this invention is to provide a modular and reusable thermal simulation method and system suitable for heterogeneous integrated circuits, so as to solve the problems of low efficiency and poor reusability in the existing technology in multi-scenario thermal analysis.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a modular and reusable core thermal simulation method, comprising the following steps:

[0006] S1. The heterogeneous integrated circuit is functionally decomposed into multiple independent modules (such as chip modules, bump modules, through-silicon via modules, interposer modules, heat dissipation boundary modules, etc.), and further layered along the vertical direction. For each layer, a two-dimensional mesh is generated using Delaunay triangulation, and then extruded according to layer thickness to form a three-dimensional triangular prism mesh. This layered mesh allows for high mesh density settings for microstructures such as TSVs, RDLs, and TIMs, while also allowing for coarser meshes in regions with small thermal gradients. Compared to existing methods that uniformly decompose the entire package at once, this step encapsulates geometry, materials, and boundary conditions within independent modules. Subsequent modeling only occurs within modules where changes occur, reducing the workload of repeated mesh generation and global model reconstruction.

[0007] S2. A thermal resistance network is established for each module mesh. The thermal resistance network of each module is constructed using the electrothermal correspondence. The centroid of the mesh element serves as the network node. The thermal resistance between adjacent nodes is calculated based on the thermal contact area and the material's thermal conductivity. Nodes on the module boundaries form numerous interface ports, leading to a high-order admittance matrix. To improve reuse efficiency, this invention aggregates ports with similar thermal behaviors into supernodes based on material regions and geometric connectivity. The port aggregation matrix is ​​then used to reduce the order of the original admittance matrix, resulting in an equivalent low-order module. During port aggregation, critical micro-interconnect ports are retained, while other ports are aggregated by region, maintaining the input-output equivalence relationship.

[0008] S3. Calculate the thermal conductivity matrix of the module, and based on the material region, geometric connectivity, and thermal response similarity of the module's boundary nodes, aggregate ports with similar thermal behavior into supernodes, constructing a port aggregation matrix. This process reduces the order of the thermal conductivity matrix, retaining key microstructure ports to obtain a low-order thermal module that maintains input-output equivalence. The port aggregation matrix S is a binary matrix, where each column corresponds to a supernode, and each row corresponds to an original boundary port. If the original port belongs to that supernode, the corresponding element is set to 1; otherwise, it is set to 0. The low-order thermal conductivity matrix is ​​obtained, and then... This yields a low-order power vector. Compared to directly solving the complete RC network, this step significantly reduces the matrix dimension while preserving the relationship between external port heat flux and temperature; specifically as follows:

[0009] S31: Take the centroid of each grid cell as a thermal resistance network node. Calculate the thermal resistance between adjacent nodes based on the equivalent contact area between adjacent grid cells, the distance from the centroid to the contact interface, and the thermal conductivity of the material. Obtain the corresponding thermal conductivity from the reciprocal of the thermal resistance.

[0010] S32: For mesh elements located at the outer boundary of the module, introduce boundary thermal resistance and convective heat transfer thermal resistance to construct an equivalent thermal connection between the boundary node and the environment to simulate ambient temperature, cooling conditions or heat dissipation boundary.

[0011] S33: Construct a module thermal conductivity matrix based on the thermal resistance network, and divide the module nodes into internal nodes and boundary port nodes according to the physical location of the nodes. The internal nodes are used to describe the internal heat conduction behavior of the module, and the boundary port nodes are used to describe the thermal coupling behavior between the module and adjacent modules.

[0012] S34: Static elimination is performed on the degrees of freedom of the internal nodes of the module. Based on the thermal coupling relationship between the boundary port nodes and the cross thermal coupling relationship between the internal nodes and the boundary port nodes, an equivalent boundary thermal conduction matrix with respect to the boundary ports is generated, thereby reducing the module model order while maintaining the input and output thermal response of the module boundary.

[0013] S35: Classify the module boundary ports, mark ports related to key microstructures, main heat transfer paths or hot spots as reserved ports, and mark ports located in the same material region and with geometric connectivity and similar thermal behavior as aggregateable ports;

[0014] S36: The aggregateable ports are divided into several port groups according to material properties, spatial continuity and thermal coupling relationship. Each port group corresponds to a supernode, and a port aggregation mapping relationship between the original ports and supernodes is established. Among them, the key microstructure ports are preserved through unit mapping relationship.

[0015] S37: The equivalent boundary thermal conductivity matrix is ​​reduced in order using port aggregation mapping to obtain a low-order module boundary thermal conductivity matrix. The equivalent thermal conductivity of the aggregated port group is obtained by summing the thermal conductivity of each original port within that group. This ensures that the generated low-order thermal module maintains an equivalent input-output thermal response at the boundary ports to the original high-order module, while simultaneously reducing the number of module ports and the global solution scale.

[0016] S4. Each low-order thermal module is treated as a reusable module with slots. They are coupled and assembled into the target structure as needed via supernodes. Based on different scenarios involving layout, stacking configuration, interface materials, heat dissipation boundaries, and power distribution, the corresponding module connection methods, port thermal resistances, or injected power are updated to form the global low-order thermal conduction equation KallTall = Pall + Qamb, and the temperature distribution of the target structure is solved. Compared to existing methods that rebuild a complete finite element model for each scenario, this step moves the repetitive calculations to the module library construction stage. During scenario switching, the main tasks are module connection, parameter updates, and low-order matrix solving, making it suitable for rapid thermal design iterations in multi-core, multi-stack schemes.

[0017] In step S1, the functional modules include a chip module, a bump module, a through-silicon via (TSV) module, and an interposer module. Each functional module is divided into multiple vertical sub-layers based on its internal microstructures such as TSVs, RDLs, and TIMs, and an independent mesh is generated in each sub-layer. The improvement of this step lies in splitting the cross-scale packaging structure into independently maintainable mesh cells, allowing different modules to use different resolutions and be reused individually, avoiding the generation of a large number of redundant cells near the microstructures in traditional globally unified meshes.

[0018] In step S3, by analyzing the thermal conductivity, geometric connectivity, and thermal response similarity of the materials where the ports are located, ports located in the same material region and with similar thermal behavior are aggregated into supernodes, and a binary indicator matrix is ​​constructed to represent the mapping relationship between each port and the supernode. The improvement of this step lies in not simply deleting boundary ports, but maintaining heat flux conservation and input-output equivalence at the supernode level; thus reducing the number of ports in low-order modules while retaining key thermal paths such as TSVs, RDLs, hot spots, and power injection regions.

[0019] In step S4, when the core layout or stacking configuration changes, the target structure can be reconstructed by reconnecting the supernodes of the lower-order modules. When the interface material or heat dissipation boundary changes, only the equivalent thermal resistance, convective heat transfer coefficient, and ambient temperature terms of the corresponding ports need to be updated. When the power distribution changes, only the equivalent current source of the corresponding node of the active module needs to be adjusted. The improvement of this step lies in transforming multiple scenario changes into module connection relationships and a small number of boundary parameter changes, without having to repeat the complete geometric modeling, mesh generation, and high-order matrix extraction.

[0020] A core thermal simulation system for implementing the method includes:

[0021] Modular decomposition and meshing unit, used to decompose the core-particle heterogeneous integrated system into functional modules and construct a three-dimensional mesh;

[0022] The thermal resistance extraction unit is used to calculate the thermal resistance network of each module based on the mesh and establish the thermal conductivity matrix.

[0023] Port aggregation unit is used to aggregate module boundary ports based on material properties and geometric connectivity, construct a port aggregation matrix, and generate low-order thermal modules;

[0024] The module assembly unit is used to assemble low-order thermal modules into the target structure through supernodes, and update the module connection relationship, port thermal resistance or power source according to different scenarios.

[0025] The thermal simulation solution unit is used to solve the assembled thermal module network and output the temperature distribution of the chip heterogeneous integrated circuit under different scenarios.

[0026] The module decomposition and meshing unit uses the Delaunay triangulation algorithm to generate a two-dimensional mesh in each sub-layer, and then extrudes it according to the layer thickness to form a three-dimensional triangular prism mesh; the port aggregation unit reduces the order of the original thermal conductivity matrix through the port aggregation matrix, so that the input and output characteristics of the low-order module are equivalent to those of the original module.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. Balancing high fidelity and reusability: Through hierarchical meshing and port aggregation, high-resolution thermal paths are preserved near TSVs, RDLs, TIMs, bumps, and hotspots, while low-order equivalent representations are used in regions with smooth thermal response. Therefore, the model order can be significantly reduced while maintaining the accuracy of micro-interconnects and local hotspots, and the same core, bump, or interposer module can be reused in different packaging schemes.

[0029] 2. High Simulation Efficiency in Multiple Scenarios: Utilizing modular assembly, simulations can be completed by simply adjusting module connections, port thermal resistance, convection heat transfer parameters, or power sources to address variations in core layout, stacking order, interface materials, heat dissipation boundaries, and power distribution. Compared to rebuilding a complete finite element model for each design change, this method avoids redundant meshing and extraction of global high-order thermal resistance networks. Experiments show that it is nearly an order of magnitude faster than the commercial finite element tool COMSOL in multiple scenarios.

[0030] 3. Flexible resolution control: For local areas requiring high resolution, some modules' high-order models or key ports can be retained, while other areas use low-order models, thus achieving a flexible balance between global speed and local accuracy. In the early architecture exploration phase, low-order modules can be used to quickly select solutions, and in the final verification phase, they can be replaced with higher-order local modules for fine verification.

[0031] 4. The algorithm process is clear and easy to integrate into engineering: This method breaks down the thermal simulation process into four stages: module mesh generation, thermal resistance network extraction, port aggregation and order reduction, and module assembly and solution. Each stage can be implemented and verified independently. The low-order modules are stored in the form of thermal conduction matrix, port mapping matrix, boundary parameters and power vector, which can be directly connected to SPICE-type network solvers or other matrix solvers, which facilitates batch scenario evaluation in the core design process.

[0032] 5. Fast response to local design modifications: When only a specific core particle, local interconnect, interface material, or heat dissipation condition is modified, the low-order thermal model of the unchanged module does not need to be regenerated; only the affected module and its adjacent supernode connections need to be updated. This feature is suitable for the frequent layout exploration, stacking order comparison, and heat dissipation scheme evaluation in core particle heterogeneous integration, and can reduce the cost of thermal design iteration. Detailed Implementation

[0033] The following provides a detailed description of specific embodiments of the present invention. Those skilled in the art should understand that these embodiments are merely illustrative of the invention and are not intended to limit the scope of protection of the invention.

[0034] Example 1: A modular and reusable core thermal simulation method, the method comprising the following steps:

[0035] Module decomposition and mesh generation,

[0036] First, based on the functional division of the core-particle heterogeneous integrated system, the overall structure is decomposed into multiple functional modules Ω(i), such as core particles, bumps, embedded wiring layers, and interposer layers. Each functional module is further layered along the vertical direction, with each layer containing microstructures such as TSVs, RDLs, and TIMs, allowing for different mesh densities for different structures. Then, each layer is delaunay triangulated in the horizontal plane, ensuring that the circumcircle of the triangle does not contain other nodes, resulting in a high-quality two-dimensional mesh. Finally, the two-dimensional mesh is equidistantly extruded according to the layer thickness to generate a three-dimensional triangular prism mesh.

[0037] Thermal resistance extraction and port aggregation

[0038] After meshing each module, the centroid of each mesh element is considered as a network node using the electrothermal correspondence principle. Thermal resistance between adjacent elements is calculated based on contact area, distance, and material thermal conductivity. Module surface nodes simulate thermal boundaries using boundary thermal resistance and convective thermal resistance. In active modules, equivalent current sources are introduced at corresponding nodes to represent power injection. As the mesh becomes finer, module boundaries typically contain numerous ports, and direct involvement in calculations can lead to an excessively large admittance matrix dimension. Therefore, this invention aggregates ports with similar thermal behaviors into supernodes based on their material regions and geometric connectivity. A port aggregation matrix S is constructed to reduce the order of the original admittance matrix, resulting in a lower-order equivalent module. Simultaneously, key micro-interconnect ports are retained to ensure unchanged input and output characteristics.

[0039] Module assembly and multi-scenario simulation,

[0040] By treating the port-aggregated modules as slotted Lego bricks, different core combinations and their heat dissipation paths can be quickly reconstructed through supernode connections. When the core layout, stacking order, or interface material changes, only the relevant modules need to be reconnected or the equivalent thermal resistance of the corresponding ports needs to be updated; the remaining modules can be directly reused without resolving the global large-scale model. When the ambient temperature or cooling conditions change, only the boundary heat source needs to be adjusted; when the power distribution changes, the equivalent current source can be adjusted at the nodes of the corresponding active modules. Therefore, this invention has a simulation efficiency far exceeding that of traditional methods in multiple scenarios.

[0041] Experimental verification

[0042] To verify the effectiveness of this invention, experiments were conducted using four 2.5D / 3D chip-based heterogeneous integration benchmarks based on the Cadence reference design. The results show that while the invention requires port aggregation in the initial simulation, which takes some time, module reuse significantly reduces the total simulation time across 100 different scenarios. For example, in the most complex 3D benchmark (Chiplet_3D_12), this invention achieves a speedup of 10.39× compared to COMSOL and 8.41× compared to a complete RC network.

[0043] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. A modular and reusable core thermal simulation method, characterized in that, Includes the following steps: S1. The heterogeneous integrated circuit is decomposed into multiple independent modules according to its function and layered along the vertical direction. Each layer is generated into a two-dimensional mesh using Delaunay triangulation and then extruded according to the layer thickness to form a three-dimensional triangular prism mesh. S2. Establish a thermal resistance network for each module mesh, using the centroid of the mesh unit as the node, and calculate the thermal resistance based on the contact area, thickness and thermal conductivity of the material between adjacent nodes. The module surface nodes simulate the environmental boundary through boundary thermal resistance and convection thermal resistance. Inject an equivalent current source into the corresponding node of the active module to represent the power. S3. Calculate the thermal conductivity matrix of the module, and based on the material region and geometric connectivity of the module boundary nodes, aggregate ports with similar thermal behavior into supernodes, construct a port aggregation matrix, reduce the order of the thermal conductivity matrix, retain key microstructure ports, and obtain a low-order thermal module that maintains the equivalence of input and output. S31: Take the centroid of each grid cell as a thermal resistance network node. Calculate the thermal resistance between adjacent nodes based on the equivalent contact area between adjacent grid cells, the distance from the centroid to the contact interface, and the thermal conductivity of the material. Obtain the corresponding thermal conductivity from the reciprocal of the thermal resistance. S32: For mesh elements located at the outer boundary of the module, introduce boundary thermal resistance and convective heat transfer thermal resistance to construct an equivalent thermal connection between the boundary node and the environment to simulate ambient temperature, cooling conditions or heat dissipation boundary. S33: Construct a module thermal conductivity matrix based on the thermal resistance network, and divide the module nodes into internal nodes and boundary port nodes according to the physical location of the nodes. The internal nodes are used to describe the internal heat conduction behavior of the module, and the boundary port nodes are used to describe the thermal coupling behavior between the module and adjacent modules. S34: Static elimination is performed on the degrees of freedom of the internal nodes of the module. Based on the thermal coupling relationship between the boundary port nodes and the cross thermal coupling relationship between the internal nodes and the boundary port nodes, an equivalent boundary thermal conduction matrix with respect to the boundary ports is generated, thereby reducing the module model order while maintaining the input and output thermal response of the module boundary. S35: Classify the module boundary ports, mark ports related to key microstructures, main heat transfer paths or hot spots as reserved ports, and mark ports located in the same material region and with geometric connectivity and similar thermal behavior as aggregateable ports; S36: The aggregateable ports are divided into several port groups according to material properties, spatial continuity and thermal coupling relationship. Each port group corresponds to a supernode, and a port aggregation mapping relationship between the original ports and supernodes is established. Among them, the key microstructure ports are preserved through unit mapping relationship. S37: The equivalent boundary thermal conductivity matrix is ​​reduced in order using port aggregation mapping to obtain a low-order module boundary thermal conductivity matrix. The equivalent thermal conductivity of the aggregated port group is obtained by summing the thermal conductivity of each original port within that group. This ensures that the generated low-order thermal module maintains an equivalent input-output thermal response at the boundary ports to the original high-order module, while simultaneously reducing the number of module ports and the global solution scale. S4. Each low-order thermal module is treated as a reusable module with slots. It is coupled and assembled into the target structure as required through supernodes. Based on different scenarios such as layout, stacking configuration, interface material, heat dissipation boundary and power distribution, the corresponding module connection method, port thermal resistance or injected power is updated to achieve rapid thermal simulation in multiple scenarios.

2. The core thermal simulation method according to claim 1, characterized in that, In step S1, the functional modules include a core module, a bump module, a through-silicon via module, an interposer module, and a heat dissipation boundary module. Each functional module is divided into multiple sub-layers along the vertical direction according to the material distribution and thickness of its internal TSV, RDL, TIM, and metal interconnect structure. After generating an independent two-dimensional mesh in each sub-layer, it is extruded into a three-dimensional triangular prism mesh. This allows local microstructures to use a higher mesh density, while structures far from hot spots or interconnect areas use a lower mesh density. This reduces the number of invalid meshes compared to overall unified mesh modeling and ensures that subsequent design changes only affect the corresponding functional modules.

3. The core thermal simulation method according to claim 1, characterized in that, In step S3, by analyzing the thermal conductivity, geometric connectivity, and thermal response similarity of the materials where the ports are located, ports located in the same material region and with similar thermal behavior are aggregated into supernodes, and a binary port aggregation matrix S is constructed to represent the mapping relationship between each original port and the supernode; the module thermal conductivity matrix K is reduced in order, retaining power ports, TSV ports, RDL ports, and ports near hot spots, so that the low-order thermal module maintains the equivalent temperature-heat flow input-output relationship with the original high-order module at the external ports.

4. The core thermal simulation method according to claim 1, characterized in that, In step S4, when the core layout or stacking configuration changes, the target structure is reconstructed by reconnecting the supernodes of the low-order modules; when the interface material, heat sink, or convection boundary changes, only the equivalent thermal resistance, convection heat transfer coefficient, or ambient temperature term of the corresponding port is updated; when the power distribution changes, only the equivalent current source of the node corresponding to the active module is adjusted, and the global low-order thermal conduction equation after assembly is solved, thereby avoiding re-meshing of the complete core package and re-extraction of the global high-order thermal resistance network.

5. A core thermal simulation system for implementing the method of any one of claims 1 to 4, comprising: Modular decomposition and meshing unit, used to decompose the core-particle heterogeneous integrated system into functional modules and construct a three-dimensional mesh; The thermal resistance extraction unit is used to calculate the thermal resistance network of each module based on the mesh and establish the thermal conductivity matrix. Port aggregation unit is used to aggregate module boundary ports based on material properties and geometric connectivity, construct a port aggregation matrix, and generate low-order thermal modules; The module assembly unit is used to assemble low-order thermal modules into the target structure through supernodes, and update the module connection relationship, port thermal resistance or power source according to different scenarios. The thermal simulation solution unit is used to solve the assembled thermal module network and output the temperature distribution of the chip heterogeneous integrated circuit under different scenarios.

6. The core particle thermal simulation system according to claim 5, characterized in that, The module decomposition and meshing unit uses the Delaunay triangulation algorithm to generate a two-dimensional mesh in each sub-layer, and then extrudes it according to the layer thickness to form a three-dimensional triangular prism mesh; the port aggregation unit reduces the order of the original thermal conductivity matrix through the port aggregation matrix, so that the input and output characteristics of the low-order module are equivalent to those of the original module.