An instruction transmission method and device based on dependency chain tracking and a chip

Abstract

The application discloses a kind of instruction launch method, device and chip based on dependence chain tracking, comprising: in response to the long-delay instruction identified, the delay flag bit of the corresponding table entry in the renaming table with its destination logical register is set to active state, and the first physical register number allocated for destination logical register is written into global delay source field;In response to the source logical register of the successor instruction in the delay flag bit of the corresponding table entry in renaming table is active state, the successor instruction is marked as delayed instruction, and global delay source field is passed to the instruction;Delayed instruction is temporarily stored to delay queue, when long-delay instruction executes completion or before execution completes, preset period, generate the wake-up signal carrying first physical register number and broadcast to renaming table and delay queue, the activation flag bit of the delayed instruction matched successfully is set from invalid state to active state, and is moved into launch queue.The application can effectively improve launch queue utilization.

Description

Technical Field

[0001] This invention relates to the field of computer processor microarchitecture design technology, and in particular to an instruction issuing method, apparatus and chip based on dependency chain tracing. Background Technology

[0002] In the out-of-order execution architecture of modern high-performance processors, instructions are renamed in registers and written to the issue queue, awaiting the readiness of their source operands before being issued for execution. When long-delayed instructions appear in the instruction stream, all subsequent instructions that directly or indirectly depend on the result of those long-delayed instructions cannot become ready until the long-delayed instructions they depend on complete. These subsequent instructions that depend on the results of long-delayed instructions occupy issue queue entries for extended periods without being executed, resulting in low issue queue utilization.

[0003] There is currently no effective solution to the above problems. Summary of the Invention

[0004] This specification provides an instruction issuance method, apparatus, and chip based on dependency chain tracing to solve the problem in the prior art where subsequent instructions that depend on the results of long-delayed instructions occupy issuance queue entries for a long time but cannot be executed, resulting in low issuance queue utilization.

[0005] Firstly, embodiments of this specification provide an instruction issuance method based on dependency chain tracing, including: In response to the identified long delay instruction, the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long delay instruction is set to an active state to mark the current dependency chain start point, and the first physical register number allocated to the destination logical register is written into the global delay source field of the renaming table. In response to the source logic register of the subsequent instruction having the delay flag bit of the corresponding entry in the renaming table in a valid state, the subsequent instruction is determined to be on the current dependency chain, the subsequent instruction is marked as a delayed instruction, and the global delay source head field is passed to the delayed instruction. The delayed instruction is temporarily stored in the delay queue, and the activation flag of the delayed instruction is initialized to an invalid state. When the long delayed instruction is completed or at a preset period before completion, a wake-up signal carrying the first physical register number is generated and broadcast to the renaming table and the delay queue for corresponding matching operations. When the matching is successful, the activation flag of the successfully matched delayed instruction is set from an invalid state to an valid state. Delayed instructions with the activation flag set to valid are moved from the delay queue to the launch queue.

[0006] In some embodiments, the method further includes: When the current instruction is not a memory access instruction, the instruction opcode of the current instruction is matched with the preset long-delay instruction type. If the match is successful, the current instruction is identified as a long-delay instruction. When the current instruction is a memory access instruction, the memory access latency prediction mechanism is used to predict whether a cache miss will occur. If so, the memory access instruction is determined to be a long-latency instruction.

[0007] In some embodiments, the method further includes: The long delay instruction is written into the launch buffer, and the pending delay flag of the corresponding entry of the long delay instruction in the launch buffer is set to an invalid state, so that the long delay instruction can be directly moved into the launch queue.

[0008] In some embodiments, the method further includes: The delayed instruction is written into the launch buffer, and the delayed flag of the corresponding entry of the delayed instruction in the launch buffer is set to a valid state, so as to temporarily store the delayed instruction in the delay queue.

[0009] In some embodiments, passing the global delay source field to the instruction to be delayed includes: Copy the value of the global delay source field in the rename table to the delay source field of the corresponding entry in the launch cache for the instruction to be delayed.

[0010] In some embodiments, the method further includes: In response to the fact that the delay flag bits of the source logic register corresponding to the subsequent instruction in the renaming table are all in an invalid state, it is determined that the subsequent instruction is not on the current dependency chain, and the subsequent instruction is marked as a non-delay instruction; Write the non-delayed instruction into the transmit buffer, and set the delay flag of the corresponding entry of the non-delayed instruction in the transmit buffer to an invalid state; If there is an idle entry in the launch queue, the non-delayed instruction is moved directly into the launch queue; otherwise, the non-delayed instruction is kept in the launch buffer.

[0011] In some embodiments, the wake-up signal is also broadcast to the transmit buffer. After receiving the wake-up signal, the transmit buffer matches the first physical register number with the delay source field stored in each entry of the transmit buffer. When a match is successful, the pending delay flag bit of the corresponding entry in the matched transmit buffer is set to an invalid state so that the pending delay instruction can be directly moved into the transmit queue.

[0012] In some embodiments, generating a wake-up signal carrying the first physical register number and broadcasting it to the renaming table and delay queue for corresponding matching operations includes: After receiving the wake-up signal, the renaming table matches the first physical register number with the global delay source field. When the match is successful, it sets all delay flags of the current dependency chain in the renaming table and the global delay source field to an invalid state, so as to cut off the current dependency chain and track new long delay instructions. After receiving the wake-up signal, the delay queue matches the first physical register number with the delay source field stored in each entry of the delay queue. When the match is successful, the activation flag of the delayed instruction in the corresponding entry of the delay queue is set from invalid to valid, so as to remove the delayed instruction from the delay queue and move it into the transmission queue.

[0013] In some embodiments, the instruction to be delayed is removed from the delay queue using any of the following removal methods: The activation flag of each entry in the delay queue is checked sequentially according to the storage order. If there is a delayed instruction with the activation flag in a valid state, it is removed according to the storage order until all delayed instructions with the activation flag in a valid state are removed. The activation flag of each entry is checked sequentially according to the storage order of the delay queue. Only when the activation flag of the first entry is valid, the instruction to be delayed at the head of the queue is removed. The instruction to be delayed at the rear of the delay queue is removed after all the activation flags of the preceding instructions to be delayed are valid and removed in sequence. The activation flag bits of all entries in the delay queue are scanned in parallel, and delayed instructions with any valid activation flag bit are selected out in random order and removed without being restricted by the storage order of the delay queue.

[0014] In some embodiments, the method further includes: Monitor the number of pending instruction entries stored in the delay queue. When the delay queue is not empty, configure at least one entry in the launch queue as a reserved state. The launch queue entry in the reserved state is only used to receive pending instructions whose activation flag is valid when removed from the delay queue. When the delay queue becomes empty, the reserved state is released, restoring the entries in the launch queue to be available for use by instructions from the launch buffer.

[0015] In some embodiments, the method further includes: When the successor instruction is marked as a delayed instruction, the delay flag corresponding to the destination logic register of the successor instruction in the renaming table is set to an active state, so as to pass the current dependency chain down to the next level successor instruction with the destination logic register as the source operand.

[0016] In some embodiments, the renaming table is further provided with multiple global delay source fields, each global delay source field being used to record the delay source of a dependency chain; each entry of the renaming table is further provided with multiple delay flags, each of the multiple delay flags corresponding to a global delay source field.

[0017] In some embodiments, when multiple long-delayed instructions appear simultaneously in the instruction stream: If the number of currently tracked dependency chains has not reached the maximum number supported by the renaming table, then an idle global delay source field is allocated for the new long-delay instruction, the destination physical register number of the new long-delay instruction is written into the idle global delay source field, and the delay flag bit corresponding to the idle global delay source field in the entry of the renaming table corresponding to the destination logical register of the new long-delay instruction is set to a valid state. If the number of currently tracked dependency chains has reached the maximum number supported by the renaming table, then a release operation is performed on at least one occupied global delay source field, and the delay flag corresponding to the at least one global delay source field in the renaming table is set to an invalid state. Then, the released global delay source field is allocated for a new long delay instruction and a new dependency chain tracking is restarted.

[0018] Secondly, embodiments of this specification also provide an instruction issuing device based on dependency chain tracing, comprising: The first response module is used to respond to the identified long delay instruction by setting the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long delay instruction to a valid state, so as to mark the current dependency chain start point, and writing the first physical register number allocated to the destination logical register into the global delay source field of the renaming table. The second response module is used to respond to the fact that the delay flag bit of the corresponding entry in the renaming table of the source logic register of the subsequent instruction is in a valid state, to determine that the subsequent instruction is on the current dependency chain, to mark the subsequent instruction as a delayed instruction, and to pass the global delay source field to the delayed instruction. The delay and wake-up module is used to temporarily store the instruction to be delayed in the delay queue and initialize the activation flag of the instruction to be delayed to an invalid state. When the long delay instruction is completed or at a preset period before completion, a wake-up signal carrying the first physical register number is generated and broadcast to the renaming table and the delay queue for corresponding matching operations. When the matching is successful, the activation flag is set from an invalid state to an valid state. The shift module is used to shift delayed instructions with the activation flag set to a valid state from the delay queue into the launch queue.

[0019] Thirdly, embodiments of this specification also provide a processor, including: A renaming table, wherein each entry of the renaming table is set with a delay flag, and the renaming table is also set with at least one global delay source field; A launch cache, coupled after the renaming table, wherein each entry of the launch cache is configured with a pending delay flag and a delay source field; A delay queue, coupled after the launch buffer, wherein each entry of the delay queue is configured with an activation flag and a delay source field; A launch queue, coupled after the delay queue, is used to store instructions for preparing to launch, the instructions including at least long-delay instructions; An execution stage includes at least one execution pipeline for executing instructions emitted from the launch queue and generating a wake-up signal when the long-delayed instruction is completed or at a preset period before completion. The control logic connects the renaming table, the launch buffer, the delay queue, the launch queue, and the execution level, and is used to execute the steps of the method described in the first aspect.

[0020] Fourthly, embodiments of this specification also provide a chip, including a processor and a memory for storing processor-executable instructions, wherein the processor executes the instructions to implement the steps of the method described in the first aspect above.

[0021] Fifthly, embodiments of this specification also provide a computer storage medium storing computer program instructions that, when executed by a processor, implement the steps of the method described in the first aspect.

[0022] Sixthly, embodiments of this specification also provide a computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0023] This specification provides an instruction issuance method, apparatus, and chip based on dependency chain tracing. By setting the delay flag bit of the entry corresponding to the destination logic register of a long-delayed instruction in the renaming table to a valid state, the starting point of the current dependency chain is marked. The first physical register number allocated to the destination logic register is written into the global delay source field, achieving precise marking of the current dependency chain source. By checking the delay flag bit of the subsequent instruction source logic register to determine whether the subsequent instruction is on the current dependency chain, and when the delay flag bit is valid, the subsequent instruction is marked as a pending delay instruction, and the global delay source field is passed to the pending delay instruction, achieving automatic downward propagation of the dependency chain. By temporarily storing the pending delay instruction in the delay queue and initializing the activation flag bit to an invalid state, subsequent instructions dependent on the result of the long-delayed instruction no longer ineffectively occupy issuance queue entries, releasing issuance queue resources. By generating a wake-up signal carrying the first physical register number and broadcasting it to the renaming table and delay queue at a preset period before or after the long-delayed instruction completes execution, and upon successful matching, the activation flag bit of the pending delay instruction is set to a valid state and moved into the issuance queue, achieving precise wake-up and rollback of dependency chain instructions. The above method solves the problem in the prior art where subsequent instructions that rely on the results of long-delayed instructions occupy the issue queue entries for a long time but cannot be executed, resulting in low issue queue utilization. It can effectively improve issue queue utilization and processor execution efficiency without changing the issue queue depth. Attached Figure Description

[0024] The accompanying drawings, which are included to provide a further understanding of this specification and form part of it, do not constitute a limitation thereof. In the drawings: Figure 1 This is an architecture diagram of the back-end of a mainstream processor provided in the embodiments of this specification; Figure 2 This is a flowchart illustrating an instruction issuance method based on dependency chain tracing provided in the embodiments of this specification; Figure 3 This is a schematic diagram of the non-delayed instruction processing operation provided in the embodiments of this specification; Figure 4 This is a schematic diagram illustrating the matching operation of the renaming table and the delayed queue provided in the embodiments of this specification; Figure 5 This is a flowchart illustrating the anti-deadlock control steps provided in the embodiments of this specification; Figure 6 This is a diagram showing the information in the renaming table and issue buffer after the instruction stream enters the processor backend, as provided in the embodiments of this specification. Figure 7 This is an overall structural block diagram of the improved processor backend provided in the embodiments of this specification; Figure 8 This is a schematic diagram of the structural composition of an instruction issuing device based on dependency chain tracing provided in the embodiments of this specification; Figure 9 This is a schematic diagram of the structure of a chip provided in an embodiment of this specification. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0026] To improve execution efficiency, high-performance central processing units (CPUs) typically employ out-of-order execution microarchitecture. Front-end operations such as instruction fetching and decoding need to be executed sequentially. After register renaming, instructions enter the back-end for out-of-order execution, and finally, after instruction execution is complete, they are committed in order. Instructions that have completed register renaming are placed in the instruction issue queue to wait. When entering the instruction issue queue, the readiness of the source operands is checked. Source operands that are not ready will wait for the instructions they depend on to be broadcast and woken up before they complete execution. Wake-up source operands are marked as ready. Once all source operands are ready, the instruction can be issued and enter the execution pipeline (pipes: pipe e0~pipe e3) to complete the instruction operation.

[0027] like Figure 1 As shown, the backend of mainstream high-performance processors can currently include: Rename: The source register is translated from its logical register number (LRN) to its physical register number (PRN) through a rename map. At the same time, a new physical register (PRF) is allocated for the destination register, and the corresponding physical register number is written to the corresponding entry in the rename map.

[0028] Issue buffer: Renamed instructions are written sequentially to the issue buffer. This structure does not track the source register readiness information of the instructions; it only records instructions that have been renamed but cannot enter the issue queue temporarily.

[0029] Issue queue: After an instruction enters the issue queue, its source registers are checked for readiness. If all source registers are ready, the instruction can be picked and issued to the execution pipeline (pipe: pipee0~pipee3) for execution. The arbitration logic for selecting an instruction from multiple ready instructions is usually that the instruction that appears earlier in the instruction sequence takes precedence (usually the instruction that entered the issue queue earlier). All instructions must enter the issue queue before execution. Each entry in the issue queue contains source operand fields src1, src2, and src3, and a corresponding readiness flag bit rdy. The source operand fields are equivalent to the source registers.

[0030] Execution pipeline (pipe e0~pipe e3): The functional unit for instruction execution. Multiple execution pipelines can run in parallel, and the issue queue will have multiple logics for selecting ready instructions. At some point before the execution of an instruction issued to the execution pipeline is completed, the physical register number corresponding to the destination register of the instruction to be executed is broadcast to the issue queue, waking up instructions that depend on this register (instructions whose source register contains this register).

[0031] Physical register file (PRF): Not in Figure 1 The result of the instruction calculation is stored by indexing the physical register number, and it also provides data for the source operands of the instruction.

[0032] In existing technologies, instructions are typically written sequentially to the issue queue, where they wait for all source registers to become ready. When an instruction in the instruction stream requires a long time to complete (such as division or square root instructions, with instruction latency generally exceeding 10 clock cycles), instructions dependent on this instruction's destination register will also experience a prolonged delay before being awakened, during which time they must remain in the execution queue. Currently, the implementation cost of processor execution queues is high, and increasing the depth of the execution queue is difficult, while the depth of the execution queue significantly impacts processor execution efficiency. When the above situation occurs, the issue queue is occupied by a large number of instructions that cannot become ready in a short time. Instructions later in the instruction sequence may be ready, but there are no free issue queue entries to accommodate them, so they have no opportunity to be issued and executed, resulting in decreased issue queue utilization and affecting processor execution efficiency.

[0033] To address the aforementioned issues, embodiments of this specification provide an instruction issuance method, apparatus, and chip based on dependency chain tracing. This method can alleviate the problem of decreased issuance queue utilization efficiency caused by subsequent dependent instructions (i.e., follower instructions) of long-latency instructions occupying the issuance queue for extended periods without being ready or issued for execution. In cases where the issuance queue depth cannot be significantly increased, this method improves issuance queue utilization efficiency, thereby enhancing processor execution efficiency.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0035] This specification provides the operational steps of the methods described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the methods shown in the embodiments or drawings can be executed sequentially or in parallel.

[0036] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of the present invention. However, they do not mean that the applicant has used or necessarily used such solutions.

[0037] The following is a description of the key terms used in this application: Logical Register Number (LRN): A register number defined in the instruction set architecture. It is a register identifier visible to the programmer, such as X0 to X30 in the ARM architecture. The number of logical registers is limited, typically sixteen to thirty-two, and they are repeatedly used by different instructions.

[0038] Physical Register Number (PRN): An index number in the processor's internal physical register file, used to uniquely identify a physical memory location. Physical registers are not visible to the programmer and are used only internally by the processor.

[0039] Register renaming is a technique that dynamically maps logical register numbers in instructions to physical register numbers. It eliminates write-after-write and read-after-write conflicts, improving instruction-level parallelism. A renaming table stores the mapping relationship between each logical register and its corresponding physical register.

[0040] Long-latency instructions: Instructions whose execution delay exceeds a preset clock cycle threshold. Typical examples include division instructions and square root instructions, which typically require ten to thirty clock cycles to complete. In addition, memory access instructions that result in cache misses may also be classified as long-latency instructions.

[0041] Dependency chain: A sequence of instructions consisting of a long-delayed instruction and all its successor instructions that are directly or indirectly dependent on the result of that instruction. Each instruction in the dependency chain uses the result of its predecessor instruction as one of its source operands.

[0042] Delay source: The starting point of a dependency chain, i.e., the first physical register number (or destination physical register number) of a long-delayed instruction, used to uniquely identify a dependency chain.

[0043] Issue queue: A storage structure used to store instructions that have completed register renaming and are waiting for their source operands to be ready. Instructions in the issue queue monitor the readiness status of their source operands, and are eligible to be issued for execution when all source operands are ready.

[0044] Delayed Queue: A new instruction cache structure introduced in this invention, located between the issue cache and the issue queue, used to temporarily store subsequent instructions that depend on long-delayed instructions. The delayed queue does not actively monitor the readiness status of the source operands of internal instructions; it only waits for a wake-up signal from the long-delayed instruction.

[0045] Launch Buffer: An instruction cache structure located between the renaming level and the launch queue, used to temporarily store instructions that have been renamed but have not yet entered the launch queue.

[0046] Wake-up signal: A broadcast signal issued by the execution pipeline when the execution of a long-delayed instruction is completed or at a preset period before the completion of the instruction. It carries the first physical register number of the long-delayed instruction and is used to notify the subsequent instructions waiting for the result that their source operands are ready.

[0047] Activation flag: A status flag set for each entry in the delay queue, used to indicate whether the subsequent instruction has been awakened. When the activation flag is active, it means that the long-delayed instruction that the subsequent instruction was waiting for has completed execution and can be removed from the delay queue.

[0048] Delay flag: A status flag set for each entry in the transmit buffer to indicate whether the instruction needs to be temporarily stored in the delay queue.

[0049] Delay flag: One or more status flags set for each entry in the renaming table to indicate whether the logical register is on a traced dependency chain.

[0050] Global Delay Source Field: A register field set in the rename table to store the delay source of the currently being traced dependency chain. When the processor supports tracing multiple dependency chains simultaneously, multiple global delay source fields can be set in the rename table.

[0051] The following section, with reference to the accompanying drawings, provides a detailed description of an instruction issuance method based on dependency chain tracing, as described in the embodiments of this specification.

[0052] Figure 2 This is a flowchart illustrating an instruction issuance method based on dependency chain tracing provided in the embodiments of this specification. Although this specification provides method operation steps or apparatus structures as shown in the following embodiments or figures, more or fewer operation steps or module units may be included in the method or apparatus based on conventional or non-inventive effort. In steps or structures where there is no logically necessary causal relationship, the execution order of these steps or the module structure of the apparatus is not limited to the execution order or module structure described in the embodiments and figures of this specification. When the method or module structure is applied in actual devices or terminal products, it can be executed sequentially or in parallel according to the method or module structure shown in the embodiments or figures (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed processing environment). Figure 2 As shown, the method may include: S201: In response to the identified long delay instruction, set the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long delay instruction to a valid state to mark the current dependency chain start point, and write the first physical register number allocated to the destination logical register into the global delay source field of the renaming table. S202: In response to the source logic register of the successor instruction having the delay flag bit of the corresponding entry in the renaming table being valid, the successor instruction is determined to be on the current dependency chain, the successor instruction is marked as a delay instruction, and the global delay source field is passed to the delay instruction. S203: The instruction to be delayed is temporarily stored in the delay queue, and the activation flag of the instruction to be delayed is initialized to an invalid state. When the long delay instruction is completed or at a preset period before completion, a wake-up signal carrying the first physical register number is generated and broadcast to the renaming table and the delay queue for corresponding matching operations. When the matching is successful, the activation flag of the matched instruction to be delayed is set from an invalid state to an valid state. S204: Move the delayed instructions with the activation flag set to the active state from the delay queue into the launch queue.

[0053] Specifically, when the processor identifies the currently processed instruction (hereinafter referred to as the current instruction) as a long-delayed instruction, the long-delayed instruction first enters the renaming stage, executing the above-mentioned S201: The processor sets the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long-delayed instruction to a valid state. The purpose of this operation is to mark that the destination logical register of the long-delayed instruction is located at the beginning of the current dependency chain. At the same time, the processor allocates a new physical register for the destination logical register of the long-delayed instruction, called the first physical register number, and writes the first physical register number into the global delay source field of the renaming table. The purpose of this operation is to record the source identifier of the current dependency chain, so that all instructions in the entire dependency chain can know which long-delayed instruction they depend on.

[0054] Subsequently, when the successor instruction enters the renaming stage, S202 is executed: the processor checks each source logic register of the successor instruction and reads the delay flag bits of the corresponding entries in the renaming table. If any delay flag bit is valid, it indicates that the source operand of the successor instruction comes from a destination logic register in the current dependency chain, and therefore the successor instruction is located in the current dependency chain. At this time, the processor marks the successor instruction as a pending delay instruction and passes the value of the global delay source field in the renaming table to the pending delay instruction. This passing can be achieved by copying the value of the global delay source field to the delay source field of the corresponding entry in the issue buffer, so that the pending delay instruction knows which long-delayed instruction it depends on.

[0055] When a delayed instruction is removed from the issue buffer, the temporary storage operation described in S203 above is performed: the processor temporarily stores the delayed instruction in the delay queue instead of sending it directly to the issue queue. When writing the delayed instruction into the delay queue, the processor initializes its activation flag to an invalid state, indicating that the instruction has not yet been woken up and its dependent long-delayed instructions have not yet been completed.

[0056] When a long-delayed instruction completes execution in the execution pipeline or at a preset period before completion, the wake-up operation described in S203 is executed: the execution pipeline generates a wake-up signal carrying the first physical register number of the long-delayed instruction. The processor broadcasts this wake-up signal to the renaming table and the delay queue. The renaming table and the delay queue perform corresponding matching operations: the renaming table matches the physical register number carried by the wake-up signal with the global delay source field; if a match is successful, the delay flag and the global delay source field are cleared or set to an invalid state to break the current dependency chain; the delay queue matches the physical register number carried by the wake-up signal with the delay source field stored in each table entry, and sets the activation flag of the successfully matched delayed instructions from an invalid state to an active state, indicating that these instructions can be removed.

[0057] Finally, during the deferred queue removal, the above-described S204 is executed: the processor removes the deferred instructions whose activation flag is valid from the deferred queue and moves them into the issue queue. After these instructions enter the issue queue, since the long-deferred instructions they depend on have completed, their source operands will be marked as ready, and thus they can be issued and executed quickly.

[0058] The aforementioned preset period can refer to one or more clock cycles earlier than the completion of a long-delayed instruction. The wake-up signal can be generated and broadcast upon completion of the long-delayed instruction, or it can be generated and broadcast one or more clock cycles before completion. When the wake-up signal is generated and broadcast in advance, the delayed instructions already activated in the delay queue can begin their removal operation earlier, thus shortening the waiting time from wake-up to issuance for dependency chain instructions. The value of this preset period can be statically set through hardware configuration registers, or it can be dynamically adjusted by the processor at runtime based on the actual execution progress of the long-delayed instruction or the current queue state.

[0059] It should be noted that the source logic register of a long-delayed instruction can be a logic register that stores the source operand, such as the logic registers used for the dividend and divisor in a division instruction. The destination logic register of a long-delayed instruction can be a logic register that stores the calculation result, such as the logic registers storing the quotient and remainder in a division instruction. The source logic register of a subsequent instruction can be a logic register that reads the source operand from the result of the long-delayed instruction or the preceding instruction in the dependency chain. The destination logic register of a subsequent instruction can be a logic register that stores the calculation result of the subsequent instruction.

[0060] For example, a division instruction divides LRN2 and LRN3, storing the result in LRN1. In this case, LRN1 is the destination logical register for the division instruction, and LRN2 and LRN3 are the source logical registers. Similarly, an addition instruction adds LRN1 and LRN5, storing the result in LRN4. In this case, LRN1 and LRN5 are the source logical registers for the addition instruction. LRN1 is precisely the destination logical register for the division instruction; therefore, the addition instruction depends on the result of the division instruction and is located on the dependency chain of the division instruction. The value stored in LRN5 is independent data and does not depend on the result of the division instruction. LRN4 is the destination logical register for the addition instruction.

[0061] By renaming the table to mark the starting point of the current dependency chain and passing the global delay source field to the instruction to be delayed, accurate identification of the dependency chain is achieved. By temporarily storing the instruction to be delayed in the delay queue, the instruction to be delayed is decoupled from the launch queue, solving the technical problem of the instruction to be delayed ineffectively occupying launch queue resources. Through the broadcasting and matching of wake-up signals, accurate wake-up and rollback of dependency chain instructions are achieved. Ultimately, without changing the launch queue depth, launch queue utilization and processor execution efficiency can be effectively improved.

[0062] In some embodiments, the process of identifying long-delay instructions may be included before S201, specifically including: When the current instruction is not a memory access instruction, the instruction opcode of the current instruction is matched with the preset long-delay instruction type. If the match is successful, the current instruction is identified as a long-delay instruction. When the current instruction is a memory access instruction, the memory access latency prediction mechanism is used to predict whether a cache miss will occur. If so, the memory access instruction is determined to be a long-latency instruction.

[0063] Specifically, before an instruction enters the renaming stage for long-delayed instructions, the processor first identifies and determines whether the current instruction is a long-delayed instruction. The processor internally maintains a long-delayed instruction type table, which lists all instruction types identified as long-delayed, such as division instructions, square root instructions, and floating-point arithmetic instructions. The processor can read the opcode of the current instruction and compare or match it with the long-delayed instruction type in the long-delayed instruction type table. If a match is found, the current instruction is determined to be a long-delayed instruction. If no match is found, it is processed as a regular instruction.

[0064] For memory access instructions, the processor uses cache prediction logic to determine whether a cache miss is possible. The cache prediction logic can be as follows: if the address of the memory access instruction has not been cache-hunted in previous accesses, it is predicted or determined to be a cache miss; if the address of the memory access instruction has been cache-hunted in the most recent access, it is predicted to be a cache hit. If a cache miss is predicted or determined, the memory access instruction is classified as a long-latency instruction. Otherwise, it is processed as a regular memory access instruction.

[0065] After the above identification and judgment are completed, instructions identified as long-delay instructions will enter the long-delay instruction renaming stage, that is, the operation in S201 above will be executed. Instructions not identified as long-delay instructions will be renamed according to the normal process, and the marking operation in S201 above will not be executed.

[0066] It should be noted that the long-latency instructions in this invention can include instructions such as division and square root instructions, which require many clock cycles to complete in the execution unit, as well as memory access instructions with long latency. For memory access instructions, the processor can select long-latency memory access instructions as the source of latency through speculative means. For example, when the address of a memory access instruction is not found in the cache, data needs to be read from main memory, and the latency can reach hundreds of clock cycles. In this case, the memory access instruction can be identified as a long-latency instruction, and subsequent dependent chain instructions can be temporarily stored in the latency queue. This invention can cover more types of long-latency instruction scenarios and has a wide range of applications.

[0067] By combining instruction opcode matching and cache prediction logic, the processor can accurately distinguish between long-latency instructions and ordinary instructions, thus providing the correct starting point for subsequent dependency chain tracing and avoiding unnecessary resource waste caused by mislabeling ordinary instructions as long-latency instructions.

[0068] In some embodiments, the operation of writing long-delay instructions to the transmit buffer may be included after S201 above: The long delay instruction is written into the launch buffer, and the pending delay flag of the corresponding entry of the long delay instruction in the launch buffer is set to an invalid state, so that the long delay instruction can be directly moved into the launch queue.

[0069] Specifically, after a long-delayed instruction is renamed, it is written to the issue cache. During writing, the processor sets the deferred flag of the corresponding entry in the issue cache. Since the long-delayed instruction itself does not depend on the result of any other instruction, its deferred flag is set to an invalid state (e.g., 0). When the long-delayed instruction is removed from the issue cache, the processor reads its deferred flag, finds it invalid, and moves it directly into the issue queue according to the routing rules, rather than sending it to the deferred queue. The routing rules are as follows: instructions with an invalid deferred flag are directly moved into the issue queue, while instructions with a valid deferred flag are temporarily stored in the deferred queue. In this way, long-delayed instructions can enter the issue queue and begin execution as quickly as possible, thereby shortening their startup latency and producing results quickly to wake up subsequent instructions in their dependency chain.

[0070] By setting the pending flag of the corresponding entry in the issue buffer to an invalid state, long-delayed instructions can bypass the delay queue and directly enter the issue queue to start execution, shortening the execution start time of long-delayed instructions and helping to wake up subsequent instructions on the dependency chain as soon as possible.

[0071] In some embodiments, before passing the global delay source field to the instruction to be delayed in S202 above, the operation of writing the instruction to be delayed into the transmit buffer may also be included: The delayed instruction is written into the launch buffer, and the delayed flag of the corresponding entry of the delayed instruction in the launch buffer is set to a valid state, so as to temporarily store the delayed instruction in the delay queue.

[0072] Specifically, after a pending instruction is identified as being on the dependency chain during the renaming phase, it is written to the issue cache. During writing, the processor can set the pending flag of the corresponding entry in the issue cache for that instruction. Since the pending instruction depends on a long-delayed instruction that has not yet been completed, its pending flag is set to a valid state (e.g., 1). When the pending instruction is removed from the issue cache, the processor reads its pending flag, finds it to be valid, and temporarily stores it in the delay queue according to the routing rules, instead of directly sending it to the issue queue. In this way, the pending instruction does not enter the issue queue and occupy valuable entries, but is safely stored in the delay queue awaiting wake-up.

[0073] By setting the pending-delay flag of the corresponding entry in the launch buffer to a valid state, the pending-delay instruction can be correctly guided to the delay queue, thus decoupling the pending-delay instruction from the launch queue and preventing the pending-delay instruction from invalidally occupying launch queue resources.

[0074] In some embodiments, passing the global delay source field to the instruction to be delayed in S202 above may, in specific implementation, include: Copy the value of the global delay source field in the rename table to the delay source field of the corresponding entry in the launch cache for the instruction to be delayed.

[0075] Specifically, after the processor sets the delay flag bit of the corresponding entry in the issue cache for the aforementioned delayed instruction, or simultaneously, the processor can also read the value of the currently valid global delay source field in the rename table (i.e., the first physical register number of the long-delayed instruction, such as PRN100), and copy this value to the delay source field of the corresponding entry in the issue cache for that delayed instruction, or copy it to the delay source field of the corresponding entry in the issue cache for that delayed instruction. This operation is achieved by writing the value of the global delay source field to the delay source field of the delayed instruction when writing to the issue cache. In this way, each delayed instruction records its dependent delay source in the issue cache. When the delayed instruction is subsequently removed from the issue cache and written to the delay queue, the value of the delay source field is copied to the corresponding entry in the delay queue. When the long-delayed instruction completes and broadcasts a wake-up signal, the delay queue can determine which delayed instructions should be activated by comparing the delay source fields stored in each entry with the first physical register number carried by the wake-up signal. The launch buffer can also use the same matching method to directly clear the delay flag of pending instructions that have not yet been moved out, allowing them to bypass the delay queue and enter the launch queue directly.

[0076] By copying the value of the global delay source field in the rename table to the delay source field of the corresponding entry in the launch buffer of the instruction to be delayed, the dependency chain source information is accurately transmitted when the instruction to be delayed is written to the launch buffer and transferred to the delay queue along with the instruction flow, providing a comparison basis for the matching operation during the subsequent wake-up signal broadcast.

[0077] In some embodiments, see Figure 3 As shown, the above-mentioned S201 may include processing operations for non-delayed instructions: S301: In response to the fact that the delay flag bits corresponding to the source logic register of the subsequent instruction in the renaming table are all in an invalid state, it is determined that the subsequent instruction is not on the current dependency chain, and the subsequent instruction is marked as a non-delay instruction. S302: Write the non-delayed instruction into the transmit buffer, and set the delay flag bit of the corresponding entry of the non-delayed instruction in the transmit buffer to an invalid state; S303: If there is an idle entry in the launch queue, the non-delayed instruction is directly moved into the launch queue; otherwise, the non-delayed instruction is kept in the launch buffer.

[0078] Specifically, when a subsequent instruction enters the renaming stage, the processor checks each source logic register of the subsequent instruction and reads the delay flag bit of the corresponding entry in the renaming table. If the delay flag bits of all source logic registers of the subsequent instruction are invalid (i.e., no source logic register is marked as being on the current dependency chain), it means that the subsequent instruction does not depend on the result of any incomplete long-delayed instruction. In this case, the processor can mark the subsequent instruction as a non-delayed instruction.

[0079] Subsequently, the processor writes the non-delayed instruction to the issue buffer. During writing, the processor sets the delay flag of the corresponding entry in the issue buffer to an invalid state (e.g., 0), indicating that the instruction does not need to be temporarily stored in the delay queue. When the non-delayed instruction is removed from the issue buffer, the processor checks whether there is a free entry in the issue queue. If there is a free entry in the issue queue, the non-delayed instruction is directly moved into the issue queue, and it can then wait for the source operand to become ready before being issued and executed. If the issue queue is full (i.e., all entries are occupied), the non-delayed instruction is kept in the issue buffer, waiting for a free entry to become available in the issue queue before being moved into it.

[0080] It should be noted that non-delayed instructions can include two categories: one is independent instructions whose source operands do not depend on the result of any long-delayed instructions; the other is the long-delayed instruction itself, whose delay flag is also set to invalid. Both types of instructions are processed according to the same routing rules: when the delay flag is invalid, it is directly moved into the transmit queue; when the delay flag is valid, it is temporarily stored in the delay queue.

[0081] By invalidating the delay flag bits in the renaming table of the source logic registers of subsequent instructions, the subsequent instructions are marked as non-delayed instructions, and the delay flag bit of their corresponding entries in the issue buffer is set to invalid. This allows non-delayed instructions to be directly moved into the issue queue according to the splitting rules when removed from the issue buffer. By moving them directly into the issue queue when there are free entries and retaining them in the issue buffer when the issue queue is full, non-delayed instructions are prevented from being blocked or discarded due to a full issue queue. Furthermore, sharing the same splitting rules with delayed instructions simplifies hardware implementation.

[0082] In some embodiments, the wake-up signal in S203 above can also be broadcast to the transmit buffer. After receiving the wake-up signal, the transmit buffer matches the first physical register number with the delay source field stored in each entry of the transmit buffer. When the match is successful, the delay flag bit of the corresponding entry in the matched transmit buffer is set to an invalid state so as to move the delay instruction directly into the transmit queue.

[0083] Specifically, when a long-delayed instruction completes execution or at a preset period before completion, the wake-up signal generated by the execution pipeline can be broadcast not only to the rename table and the delay queue, but also to the issue buffer. The issue buffer may contain some instructions that have not yet been removed and are awaiting delay. The awaiting delay flag of these instructions is valid, and their delay source field stores the first physical register number of the long-delayed instruction they depend on.

[0084] After receiving a wake-up signal, the issue buffer iterates through all valid entries, matching the delay source field of each entry with the first physical register number carried in the wake-up signal. If a match is found, it indicates that the long-delayed instruction on which the delayed instruction in that entry depends has completed. At this point, the processor sets the delay flag of that entry from a valid state to an invalid state (e.g., 0). Subsequently, when these instructions are removed from the issue buffer, because their delay flag has become invalid, they will be directly moved into the issue queue according to the routing rules, without having to go through the delay queue. In this way, delayed instructions that have not yet entered the delay queue can bypass the delay queue and directly enter the issue queue, speeding up the execution pipeline for these instructions.

[0085] By broadcasting the wake-up signal to the issue buffer, the issue buffer can receive notifications of the completion of long-delayed instructions. The issue buffer matches the first physical register number carried by the wake-up signal with the delay source field stored in each entry in the issue buffer, and sets the pending delay flag of the matched entry to an invalid state when a match is successful. This allows pending instructions that have not yet been removed from the issue buffer to be "released" in advance, so that they can directly enter the issue queue when removed from the issue buffer later, without having to go through the delay queue again, further shortening the latency of these instructions entering the execution pipeline.

[0086] In some embodiments, see Figure 4 As shown, the process in S203 above, which involves generating a wake-up signal carrying the first physical register number and broadcasting it to the renaming table and the delay queue for corresponding matching operations, may, in a specific implementation, include: S401: After receiving the wake-up signal, the renaming table matches the first physical register number with the global delay source field. When the match is successful, it sets all delay flags of the current dependency chain in the renaming table and the global delay source field to an invalid state, so as to cut off the current dependency chain and track new long delay instructions. S402: After receiving the wake-up signal, the delay queue matches the first physical register number with the delay source field stored in each entry of the delay queue. When the match is successful, the activation flag of the delayed instruction in the corresponding entry of the delay queue is set from invalid to valid, so as to remove the delayed instruction from the delay queue and move it into the transmission queue.

[0087] Specifically, when a long-delayed instruction completes execution or at a preset period before completion, the execution pipeline generates a wake-up signal carrying the first physical register number of the long-delayed instruction and broadcasts it to the renaming table and the delay queue.

[0088] Upon receiving a wake-up signal, the rename table compares or matches the first physical register number carried in the wake-up signal with the value of the global delay source field stored in the rename table. If they match (i.e., a successful match), it indicates that the source instruction of the currently tracing dependency chain has completed (i.e., the long-delay instruction has been executed). At this point, the processor sets all delay flags of the current dependency chain in the rename table (i.e., all delay flags corresponding to the destination logic registers marked as being located on this dependency chain) to an invalid state, and also sets the global delay source field to an invalid state. This operation breaks the current dependency chain, preventing subsequent new instructions from being incorrectly marked as belonging to a completed dependency chain, while simultaneously releasing the global delay source field for tracing new long-delay instructions.

[0089] After receiving a wake-up signal, the delay queue compares the first physical register number carried in the wake-up signal with the delay source field stored in each entry of the delay queue in parallel. For entries that match successfully, it indicates that the long-delayed instruction on which the delayed instruction stored in that entry depends has been completed. At this point, the processor sets the activation flag of these entries from an invalid state to a valid state. Delayed instructions with valid activation flags can then be removed from the delay queue and moved into the issue queue, awaiting execution.

[0090] Upon receiving a wake-up signal via the renaming table, the first physical register number is matched against the global delay source field. If a match is successful, all delay flags of the current dependency chain and the global delay source field in the renaming table are set to invalid, ensuring that completed dependency chains are precisely severed and preventing subsequent new instructions from being incorrectly marked as belonging to that dependency chain. Simultaneously, the global delay source field is released for tracking new long-delayed instructions. Similarly, upon receiving a wake-up signal via the delay queue, the first physical register number is matched against the delay source fields stored in each entry. If a match is successful, the activation flag of the matched delayed instruction is set from invalid to valid, ensuring that only delayed instructions on dependency chains belonging to currently completed long-delayed instructions are activated, while delayed instructions on other dependency chains remain in a waiting state. This achieves selective and precise wake-up of dependency chain instructions.

[0091] In some embodiments, the above-mentioned delayed instructions can be removed from the delay queue using any of the following removal methods: The activation flag of each entry in the delay queue is checked sequentially according to the storage order. If there is a delayed instruction with the activation flag in a valid state, it is removed according to the storage order until all delayed instructions with the activation flag in a valid state are removed. The activation flag of each entry is checked sequentially according to the storage order of the delay queue. Only when the activation flag of the first entry is valid, the instruction to be delayed at the head of the queue is removed. The instruction to be delayed at the rear of the delay queue is removed after all the activation flags of the preceding instructions to be delayed are valid and removed in sequence. The activation flag bits of all entries in the delay queue are scanned in parallel, and delayed instructions with any valid activation flag bits are selected out of order and removed without being restricted by the storage order of the delay queue.

[0092] Specifically, when a delayed instruction in the delay queue is awakened (i.e., the activation flag is set to a valid state), it needs to be removed from the queue and sent to the launch queue. This invention provides three selectable removal methods, which the processor can choose according to design requirements or dynamically switch between in different scenarios. The specific removal methods are as follows: The first removal method (sequential full removal): The processor repeatedly performs the following removal operation until there are no more instructions with valid activation flags in the delay queue, that is, until all instructions with valid activation flags are removed: First, starting from the head of the delay queue, the processor checks the activation flags of each entry sequentially, finds the first instruction with a valid activation flag, and removes it. After removal, the entry occupied by that instruction is released, and subsequent instructions move forward sequentially. Then, the processor starts again from the new head of the queue, searches for the first instruction with a valid activation flag, and removes it. This process is repeated until no more instructions with valid activation flags are found after traversing the entire delay queue. The characteristic of this method is that regardless of whether the activated instructions are consecutive in the queue, and regardless of whether there are any inactive instructions in between, as long as there is any instruction with a valid activation flag in the delay queue, the removal operation will continue until all activated instructions have been removed. Inactive instructions remain unaffected and continue to be held in the delay queue awaiting subsequent wake-up.

[0093] The second shift method (conditional shift): The processor only checks the activation flag of the head entry. Only when the activation flag of the head entry is valid is the deferred instruction at the head of the queue shifted out. After shifting, the second instruction in the original queue becomes the new head, and the processor checks the activation flag of the new head again, repeating the above process. Deferred instructions at the back of the queue must wait for all preceding instructions to be activated and shifted out before becoming the head and being shifted out. This method strictly guarantees that the shift order of instructions is consistent with the storage order; even if a later instruction has been activated, it must wait for its preceding instruction to be shifted out first.

[0094] The third removal method (out-of-order removal): The processor scans the activation flags of all entries in the delay queue in parallel, that is, it reads the activation flags of all entries at the same time. Then, from all the instructions to be delayed that have valid activation flags, it randomly selects one or more instructions to be removed, and the removal order is not restricted by the storage order of the delay queue. For example, the processor can prioritize removing instructions that are earlier in the program sequence, or it can prioritize removing older instructions, or it can select randomly. In this method, all activated instructions to be delayed have a chance to be removed, and there is no problem of being blocked by inactive instructions.

[0095] For example: Suppose there are 5 entries in the delay queue, stored in the following order from head to tail: Instruction A, Instruction B, Instruction C, Instruction D, and Instruction E. The activation flags of each instruction are as follows: Instruction A is active, Instruction B is active, Instruction C is inactive, Instruction D is active, and Instruction E is active.

[0096] For the first removal method (sequential full removal): The processor repeatedly searches for the first active instruction starting from the head of the queue and removes it. In the first round, instruction A is removed, and the queue becomes B, C, D, E; in the second round, instruction B is removed, and the queue becomes C, D, E; in the third round, instruction D is removed, and the queue becomes C, E; in the fourth round, instruction E is removed, and the queue becomes C. Finally, instructions A, B, D, and E are all removed, while instruction C is retained.

[0097] For the second removal method (conditional sequential removal): The processor only checks the head instruction. In the first round, the head instruction A is activated, so instruction A is removed, and the queue becomes B, C, D, E. In the second round, the new head instruction B is activated, so instruction B is removed, and the queue becomes C, D, E. In the third round, the new head instruction C is not activated, so removal stops. Finally, instructions A and B are removed, while instructions C, D, and E are retained (instructions D and E are activated, but cannot be removed because they are blocked by instruction C).

[0098] For the third method of removal (out-of-order removal): The processor scans all instructions in parallel, selects the active instructions A, B, D, and E at once, and then removes them out of order, unaffected by instruction C. Ultimately, instructions A, B, D, and E are all removed, while instruction C remains.

[0099] This invention provides a variety of flexible delayed queue removal strategies. The first method continuously removes instructions until all activated instructions are removed, the second method strictly guarantees the removal order, and the third method removes all activated instructions at once with the highest efficiency.

[0100] In some embodiments, see Figure 5 As shown, deadlock prevention control steps may also be included after S204 above: S501: Monitor the number of entries of delayed instructions stored in the delay queue. When the delay queue is not empty, configure at least one entry in the launch queue as a reserved state. The launch queue entry in the reserved state is only used to receive delayed instructions whose activation flag is valid when removed from the delay queue. S502: When the delay queue becomes empty, the reserved state is released, so that the entries in the launch queue are restored to be available for use by instructions from the launch buffer.

[0101] Specifically, to prevent the system from entering a deadlock state, this invention also provides a deadlock prevention control mechanism. Deadlock scenarios can occur as follows: If the launch queue is completely filled with non-delayed instructions or long-delayed instructions from the launch buffer, while the delay queue contains activated delayed instructions waiting to be moved into the launch queue, these activated delayed instructions cannot enter the launch queue. Simultaneously, instructions in the launch queue may not be able to complete execution and release entries in a timely manner due to dependencies or execution delays, leading to a circular waiting deadlock in the system.

[0102] To address the aforementioned issues, a monitoring unit can be incorporated into the processor to continuously monitor the number of pending instruction entries stored in the delay queue. When the monitoring unit detects that the delay queue is not empty (i.e., there is at least one pending instruction in the delay queue), the processor configures at least one entry in the issue queue as reserved. Issue queue entries in this reserved state have specific occupancy rules: they are only used to receive pending instructions whose activation flag is valid when removed from the delay queue; any instructions from the issue buffer (including non-pending instructions and long-delayed instructions) are prohibited from occupying these reserved entries.

[0103] When all pending instructions in the delay queue have been removed (i.e., the delay queue becomes empty), the processor releases the reserved state of the issue queue entries, restoring them to their normal state. After restoration, these entries are available for normal use by instructions from the issue buffer.

[0104] The number of reserved entries can be configured according to design requirements. For example, one entry can always be reserved to ensure that there is at least one available position for delayed instructions in the delay queue. The number of reserved entries can also be dynamically adjusted based on the depth of the delay queue. The specific position of a reserved entry can be a fixed position in the launch queue (such as the last entry) or a dynamically allocated position.

[0105] By reserving a launch queue entry when the delay queue is not empty for receiving instructions that have been moved out of the delay queue, the deadlock problem of activated instructions waiting to be delayed being unable to be moved in due to the launch queue being full is avoided, thus ensuring the normal operation of the system.

[0106] In some embodiments, after marking the successor instruction as a delayed instruction in S202 above, the operation of passing the dependency chain down may also be included: When the successor instruction is marked as a delayed instruction, the delay flag corresponding to the destination logic register of the successor instruction in the renaming table is set to an active state, so as to pass the current dependency chain down to the next level successor instruction with the destination logic register as the source operand.

[0107] Specifically, when a successor instruction is determined to be on the current dependency chain and marked as a delayed instruction during the renaming phase, the processor not only needs to mark the successor instruction itself, but also needs to mark the destination logic register of the successor instruction as being on the dependency chain, so as to realize the downward propagation of the dependency chain.

[0108] The specific operation can be as follows: During the renaming phase, after the processor allocates a new physical register for the destination logical register of the subsequent instruction, it sets the delay flag bit of the entry in the renaming table corresponding to the destination logical register to a valid state. Thus, when a next-level instruction (i.e., a third-level instruction) enters the renaming phase with the destination logical register as its source operand, the processor reads the delay flag bit corresponding to the source logical register in the renaming table, finds it to be valid, and thus determines that the third-level instruction is also on the current dependency chain, marking it as a delayed instruction.

[0109] In this way, dependency chain marking propagates down the data dependency hierarchy: the destination logic register of a long-latency instruction is marked → the first-level successor instruction is marked because its source register is marked, and its destination register is also marked → the second-level successor instruction is marked because its source register is marked, and its destination register is also marked → and so on. In this way, all instructions in the entire dependency chain can be automatically identified without additional tracing logic.

[0110] For example, as mentioned earlier, the destination logic register LRN1 of a long-delayed instruction (division instruction) is marked as valid in the renaming table. The first-level successor instruction (addition instruction) is determined to be a delayed instruction because its source logic register LRN1 is marked, and its destination logic register LRN4 is also marked as valid. When the second-level successor instruction (subtraction instruction) enters the renaming stage with LRN4 as its source logic register, it reads that the delay flag of LRN4 is valid, and is therefore automatically determined to be a delayed instruction. Thus, the dependency chain is passed from LRN1 to LRN4, and then to LRN6, achieving automatic tracing of the complete dependency chain.

[0111] By setting the delay flag of the destination logic register of the subsequent instruction to an active state, the dependency chain marker can be automatically passed down along the data dependency relationship. Subsequent instructions can be identified as delayed instructions without additional judgment, thus realizing complete tracking of the dependency chain.

[0112] In some embodiments, the above-described renaming table can also support tracking multiple dependency chains simultaneously: The renaming table also has multiple global delay source fields, each of which records the delay source of a dependency chain; each entry in the renaming table also has multiple delay flags, each of which corresponds to a global delay source field.

[0113] In some embodiments, when multiple long-delayed instructions appear simultaneously in the instruction stream: If the number of currently tracked dependency chains has not reached the maximum number supported by the renaming table, then an idle global delay source field is allocated for the new long-delay instruction, the destination physical register number of the new long-delay instruction is written into the idle global delay source field, and the delay flag bit corresponding to the idle global delay source field in the entry of the renaming table corresponding to the destination logical register of the new long-delay instruction is set to a valid state. If the number of currently tracked dependency chains has reached the maximum number supported by the renaming table, then a release operation is performed on at least one occupied global delay source field, and the delay flag corresponding to the at least one global delay source field in the renaming table is set to an invalid state. Then, the released global delay source field is allocated for a new long delay instruction and a new dependency chain tracking is restarted.

[0114] Specifically, in the aforementioned embodiments, the renaming table only supports tracking one dependency chain at a time. To further improve the processor's parallel processing capabilities, when multiple long-delay instructions appear simultaneously in the instruction stream, this invention also provides an implementation method for simultaneously tracking multiple dependency chains.

[0115] In terms of hardware architecture, the renaming table can have multiple global latency source fields, for example, K global latency source fields (K can be an integer greater than or equal to 2). Each global latency source field records the latency source of an independent dependency chain (i.e., the first physical register number of the long-latency instruction on that dependency chain). Correspondingly, each entry in the renaming table has K latency flags, each of which corresponds to a global latency source field. Specifically, the i-th latency flag corresponds to the i-th global latency source field and is used to indicate whether the logical register corresponding to the current entry is located on the i-th dependency chain.

[0116] When a long-delayed instruction is identified, the processor checks whether the number of dependency chains currently being tracked has reached the maximum number K supported by the rename table. If not, a free global delay source field (i.e., a currently unused field) is allocated for the new long-delayed instruction, the first physical register number of the long-delayed instruction is written to the free field, and the delay flag corresponding to the free field in the entry of the rename table corresponding to the destination logical register of the long-delayed instruction is set to an active state. Thus, the destination logical register of the long-delayed instruction is marked as being located at the start of a newly created dependency chain.

[0117] If the number of currently tracked dependency chains has reached the maximum number K (i.e., all global latency source fields are occupied), the processor cannot allocate a free global latency source field for a newly identified long-latency instruction. In this case, the processor performs a release operation on at least one occupied global latency source field (e.g., invalidates the field or marks it as free) and invalidates the latency flag corresponding to the released global latency source field in the renaming table. This release operation can be performed on all occupied global latency source fields (i.e., clears them all), or it can be performed on some occupied global latency source fields (e.g., selects the earliest established dependency chain or the lowest priority dependency chain for release). Then, the new long-latency instruction is treated as the starting point of a new dependency chain, a released global latency source field is allocated to it, its first physical register number is written to that field, and the corresponding latency flag is set to valid to restart new dependency chain tracking.

[0118] When a subsequent instruction enters the renaming phase, the processor checks the K delay flags in the renaming table entry corresponding to each source logic register of the subsequent instruction. If any one of the delay flags is valid, the processor determines that the subsequent instruction is on the dependency chain corresponding to that valid flag, marks it as a delayed instruction, and passes the value of the corresponding global delay source field to the delayed instruction. If multiple delay flags are valid simultaneously, the subsequent instruction is marked as belonging to multiple dependency chains, and the values ​​of the corresponding multiple global delay source fields are recorded in the delay source field of the corresponding entry in the issue buffer.

[0119] When a long-delayed instruction in a multi-dependency chain completes execution or at a preset period before completion, a wake-up signal is generated carrying the first physical register number of that long-delayed instruction. Upon receiving the wake-up signal, the rename table matches this number with the values ​​of each global delay source field, setting only the globally delayed source field that matches successfully to an invalid state, and clearing the delay flags corresponding to that global delay source field in all table entries. Other global delay source fields and other delay flags remain unchanged. In this way, the dependency chain corresponding to the completed long-delayed instruction is precisely severed, while other incomplete dependency chains continue to be tracked normally.

[0120] By setting multiple global latency source fields and corresponding latency flags, the renaming table can simultaneously track multiple independent dependency chains. Through rules such as allocating free fields, releasing at least one occupied global latency source field when the limit is reached, and selectively clearing only matching dependency chains upon wakeup, complete management and precise tracking of multiple dependency chains are achieved, improving the processor's processing power and resource utilization in scenarios with multiple long-latency instructions running concurrently. This invention can simultaneously track and manage multiple dependency chains in scenarios with multiple long-latency instructions running concurrently, further enhancing the processor's parallel processing capabilities.

[0121] The following example of a specific instruction flow fully demonstrates the processing procedure of this invention. For ease of explanation, assume the processor is configured as follows: the issue queue depth is four entries, and the delay queue depth is four entries. Assume the division instruction is predefined as a long-delay instruction with an execution delay of twenty clock cycles.

[0122] Assume the instruction stream contains the following seven instructions in sequence: The first instruction is a division instruction, which divides the values ​​in logic registers LRN2 and LRN3, and stores the result in logic register LRN1. This instruction is a long-delay instruction.

[0123] The second instruction is an addition instruction, which adds the values ​​in logic registers LRN1 and LRN5, and stores the result in logic register LRN4. The source operand of this instruction includes LRN1, which is the destination logic register of the first instruction. Therefore, the second instruction depends on the result of the first instruction.

[0124] The third instruction is a subtraction instruction, which subtracts the value in logic register LRN4 from the value in LRN7 and stores the result in logic register LRN6. The source operand of this instruction includes LRN4, which is the destination logic register of the second instruction. Therefore, the third instruction depends on the result of the second instruction, and thus indirectly depends on the result of the first instruction.

[0125] The fourth instruction is a multiplication instruction, which multiplies the values ​​in logic registers LRN9 and LRN10, and stores the result in logic register LRN8. The source operand of this instruction does not depend on the result of any of the preceding instructions; therefore, it is an independent instruction.

[0126] The fifth instruction is a logical AND instruction, which performs a bitwise AND operation on the values ​​in logic registers LRN12 and LRN13, and stores the result in logic register LRN11. This instruction is also a standalone instruction.

[0127] The sixth instruction is a logical OR instruction, which performs a bitwise OR operation on the values ​​in logic registers LRN15 and LRN16, and stores the result in logic register LRN14. This instruction is also a standalone instruction.

[0128] The seventh instruction is an addition instruction, which adds the values ​​in logic registers LRN18 and LRN19 and stores the result in logic register LRN17. This instruction is also a standalone instruction.

[0129] The first, second, and third instructions form a dependency chain: the first instruction is the source long-delay instruction, the second instruction directly depends on the first instruction, and the third instruction indirectly depends on the first instruction. Instructions four through seven are all independent instructions and do not depend on any long-delay instructions.

[0130] The processing procedure can be as follows: The first step is to process the first instruction (long-delayed instruction).

[0131] The processor identifies the first instruction as a long-delay instruction, sets the delay flag of the corresponding entry in the renaming table of its destination logic register LRN1 to a valid state, and marks the start of the current dependency chain. At the same time, it assigns the first physical register number PRN100 to LRN1 and writes PRN100 into the global delay source field of the renaming table.

[0132] The first instruction is written to the transmit buffer, and its pending delay flag is set to an invalid state (e.g., 0). When the instruction is removed from the transmit buffer, because its pending delay flag is invalid, it is directly moved into the transmit queue according to the diversion rules.

[0133] The second step is to process the second instruction (which depends on the first instruction).

[0134] The processor checks the delay flag bit corresponding to the source logic register LRN1 of the second instruction in the renaming table and finds it to be valid. Therefore, it determines that the second instruction is on the current dependency chain and marks it as a delayed instruction.

[0135] Write the second instruction to the launch buffer, set its pending delay flag to a valid state (e.g., 1), and copy the value PRN100 of the global delay source field to the delay source field of the corresponding entry in the launch buffer.

[0136] When the second instruction is removed from the transmit buffer, it is temporarily stored in the delay queue according to the diversion rule because its pending delay flag is in a valid state, and its activation flag is initialized to an invalid state (such as 0).

[0137] The third step is to process the third instruction (which depends on the second instruction's successor).

[0138] The processor checks the delay flag in the renaming table for the source logic register LRN4 of the third instruction. Since the delay flag in the destination logic register LRN4 was already set to a valid state when the second instruction was marked as a delayed instruction (passing down the dependency chain), the processor finds that the delay flag in LRN4 is valid, determines that the third instruction is in the current dependency chain, and marks it as a delayed instruction.

[0139] Write the third instruction to the launch buffer, set its pending delay flag to a valid state (e.g., 1), and copy the value PRN100 of the global delay source field to the delay source field of the corresponding entry in the launch buffer.

[0140] When the third instruction is removed from the transmit buffer, it is temporarily stored in the delay queue according to the diversion rule because its pending delay flag is in a valid state, and its activation flag is initialized to an invalid state (such as 0).

[0141] The fourth step is to process instructions four through seven (independent instructions).

[0142] The processor checks the delay flag bits corresponding to the source logic registers of these instructions in the renaming table and finds that they are all invalid. Therefore, it determines that these instructions are not on the current dependency chain and marks them as non-delayed instructions.

[0143] These instructions are written to the transmit buffer, and their pending delay flag is set to an invalid state (e.g., 0). When these instructions are removed from the transmit buffer, because their pending delay flag is invalid, they are directly moved into the transmit queue according to the diversion rules.

[0144] Step 5: Queue status during the execution of the first instruction.

[0145] During the twenty clock cycles of the execution of the first instruction, the transmit queue is occupied by the first instruction and the fourth, fifth, and sixth instructions (a total of four entries, which is full). The delay queue contains the second and third instructions, both of which have their activation flags in an invalid state (e.g., 0).

[0146] At this point, the fourth, fifth, and sixth independent instructions are ready and can be launched for execution. The second and third instructions are temporarily stored in the delay queue and do not occupy launch queue resources.

[0147] Step 6: The first instruction has been executed.

[0148] Twenty clock cycles later, the first instruction is completed, and the execution pipeline generates a wake-up signal carrying PRN100, which is broadcast to the renaming table, the issue buffer, and the delay queue.

[0149] Rename table response: Match the PRN100 carried by the wake-up signal with the global delay source field. If the match is successful, clear all delay flags (delay flags corresponding to LRN1, LRN4, and LRN6) and the global delay source field of the current dependency chain in the rename table, and cut off the current dependency chain.

[0150] Issue buffer response: If the second or third instruction has not yet been removed from the issue buffer, its delay source field is PRN100. If the match is successful, its pending delay flag is cleared.

[0151] Delay queue response: Match the PRN100 carried by the wake-up signal with the delay source field stored in each table entry. The delay source field of the second and third instructions is PRN100. If the match is successful, set the activation flag of these two instructions from an invalid state (e.g., 0) to an valid state (e.g., 1).

[0152] Step 7: Delay queue instruction checkout.

[0153] The second and third instructions activated in the delay queue are removed sequentially and moved into the launch queue. Once these instructions enter the launch queue, their source operands are marked as ready because the first instruction they depend on has already completed, and they are quickly launched for execution.

[0154] Step 8: Processing subsequent instructions.

[0155] The seventh instruction and other subsequent instructions entered the launch queue one after another as entries were released from the launch queue and were executed normally.

[0156] As can be seen from the above example, during the twenty clock cycles of the first instruction's execution, the issue queue is effectively occupied by the first instruction and three independent instructions, improving issue queue utilization. Delayed instructions (the second and third instructions) are safely stored in the delay queue without interfering with issue queue resources. After the first instruction completes, instructions on the dependency chain are precisely woken up and moved back to the issue queue for execution. This invention effectively solves the problem of delayed instructions ineffectively occupying issue queue resources, improving issue queue utilization and processor execution efficiency.

[0157] In some embodiments, the present invention can postpone the entry of instructions on long-delay instruction dependency chains into the issue queue in ways not limited to adding an additional separate delay queue. For example, the issue cache can be modified to a structure of sequential writes and out-of-order reads. In this implementation, the processor prioritizes reading instructions that do not need to be delayed into the issue queue (i.e., non-delayed instructions), while keeping instructions that need to be delayed (i.e., delayed instructions) in the issue cache and not reading them out, thereby achieving the purpose of delaying the entry of the remaining instructions into the issue queue. Through the above alternative implementations, the present invention can achieve the same technical effect without adding an independent delay queue hardware structure, providing a more flexible implementation scheme.

[0158] In some embodiments, the processor execution module may not necessarily include an issue cache structure. The foregoing embodiments illustrate an execution module including structures such as a renaming table, issue cache, and issue queue, but the processor may also omit an issue cache. In this case, after an instruction completes its renaming, it can directly choose to enter either the delay queue or the issue queue. Specifically, instructions identified as pending delay are directly written to the delay queue, and their activation flag is initialized to an invalid state. Instructions identified as not pending delay are directly written to the issue queue. Through this simplified structure, the present invention can implement the same dependency chain tracing and instruction routing functions in a processor that omits an issue cache, reducing hardware overhead.

[0159] In some embodiments, the timing of broadcasting the wake-up signal forward for long-delay instructions is not limited to the moment the long-delay instruction completes execution. The foregoing embodiments illustrate generating the wake-up signal at the moment the long-delay instruction completes execution or at a preset period before completion, but the invention is not limited to this. The broadcast timing of the wake-up signal can also adopt any of the following schemes: The first scheme is to broadcast at the moment the long-delay instruction completes execution or at a preset period before completion, as described in the foregoing embodiments; the second scheme is to broadcast at a fixed delay period before the long-delay instruction finishes execution, that is, to broadcast the wake-up signal several clock cycles in advance before the instruction completes execution, allowing instructions on the dependency chain to prepare in advance; the third scheme is to broadcast at a fixed delay period after the long-delay instruction enters the issue queue, that is, to start timing from when the instruction enters the issue queue, and broadcast the wake-up signal after a preset fixed delay period. Through the above flexible broadcast timing selection, the processor can select the optimal broadcast timing according to the actual execution latency characteristics of different long-delay instructions, further optimizing performance.

[0160] In some embodiments, the single-threaded working mechanism described in this invention can be extended to multi-threaded processors. In a multi-threaded processor, each thread can store its own rename table information, meaning each thread has an independent global delay source field and delay flag. Other structures, such as the issue buffer, delay queue, and issue queue, can be shared among multiple threads or set independently for each thread. When multiple threads execute simultaneously, long-delayed instructions and their dependency chains from different threads are distinguished by thread identifiers, ensuring they do not interfere with each other. Through these extensions, this invention can be applied to multi-threaded processor scenarios, further improving the instruction issue efficiency of multi-threaded processors.

[0161] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. For details, please refer to the foregoing descriptions of the relevant processing embodiments; they will not be repeated here.

[0162] The foregoing has described specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are possible or may be advantageous.

[0163] In a specific scenario, this invention proposes a method for tracking the dependency chain of long-delay instructions (i.e., long-delay instructions, such as division and square root instructions). After a long-delay instruction enters the emission queue, the instructions in its dependency chain are temporarily stored in a delay queue to prevent them from occupying the emission queue and to allow later-order instructions that are not marked as dependents to enter the emission queue. At a specific time after the long-delay instruction is emitted, a separate wake-up logic wakes up the instructions in its dependency chain from the delay queue. Once woken up, the instructions in the delay queue are removed from the delay queue and moved into the emission queue. Specifically, this may include: 1. Tracing the dependency chain structure of long-latency instructions Rename the table and add the following information: Each item adds an n-bit delay flag: marking whether the architecture register is on the n-chain of dependencies being tracked. If any one of the n bits is set to 1, instructions that depend on this register need to be delayed before entering the issue queue.

[0164] The entire renaming table adds n delay source physical register information (delay head): records the destination physical register number of the source long-delay instructions on the n dependency chains being traced, and this information is updated every time a long-delay instruction is renamed.

[0165] Information added to the launch buffer: Each item is added with a to-be-delay flag; Each item adds delay head physical register information.

[0166] See Figure 6 As shown, Figure 6 This diagram illustrates the information in the renaming table and issue buffer after the instruction stream enters the processor backend, as provided in the embodiments of this specification. It shows the dynamic update process of the renaming table and issue buffer after five instructions enter the processor backend in sequence. The instruction stream used can be as follows: Instruction 1: div LRN1,LRN0; Instruction 2: add LRN2,LRN1; Instruction 3: sub LRN3,LRN2; Instruction 4: mul LRN4,LRN0; Instruction 5: div LRN1,LRN3.

[0167] First, instruction 1 (div LRN1, LRN0) is identified as a long-delay instruction. During the register renaming phase, a new physical register PRN1 is allocated to its destination logical register LRN1. This invention adds an n-bit delay flag (Delay) to each entry in the renaming table to mark whether the register is on the n-chain dependency chain being tracked. If any one of the n bits is set to 1, the instruction dependent on this register needs to be delayed before entering the issue queue. In this embodiment, n=1, meaning the corresponding delay flag Delay[0]=1, where 1 indicates a valid state. Therefore, the delay flag Delay[0] of the entry corresponding to the destination logical register LRN1 in the renaming table is set to a valid state, thus marking the start of the current dependency chain. Simultaneously, this invention adds n global delay source fields (delay head) to the entire renaming table to record the first physical register number of the source long-delay instruction on the n-chain dependency chain being tracked. This information is updated each time a long-delay instruction is renamed. Therefore, the allocation of a new physical register PRN1 for LRN1 is written into the global delay source field (delay head) of the renaming table. Furthermore, this invention adds a "to-be-delay" flag and a "delay head" to each entry in the launch buffer. A "to-be-delay" flag of 1 indicates that the instruction needs to be temporarily stored in the delay queue when it is removed from the launch buffer, while a flag of 0 indicates that it enters the launch queue directly. The "delay head" stores the source physical register number of the dependency chain to which the instruction belongs. Therefore, when instruction 1 is written to the launch buffer, its "to-be-delay" flag is set to 0, ensuring that long-delay instructions can directly enter the launch queue for execution.

[0168] Next, instruction 2 (add LRN2, LRN1) is processed. The source logic register of this instruction contains LRN1. During the renaming process, the delay flag bit Delay [0] of the corresponding entry of LRN1 in the renaming table is read and found to be 1. It is determined that this instruction is on the currently tracked long-delay instruction dependency chain and is marked as a pending delay instruction (belonging to a non-long-delay instruction). Subsequently, a new physical register PRN2 is allocated for the destination logic register LRN2 of instruction 2. In order to realize the downward propagation of the dependency chain, the delay flag bit Delay [0] of the corresponding entry of LRN2 in the renaming table is also updated to 1. When instruction 2 is written to the issue buffer, its pending delay flag bit to-be-delay is set to 1, indicating that the instruction needs to be temporarily stored in the delay queue when it is removed from the issue buffer. At the same time, the value of the global delay source field delay head PRN1 in the renaming stage is copied to the delay source field delay head of the instruction in the issue buffer to record the source identifier of its dependency chain.

[0169] Then, instruction 3 (sub LRN3, LRN2) is processed. The source logical register of this instruction is LRN2. During the renaming process, the delay flag bit Delay [0] of the corresponding entry in the renaming table for LRN2 is read and found to be 1, indicating that this instruction is also on the currently tracked long delay instruction dependency chain. The operation process is the same as that of instruction 2. A new physical register PRN3 is allocated for the destination logical register LRN3 of instruction 3, and the delay flag bit Delay [0] of the corresponding entry in the renaming table for LRN3 is set to 1 to continue passing the dependency chain. When instruction 3 is written to the issue buffer, its delay flag bit to-be-delay is set to 1, and the delay head field delay head is set to PRN1.

[0170] Next, instruction 4 (mul LRN4, LRN0) is processed. The source logical registers of this instruction are LRN0 and LRN4. During the renaming, the delay flag bit Delay [0] of the corresponding entries of these two logical registers in the renaming table is read. It is found that both are 0, indicating that this instruction is not on the currently tracked long delay instruction dependency chain, and it is marked as a non-delayed instruction. A new physical register PRN4 is allocated for the destination logical register LRN4 of instruction 4, and the delay flag bit Delay [0] of the corresponding entry of LRN4 in the renaming table is updated to 0. When instruction 4 is written to the launch buffer, its to-be-delay flag bit is set to 0, and the delay head field is set to an invalid state to ensure that the instruction can directly enter the launch queue for execution.

[0171] Finally, instruction 5 (div LRN1, LRN3) is processed. This instruction is also a long-delay instruction. Since the mechanism shown in this embodiment only tracks the dependency chain of one long-delay instruction at a time, the new long-delay instruction will first clear the delay flag bit Delay [0] of all logical registers in the renaming table and set the global delay source field delay head to an invalid state. Then, it will restart the tracking of a dependency chain in the manner of instruction 1. A new physical register PRN5 is allocated to the destination logical register LRN1 of instruction 5. The delay flag bit Delay [0] of the corresponding entry of LRN1 in the renaming table is set to 1 to mark the starting point of the new dependency chain. PRN5 is written to the global delay source field delay head of the renaming table. When instruction 5 is written to the transmit buffer, its to-be-delay flag bit is set to 0, and the delay source field delay head is set to an invalid state.

[0172] 2. Delayed queue

[0173] The delay queue is a structure added in this invention. Similar to the issue buffer, it is an instruction buffer that does not track whether the source register is ready. Each entry in the delay queue stores information similar to that in the issue buffer, with the following differences: Instead of a to-be-delay flag in the issue buffer, an active flag is added. When an instruction is removed from the issue buffer, its destination is determined by the to-be-delay flag: if the to-be-delay flag is 0, it is directly moved into the issue queue; if the to-be-delay flag is 1, it is temporarily stored in the delay queue. When an instruction in the delay queue is activated by a long-delay instruction broadcast (active=1), it can be moved out of the delay queue and into the issue queue.

[0174] 3. Long delay command wake-up

[0175] In order to move instructions temporarily stored in the delay queue into the issue queue at the appropriate time, the destination physical register of the long-delayed instruction needs to be broadcast to the preceding physical structure when the execution of the long-delayed instruction is completed: Broadcast to rename table: If the physical register of the delay source stored in the current rename table is the same as the broadcast physical register, then clear all delay flags in the rename table to prevent the delay flag of subsequent instructions from being marked as 1.

[0176] Broadcast to transmit buffer: All entries in the transmit buffer with the pending delay flag bit = 1 and the physical register of the delay source is the same as the broadcast physical register, update the pending delay flag bit to 0 to avoid being temporarily stored in the delay queue.

[0177] Broadcast to the delay queue: For entries in the delay queue whose delay source physical register is the same as the broadcast physical register, update the activation flag to 1.

[0178] After a long-delayed instruction is broadcast, activated instructions in the delay queue can be removed from the delay queue and moved into the transmit queue; the removal logic is not limited and can include, but is not limited to: The instructions are removed sequentially from the delay queue. As long as there are activated instructions in the delay queue, the instructions are removed in order until all activated instructions have been removed.

[0179] The delayed queue is removed sequentially, but only activated instructions can be removed. Instructions in the middle of the delayed queue can only be removed sequentially after the head instructions have been activated.

[0180] The delayed queue is removed out of order, and the activated instructions are selected and removed from the delayed queue.

[0181] See Figure 7 As shown, Figure 7 This is a block diagram of the overall structure of the improved backend processor provided in the embodiments of this specification. The invention achieves early tracking of long-latency instruction dependency chains, dynamic instruction routing, and precise wake-up scheduling by adding a delay queue between the issue buffer and the issue queue, and by expanding the fields of the renaming table and the issue buffer. Specifically, it can be as follows: The renaming unit, located at the very front of the processor backend, receives the instructions decoded by the frontend and completes register renaming and dependency chain tracing. Its core is the extended renaming table, which is indexed by the logical register number (LRN, i.e., the architecture register number defined by the instruction set). Each entry stores the corresponding physical register number (PRN, corresponding to the actual storage unit of the physical register file, used to eliminate spurious data dependencies). In this invention, n delay flag bits Delay [n-1:0] are added to each entry of the renaming table. Each bit corresponds to an independent dependency chain. A bit value of 1 indicates that the logical register belongs to the corresponding dependency chain. Instructions that depend on this register need to be marked as delayed instructions. In this embodiment, n=1 corresponds to Delay [0]. At the same time, n global delay source fields delay head 0~delay head n-1 are added to the renaming table. Each field stores the first physical register number of a long-delay instruction that is currently being tracked as the source of the dependency chain, serving as the unique identifier of the entire dependency chain. The issue buffer, coupled after the renaming unit, is used to cache instructions that have completed the renaming process. This invention adds a "to-be-delay" flag and a "delay head" field to each entry. A "to-be-delay" flag of 1 indicates that the instruction needs to be temporarily stored in the delay queue when it is removed from the issue buffer, while 0 indicates it is directly moved into the issue queue. The delay head field stores the source physical register number of the dependency chain to which the instruction belongs, copied from the global delay head field in the renaming phase, and is used for subsequent wake-up matching. The core addition of this invention, the delay queue, is coupled between the issue buffer and the issue queue. It is used to temporarily store dependency chain instructions of long-delayed instructions. Its structure is similar to the issue buffer but does not track the readiness status of source operands, resulting in significantly lower hardware complexity than the issue queue. Each entry includes an "active" flag and a "delay head" field. An "active" flag of 1 indicates that the instruction has been woken up and can be moved into the issue queue, while 0 indicates it is in a waiting state. The issue queue, coupled after the delay queue, is the core structure for scheduling ready instruction execution. Each entry contains source operand fields src1, src2, and src3, and a corresponding ready flag bit rdy. A ready flag of 1 indicates that the corresponding source operand is ready. When all source operands are ready, the instruction can be selected for issuance. This invention stipulates that when the delay queue is not empty, the issue queue must reserve at least one entry in a dedicated state, only accepting instructions removed from the delay queue and prohibiting the acceptance of instructions from the issue buffer to avoid deadlock. Coupled after the issue queue are multiple parallel execution pipelines pipe e0~pipe e3, used to execute instructions issued from the issue queue. When a long-delayed instruction completes execution or at a preset period before completion, the execution pipeline generates a wake-up signal carrying its destination physical register number and broadcasts it to the three upstream modules: the renaming table, the issue buffer, and the delay queue.In actual operation, instructions are routed based on their pending delay flags when removed from the issue buffer: instructions with a pending delay flag of 0 (including long-delay instructions themselves and non-dependent instructions) are moved directly into the issue queue along the left arrow in the diagram; dependent chain instructions with a pending delay flag of 1 are temporarily stored in the delay queue along the upper arrow in the diagram, and their activation flag is initialized to 0. Ready instructions in the issue queue are selected and issued to the execution pipeline. When a long-delay instruction completes execution or at a preset period before completion, a wake-up signal is broadcast. After a successful match in the renaming table, all delay flags of the corresponding dependent chain are cleared, and the corresponding global delay source field is set to invalid to sever completed dependent chains. After a successful match in the issue buffer, the pending delay flag of the corresponding entry is set to 0, allowing pending delay instructions that have not yet been removed to directly enter the issue queue. After a successful match in the delay queue, the activation flag of the corresponding entry is set to 1. Finally, instructions with an activation flag of 1 in the delay queue are moved into the issue queue along the lower arrow in the diagram, waiting for their source operands to be ready before being issued and executed.

[0182] This accompanying figure clearly illustrates the three core improvements of this invention: a low-cost delay queue is added between the launch buffer and the launch queue to temporarily store dependency chain instructions that cannot be ready in the short term; the dependency chain is automatically tracked with zero additional hardware overhead by expanding the renaming table; and cross-module broadcast wake-up logic is added to achieve accurate wake-up and orderly migration of dependency chain instructions. Without increasing the depth of the high-cost launch queue, the problem of low queue utilization caused by long-delay instruction dependency chains occupying the launch queue for a long time is fundamentally solved.

[0183] This invention optimizes the issue queue in current high-performance processors. The issue queue depth significantly impacts performance, but its complex structure makes it difficult to substantially increase the depth without affecting the processor's clock speed. This invention observes that when long-latency instructions appear in the instruction stream, the issue queue becomes occupied by numerous dependency chains of these long-latency instructions. These instructions cannot be woken up in the short term, leading to a significant decrease in issue queue utilization. To address this problem, this invention proposes a solution to improve issue queue utilization efficiency in this scenario. This solution can improve the efficiency of the execution module without increasing the issue queue depth, thereby enhancing processor performance.

[0184] Based on the same inventive concept, this specification also provides an instruction issuing device based on dependency chain tracing, as described in the following embodiments. Since the principle of the instruction issuing device based on dependency chain tracing is similar to that of the instruction issuing method based on dependency chain tracing, the implementation of the instruction issuing device based on dependency chain tracing can be found in the embodiments of the instruction issuing method based on dependency chain tracing; repeated details will not be elaborated further. Reference Figure 8 As shown, the device may include: The first response module 801 can be used to respond to the identified long delay instruction by setting the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long delay instruction to a valid state, so as to mark the current dependency chain start point, and writing the first physical register number allocated to the destination logical register into the global delay source field of the renaming table. The second response module 802 can be used to respond to the fact that the delay flag bit of the corresponding entry in the renaming table of the source logic register of the subsequent instruction is in a valid state, to determine that the subsequent instruction is on the current dependency chain, to mark the subsequent instruction as a delayed instruction, and to pass the global delay source field to the delayed instruction. The delay and wake-up module 803 can be used to temporarily store the instruction to be delayed in the delay queue and initialize the activation flag of the instruction to be delayed to an invalid state. When the long delay instruction is completed or at a preset period before completion, a wake-up signal carrying the first physical register number is generated and broadcast to the renaming table and the delay queue for corresponding matching operations. When the matching is successful, the activation flag is set from an invalid state to an valid state. The shift module 804 can be used to shift delayed instructions with the activation flag bit set to a valid state from the delay queue into the launch queue.

[0185] In some embodiments, the first response module 801 may further include, when the current instruction is not a memory access instruction, matching the instruction opcode of the current instruction with a preset long-delay instruction type, and identifying the current instruction as a long-delay instruction when the match is successful; when the current instruction is a memory access instruction, predicting whether a cache miss occurs in the memory access instruction through a memory access latency prediction mechanism, and if so, determining the memory access instruction as a long-delay instruction.

[0186] In some embodiments, the first response module 801 described above may further be used to write the long delay instruction into the transmit buffer and set the pending delay flag bit of the corresponding entry of the long delay instruction in the transmit buffer to an invalid state, so as to move the long delay instruction directly into the transmit queue.

[0187] In some embodiments, the second response module 802 may further be used to write the delayed instruction into the launch buffer and set the delayed flag bit of the corresponding entry of the delayed instruction in the launch buffer to a valid state, so as to temporarily store the delayed instruction in the delay queue.

[0188] In some embodiments, the second response module 802 may further be used to copy the value of the global delay source field in the renaming table to the delay source field of the corresponding entry in the launch cache of the instruction to be delayed.

[0189] In some embodiments, the first response module 801 may further be used to respond to the fact that the delay flag bit corresponding to the source logic register of the subsequent instruction in the renaming table is in an invalid state, so as to determine that the subsequent instruction is not on the current dependency chain, mark the subsequent instruction as a non-delay instruction; write the non-delay instruction into the launch buffer, and set the delay flag bit of the corresponding entry of the non-delay instruction in the launch buffer to an invalid state; when there is an idle entry in the launch queue, move the non-delay instruction directly into the launch queue, otherwise, keep the non-delay instruction in the launch buffer.

[0190] In some embodiments, the delay and wake-up module 803 can also be used to broadcast the wake-up signal to the transmit buffer. After receiving the wake-up signal, the transmit buffer matches the first physical register number with the delay source field stored in each entry of the transmit buffer. When a match is successful, the pending delay flag bit of the corresponding entry in the matched transmit buffer is set to an invalid state, so that the pending delay instruction is directly moved into the transmit queue.

[0191] In some embodiments, the delay and wake-up module 803 can also be used to, after the renaming table receives the wake-up signal, match the first physical register number with the global delay source field, and when the match is successful, set all delay flags of the current dependency chain in the renaming table and the global delay source field to an invalid state, so as to cut off the current dependency chain and track new long delay instructions; after the delay queue receives the wake-up signal, match the first physical register number with the delay source field stored in each entry of the delay queue, and when the match is successful, set the activation flag of the delayed instruction to be delayed in the corresponding entry of the matched delay queue from an invalid state to an valid state, so as to remove the delayed instruction from the delay queue and move it into the launch queue.

[0192] In some embodiments, the shift-in module 804 can be specifically used to shift the delayed instruction out of the delay queue using any of the following shift-out methods: checking the activation flag of each entry sequentially according to the storage order of the delay queue; if there is a delayed instruction with a valid activation flag, shifting it out according to the storage order until all delayed instructions with valid activation flags are shifted out; checking the activation flag of each entry sequentially according to the storage order of the delay queue; shifting out the delayed instruction at the head of the queue only when the activation flag of the head entry is valid; delayed instructions at the rear of the delay queue are shifted out only after all their preceding delayed instructions have valid activation flags and have been shifted out sequentially; or scanning the activation flags of all entries in the delay queue in parallel, randomly selecting delayed instructions with valid activation flags to shift out, regardless of the storage order of the delay queue.

[0193] In some embodiments, the shift-in module 804 may further be used to monitor the number of entries of delayed instructions stored in the delay queue. When the delay queue is not empty, at least one entry in the launch queue is configured as a reserved state. The launch queue entry in the reserved state is only used to receive delayed instructions whose activation flag is valid when they are removed from the delay queue. When the delay queue becomes empty, the reserved state is released, so that the entries in the launch queue are restored to be available for use by instructions from the launch buffer.

[0194] In some embodiments, the second response module 802 may further be used to set the delay flag corresponding to the destination logic register of the subsequent instruction in the renaming table to an active state when the subsequent instruction is marked as a delayed instruction, so as to pass the current dependency chain down to the next level of subsequent instructions with the destination logic register as the source operand.

[0195] In some embodiments, the renaming table in the first response module 801 is further provided with multiple global delay source fields, each global delay source field being used to record the delay source of a dependency chain; each entry in the renaming table is further provided with multiple delay flags, each of the multiple delay flags corresponding to a global delay source field.

[0196] In some embodiments, the renaming table, after being configured with multiple global delay source fields, can also be used for: when multiple long-delay instructions appear simultaneously in the instruction stream: if the number of currently tracked dependency chains has not reached the maximum number supported by the renaming table, then an idle global delay source field is allocated for the new long-delay instruction, the destination physical register number of the new long-delay instruction is written into the idle global delay source field, and the delay flag corresponding to the idle global delay source field in the entry of the renaming table corresponding to the destination logical register of the new long-delay instruction is set to an active state; if the number of currently tracked dependency chains has reached the maximum number supported by the renaming table, then a release operation is performed on at least one occupied global delay source field, and the delay flag corresponding to the at least one global delay source field in the renaming table is set to an inactive state, and then the released global delay source field is allocated for the new long-delay instruction and new dependency chain tracking is restarted.

[0197] As can be seen from the above, the instruction issuing device based on dependency chain tracing provided in the embodiments of this specification can improve the efficiency of the issuing queue utilization, thereby improving the processor execution efficiency, when the issuing queue depth cannot be significantly increased.

[0198] This specification also provides an embodiment of a chip, such as... Figure 9 As shown, the chip may include a processor 901 and a memory 902, wherein the processor 901 and the memory 902 can be connected via a bus or other means. Figure 9 Taking the example of a connection between China and Israel via a bus.

[0199] Processor 901 can be a central processing unit (CPU). Processor 901 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0200] The memory 902, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the data prefetching method in the embodiments of the present invention. The processor 901 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions, and modules stored in the memory 902, thereby implementing the data prefetching method in the above method embodiments.

[0201] The memory 902 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 901, etc. Furthermore, the memory 902 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 902 may optionally include memory remotely located relative to the processor 901, and these remote memories may be connected to the processor 901 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0202] The one or more modules are stored in the memory 902, and when executed by the processor 901, they perform the following: Figure 2 The instruction issuance method based on dependency chain tracing is shown.

[0203] For details regarding the chip, please refer to the relevant descriptions and effects in the above method embodiments; they will not be repeated here.

[0204] In some embodiments, the processor may include a renaming table, each entry of which is configured with a delay flag and at least one global delay source field; a launch cache, coupled after the renaming table, each entry of which is configured with a pending delay flag and a delay source field; a delay queue, coupled after the launch cache, each entry of which is configured with an activation flag and a delay source field; a launch queue, coupled after the delay queue, for storing instructions ready to be launched, the instructions including at least long-delay instructions; an execution stage, including at least one execution pipeline, for executing instructions launched from the launch queue and generating a wake-up signal when the long-delay instructions have been executed or at a preset period before their completion; and control logic, connecting the renaming table, the launch cache, the delay queue, the launch queue, and the execution stage, for executing, etc. Figure 2 The instruction issuance method based on dependency chain tracing is shown.

[0205] This specification also provides a computer storage medium storing computer program instructions, which, when executed, implement the steps of the instruction issuance method based on dependency chain tracing described above.

[0206] This specification also provides a computer program product comprising a computer program that, when executed, implements the steps of the above-described instruction issuance method based on dependency chain tracing.

[0207] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0208] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. The focus of each embodiment is to describe the differences from other embodiments.

[0209] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0210] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0211] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute certain parts of the methods of various embodiments of this application.

[0212] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer chips, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0213] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0214] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to the embodiments described herein by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A method for issuing instructions based on dependency chain tracing, characterized in that, include: In response to the identified long delay instruction, the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long delay instruction is set to an active state to mark the current dependency chain start point, and the first physical register number allocated to the destination logical register is written into the global delay source field of the renaming table. In response to the source logic register of the subsequent instruction having the delay flag bit of the corresponding entry in the renaming table in a valid state, the subsequent instruction is determined to be on the current dependency chain, the subsequent instruction is marked as a delayed instruction, and the global delay source head field is passed to the delayed instruction. The delayed instruction is temporarily stored in the delay queue, and the activation flag of the delayed instruction is initialized to an invalid state. When the long delayed instruction is completed or at a preset period before completion, a wake-up signal carrying the first physical register number is generated and broadcast to the renaming table and the delay queue for corresponding matching operations. When the matching is successful, the activation flag of the successfully matched delayed instruction is set from an invalid state to an valid state. Delayed instructions with the activation flag set to valid are moved from the delay queue to the launch queue.

2. The method according to claim 1, characterized in that, The method further includes: When the current instruction is not a memory access instruction, the instruction opcode of the current instruction is matched with the preset long-delay instruction type. If the match is successful, the current instruction is identified as a long-delay instruction. When the current instruction is a memory access instruction, the memory access latency prediction mechanism is used to predict whether a cache miss will occur. If so, the memory access instruction is determined to be a long-latency instruction.

3. The method according to claim 1, characterized in that, The method further includes: The long delay instruction is written into the launch buffer, and the pending delay flag of the corresponding entry of the long delay instruction in the launch buffer is set to an invalid state, so that the long delay instruction can be directly moved into the launch queue.

4. The method according to claim 1, characterized in that, The method further includes: The delayed instruction is written into the launch buffer, and the delayed flag of the corresponding entry of the delayed instruction in the launch buffer is set to a valid state, so as to temporarily store the delayed instruction in the delay queue.

5. The method according to claim 1, characterized in that, The step of passing the global delay source field to the instruction to be delayed includes: Copy the value of the global delay source field in the rename table to the delay source field of the corresponding entry in the launch cache for the instruction to be delayed.

6. The method according to claim 1, characterized in that, The method further includes: In response to the fact that the delay flag bits of the source logic register corresponding to the subsequent instruction in the renaming table are all in an invalid state, it is determined that the subsequent instruction is not on the current dependency chain, and the subsequent instruction is marked as a non-delay instruction; Write the non-delayed instruction into the transmit buffer, and set the delay flag of the corresponding entry of the non-delayed instruction in the transmit buffer to an invalid state; If there is an idle entry in the launch queue, the non-delayed instruction is moved directly into the launch queue; otherwise, the non-delayed instruction is kept in the launch buffer.

7. The method according to claim 1, characterized in that, The wake-up signal is also broadcast to the transmit buffer. After receiving the wake-up signal, the transmit buffer matches the first physical register number with the delay source field stored in each entry of the transmit buffer. When the match is successful, the delay flag bit of the corresponding entry in the matched transmit buffer is set to an invalid state so that the delay instruction can be directly moved into the transmit queue.

8. The method according to claim 1, characterized in that, The step of generating a wake-up signal carrying the first physical register number and broadcasting it to the renaming table and delay queue for corresponding matching operations includes: After receiving the wake-up signal, the renaming table matches the first physical register number with the global delay source field. When the match is successful, it sets all delay flags of the current dependency chain in the renaming table and the global delay source field to an invalid state, so as to cut off the current dependency chain and track new long delay instructions. After receiving the wake-up signal, the delay queue matches the first physical register number with the delay source field stored in each entry of the delay queue. When the match is successful, the activation flag of the delayed instruction in the corresponding entry of the delay queue is set from invalid to valid, so as to remove the delayed instruction from the delay queue and move it into the transmission queue.

9. The method according to claim 8, characterized in that, Remove the delayed instruction from the delay queue using any of the following removal methods: The activation flag of each entry in the delay queue is checked sequentially according to the storage order. If there is a delayed instruction with the activation flag in a valid state, it is removed according to the storage order until all delayed instructions with the activation flag in a valid state are removed. The activation flag of each entry is checked sequentially according to the storage order of the delay queue. Only when the activation flag of the first entry is valid, the instruction to be delayed at the head of the queue is removed. The instruction to be delayed at the rear of the delay queue is removed after all the activation flags of the preceding instructions to be delayed are valid and removed in sequence. The activation flag bits of all entries in the delay queue are scanned in parallel, and delayed instructions with any valid activation flag bits are selected out of order and removed without being restricted by the storage order of the delay queue.

10. The method according to claim 1, characterized in that, The method further includes: Monitor the number of pending instruction entries stored in the delay queue. When the delay queue is not empty, configure at least one entry in the launch queue as a reserved state. The launch queue entry in the reserved state is only used to receive pending instructions whose activation flag is valid when removed from the delay queue. When the delay queue becomes empty, the reserved state is released, restoring the entries in the launch queue to be available for use by instructions from the launch buffer.

11. The method according to claim 1, characterized in that, The method further includes: When the successor instruction is marked as a delayed instruction, the delay flag corresponding to the destination logic register of the successor instruction in the renaming table is set to an active state, so as to pass the current dependency chain down to the next level successor instruction with the destination logic register as the source operand.

12. The method according to claim 1, characterized in that, The renaming table also has multiple global delay source fields, each of which records the delay source of a dependency chain; each entry in the renaming table also has multiple delay flags, each of which corresponds to a global delay source field.

13. The method according to claim 12, characterized in that, When multiple long-delayed instructions appear simultaneously in the instruction stream: If the number of currently tracked dependency chains has not reached the maximum number supported by the renaming table, then an idle global delay source field is allocated for the new long-delay instruction, the destination physical register number of the new long-delay instruction is written into the idle global delay source field, and the delay flag bit corresponding to the idle global delay source field in the entry of the renaming table corresponding to the destination logical register of the new long-delay instruction is set to a valid state. If the number of currently tracked dependency chains has reached the maximum number supported by the renaming table, then a release operation is performed on at least one occupied global delay source field, and the delay flag corresponding to the at least one global delay source field in the renaming table is set to an invalid state. Then, the released global delay source field is allocated for a new long delay instruction and a new dependency chain tracking is restarted.

14. A command issuing device based on dependency chain tracing, characterized in that, include: The first response module is used to respond to the identified long delay instruction by setting the delay flag bit of the entry in the renaming table corresponding to the destination logical register of the long delay instruction to a valid state, so as to mark the current dependency chain start point, and writing the first physical register number allocated to the destination logical register into the global delay source field of the renaming table. The second response module is used to respond to the fact that the delay flag bit of the corresponding entry in the renaming table of the source logic register of the subsequent instruction is in a valid state, to determine that the subsequent instruction is on the current dependency chain, to mark the subsequent instruction as a delayed instruction, and to pass the global delay source field to the delayed instruction. The delay and wake-up module is used to temporarily store the instruction to be delayed in the delay queue and initialize the activation flag of the instruction to be delayed to an invalid state. When the long delay instruction is completed or at a preset period before completion, a wake-up signal carrying the first physical register number is generated and broadcast to the renaming table and the delay queue for corresponding matching operations. When the matching is successful, the activation flag is set from an invalid state to an valid state. The shift module is used to shift delayed instructions with the activation flag set to a valid state from the delay queue into the launch queue.

15. A processor, characterized in that, include: A renaming table, wherein each entry of the renaming table is set with a delay flag, and the renaming table is also set with at least one global delay source field; A launch cache, coupled after the renaming table, wherein each entry of the launch cache is configured with a pending delay flag and a delay source field; A delay queue, coupled after the launch buffer, wherein each entry of the delay queue is configured with an activation flag and a delay source field; A launch queue, coupled after the delay queue, is used to store instructions for preparing to launch, the instructions including at least long-delay instructions; An execution stage includes at least one execution pipeline for executing instructions emitted from the launch queue and generating a wake-up signal when the long-delayed instruction is completed or at a preset period before completion. The control logic connects the renaming table, the launch buffer, the delay queue, the launch queue, and the execution level, and is used to execute the steps of the method according to any one of claims 1 to 13.

16. A chip, characterized in that, It includes a processor and a memory for storing processor-executable instructions, wherein the processor, when executing the instructions, implements the steps of the method according to any one of claims 1 to 13.

17. A computer storage medium, characterized in that, The computer storage medium stores computer program instructions, which, when executed by a processor, implement the steps of the method according to any one of claims 1 to 13.

18. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 13.

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