A memristor-based near-sensing and computing integrated analog macro circuit

Abstract

The application discloses a kind of based on near-sensing memory and calculation integrated analog macrocircuit of memristor, including sequentially signal connection's sampling unit, first memristor array, pulse generation module, asynchronous communication module, second memristor array and neuron processing circuit;The sampling unit accesses sensor analog signal and does amplitude conditioning;The first memristor array is with array unit architecture to complete analog domain convolution multiplication, to realize feature extraction;The pulse generation module converts analog convolution result into sparse pulse sequence;The asynchronous communication module realizes interlayer asynchronous transmission in event-driven mode;The second memristor array executes analog multiplication and weighting operation to pulse signal;The neuron processing circuit outputs digital classification result by charge accumulation and threshold discrimination.This based on near-sensing memory and calculation integrated analog macrocircuit of memristor, with the beneficial effects of simple structure, low overall power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a near-inductance in-memory computing analog macro circuit based on memristors. Background Technology

[0002] With the rapid development of artificial intelligence and deep learning networks, Convolutional Neural Networks (CNNs) and Spiking Neural Networks (SNNs) have achieved success in image processing and temporal signal processing. However, in traditional architectures, sensors, memory, and processors are separated. In the traditional von Neumann computing architecture, the analog electrical signals generated by sensors need to be converted to the digital domain by an analog-to-digital converter (ADC) and stored in memory. For specific tasks, the stored signals are read to perform calculations in the digital domain. The requirement for a fully digital domain and the separation of storage and computation creates the "power wall" problem, namely the huge power consumption caused by the frequent analog-to-digital conversion of sensor signals and the back-and-forth movement of data in memory.

[0003] In existing technologies, the analog neural network near the sensor uses an analog convolutional neural network (Analog-CNN) as a preprocessing module to extract features and output a 0 / 1 binary digital signal. The ANN is then used to calculate the speech signal detection result (JSSC 2022). Extracting features in the analog domain and converting them into binary digital signals significantly reduces computational power consumption, with an average power consumption of only 108 nW, achieving a 91% accuracy rate in speech signal recognition. However, traditional analog computing has several problems: First, the convolution circuit for analog feature extraction is implemented using analog circuits built with transistors. Transistors generally process small signals and need to operate within a specific operating range, which can easily introduce signal distortion and limit the input range of the signal.

[0004] Secondly, analog circuits need to store weights in RAM to perform multiplication and addition operations. During the calculation process, the RAM data is read and fed into the analog calculation circuit, which introduces additional power consumption for reading and moving the stored data.

[0005] Third, in the acceleration of digital domain computing neural networks, no optimization design was made for the sparsity characteristics of the data, which cannot avoid redundant static power consumption due to the high sparsity of the data.

[0006] Therefore, in response to the challenges and bottlenecks faced in sensor-side computation, this invention proposes a near-sensing in-memory computing circuit based on memristor devices. The analog signal generated by the sensor is directly fed into the memristor array, and multiplication and addition calculations are achieved by summing the currents of the memristor devices. At the same time, considering the sparsity of the data and the low power consumption design of the overall system, event-driven sparse pulse computation - spiking neural network computation is introduced. The neuron circuit accumulates voltage through charge sharing and generates pulses. Summary of the Invention

[0007] To overcome the above-mentioned shortcomings in the prior art, the present invention provides a memristor-based near-inductance-in-memory computing analog macro circuit with a simple architecture and low overall power consumption.

[0008] The technical solution of this invention is as follows: A near-inductive memory computing integrated analog macro circuit based on memristors includes a sampling unit, a first memristor array, a pulse generation module, an asynchronous communication module, a second memristor array, and a neuron processing circuit connected in sequence. The sampling unit receives the analog signal from the sensor and performs amplitude conditioning. The first memristor array performs analog domain convolution multiplication and addition using an array cell architecture to achieve feature extraction; The pulse generation module converts the simulated convolution result into a sparse pulse sequence. The asynchronous communication module implements inter-layer asynchronous transmission in an event-driven manner; The second memristor array performs analog multiply-accumulate and weighted operations on the pulse signal; The neuron processing circuit outputs a digital classification result through charge accumulation and threshold discrimination.

[0009] Preferably, the memristors in the first memristor array and the second memristor array are resistive switching devices with adjustable resistance and memory characteristics, including at least one of resistive random access memory (RRAM), phase change memory (PCRAM), and magnetic random access memory (MRAM).

[0010] In any of the above schemes, it is preferred that the first memristor array and the second memristor array are both composed of 1T1R units and arranged in a regular row and column manner. The 1T1R unit is composed of an NMOS transistor and a memristor connected in series. The NMOS transistor is controlled and selected via word lines, and the memristor receives input signals via bit lines.

[0011] In any of the above schemes, it is preferred that the first memristor array and the second memristor array both adopt a differential readout architecture, including a positive weight array and a negative weight array, and output voltage signals corresponding to the positive and negative weights respectively through transimpedance amplifiers, and obtain the simulated convolution result through differential operation.

[0012] In any of the above schemes, it is preferred that the pulse generation module uses a time encoding method to map the analog voltage amplitude into a pulse delay sequence.

[0013] In any of the above schemes, the preferred method is single-slope time encoding, and the pulse generation module has a built-in differential amplifier, a single-slope threshold generator, and a comparator.

[0014] In any of the above schemes, it is preferred that the asynchronous communication module adopts an address-event representation (AER) architecture and uses the REQ / ACK protocol to achieve asynchronous arbitration and address transmission of pulse events without a global clock.

[0015] In any of the above schemes, the preferred embodiment is that the second memristor array is composed of a row decoding drive circuit and an arrayed 1T1R unit, and the corresponding row unit is selected according to the address signal output by the asynchronous communication module to complete pulse weighting.

[0016] In any of the above schemes, the preferred embodiment is that the neuron processing circuit includes a weighted capacitor array, a fully differential operational amplifier, a threshold comparator, and a reset switch. It forms a membrane potential through charge sharing accumulation, and triggers pulse output and automatic reset after exceeding the threshold.

[0017] In any of the above schemes, it is preferred that the sensor analog signal accessed by the sampling unit is a continuous analog signal.

[0018] The present invention provides a near-sensing in-memory computing integrated analog macro circuit based on memristors. The signal is input to the sensor's continuous analog signal through the sampling unit and the amplitude is conditioned. The signal is then transmitted sequentially to the first memristor array. The first memristor array is used to perform analog domain convolution multiplication and addition and to extract features. The extracted analog feature signal is then sent to the pulse generation module to be converted into a sparse pulse sequence.

[0019] The sparse pulse sequence is transmitted asynchronously between layers via an asynchronous communication module in an event-driven manner, and then input into the second memristor array to perform pulse signal weighting operations; finally, the neuron processing circuit outputs the corresponding digital classification result through charge accumulation and threshold discrimination.

[0020] The entire circuit abandons the traditional analog-to-digital conversion and data buffering and moving links, and completes the end-side sensing, storage and computing closed-loop processing in the analog domain and pulse domain. Relying on the modular sequential cascade architecture, it achieves the technical effects of simplified circuit architecture and low power consumption of the whole machine. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall structure of the memristor-based near-inductance-in-memory computing analog macro circuit of the present invention.

[0022] Figure 2 This is a schematic diagram of the RRAM 1T1R storage unit and read / write operations of the memristor-based near-inductive storage and computing integrated analog macro circuit of the present invention.

[0023] Figure 3 This is a schematic diagram of the internal circuit of the pulse generation module of the memristor-based near-inductance-memory computing integrated analog macro circuit of the present invention, and the implementation of the analog voltage to pulse sequence conversion.

[0024] Figure 4 This is a schematic diagram of the event-driven architecture of the AER asynchronous communication module based on a memristor-based near-inductance-in-memory computing analog macro circuit of the present invention.

[0025] Figure 5 This is a schematic diagram of the charge-sharing accumulation and integral firing structure of the neuron circuit based on the memristor-based near-inductive memory-computing integrated analog macrocircuit of the present invention. Detailed Implementation

[0026] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, terms such as "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] This embodiment provides a near-inductive-in-memory computing analog macrocircuit based on memristors, belonging to the fields of integrated circuit design and direct sensor signal computation technology. It can be applied to intelligent task processing scenarios with integrated sensing, memory, and computing close to the sensor end, enabling real-time analysis and identification of time-series tasks such as audio signal activity and ECG signal abnormalities. The memristor devices used include, but are not limited to, resistive random access memory (RRAM), phase-change memory (PCRAM), and magnetic random access memory (MRAM), which are resistive devices with adjustable resistance and charge memory characteristics. The overall hardware circuit is built on a hybrid network algorithm architecture of convolutional neural network and spiking neural network, which can effectively optimize the overall performance of next-generation low-power intelligent hardware systems such as neuromorphic computing and in-memory computing.

[0029] This invention abandons the traditional von Neumann discrete architecture design, breaking the inherent layout where sensors, memory, and processors are independent. It does not introduce an ADC analog-to-digital converter throughout the entire process. The continuous analog electrical signal output by the sensor in the time domain does not need to undergo analog-to-digital conversion or be cached and moved by external memory. It can be directly sent to the memristor array to complete in-situ computing and feature extraction. This fundamentally avoids the huge power consumption caused by frequent analog-to-digital conversion and repeated data movement in traditional solutions. It solves the industry bottleneck problems of existing analog convolution circuits, such as easy signal distortion, high power consumption for weight data reading and moving, and lack of power optimization for data sparsity.

[0030] like Figure 1 As shown, the overall circuit architecture of this invention is configured sequentially according to the signal flow as a first memristor array, a pulse generation module, an asynchronous communication module, a second memristor array, and a neuron processing circuit, forming a complete end-to-end processing architecture of analog input—feature extraction—pulse encoding—asynchronous transmission—secondary weighting—neuraln integration and decision. The overall signal flow is as follows: continuous analog signal from the sensor → the first memristor array completes analog domain multiplication and convolution operations → the pulse generation module completes the conversion of analog voltage to sparse pulse sequence → the AER asynchronous communication module realizes event-driven inter-layer transmission → the second memristor array completes pulse weighting and feature inference → the neuron processing circuit outputs the final classification result after charge sharing accumulation and threshold comparison, realizing a true integrated sensor-memory-computing design without ADC or additional storage weight transfer throughout the entire process.

[0031] The first and second memristor arrays are configured with multiple bit lines BL~BLn that are connected in parallel to multiple analog input voltages. ~ To achieve precise separation of positive and negative weights and to offset the effects of common-mode noise and process variations, the circuit adopts a differential readout design. The output current of the positive weight array is converted by a transimpedance amplifier (TIA) to obtain the positive weight readout voltage. The output current of the negative weighted array is converted by a transimpedance amplifier (TIA) to obtain the negative weighted readout voltage. , and The data is then fed into subsequent circuit modules for difference and weighting operations, ultimately yielding the memristor array output.

[0032] like Figure 2 As shown, the first memristor array and the second memristor array involved in this invention both adopt a 1T1R basic memory cell architecture, and each memory cell is composed of an NMOS transistor and a memristor device connected in series. Figure 2 The diagram shows the structure of a 1T1R memory cell. The transistor gate is connected to the word line WL, the source is connected to the source line SL, the drain is connected to the upper electrode of the memristor, and the lower electrode of the memristor is connected to the bit line BL. Figure 2The diagram illustrates the cell voltage operation for writing with low impedance, writing with high impedance, and reading / in-memory computation. During in-array computation, the external timing control circuit sequentially selects the corresponding NMOS transistor switches row by row via word lines. The bit line BL is directly connected to the raw input signal from the sensor in the form of an analog voltage. The memristor's own resistance state corresponds to fixed synaptic weights, and the analog multiplication and addition operation of the input voltage and conductance weights is realized based on the magnitude of the current flowing through the memristor. The cell currents on multiple bit lines can be naturally superimposed at the common node of the bit lines to complete the multiplication and addition feature calculation required by the convolutional neural network.

[0033] In practical applications, taking the raw analog signals output by proximity sensors such as audio and ECG as examples, the signal amplitude is weak, easily affected by environmental interference, and has baseline drift. If these signals are directly fed into a memristor array, the signal amplitude is likely to be too low and drowned out by the background noise, or the amplitude is too high and causes the memristor to saturate and distort. This circuit features a front-end sampling unit, naturally adapted to the characteristics of weak analog signals. Relying on the signal conditioning logic built into the sampling unit, it can pre-amplify and match the level amplitude of the original analog signal, precisely limiting the dynamic range of the signal within the operating range of the memristor's linear resistive transformer. At the same time, the sampling unit uses equal timing slots to uniformly sample continuous analog waveforms. The timing sequence of adjacent 1T1R units is continuous, and the waveform amplitude is naturally correlated. By utilizing the continuity of the waveform to form a local smoothing constraint, combined with the conduction threshold characteristics of the memristor itself, it can spontaneously suppress instantaneous glitches and weak noise components. While working with the first memristor array to complete the analog convolution feature extraction, it also achieves the first layer of passive noise reduction, effectively making up for the defects of traditional transistor analog convolution circuits, such as easy distortion and limited input range.

[0034] like Figure 3 As shown, the analog characteristic voltage signal output by the first memristor array is fed into the subsequent pulse generation module, which implements its internal functions. The module integrates sub-circuits such as an analog subtractor, sample-and-hold circuit, integrator, single-slope threshold generator, voltage comparator, and pulse generator. During operation, the positive and negative weighted array outputs... and First, an analog subtractor is used to perform the difference operation. The pulse coding module for the difference voltage uses a single-slope time coding mechanism to combine the difference voltage with the single-slope adjustable threshold voltage. Perform real-time comparison, when When the comparator outputs a high level, the comparator outputs a high level; when... When the comparator outputs a low level, the pulse generator triggers the monostable circuit when the comparator outputs a high level, generating a fixed-width pulse signal (e.g., a pulse width of 10ns). Simultaneously, a reset signal is generated to reset the comparator and the single-slope voltage generator to zero. Then, the next pulse signal generation cycle begins. This triggers the pulse generator to output a fixed-width sparse pulse signal, with the signal information represented by the pulse generation time delay and pulse frequency.

[0035] This single-slope time encoding method can map analog characteristic voltages of different amplitudes into pulse sequences with different time intervals. The pulse delay time fully carries the spatial and temporal information of the original analog characteristics, and can complete the lossless conversion from the analog domain to the pulse event domain without relying on analog-to-digital conversion. At the same time, the module circuit structure is simple, the overall power consumption is extremely low, and the sensitivity to the static operating point of transistors is low. From the architecture, it avoids the drawback of traditional analog multipliers that are prone to introducing signal distortion. The output regular sparse pulse sequence can provide a standard signal basis for subsequent asynchronous event transmission.

[0036] like Figure 4 As shown, the sparse pulse sequence output by the pulse generation module is connected to the asynchronous communication module. This module uses the address-event representation AER protocol to realize asynchronous communication between layers, and its overall architecture and handshake interaction logic are described. The module consists of a transmitting AER encoder, arbitrator, address bus, and a receiving AER decoder, line decoder, and word line driver circuit. It does not require global clock synchronization throughout the process, relying solely on an event-triggered mechanism to complete inter-layer data interaction. When the L-th layer pulse generation module generates a valid pulse event, multiple concurrent pulse signals are sent to the arbitrator inside the AER encoder. The arbitrator can use polling, fixed priority, or fair competition strategies to prioritize and arbitrate multiple events. The selected neuron address Addr_i is latched onto the address bus, and a request signal REQ is sent to the receiving end. The receiving AER decoder monitors the REQ valid level in real time. If it is in an idle and receptive state, it sends an acknowledgment signal ACK back to the transmitting end, forming a standard REQ / ACK asynchronous handshake mechanism.

[0037] After receiving the ACK response, the encoder confirms successful address transmission, releases the current request, and enters the next round of event arbitration. The decoder, after latching the valid address information, drives the corresponding row decoder and word line driver to pull the corresponding row word line WL of the L+1 layer's second memristor array high, precisely activating the synaptic weights stored within all 1T1R cells of that row. This AER asynchronous communication mode only transmits valid pulse events and corresponding address information, eliminating redundant and invalid data transmission. It fully adapts to the sparse characteristics of neural network data, significantly reducing the amount of data transmitted between layers and static redundant power consumption, meeting the low-power design requirements of edge hardware.

[0038] The pulse signal, after address event transmission via the AER asynchronous communication module, is connected to the second memristor array. This array also uses the 1T1R basic memory cell row-column regular arrangement architecture, with each cell storing various synaptic weights required by the spiking neural network (SNN). Based on the event address parsed by the AER decoder, the array selectively selects the corresponding 1T1R cell. With the cooperation of a fixed pulse voltage on the bit line, it performs a weighted calculation of the input pulse signal and the memristor weight conductance. The multiple weighted currents are accumulated and summarized at the line nodes, realizing deep neural network calculation and intelligent inference of the front-end basic features. This further enhances the effective feature response capability, suppresses irrelevant redundant information, and improves the overall signal recognition and discrimination.

[0039] like Figure 5 As shown, the current pulse signal output by the second memristor array is converted into a voltage pulse and finally sent to the multi-bit weighted computational neuron processing circuit, which has an internal charge-sharing accumulation and integration firing structure. The neuron processing circuit mainly consists of a weighted capacitor array, a fully differential operational amplifier, a threshold comparator, an asynchronous reset circuit, and a leakage circuit. The weighted capacitor array is configured with multiple weighted capacitors of different capacitance values ​​(1C, 2C, 4C, 8C) to realize multi-bit weight configuration. Each capacitor is connected to the input node through an independent MOS transistor switch. The neuron circuit uses charge pump technology to integrate the voltage of the integrating capacitor. Taking a single-sided circuit as an example, when the circuit is in a static state and there is no input pulse, the switch... connect The transistors connected by diodes form a pre-charge path, enabling the node to... Stable and maintained at Potential, in which This is the transistor's on-state voltage drop. At this time, the integrating capacitor CM1 maintains the potential value of the previous cycle, while the charge pump path is high via the CHG signal and is in the off state. When the input spike signal generates a voltage... After stabilization, switch on. connect Terminal, voltage Applied to coupling capacitor When the bottom electrode is used, due to the capacitive coupling effect, the node... The potential rises synchronously to The gate control voltage CHG of transistor M2 controls the charge sharing process, which is controlled by... Decrease to approximately This drives M2 into the conduction range. After M2 is turned on, the node... Integrating capacitor Injecting charge enables a discrete integration operation. With... The potential gradually decreased to When M2 enters the cutoff region, the charge injection process terminates. This self-limiting mechanism ensures a fixed charge increment for each input pulse, avoiding overcharging and improving integration accuracy. Before the input pulse ends, Switch to again The capacitive coupling effect still exists. The potential was pulled down to Simultaneously, the CHG signal ends charge sharing. At this time, transistor M1 in the voltage recovery circuit is triggered and turns on, providing a charging path for coupling capacitor CM1, restoring it to its initial pre-charge potential, thus completing the state recovery after a single pulse and ensuring that the next input pulse can operate under the same initial conditions. This recovery process is decoupled from the integration path, avoiding interference with the integration capacitor potential. As multiple input pulses continue to arrive, the integration capacitor... The potential on it gradually accumulates.

[0040] The positive input terminal of the fully differential operational amplifier is connected to the membrane potential calculated with positive weights. The negative input terminal is connected to the membrane potential calculated with negative weights. The membrane potential is differentially followed and then fed into a threshold comparator. The comparator has a built-in fixed threshold reference level. When the accumulated membrane potential exceeds the preset threshold, the comparator level flips and outputs a Spike_out pulse signal, which is the final valid digital classification result. For environmental interference pulses with weak amplitude and scattered quantity, the membrane potential cannot accumulate to the threshold level and will be automatically shielded by the circuit without output, forming the second layer of accurate noise reduction and discrimination at the back end. After the neuron completes one pulse firing and result output, the internal reset circuit is triggered immediately to quickly discharge and clear the charge of the weighted capacitor array plates, restoring the membrane potential to the initial state, and entering the next round of charge integration and threshold discrimination cycle, realizing continuous and uninterrupted real-time processing of analog signals. In the fully differential neuron circuit, when and The potential difference rises and exceeds the set threshold. At this time, the spike generation circuit is triggered, outputting neuron pulse signals. After the neuron completes one pulse firing and output, the internal AER asynchronous handshake reset circuit is immediately triggered to quickly discharge and clear the charge on the weighted capacitor array plates, restoring the membrane potential to its initial state, and entering the next round of charge integration and threshold discrimination loop, realizing continuous and uninterrupted real-time processing of analog signals.

[0041] In summary, this invention utilizes a 1T1R memristor array to construct a CNN-SNN hybrid hardware architecture, completely eliminating the ADC analog-to-digital conversion stage. The sampling unit performs signal conditioning, piecewise sampling, convolution multiplication and addition, and shallow noise reduction in the analog domain. Low-distortion conversion from analog signals to sparse pulses is achieved through single-slope time coding. AER event-driven asynchronous communication adapts to the sparse data characteristics and reduces transmission power consumption. Finally, deep feature inference using a second memristor array and charge integration thresholding by the neuron processing circuit form a complete near-sensing in-memory computing analog macrocircuit. The overall architecture solves the technical pain points of traditional sensing computing, such as high ADC conversion power consumption, large data transfer overhead, analog circuit distortion, and insufficient power optimization for sparse data. It is widely adaptable to low-power, high-accuracy intelligent recognition tasks for various edge-side near-sensing analog sensing signals.

[0042] The above-described embodiments are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A near-inductance in-memory computing analog macrocircuit based on memristors, characterized in that: It includes a sampling unit with sequentially connected signals, a first memristor array, a pulse generation module, an asynchronous communication module, a second memristor array, and a neuron processing circuit; The sampling unit receives the analog signal from the sensor and performs amplitude conditioning. The first memristor array performs analog domain convolution multiplication and addition using an array cell architecture to achieve feature extraction; The pulse generation module converts the simulated convolution result into a sparse pulse sequence. The asynchronous communication module implements inter-layer asynchronous transmission in an event-driven manner; The second memristor array performs analog multiply-accumulate and weighted operations on the pulse signal; The neuron processing circuit outputs a digital classification result through charge accumulation and threshold discrimination.

2. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: The memristors in the first memristor array and the second memristor array are resistive switching devices with adjustable resistance and memory characteristics, including at least one of resistive random access memory (RRAM), phase change memory (PCRAM), and magnetic random access memory (MRAM).

3. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: Both the first memristor array and the second memristor array are composed of 1T1R units and arranged in a regular row and column manner. Each 1T1R unit is composed of an NMOS transistor and a memristor connected in series. The NMOS transistor is controlled and selected via word lines, and the memristor receives input signals via bit lines.

4. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: Both the first memristor array and the second memristor array adopt a differential readout architecture, including a positive weight array and a negative weight array. The voltage signals corresponding to the positive and negative weights are output through transimpedance amplifiers, and the simulated convolution result is obtained through differential operation.

5. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: The pulse generation module uses time encoding to map the analog voltage amplitude into a pulse delay sequence.

6. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 5, characterized in that: The time encoding method is single-slope time encoding, and the pulse generation module has a built-in differential amplifier, a single-slope threshold generator, and a comparator.

7. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: The asynchronous communication module adopts an address-event representation (AER) architecture and uses the REQ / ACK protocol to achieve asynchronous arbitration and address transmission of pulse events without a global clock.

8. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: The second memristor array consists of a row decoding drive circuit and an arrayed 1T1R unit. It selects the corresponding row unit to complete pulse weighting based on the address signal output by the asynchronous communication module.

9. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: The neuron processing circuit includes a weighted capacitor array, a fully differential operational amplifier, a threshold comparator, and a reset switch. It forms a membrane potential through charge sharing and accumulation, and triggers a pulse output and automatically resets after exceeding the threshold.

10. The near-inductance in-memory computing analog macro circuit based on memristors as described in claim 1, characterized in that: The sensor analog signal received by the sampling unit is a continuous analog signal.

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