A lightweight PCB defect detection method

Abstract

The application discloses a light-weight PCB defect detection method, which is applied to the technical field of printed circuit boards (PCBs) and comprises the following steps: acquiring an image of a PCB from an input end and performing feature extraction to obtain image features; performing feature map fusion on the image features based on an FPN-PAN structure to obtain multi-scale fusion features; and processing the multi-scale fusion image based on a decoupling head to obtain a detection result and outputting the detection result. The method solves the problem of inaccurate identification of the micro defects of the PCB in the prior art.

Description

Technical Field

[0001] This application is applied in the field of printed circuit board technology, specifically, it relates to a lightweight PCB defect detection method. Background Technology

[0002] As electronic products become increasingly integrated and miniaturized, the manufacturing density and wiring complexity of printed circuit boards (PCBs) have significantly increased. During PCB production, limitations imposed by etching, drilling, and other processes make it highly susceptible to six typical defects: missing holes, mouse bites, open circuits, short circuits, spurs, and spurious copper. These defects directly impact the performance and lifespan of electronic products; therefore, efficient and accurate automated defect detection is crucial.

[0003] Existing PCB defect detection technologies mainly include traditional detection methods and deep learning-based methods.

[0004] Traditional inspection methods include: Electrical testing, which detects internal short circuits or open circuits by testing the electrical continuity of the PCB, but cannot detect external defects and is costly. Manual visual inspection relies on operator experience, is inefficient, and is easily affected by subjective factors, leading to high rates of false positives and false negatives. Traditional optical inspection (AOI) compares images based on preset rules, is sensitive to changes in lighting and background noise, and is difficult to adapt to complex and changing industrial environments.

[0005] Deep learning-based methods: In recent years, single-stage object detection algorithms, represented by the YOLO (You Only Look Once) series, have become the preferred choice for industrial deployment due to their good balance between detection speed and accuracy. However, directly applying general object detection models to PCB defect detection still faces significant technical bottlenecks, including the contradiction between lightweight design and accuracy: To deploy on resource-constrained edge devices, lightweight models (such as YOLOv5n and YOLOv8n) are often used. However, while compressing the number of parameters, these models often weaken their ability to extract features from small, irregular defects (such as burrs and open circuits), leading to a decrease in detection accuracy. Rigid feature fusion mechanisms: The attention mechanisms in existing models (such as the C2PSA module in YOLOv11n) typically use a fixed weighting method to fuse channel and spatial features. This approach cannot adaptively adjust the focus based on the characteristics of different defect types (for example, "mouse bite" defects rely more on channel features for identification, while "short circuit" defects rely more on spatial features for localization). Meanwhile, the lack of effective residual connections makes it easy for original detailed information to be lost during transmission in deep networks, affecting the preservation of weak defect features. Summary of the Invention

[0006] To address the problem of inaccurate identification of minute defects in PCBs in existing technologies, this application discloses a lightweight PCB defect detection method, specifically:

[0007] A lightweight PCB defect detection method, the method comprising:

[0008] The image of the PCB is acquired from the input terminal, and its features are extracted to obtain the image features.

[0009] Based on the FPN-PAN structure, feature maps are fused to obtain multi-scale fused features.

[0010] The decoupling head is used to process multi-scale fused images to obtain and output detection results.

[0011] Optionally, the step of acquiring an image of the PCB from the input terminal and performing feature extraction to obtain image features includes:

[0012] The input terminal takes a 640×640 pixel RGB image of the PCB and performs convolution processing through the C3K2 module to obtain the convolutional features.

[0013] The convolutional features are processed by two cascaded C3K2_IDWD modules to obtain features after multiple convolutions.

[0014] Feature recalibration is performed on features after multiple convolution processing using a gated residual channel-spatial attention mechanism to obtain image features.

[0015] Optionally, the convolution-processed features are processed by two cascaded C3K2_IDWD modules to obtain features after multiple convolution processing, including:

[0016] The C3K2_IDWD module comprises a deep convolutional attention unit, a deep convolutional unit with a dynamic multi-branch network convolutional structure, and a C3k2 multi-branch dynamic depth separable convolutional unit.

[0017] The features obtained from the convolution process are calibrated by the deep convolutional attention unit, and the calibrated features are output.

[0018] The calibrated features are input into the deep convolutional unit of the dynamic multi-branch network convolutional structure, and the feature maps of each output channel are stitched together to form a stitched feature map.

[0019] After concatenation, the features are processed by a C3k2 multi-branch dynamic depthwise separable convolutional unit, and the features on the input side and the features on the output side of the unit are added element-wise to form a residual connection.

[0020] Optionally, the step of performing feature calibration on the features obtained from convolution processing by the deep convolutional attention unit and outputting the calibrated features includes:

[0021] The calibrated features are subjected to global pooling to compress the spatial dimension, resulting in channel statistical vectors;

[0022] The channel statistics vector is compressed through a fully connected layer, and then restored through another fully connected layer.

[0023] The channel attention weights are obtained from the recovered channel count and multiplied with the image features to obtain the calibrated features.

[0024] Optionally, the calibrated features are input into the deep convolutional units of the dynamic multi-branch network convolutional structure, and the feature maps of each output channel are concatenated into a concatenated feature map, including:

[0025] The deep convolutional unit of the dynamic multi-branch network convolutional structure includes identity mapping branch, square branch, and vertical / horizontal branch;

[0026] Based on the identity mapping branch, the features of the calibrated features are preserved to ensure lossless information transmission;

[0027] Based on the square branch, K×K depth convolution is performed on the calibrated features to obtain the local two-dimensional context information of the calibrated features;

[0028] Based on vertical / horizontal branches, 1×K and K×1 strip convolutions are performed on the calibrated features to obtain the horizontal and vertical dependencies of the calibrated features over long distances.

[0029] Based on the fusion unit, the outputs of the identity mapping branch, the square branch, and the vertical / horizontal branch are concatenated along the channel dimension and weighted by the deep convolutional attention unit to obtain the concatenated features.

[0030] Optionally, the concatenated features are processed by a C3k2 multi-branch dynamic depthwise separable convolutional unit, and the features on the input side and the features on the output side of the unit are added element-wise to form a residual connection, including:

[0031] The concatenated features are input into a 1×1 convolution expansion channel, and then input into the identity mapping channel and the deep convolutional units of n dynamic multi-branch network convolutional structures along the channel dimension for nonlinear transformation.

[0032] The feature sequence after nonlinear transformation and the feature sequence of the identity mapping channel are concatenated along the channel dimension to obtain the channel concatenation feature.

[0033] The channel splicing features are compressed by 1×1 convolution, batch normalized, and SiLU activated, and then added to the image features to form residual connections.

[0034] Optionally, the step of recalibrating the features after multiple convolution processing using a gated residual channel-spatial attention mechanism to obtain image features includes:

[0035] After multiple convolutions, the features are processed by convolutional modules to obtain local features; the local features are then processed by channel branches and spatial branches to obtain channel attention weights and spatial attention weights.

[0036] Based on the features after multiple convolutional processing with channel attention weights and spatial attention weights respectively, and based on a gating network, a fusion weight matrix is ​​generated;

[0037] Based on the fusion weight matrix, local features are dynamically weighted to obtain the gated fusion output;

[0038] The output after gating and fusion is fused with the features after multiple convolution processing to obtain image features.

[0039] Optionally, the feature map fusion of image features based on the FPN-PAN structure to obtain multi-scale fused features includes:

[0040] Continuously acquire image features and perform image feature recognition;

[0041] Based on the image feature recognition results, the temporal and spatial order and fusion method of image features are obtained;

[0042] Based on the fusion method, the feature maps are fused at multiple scales according to the order in which the image features are received, so as to obtain multi-scale fused features.

[0043] Optionally, the process of processing the multi-scale fused image based on the decoupling head to obtain and output the detection result includes:

[0044] Acquire multi-scale fused images and perform target and boundary recognition based on the decoupling head;

[0045] Based on the target recognition and bounding box recognition results, PCB defect detection results are acquired and output.

[0046] The beneficial effects of this application include:

[0047] 1. Significantly improves the accuracy of detecting minute defects. The C3K2_IDWD module in this application introduces multi-branch depthwise separable dynamic convolution, utilizing three different convolution kernel shapes—square, horizontal, and vertical—to extract features in parallel. This enables the capture of geometric features of minute defects (such as burrs and open circuits) from multiple directions and scales, effectively characterizing even extremely small defects, ultimately significantly improving the mAP50-95 index and reducing the false negative rate.

[0048] 2. Achieving more accurate defect localization. The channel-spatial attention module in this application adopts a gated dynamic fusion mechanism and introduces residual connections. The gating mechanism adaptively allocates the weights of channel and spatial attention according to the image content, and the residual connections ensure the lossless transmission of original edge details. The model can accurately focus on the defect area in complex backgrounds, ultimately achieving high-precision bounding box regression and improving localization accuracy.

[0049] 3. Achieving a balance between lightweight design and high performance. The C3K2_IDWD in this application extensively utilizes depthwise separable convolutions and striped convolutions, while the channel-spatial attention module employs a lightweight gated network. This significantly reduces computational redundancy associated with standard convolutions, ultimately achieving a 33.0% reduction in parameters and a 16.0% reduction in computation while maintaining an mAP50 of 96.7%, making it suitable for edge device deployment. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments of this application or the prior art will be briefly introduced below. Obviously, the following description is only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. The drawings are used to provide a further understanding of this disclosure and constitute a part of the specification. They are used together with the following detailed description to explain this disclosure, but do not constitute a limitation of this disclosure. In the drawings:

[0051] Figure 1 A flowchart illustrating a lightweight PCB defect detection method provided in this application embodiment;

[0052] Figure 2 A prior art flowchart illustrating a lightweight PCB defect detection method provided in this application embodiment;

[0053] Figure 3 A flowchart illustrating the multi-branch depthwise separable convolutional attention workflow of a lightweight PCB defect detection method provided in this application embodiment;

[0054] Figure 4A flowchart illustrating the multi-branch depth-separable dynamic convolution workflow of a lightweight PCB defect detection method provided in this application embodiment;

[0055] Figure 5 A flowchart illustrating the C3k2 multi-branch dynamic depthwise separable convolution workflow for a lightweight PCB defect detection method provided in this application embodiment;

[0056] Figure 6 The flowchart shows the channel-space attention module of a lightweight PCB defect detection method provided in this application embodiment. Detailed Implementation

[0057] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. Furthermore, in the embodiments of this application, "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0058] To address the problems existing in the prior art, this application discloses a lightweight PCB defect detection method, such as... Figure 1 The diagram shown is a flowchart of a lightweight PCB defect detection method provided in an embodiment of this application. Specifically:

[0059] A lightweight PCB defect detection method, the method comprising:

[0060] The image of the PCB is acquired from the input terminal, and its features are extracted to obtain the image features.

[0061] Based on the FPN-PAN structure, feature maps are fused to obtain multi-scale fused features.

[0062] The decoupling head is used to process multi-scale fused images to obtain and output detection results.

[0063] The process of acquiring an image of the PCB from the input terminal and extracting its features to obtain image features includes:

[0064] The input terminal takes a 640×640 pixel RGB image of the PCB and performs convolution processing through the C3K2 module to obtain the convolutional features.

[0065] The convolutional features are processed by two cascaded C3K2_IDWD modules to obtain features after multiple convolutions.

[0066] Feature recalibration is performed on features after multiple convolution processing using a gated residual channel-spatial attention mechanism to obtain image features.

[0067] The convolutional features are processed by two cascaded C3K2_IDWD modules to obtain multi-convolutional features, including:

[0068] The C3K2_IDWD module comprises a deep convolutional attention unit, a deep convolutional unit with a dynamic multi-branch network convolutional structure, and a C3k2 multi-branch dynamic depth separable convolutional unit.

[0069] The features obtained from the convolution process are calibrated by the deep convolutional attention unit, and the calibrated features are output.

[0070] The calibrated features are input into the deep convolutional unit of the dynamic multi-branch network convolutional structure, and the feature maps of each output channel are stitched together to form a stitched feature map.

[0071] After concatenation, the features are processed by a C3k2 multi-branch dynamic depthwise separable convolutional unit, and the features on the input side and the features on the output side of the unit are added element-wise to form a residual connection.

[0072] The step of performing feature calibration on the features obtained from convolution processing by the deep convolutional attention unit and outputting the calibrated features includes:

[0073] The calibrated features are subjected to global pooling to compress the spatial dimension, resulting in channel statistical vectors;

[0074] The channel statistics vector is compressed through a fully connected layer, and then restored through another fully connected layer.

[0075] The channel attention weights are obtained from the recovered channel count and multiplied with the image features to obtain the calibrated features.

[0076] The calibrated features are input into the deep convolutional units of the dynamic multi-branch network convolutional structure, and the feature maps of each output channel are concatenated into a concatenated feature map, including:

[0077] The deep convolutional unit of the dynamic multi-branch network convolutional structure includes identity mapping branch, square branch, and vertical / horizontal branch;

[0078] Based on the identity mapping branch, the features of the calibrated features are preserved to ensure lossless information transmission;

[0079] Based on the square branch, K×K depth convolution is performed on the calibrated features to obtain the local two-dimensional context information of the calibrated features;

[0080] Based on vertical / horizontal branches, 1×K and K×1 strip convolutions are performed on the calibrated features to obtain the horizontal and vertical dependencies of the calibrated features over long distances.

[0081] Based on the fusion unit, the outputs of the identity mapping branch, the square branch, and the vertical / horizontal branch are concatenated along the channel dimension and weighted by the deep convolutional attention unit to obtain the concatenated features.

[0082] The concatenated features are processed by a C3k2 multi-branch dynamic depthwise separable convolutional unit, and the features on the input side and the features on the output side of the unit are added element-wise to form a residual connection, including:

[0083] The concatenated features are input into a 1×1 convolution expansion channel, and then input into the identity mapping channel and the deep convolutional units of n dynamic multi-branch network convolutional structures along the channel dimension for nonlinear transformation.

[0084] The feature sequence after nonlinear transformation and the feature sequence of the identity mapping channel are concatenated along the channel dimension to obtain the channel concatenation feature.

[0085] The channel splicing features are compressed by 1×1 convolution, batch normalized, and SiLU activated, and then added to the image features to form residual connections.

[0086] The method of recalibrating features after multiple convolution processing using a gated residual channel-spatial attention mechanism to obtain image features includes:

[0087] After multiple convolutions, the features are processed by convolutional modules to obtain local features; the local features are then processed by channel branches and spatial branches to obtain channel attention weights and spatial attention weights.

[0088] Based on the features after multiple convolutional processing with channel attention weights and spatial attention weights respectively, and based on a gating network, a fusion weight matrix is ​​generated;

[0089] Based on the fusion weight matrix, local features are dynamically weighted to obtain the gated fusion output;

[0090] The output after gating and fusion is fused with the features after multiple convolution processing to obtain image features.

[0091] The method based on the FPN-PAN structure performs feature map fusion on image features to obtain multi-scale fused features, including:

[0092] Continuously acquire image features and perform image feature recognition;

[0093] Based on the image feature recognition results, the temporal and spatial order and fusion method of image features are obtained;

[0094] Based on the fusion method, the feature maps are fused at multiple scales according to the order in which the image features are received, so as to obtain multi-scale fused features.

[0095] The process of processing multi-scale fused images based on the decoupling head to obtain and output detection results includes:

[0096] Acquire multi-scale fused images and perform target and boundary recognition based on the decoupling head;

[0097] Based on the target recognition and bounding box recognition results, PCB defect detection results are acquired and output.

[0098] Below, we will provide a detailed explanation of all the above content, specifically:

[0099] like Figure 2 The diagram shown is a prior art flowchart of a lightweight PCB defect detection method provided in this application embodiment. This technical solution is the closest to the technical solution of this application. The YOLOv11n network architecture mainly consists of three parts: backbone network, neck network and head.

[0100] Input: Receives RGB images with a size of 640×640 pixels.

[0101] The backbone network is responsible for extracting multi-scale features from the input image. It consists of multiple convolutional layers (Conv), a C3K2 module, an SPPF module, and a C2PSA module connected in series. The C3K2 module is the core feature extraction unit, designed based on the CSPNet structure, used to capture deep semantic information of the image. The C2PSA module is located at the end of the backbone network and is used to enhance the network's focus on key features.

[0102] The neck network employs an FPN-PAN (Feature Pyramid Network - Path Aggregation Network) structure. Through upsampling and concatenation operations, it fuses feature maps output from different stages of the backbone network, achieving effective interaction between deep semantic information and shallow detail information, thus enhancing the detection capability for targets of different sizes.

[0103] The detection head receives the multi-scale fusion features output by the neck network. It adopts a decoupled head structure to perform target classification and bounding box regression tasks separately, and finally outputs the detection results.

[0104] Among them, the C3K2 module in the standard YOLOv11n uses a conventional convolutional structure, and its fixed receptive field is insufficient to fully capture the multi-scale features of minute defects in PCBs. At the same time, the C2PSA module uses a simple weighted summation method when fusing features, which fails to effectively distinguish the dynamic weights of channel and spatial information, and lacks a direct protection path for the original features, resulting in insufficient accuracy in locating minute defects in complex backgrounds.

[0105] The shortcomings of the prior art include:

[0106] Disadvantage 1: Insufficient ability to extract minute defect features

[0107] The existing C3K2 module uses a fixed-size convolutional kernel, resulting in a single receptive field. Due to the extremely small size and varied shapes of PCB defects (such as burrs and open circuits), a single receptive field is insufficient to cover multi-scale features. During deep extraction, the features of minute defects are easily submerged or lost by background noise, leading to a high false negative rate for minute defects and limiting the mAP50-95 index.

[0108] Disadvantage 2: Rigid feature fusion mechanism, resulting in low positioning accuracy.

[0109] Existing C2PSA modules use a simple weighted summation method to fuse channel and spatial attention. This approach assumes that channel and spatial information are equally important at all locations, and cannot adaptively adjust the weights for different defect types (e.g., "mouse bite" emphasizes channel information, "short circuit" emphasizes spatial information). Furthermore, the lack of residual connections causes the original detailed information to attenuate during deep propagation, making it difficult for the model to accurately locate defect edges in complex backgrounds, resulting in poor detection box regression accuracy.

[0110] Disadvantage 3: It is difficult to balance model complexity and accuracy.

[0111] To improve accuracy, it is usually necessary to increase the network depth or width. Increasing the network size leads to an exponential increase in the number of parameters and computational cost (FLOPs), reduces the model inference speed, makes it difficult to deploy on industrial edge devices with limited computing resources, and fails to meet the needs of real-time online detection in industrial fields.

[0112] The C3K2_IDWD module was included to replace the C3K2 module in the Backbone and Neck, aiming to enhance multi-scale perception capabilities and reduce computational costs. It consists of three parts: a multi-branch depthwise separable convolutional attention unit, a multi-branch depthwise separable dynamic convolution, and a C3k2 multi-branch dynamic depthwise separable convolution.

[0113] Multi-branch depthwise separable convolutional attention unit: Workflow diagram as follows Figure 3The diagram shows the workflow of a multi-branch depthwise separable convolutional attention unit in a lightweight PCB defect detection method provided in this application. The input feature map (B×C×H×W) is first compressed in spatial dimension by global average pooling (GAP) to obtain a channel statistics vector (B×C×1×1). This vector then passes through two fully connected (FC) layers for channel interaction. The first FC layer compresses the number of channels to max(C / r, 4) (where r is the compression coefficient) to prevent information collapse; the second FC layer restores the number of channels. Layer Norm, ReLU, and Sigmoid activation functions are used in between. Finally, the channel attention weights output by the Sigmoid function are multiplied channel-by-channel with the original input feature map to complete feature calibration. Results: By employing a "large-scale channel compression" and "spatial convolution-free" strategy, the feature representation of key channels is enhanced and redundant responses are suppressed without increasing inference latency.

[0114] Among them, multi-branch depthwise separable dynamic convolution: the workflow diagram is as follows Figure 4 The diagram illustrates the multi-branch depthwise separable dynamic convolution workflow of a lightweight PCB defect detection method provided in this application embodiment. The input feature map is divided into four groups according to channels. **Identity Branch:** Preserves the original features, ensuring lossless information transfer. **Square Branch:** Employs K×K (e.g., 3×3) depthwise convolutions to capture local two-dimensional contextual information. **Vertical / Horizontal Branches:** Employ 1×K and K×1 (e.g., 1×7 and 7×1) strip convolutions respectively to efficiently model long-distance vertical and horizontal dependencies, achieving a larger receptive field with lower computational cost. **Fusion:** The outputs of the three convolutional branches are concatenated along the channel dimension and then dynamically weighted by the multi-branch depthwise separable convolutional attention module. Finally, the weighted features are concatenated with the output of the identity branch along the channel dimension to obtain the final output.

[0115] Among them, the C3k2 multi-branch dynamic depthwise separable convolution has the following workflow diagram: Figure 5The diagram shows the C3k2 multi-branch dynamic depth-separable convolutional workflow of a lightweight PCB defect detection method provided in this application embodiment, designed based on a cross-stage partial network architecture. The input features first pass through a 1×1 convolution to expand the channel, then are split in two along the channel dimension. One path remains unchanged, serving as the identity mapping; the other path undergoes nonlinear transformation through n multi-branch depth-separable dynamic convolutional units. Finally, the transformed feature sequence is concatenated with the identity mapping branch along the channel dimension, then passed through a 1×1 convolution to compress the channel, followed by batch normalization (BN) and SiLU activation. If the residual connection condition is met, the output is added to the original input of the module to form a residual connection.

[0116] Specifically, the channel-spatial attention module (gated residual channel-spatial attention mechanism) replaces the C2PSA module at the backbone end, aiming to solve the problems of feature fusion rigidity and information loss. The module's workflow is as follows: Figure 6 The diagram shown is a flowchart of the channel-spatial attention module of a lightweight PCB defect detection method provided in this application embodiment. The process is as follows: Feature preprocessing: The input features first pass through a convolution module to extract local features.

[0117] Parallel attention branch:

[0118] Channel branching: Global average pooling (GAP) and global max pooling (GMP) are performed on the input features in parallel. The two outputs are concatenated and then passed through two fully connected layers (FC) and a Swish / Sigmoid activation function to generate channel attention weights.

[0119] Spatial branch: Multiple pooling operations (MP, MPα, MPβ, SP) are performed in parallel on the input features to extract multi-scale spatial context information, and then spatial attention weights are generated through 7×7 and 1×1 convolutions and Swish / Sigmoid activation.

[0120] Gated Dynamic Fusion:

[0121] The feature maps of the two branches are then concatenated after being weighted.

[0122] A spatially adaptive fusion weight matrix G is learned through a lightweight gated network (containing a 1×1 convolution and a sigmoid function).

[0123] By using G to dynamically weight and fuse the features of the two branches pixel by pixel, the model can adaptively allocate the dependence on channel enhancement and spatial enhancement according to the needs of different locations.

[0124] Residual Connection: The output after gating and fusion is directly added to the original input of the module (element-wise add).

[0125] Results: The gating mechanism enables more refined feature modulation, while residual connections ensure the integrity of the original spatial structure and weak signal features, preventing the loss of key defect information in deep networks.

[0126] The improved module in this application can be applied to other YOLO series (such as YOLOv8, YOLOv10) or single-stage detectors such as SSD.

[0127] The size (K-value) of the strip convolution kernels in C3K2_IDWD is adjustable. The gated network in the channel-spatial attention module can be replaced by a multilayer perceptron (MLP); residual connections can be replaced with dense connections.

[0128] Regarding the technical effects achieved in this application, the following data table 1 can be established:

[0129] Table 1 Comparison of PCB inspection performance data between IGR-YOLO and YOLOv11n

[0130]

[0131] It can be observed that, on the self-built PCB dataset, the method of this invention (IGR-YOLO) compared with YOLOv11n has improved precision (P) from 95.3% to 97%, recall (R) from 89.6% to 92.9%, mAP50 from 94.8% to 96.7%, and mAP50-95 from 55.4% to 66.7%.

[0132] Furthermore, by analyzing the resource consumption and other information required to achieve the detection effect in the application of the technical solution of this application and the prior art, the following data table 2 can be established:

[0133] Table 2 PCB Defect Detection Data Table of this Application and Prior Art

[0134]

[0135] It can be observed that, under the same experimental environment and parameter conditions, comparative experiments were conducted using classic target detection algorithms of the same type. The proposed method (IGR-YOLO) systematically evaluated the performance of various lightweight YOLO series target detection modules in PCB defect detection tasks. Experimental results show that the enhanced YOLOv11n_IGR proposed in this invention significantly outperforms current mainstream YOLO variants in detection accuracy under extremely low computational complexity. Specifically, YOLOv11n_IGR requires only 2.14 million parameters and 5.8 GFLOPs of computation, achieving an mAP of 96.7%, making it the best-performing module in this comparison. In contrast, the mAP of standard lightweight models such as YOLOv5n, YOLOv6n, YOLOv8n to YOLOv12n ranges from 93.6% to 95.3%, with most models having higher parameter counts and computational costs. Further category performance analysis shows that YOLOv11n_IGR achieves the highest average quality in confusing or small-scale defect categories such as "mouse bite," "open circuit," "spike," and "fake copper." Accuracy (AP) indicates that the model has stronger robustness and class discrimination ability in complex industrial defect detection scenarios. In summary, YOLOv11n_IGR can achieve higher detection accuracy with lower resource consumption, demonstrating good practical application value and deployment prospects in industrial vision inspection systems that balance real-time performance and energy efficiency.

[0136] Furthermore, as shown in Table 2, the lightweight PCB defect detection method provided in this application, by introducing a channel-spatial attention module, improves the detection accuracy from 95.7% and 87.8% to 97.3% and 90.3% respectively in open circuit and burr defect detection tasks with complex background interference. The experimental results demonstrate that this channel-spatial attention module can effectively preserve key PCB defect features while significantly suppressing interference from complex background noise, thereby improving detection accuracy. In addition, compared to existing C2PSA modules, the channel-spatial attention module described in this application exhibits superior robustness and feature selection capabilities, further validating its applicability and technical advantages in complex scenarios.

[0137] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to computer program instructions. The aforementioned computer program can be stored in a non-volatile storage medium, and when executed, it performs the steps of the above method embodiments. Alternatively, if the integrated unit of the present invention is implemented as a software functional module and sold or used as an independent product, it can also be stored in a non-volatile storage medium. Based on this understanding, the technical solution of the embodiments of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a non-volatile storage medium and includes several instructions to cause an electronic device (which may be a personal computer, server, network device, etc.) to execute all or part of the methods described in the various embodiments of the present invention.

[0138] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A lightweight PCB defect detection method, characterized in that, The method includes: The image of the PCB is acquired from the input terminal, and its features are extracted to obtain the image features. Based on the FPN-PAN structure, feature maps are fused to obtain multi-scale fused features. The decoupling head is used to process multi-scale fused images to obtain and output detection results.

2. The lightweight PCB defect detection method according to claim 1, characterized in that, The process of acquiring an image of the PCB from the input terminal and extracting its features to obtain image features includes: The input terminal takes a 640×640 pixel RGB image of the PCB and performs convolution processing through the C3K2 module to obtain the convolutional features. The convolutional features are processed by two cascaded C3K2_IDWD modules to obtain features after multiple convolutions. Feature recalibration is performed on features after multiple convolution processing using a gated residual channel-spatial attention mechanism to obtain image features.

3. The lightweight PCB defect detection method according to claim 2, characterized in that, The convolutional features are processed by two cascaded C3K2_IDWD modules to obtain multi-convolutional features, including: The C3K2_IDWD module comprises a deep convolutional attention unit, a deep convolutional unit with a dynamic multi-branch network convolutional structure, and a C3k2 multi-branch dynamic depth separable convolutional unit. The features obtained from the convolution process are calibrated by the deep convolutional attention unit, and the calibrated features are output. The calibrated features are input into the deep convolutional unit of the dynamic multi-branch network convolutional structure, and the feature maps of each output channel are stitched together to form a stitched feature map. After concatenation, the features are processed by a C3k2 multi-branch dynamic depthwise separable convolutional unit, and the features on the input side and the features on the output side of the unit are added element-wise to form a residual connection.

4. The lightweight PCB defect detection method according to claim 3, characterized in that, The step of performing feature calibration on the features obtained from convolution processing by the deep convolutional attention unit and outputting the calibrated features includes: The calibrated features are subjected to global pooling to compress the spatial dimension, resulting in channel statistical vectors; The channel statistics vector is compressed through a fully connected layer, and then restored through another fully connected layer. The channel attention weights are obtained from the recovered channel count and multiplied with the image features to obtain the calibrated features.

5. The lightweight PCB defect detection method according to claim 3, characterized in that, The calibrated features are input into the deep convolutional units of the dynamic multi-branch network convolutional structure, and the feature maps of each output channel are concatenated into a concatenated feature map, including: The deep convolutional unit of the dynamic multi-branch network convolutional structure includes identity mapping branch, square branch, and vertical / horizontal branch; Based on the identity mapping branch, the features of the calibrated features are preserved to ensure lossless information transmission; Based on the square branch, K×K depth convolution is performed on the calibrated features to obtain the local two-dimensional context information of the calibrated features; Based on vertical / horizontal branches, 1×K and K×1 strip convolutions are performed on the calibrated features to obtain the horizontal and vertical dependencies of the calibrated features over long distances. Based on the fusion unit, the outputs of the identity mapping branch, the square branch, and the vertical / horizontal branch are concatenated along the channel dimension and weighted by the deep convolutional attention unit to obtain the concatenated features.

6. The lightweight PCB defect detection method according to claim 3, characterized in that, The concatenated features are processed by a C3k2 multi-branch dynamic depthwise separable convolutional unit, and the features on the input side and the features on the output side of the unit are added element-wise to form a residual connection, including: The concatenated features are input into a 1×1 convolution expansion channel, and then input into the identity mapping channel and the deep convolutional units of n dynamic multi-branch network convolutional structures along the channel dimension for nonlinear transformation. The feature sequence after nonlinear transformation and the feature sequence of the identity mapping channel are concatenated along the channel dimension to obtain the channel concatenation feature. The channel splicing features are compressed by 1×1 convolution, batch normalized, and SiLU activated, and then added to the image features to form residual connections.

7. The lightweight PCB defect detection method according to claim 2, characterized in that, The method of recalibrating features after multiple convolution processing using a gated residual channel-spatial attention mechanism to obtain image features includes: After multiple convolutions, the features are processed by convolutional modules to obtain local features; the local features are then processed by channel branches and spatial branches to obtain channel attention weights and spatial attention weights. Based on the features after multiple convolutional processing with channel attention weights and spatial attention weights respectively, and based on a gating network, a fusion weight matrix is ​​generated; Based on the fusion weight matrix, local features are dynamically weighted to obtain the gated fusion output; The output after gating and fusion is fused with the features after multiple convolution processing to obtain image features.

8. The lightweight PCB defect detection method according to claim 1, characterized in that, The method based on the FPN-PAN structure performs feature map fusion on image features to obtain multi-scale fused features, including: Continuously acquire image features and perform image feature recognition; Based on the image feature recognition results, the temporal and spatial order and fusion method of image features are obtained; Based on the fusion method, the feature maps are fused at multiple scales according to the order in which the image features are received, so as to obtain multi-scale fused features.

9. A lightweight PCB defect detection method according to claim 1, characterized in that, The process of processing multi-scale fused images based on the decoupling head to obtain and output detection results includes: Acquire multi-scale fused images and perform target and boundary recognition based on the decoupling head; Based on the target recognition and bounding box recognition results, PCB defect detection results are acquired and output.

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