YOLO11n target detection optimization method based on huawei hisilicon hi3519dv500

Abstract

This invention discloses an optimized YOLO11n object detection method based on Huawei HiSilicon Hi3519DV500. Utilizing the Hi3519DV500 chip's built-in inference engine NNIE and the fourth-generation Yueying AI ISP, it employs an optimized architecture of three-module algorithm reconstruction and deep hardware collaboration: the backbone network replaces the original C3K2 module with the MSEAF five-branch multi-scale adaptive module, strengthening small target edge features through adaptive weighting and edge loss; a 4x downsampling P2 small target detection head is added to the Neck structure, coupled with ScalCat and Scal3DC modules to optimize cross-scale feature fusion; the SRepD reparameterized detection head unifies multi-scale detection channels, and multi-branch training enhances feature extraction; convolutional fusion during the inference stage simplifies computation; and finally, the NNIE engine completes mixed-precision INT8 quantization deployment. This invention achieves a measured inference rate of ≥80FPS and a memory usage of ≤100.3MB on the Hi3519DV500 chip platform, significantly improving detection accuracy in complex lighting and foggy environments. It is suitable for edge real-time target detection scenarios such as UAV aerial photography, security monitoring, and industrial defect detection.

Description

Technical Field

[0001] This invention relates to computer vision target detection technology, specifically to an optimized YOLO11n target detection method based on Huawei HiSilicon Hi3519DV500, which can be widely applied to embedded edge computing scenarios such as UAV airborne visual detection, real-time security video monitoring, and online defect detection of industrial products. Background Technology

[0002] YOLO11n, as a lightweight, single-stage object detection network, has been widely used in edge vision devices due to its small parameter size and fast basic inference speed. However, this model faces three key shortcomings when deployed on embedded hardware:

[0003] The small target detection performance is weak: In drone aerial photography scenes, 60-80% of the target pixel size is smaller than 32×32. After multi-layer downsampling, the small target features almost completely disappear. The original YOLO11n small target detection accuracy is only about 20%, and the problem of missed detection is prominent.

[0004] Mismatch in edge hardware computing power: The performance of onboard chips is far weaker than that of desktop GPUs. Without hardware acceleration, the original YOLO11n can achieve an inference frame rate of less than 15 FPS on embedded SoCs, which cannot meet the real-time processing requirements of 30 FPS or more for 4K video.

[0005] Poor robustness in complex environments: The input image has a low signal-to-noise ratio under conditions such as fog, low light, and image shakiness, which further leads to a significant drop in detection accuracy.

[0006] Meanwhile, Huawei HiSilicon Hi3519DV500, as an ultra-high-definition intelligent SoC launched for the vision industry, has unique hardware advantages, but there is currently no solution to deeply coordinate the algorithm optimization of YOLO11n with the hardware characteristics of Hi3519DV500. Summary of the Invention

[0007] To overcome the shortcomings of existing YOLO11n deployments on the Hi3519DV500 embedded platform in terms of accuracy, speed, and environmental adaptability, the present invention aims to provide an optimized YOLO11n target detection method based on Huawei HiSilicon Hi3519DV500. Through customized optimization of the algorithm network structure and deep adaptation and collaborative design of chip hardware resources, the method achieves a comprehensive optimal effect on the Hi3519DV500 platform, including a significant improvement in small target detection accuracy, a reduction in model parameters, and an inference speed of over 80 FPS.

[0008] To achieve the above objectives, the technical solution adopted by this invention is: a YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500, comprising the following steps:

[0009] 1) Environment Setup: The runtime environment is set up on the Hi3519DV500 chip platform; the Hi3519DV500 integrates a dual-core ARM Cortex-A55@1000MHz processor, a 2.5TOPSINT8 computing power inference engine NNIE and a fourth-generation Yueying AIISP image processing module; it is equipped with the HiSilicon NNIESDK toolchain, and configured with a MIPI-CSI image acquisition interface and DMA memory interaction channel;

[0010] 2) Perform three-module reconstruction and optimization on the original YOLO11n network, specifically involving three steps: a, b, and c.

[0011] a. Backbone network optimization: The C3K2 module of the YOLO11n backbone network is replaced with the MSEAF multi-scale edge adaptive module; MSEAF is set with 5 multi-scale feature extraction branches, each of which is a 3×3 standard convolution, a 5×5 depthwise separable convolution, a 7×7 depthwise separable convolution, and two sets of 1×1 bottleneck convolution + BN + SiLU structure; the output features of each branch are concatenated along the channels, and then adaptive weighted fusion weights are generated through lightweight channel attention to achieve background noise suppression and object edge feature enhancement;

[0012] b. Neck Structure and Detector Head Expansion and Optimization: Based on the original Neck structure P3 / P4 / P5 detector heads, a new P2 small target detector head with a corresponding 4x downsampling rate is added; a ScalCat module is connected between P2 and P3, and cascaded coordinate attention and channel attention achieve precise spatial positioning; a Scal3DC module is configured between P3 and P4 to reduce the computational power loss of cross-scale fusion; cross-scale feature fusion is optimized by combining ScalCat and Scal3DC modules, so that the P2 small target detector head retains ultra-high resolution feature details;

[0013] c. Lightweight modification of the detection head with heavy parameterization: The SRepD shared heavy parameterization detection head is adopted to unify the four detection head channels of P2 / P3 / P4 / P5 to 256 channels; during the training phase, a multi-branch parallel structure of 3×3 standard convolution, 3×3 depth convolution, and 1×1 point convolution is used to improve the feature representation capability; during the inference phase, the multi-branch is equivalently folded into a single 3×3 standard convolution through DEConv heavy parameterization, so as to achieve the unity of strong expression in training and low redundancy in inference.

[0014] 3) Utilize the NNIE inference engine to deploy the optimized YOLO11n model using INT8 quantization, and complete model conversion and inference acceleration through the complete API and HiSilicon NNIESDK toolchain;

[0015] 4) The Hi3519DV500's built-in fourth-generation Yueying AIISP image processing module is called to perform real-time preprocessing on the image input via the MIPI-CSI interface. During the processing, DRC dynamic range compression, 4K@30fps image processing, BNR backlight noise reduction, 3DNR three-dimensional noise reduction, DM detail enhancement, 6-DoF digital image stabilization, and super wide dynamic range correction are performed in sequence to complete the image quality enhancement.

[0016] 5) Model inference and result output: The image enhanced by the AIISP image processing module is input into the optimized YOLO11n model for inference. The inference engine NNIE is executed, and the dual-core ARM processor performs post-processing and outputs the target detection results. The real-time detection speed of no less than 80FPS is achieved on the Hi3519DV500 chip platform, and the memory usage does not exceed 100MB.

[0017] Furthermore, in step 2)a, the MSEAF module introduces an edge-aware loss function. During the training phase, additional supervision is provided to ensure the quality of edge feature extraction.

[0018]

[0019] in for Gradient operator, for Output features For the corresponding Edge features.

[0020] In step 2)b, a bidirectional feature pyramid network (BiFPN) is introduced into the Neck structure to assign learnable weights to the multi-scale feature fusion path, so that the P2 small target detection head can obtain a larger weight ratio in the fusion process, further enhancing the contribution of small target features.

[0021] In step 2)c, the DEConv reparameter convolution achieves an equivalent transformation through the following formula:

[0022]

[0023]

[0024] In the formula: , The weights and biases of the merged single convolutional kernels; The parameters are 3×3 standard convolution parameters; These are the parameters for depthwise convolution; The parameters are 1×1 point convolution parameters.

[0025] In step 2)c, the SRepD shared reparameterized detector head also introduces a channel sharing mechanism, so that P2 / P3 / P4 / P5 share a set of basic convolution kernels, and multi-scale adaptation is achieved by relying on parameter offset, thereby compressing the number of detector head parameters.

[0026] The quantization deployment in step 3) includes hybrid precision quantization: the MSEAF module and the ScalCat module use INT8 quantization, and the first layer convolution of the shared reparameterized detector head of SRepD retains FP16 precision; a subset of the COCO val2017 dataset is used in combination with the KL divergence algorithm to determine the optimal quantization threshold, and quantization-aware training QAT is used to offset the precision loss caused by quantization.

[0027] In step 5), during model inference and result output, the dual-core ARM processor undertakes the overall task scheduling, NMS post-processing, and control logic. The NMS adopts a DIoU-NMS variant, which optimizes the dynamic adjustment strategy of the IoU threshold for dense small target scenarios. The dual-core ARM processor and the inference engine NNIE rely on the DMA zero-copy mechanism to interactively transmit intermediate feature data, eliminate the overhead of repeated memory copying, and output detection boxes and classification results.

[0028] The beneficial effects of this invention are:

[0029] Significantly improved small target detection accuracy: MSEAF edge enhancement + P2 detection head collaborative optimization, small target mAP increased from 19.8% to 36.7%, small target false detection rate decreased by more than 60%, solving the problem of small targets "disappearing" after multiple downsampling;

[0030] Inference speed is doubled: After NNIE hardware acceleration, the chip's measured frame rate is 80.2 FPS, which is 5.6 times higher than the original 14.3 FPS, meeting the requirements for real-time processing of 4K@30fps video;

[0031] Significantly lightweight model: SRepD reparameterization and channel sharing reduce the total number of model parameters from 2.6M to 1.1M, with inference memory usage ≤100.3MB, making it suitable for embedded small-capacity storage.

[0032] Enhanced robustness in complex environments: AI ISP end-to-end image processing improves image signal-to-noise ratio by 6dB, and overall mAP is improved by more than 3.2% in low-light and foggy scenes;

[0033] Significant performance gains from hardware and software synergy: The algorithm structure is customized and optimized for the Hi3519DV500 hardware architecture, resulting in an overall performance improvement of over 30% compared to separate algorithm and hardware optimization solutions.

[0034] This invention achieves a measured inference rate of ≥80FPS and a memory usage of ≤100.3MB on the Hi3519DV500 chip platform, significantly improving detection accuracy in complex lighting and foggy environments. It is suitable for edge real-time target detection scenarios such as UAV aerial photography, security monitoring, and industrial defect detection. Attached Figure Description

[0035] Figure 1 This is a diagram of the overall system pipeline architecture of the present invention.

[0036] Figure 2 This is a diagram of the internal structure of the MSEAF multi-scale edge adaptive module in this invention.

[0037] Figure 3 This is a schematic diagram of the Neck structure, the newly added P2 small target detection head, and the cross-scale fusion module in this invention.

[0038] Figure 4 This is a schematic diagram of the dual-stage training / inference structure of the SRepD reparameterized detection head in this invention.

[0039] Figure 5 This is a schematic diagram illustrating the performance indicators of the Hi3519DV500 terminal quantitative deployment in this invention. Detailed Implementation

[0040] See appendix Figure 1 A schematic diagram of the overall architecture of the operating environment built on the Hi3519DV500 chip platform of this invention is disclosed.

[0041] The overall architecture of this invention uses the Hi3519DV500 as the core hardware platform, integrating a dual-core ARM Cortex-A55@1000MHz processor, a 2.5TOPSINT8 computing power inference engine NNIE, and a fourth-generation Yueying AIISP image processing module; it is equipped with the HiSilicon NNIE SDK toolchain, configured with a MIPI-CSI image acquisition interface and a DMA memory interaction channel; and it executes in the pipeline sequence of "image acquisition → ISP enhancement → model inference → post-processing output".

[0042] The image sensor is connected to the Hi3519DV500 chip via a MIPI-CSI interface. The raw RAW image is sent to the chip's built-in fourth-generation Yueying AI ISP image processing module for real-time preprocessing. The fourth-generation Yueying AIISP image processing module sequentially performs DRC dynamic range compression, BNR backlight noise removal, 3DNR three-dimensional noise reduction, and DM detail enhancement, improving the overall signal-to-noise ratio by 6dB. The image enhanced by the AI ​​ISP is then sent to the optimized YOLO11n model for inference, which is executed by the Hi3519DV500's built-in inference engine NNIE. The dual-core ARM Cortex-A55@1000MHz processor is responsible for overall task scheduling, NMS post-processing, and control logic. It interacts with the NNIE engine through a DMA zero-copy mechanism to avoid the overhead of repeated memory copying between the CPU and NPU.

[0043] The target detection optimization method in this invention requires a three-module reconstruction optimization of the original YOLO11n network, specifically in the following ways:

[0044] 1) See Appendix Figure 2 This is a schematic diagram of the internal structure of the MSEAF multi-scale edge adaptive module in this invention. It adopts a backbone network optimization method, replacing the C3K2 module in the backbone network with the MSEAF multi-scale edge adaptive module. MSEAF is set up with a 5-branch multi-scale feature extraction structure, specifically branch 1: 3×3 standard convolution, which captures local texture details.

[0045] Branch 2: 5×5 depthwise separable convolution, which expands the receptive field while controlling the computational load;

[0046] Branch 3: 7×7 depthwise separable convolution to capture long-distance edge correlations;

[0047] Branch 4: 1×1 bottleneck convolution + BN + SiLU activation, performing channel compression and nonlinear transformation;

[0048] Branch 5: 1×1 bottleneck convolution + BN + SiLU activation, providing supplementary channel dimension features.

[0049] The outputs of the five branches are concatenated along the channel dimension and then processed by an adaptive weighted fusion module. The weighting coefficients are generated through a lightweight channel attention mechanism (similar to the Squeeze-and-Excitation structure of SE-Net, but with 60% fewer parameters) to achieve adaptive suppression of background noise and enhancement of edge information.

[0050] In the aforementioned backbone network optimization process, the MSEAF module introduces an edge-aware loss function. During the training phase, additional supervision is provided to ensure the quality of edge feature extraction.

[0051]

[0052] in for Gradient operator, for Output features For the corresponding Edge features.

[0053] 2) See Appendix Figure 3 This is a schematic diagram of the cross-scale fusion of the Neck structure and the newly added P2 small target detection head in this invention. In the optimization of the Neck structure, a P2 small target detection head with a corresponding downsampling rate of 4 times is added on the basis of the original Neck structure P3 / P4 / P5 detection head, and the cross-scale feature fusion is optimized by combining the ScalCat and Scal3DC modules.

[0054] The P2 detector head corresponds to a 4x downsampling rate (i.e., the feature map resolution is 1 / 4 of the input image), preserving ultra-high resolution feature details and specifically targeting small targets smaller than 32×32. Compared to the original YOLO11n which only has three detector heads, P3, P4, and P5, the addition of the P2 detector head enables the model to capture small target information in the earliest feature layer, effectively solving the problem of small targets "disappearing" after multiple downsampling.

[0055] The ScalCat module is used for cross-scale connections between P2 and P3, cascading coordinate attention and channel attention. Coordinate attention significantly improves spatial localization accuracy by decomposing channel attention into two one-dimensional feature encoding processes, aggregating features along the X and Y axes respectively, with minimal increase in the number of parameters.

[0056] Scal3DC module: Applied between P3 and P4, it uses 3D separable convolution (decomposition of time dimension × spatial dimension) to reduce computation while retaining the ability to fuse cross-frame temporal features, making it suitable for continuous video stream detection scenarios.

[0057] In the above Neck structure optimization, a bidirectional feature pyramid network (BiFPN) is also introduced to assign learnable weights to the multi-scale feature fusion path, so that the P2 small target detection head can obtain a larger weight ratio in the fusion process, further enhancing the contribution of small target features.

[0058] 3) See Appendix Figure 4This is a schematic diagram of the dual-stage training / inference structure of the SRepD reparameterized detector head in this invention. The detector head undergoes a lightweight reparameterization modification, employing a shared SRepD reparameterized detector head with four detector heads unified to 256 channels. During the training phase, a multi-branch structure is used, including three parallel paths: 3×3 standard convolution, 3×3 depthwise convolution, and 1×1 pointwise convolution. The outputs of each path are concatenated and then fused using a 1×1 convolution, providing stronger feature representation capabilities.

[0059] During the inference phase, structural reparameterization is used. The DEConv reparameterized convolution transforms multi-branch convolutions into equivalent single-path 3×3 standard convolutions, reducing computation by approximately 40%. The DEConv reparameterized convolution achieves this equivalent transformation using the following formula:

[0060]

[0061]

[0062] This achieves a balance between strong training expression and low inference redundancy.

[0063] In the above process, the RepD shared reparameterized detector head introduces a channel sharing mechanism. The four detector heads share the same set of basic convolutional kernels and generate parameters for each scale detector head only by different offsets, reducing the total number of detector head parameters from the original approximately 1.2M to approximately 0.35M, a reduction of 70%.

[0064] See appendix Figure 5 This is a schematic diagram illustrating the performance metrics of the Hi3519DV500-based quantization deployment in this invention. The deployment process consists of three stages: model training, INT8 quantization conversion, and edge inference. The model is converted to the NNIE executable format using the HiSilicon SDK toolchain. Real-world testing on the Hi3519DV500 showed an inference speed of 80.2 FPS, memory usage of only 100.3 MB, and end-to-end latency as low as 12.5 ms, meeting real-time requirements.

[0065] The optimized YOLO11n model was deployed using the NNIE inference engine of the Hi3519DV500 with INT8 quantization. The quantization strategy included:

[0066] Hybrid precision quantization: INT8 quantization is used for sensitive modules such as MSEAF and ScalCat, while FP16 precision is retained for the first layer convolution of the SRepD detection head to avoid precision loss caused by the accumulation of quantization errors.

[0067] Calibration dataset: Calibration was performed using a subset of 5000 images from COCO val2017, and the optimal quantization threshold for each layer was determined using the KL divergence minimization method.

[0068] Quantization-Aware Training (QAT): During the training phase, INT8 quantization noise is simulated to adapt the model weight distribution to the low-precision representation, and the mAP loss after quantization is controlled within 0.5%.

[0069] The NNIE inference engine supports mainstream neural network frameworks such as TensorFlow Lite and ONNX, and accelerates model conversion and inference through a complete API and toolchain.

[0070] The Hi3519DV500 utilizes its built-in fourth-generation Yueying AI ISP for real-time preprocessing of the input image. This ISP supports DRC dynamic range compression, 4K@30fps image processing, BNR backlight noise reduction, 3DNR three-dimensional noise reduction, super wide dynamic range, and 6-DoF digital image stabilization, providing excellent all-weather image quality for object detection.

[0071] The AI-enhanced image is fed into the optimized YOLO11n model for inference. Compared to directly inputting the original RAW image, the detection mAP is improved by approximately 3.2 percentage points, especially in low-light conditions. The improvement is most significant in the scenario; the target detection result is output after inference. Moreover, the inference achieves a real-time detection speed of no less than 80FPS on the Hi3519DV500, with a memory usage of no more than 100MB.

[0072] During the inference process described above, the dual-core A55 processor is responsible for overall scheduling, NMS post-processing, and control logic. The NMS uses a DIoU-NMS variant, which optimizes the dynamic adjustment strategy of the IoU threshold for dense small target scenarios. The post-processing pipeline and the NNIE inference pipeline are executed in parallel, and intermediate features are transmitted through a DMA zero-copy mechanism, with an end-to-end latency as low as 12.5ms.

[0073] This device is used in edge-end real-time target detection scenarios such as drone aerial photography and detection, security video surveillance, and industrial component defect detection. The overall power consumption of the device is ≤2.2W.

[0074] The above-described optimized process is used to conduct a landing test of 120m high-altitude UAV aerial target detection as an embodiment of the present invention.

[0075] 1) In terms of hardware deployment, the optimized model is deployed on the development board of the UAV optoelectronic pod equipped with Hi3519DV500 main control, the embedded system is Ubuntu18.04, and the HiSilicon SDK version is V3.2.0; the airborne 4K camera is connected to the chip via MIPI-CSI, the power consumption of the whole machine is less than 2.1W, which meets the UAV's endurance constraints; the UAV hovers at an altitude of 120m and outputs 4K@30fps video stream.

[0076] 2) Dataset and Training Configuration: For model training, the training dataset consists of the VisDrone 2021 public aerial photography dataset plus 180,000 frames of mixed images collected on-site by enterprises, covering multiple scenes including sunny days, foggy days, dusk, and low light. The model is trained end-to-end in the PyTorch framework, with a total of 300 training epochs. The initial learning rate is 0.01, and cosine annealing is used for learning rate scheduling. Edge loss is loaded synchronously during training. With SRepD multi-branch regularization constraints, the trained model is adapted to subsequent reparameterized folding operations, and the FP32 model file size after training is 4.8MB.

[0077] 3) Model Quantization and Deployment: The FP32 model was converted to INT8 format using the HiSilicon NNIE SDK V3.2.0 toolchain. A per-channel quantization strategy was adopted during the quantization process. FP16 mixed accuracy was retained for sensitive layers such as the MSEAF multi-scale edge adaptive module and the SRepD shared reparameterized detection head, while the remaining layers were uniformly quantized to INT8. The overall quantization accuracy loss was controlled within 0.3%. The final quantized model file size was compressed from 4.8MB to 1.2MB, allowing it to be directly burned into the eMMC storage of the Hi3519DV500 development board.

[0078] 4) Test Results and Analysis: All-weather tests were conducted in actual aerial photography scenarios. The core performance indicators are as follows:

[0079]

[0080] Among them, the average size of pedestrian targets at an altitude of 120m is only 16×48 pixels, which is a typical small target. Thanks to the background noise suppression capabilities of the newly added P2 small target detection head (4 times downsampling rate) and the MSEAF edge adaptive module, the pedestrian detection mAP has been significantly improved from 20.1% in the original YOLO11n to 34.2%, and the false negative rate has been reduced from about 65% to 38%.

[0081] The end-to-end inference pipeline latency breakdown is as follows: AI ISP real-time preprocessing (DRC+BNR+3DNR+DM enhancement) takes approximately 1.2ms, the NNIE engine executes INT8 quantization model inference for approximately 10.1ms, and the dual-core A55 processor executes NMS post-processing and result encapsulation for approximately 1.2ms, resulting in a total end-to-end latency as low as 12.5ms. The measured inference speed reaches 80.2 FPS, far exceeding the 33 FPS requirement of 4K@30fps video streams, while the memory usage is only 100.3 MB, meeting the typical memory limit of 256MB for embedded platforms.

[0082] 5) Robustness Verification in Complex Environments: Comparative tests were conducted in two extreme scenarios: foggy weather (visibility <50m) and dusk (illuminance <50lux). The original YOLO11n showed a sharp drop in mAP to 11.3% in foggy weather and 15.7% in dusk. The method of this invention, benefiting from the multi-level 3D denoising and super wide dynamic range processing of the Hi3519DV500 fourth-generation Yueying AI ISP, maintained mAP at 28.6% in foggy weather and 33.4% in dusk, representing improvements of 17.3% and 17.7% respectively, verifying the significant advantages of algorithm-hardware co-design in complex environments.

Claims

1. An optimized YOLO11n target detection method based on Huawei HiSilicon Hi3519DV500, characterized in that... Includes the following steps: 1) Environment Setup: The runtime environment is set up on the Hi3519DV500 chip platform; the Hi3519DV500 integrates a dual-core ARM Cortex-A55@1000MHz processor, a 2.5TOPSINT8 computing power inference engine NNIE and a fourth-generation Yueying AIISP image processing module; it is equipped with the HiSilicon NNIESDK toolchain, and configured with a MIPI-CSI image acquisition interface and DMA memory interaction channel; 2) Perform three-module reconstruction and optimization on the original YOLO11n network, specifically involving three steps: a, b, and c. a. Backbone network optimization: The C3K2 module of the YOLO11n backbone network is replaced with the MSEAF multi-scale edge adaptive module; MSEAF is set with 5 multi-scale feature extraction branches, each of which is a 3×3 standard convolution, a 5×5 depthwise separable convolution, a 7×7 depthwise separable convolution, and two sets of 1×1 bottleneck convolution + BN + SiLU structure; the output features of each branch are concatenated along the channels, and then adaptive weighted fusion weights are generated through lightweight channel attention to achieve background noise suppression and object edge feature enhancement; b. Neck structure and detection head expansion and optimization: On the basis of the original Neck structure P3 / P4 / P5 detection heads, a new P2 small target detection head with a corresponding 4 times downsampling rate is added; ScalCat module is connected between P2 and P3, and cascaded coordinate attention and channel attention achieve precise spatial positioning; Scal3DC module is configured between P3 and P4 to reduce cross-scale fusion computing power loss. By combining ScalCat and Scal3DC modules to optimize cross-scale feature fusion, the P2 small target detection head retains ultra-high resolution feature details. c. Lightweight transformation of the detection head with heavy parameterization: Adopt SRepD shared heavy parameterization detection head to unify the four detection head channels P2 / P3 / P4 / P5 to 256 channels; During the training phase, a multi-branch parallel structure of 3×3 standard convolution, 3×3 depthwise convolution, and 1×1 point convolution is used to improve feature representation capabilities. During the inference phase, the multi-branch structure is equivalently folded into a single-path 3×3 standard convolution through DEConv heavy parameter convolution, achieving a balance between strong training representation and low inference redundancy. 3) Utilize the NNIE inference engine to deploy the optimized YOLO11n model using INT8 quantization, and complete model conversion and inference acceleration through the complete API and HiSilicon NNIESDK toolchain; 4) The Hi3519DV500's built-in fourth-generation Yueying AIISP image processing module is called to perform real-time preprocessing on the image input via the MIPI-CSI interface. During the processing, DRC dynamic range compression, 4K@30fps image processing, BNR backlight noise reduction, 3DNR three-dimensional noise reduction, DM detail enhancement, 6-DoF digital image stabilization, and super wide dynamic range correction are performed in sequence to complete the image quality enhancement. 5) Model inference and result output: The image enhanced by the AIISP image processing module is input into the optimized YOLO11n model for inference. The inference engine NNIE is executed, and the dual-core ARM processor performs post-processing and outputs the target detection results. The real-time detection speed of no less than 80FPS is achieved on the Hi3519DV500 chip platform, and the memory usage does not exceed 100MB.

2. The YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500 according to claim 1, characterized in that: In step 2)a, the MSEAF module introduces an edge-aware loss function. During the training phase, additional supervision is provided to ensure the quality of edge feature extraction. in for Gradient operator, for Output features For the corresponding Edge features.

3. The YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500 according to claim 1, characterized in that: In step 2)b, a bidirectional feature pyramid network (BiFPN) is introduced into the Neck structure to assign learnable weights to the multi-scale feature fusion path, so that the P2 small target detection head can obtain a larger weight ratio in the fusion process, further enhancing the contribution of small target features.

4. The YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500 according to claim 1, characterized in that: In step 2)c, the DEConv reparameter convolution achieves an equivalent transformation through the following formula: In the formula: , The weights and biases of the merged single convolutional kernels; The parameters are 3×3 standard convolution parameters; These are the parameters for depthwise convolution; The parameters are 1×1 point convolution parameters.

5. The YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500 according to claim 1, characterized in that: In step 2)c, the SRepD shared reparameterized detector head also introduces a channel sharing mechanism, so that P2 / P3 / P4 / P5 share a set of basic convolution kernels, and multi-scale adaptation is achieved by relying on parameter offset, thereby compressing the number of detector head parameters.

6. The YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500 according to claim 1, characterized in that: The quantization deployment in step 3) includes hybrid precision quantization: the MSEAF module and the ScalCat module use INT8 quantization, and the first layer convolution of the shared reparameterized detector head of SRepD retains FP16 precision; a subset of the COCO val2017 dataset is used in combination with the KL divergence algorithm to determine the optimal quantization threshold, and quantization-aware training QAT is used to offset the precision loss caused by quantization.

7. The YOLO11n target detection optimization method based on Huawei HiSilicon Hi3519DV500 according to claim 1, characterized in that: In step 5), during model inference and result output, the dual-core ARM processor undertakes the overall task scheduling, NMS post-processing, and control logic. The NMS adopts a DIoU-NMS variant, which optimizes the dynamic adjustment strategy of the IoU threshold for dense small target scenarios. The dual-core ARM processor and the inference engine NNIE rely on the DMA zero-copy mechanism to interactively transmit intermediate feature data, eliminate the overhead of repeated memory copying, and output detection boxes and classification results.

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