Display panel, display module and display device

Abstract

The application relates to the technical field of display, in particular to a display panel, a display module and a display device. The display panel comprises a substrate, a pin and a connecting line on one side of the substrate; one end of the connecting line is connected with the first pin, and the other end is connected with the second pin. The first pin is used for binding with the input pin of the driving chip, and the second pin is used for binding with the flexible circuit board. The first pin comprises a first sub-pin and a second sub-pin, the second pin comprises a third sub-pin and a fourth sub-pin, the first sub-pin and the third sub-pin are connected with the first connecting line, and the second sub-pin and the fourth sub-pin are connected with the second connecting line; at least one first dummy pin is arranged between the first sub-pin and the second sub-pin; the first lead line is routed between the first sub-pin and the second sub-pin, between the first connecting line and the second connecting line, and between the third sub-pin and the fourth sub-pin. The application can shorten the length of the connecting line and reduce the impedance of the connecting line.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel, a display module, and a display device. Background Technology

[0002] Current display technologies include COG (Chip on Glass), COF (Chip on Film), and COP (Chipon Plastic). COG involves directly bonding the driver chip to the substrate; COF involves bonding the driver chip to a flexible circuit board, which then bends to the back of the screen; and COP involves bending the back panel of the panel itself to the back of the screen. In both COG and COP technologies, the impedance of the connection between the driver chip and the flexible circuit board has always been a key consideration for developers. Because the driver chip has small pins, and the pins requiring lead wires are irregular, while the flexible circuit board typically has pins of the same size and spacing, the pins of the driver chip on the panel and the corresponding pins on the flexible circuit board are usually connected by diagonal wires. However, due to space constraints, some diagonal wires have a large angle of inclination, which can easily result in insufficient impedance. Summary of the Invention

[0003] This invention provides a display panel, a display module, and a display device to solve the technical problem of excessive impedance in the connection lines between corresponding pins on the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a substrate, and a first pin, a second pin, a connecting line and a first lead located on one side of the substrate; one end of the connecting line is connected to at least one first pin and the other end is connected to at least one second pin; Multiple first pins and multiple second pins are arranged along a first direction, with the first pins located on one side of the second pins in the second direction, and the second direction intersecting the first direction; The plurality of first pins include a first sub-pin, a second sub-pin, and a first dummy pin, with at least one first dummy pin positioned between the first sub-pin and the second sub-pin; the plurality of second pins include a third sub-pin and a fourth sub-pin, and the connecting lines include adjacent first connecting lines and second connecting lines; a first connecting line connects the first sub-pin and the third sub-pin, and a second connecting line connects the second sub-pin and the fourth sub-pin; wherein, The first lead includes a first segment, a second segment, and a third segment, with the two ends of the second segment connecting to the first segment and the third segment, respectively; The orthographic projection of the first line segment onto the substrate lies between the orthographic projections of the first sub-pin and the second sub-pin onto the substrate. The orthographic projection of the second line segment onto the substrate lies between the orthographic projections of the first connecting line and the second connecting line onto the substrate. The orthographic projection of the third line segment onto the substrate lies between the orthographic projections of the third sub-pin and the fourth sub-pin onto the substrate.

[0005] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display module, including a driver chip, a flexible circuit board, and a display panel provided in any embodiment of the present invention, wherein the driver chip is bound to a first pin, and the flexible circuit board is bound to a second pin.

[0006] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display module provided in any embodiment of the present invention.

[0007] The display panel, display module, and display device provided by the embodiments of the present invention have the following beneficial effects: The embodiments of the present invention utilize a first dummy pin setting area among a plurality of first pins to route the first lead in the area between the first and second sub-pins, the area between the first and second connecting lines, and the area between the third and fourth sub-pins. By using the first lead to separate the connecting lines on the left and right sides, the position of the second pin located on at least one side of the first lead can be appropriately adjusted, reducing the misalignment distance of the corresponding first and second pins located on at least one side of the first lead in the first direction. This shortens the length of the connecting line located on at least one side of the first lead in the first direction, thereby reducing the impedance of the connecting line and ensuring that the impedance of the connecting line meets the requirements. The embodiments of the present invention can avoid the risk of signal loss due to excessive connecting line impedance and can prevent signal loss from causing poor panel display. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a partial schematic diagram of a display panel in related technologies; Figure 2 This is a partial schematic diagram of a display panel provided in an embodiment of the present invention; Figure 3 This is a partial schematic diagram of another display panel in the related technology; Figure 4 This is another partial schematic diagram of the display surface provided in an embodiment of the present invention; Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 for Figure 6 A schematic diagram of a cross-section at the position of the tangent AA′; Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of a display module provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0010] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0011] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0012] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this invention can be combined with each other without contradiction.

[0013] Figure 1 This is a partial schematic diagram of a display panel in the related art. Figure 1The diagram illustrates multiple first pins 10, multiple second pins 20, and multiple connecting lines 30 at a partial location on the display panel. One end of each connecting line 30 is connected to a first pin 10, and the other end is connected to a second pin 20. Among the multiple first pins 10 is a dummy pin 10', which is a pin that does not need to be connected to a signal and does not need to be connected to a second pin 20. The presence of the dummy pin 10' prevents the multiple connecting lines 30 from being routed perfectly symmetrically. Furthermore, the impedance of the connecting lines 30 is limited by the routing space, line width, and spacing, which can lead to some connecting lines 30 having excessively large tilt angles and excessively long lengths, resulting in some connecting lines 30 failing to meet impedance requirements. Figure 1 The connecting line 30' shown in the diagram is a line with an excessively large tilt angle, which may result in insufficient impedance. If the impedance of the connecting line is too high, it may cause signal loss from the flexible circuit board to the driver chip, leading to poor panel display.

[0014] To address the problems existing in related technologies, embodiments of the present invention provide a display panel that utilizes the area where a dummy pin is located among multiple first pins. The lead wires that would normally need to be wound around both sides of the pin are routed within the area of ​​the dummy pin. By separating the connecting lines on the left and right sides with the lead wires, the position of the second pin located on at least one side of the lead wire can be adjusted. This reduces the lateral misalignment distance between the first and second pins connected to the adjacent connecting lines, thereby reducing the tilt angle of the diagonally pulled wires. This shortens the length of the connecting lines without increasing the longitudinal distance between the first and second pins, thus reducing the impedance of the connecting lines. The above is the main technical concept of the present invention. Specific embodiments are used below to illustrate the invention.

[0015] Figure 2 This is a partial schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This diagram illustrates a top view of a portion of the display panel, which includes a substrate. Figure 2 The first pin 10, the second pin 20, the connecting line 30, and the first lead 40 shown in the diagram are all located on the substrate. The first pin 10 is used to bond to the input pin of the driver chip, and the second pin 20 is used to bond to the flexible circuit board.

[0016] Multiple first pins 10 and multiple second pins 20 are arranged along a first direction x, with the first pins 10 located on one side of the second pins 20 in a second direction y, which intersects the first direction x. One end of a connecting line 30 is connected to at least one first pin 10, and the other end is connected to at least one second pin 20. The correspondence between the first pins 10 and the second pins 20 can be one-to-one, one-to-many, many-to-one, or many-to-many. For example, if the first pins 10 and second pins 20 are connected in a one-to-one correspondence, then one end of the connecting line 30 is connected to one first pin 10, and the other end is connected to one second pin 20. If two or more first pins 10 are connected to one second pin 20, then one end of the connecting line 30 is connected to two or more first pins 10, and the other end is connected to one second pin 20.

[0017] The plurality of first pins 10 include a first sub-pin 11, a second sub-pin 12, and a first dummy pin 13, with at least one first dummy pin 13 disposed between the first sub-pin 11 and the second sub-pin 12. Figure 2 The diagram illustrates that five first dummy pins 13 are provided between the first sub-pin 11 and the second sub-pin 12. The first dummy pins 13 are the pins among the multiple first pins 10 that are not used for signal transmission. The purpose of providing the first dummy pins 13 is to ensure the regular arrangement of multiple pins and to optimize the stress distribution of the package.

[0018] Multiple second pins 20 include a third sub-pin 21 and a fourth sub-pin 22, and connecting lines 30 include adjacent first connecting lines 31 and second connecting lines 32; a first connecting line 31 connects the first sub-pin 11 and the third sub-pin 21, and a second connecting line 32 connects the second sub-pin 12 and the fourth sub-pin 22. That is, the first connecting line 31 and the second connecting line 32 are two adjacent connecting lines 30 that are respectively connected to the first pin 10 and the second pin 20.

[0019] The first lead 40 includes a first segment 41, a second segment 42 and a third segment 43, with the two ends of the second segment 42 connected to the first segment 41 and the third segment 43 respectively.

[0020] Figure 2 A partial top view of the display panel is shown, illustrating that the top view direction of the display panel is parallel to the projection direction onto the substrate. In the top view, a structure coincides with its orthographic projection onto the substrate, such as the first line segment 41 coinciding with its orthographic projection onto the substrate. Figure 2It can be seen that the orthographic projection of the first line segment 41 onto the substrate lies between the orthographic projections of the first sub-pin 11 and the second sub-pin 12 onto the substrate; the orthographic projection of the second line segment 42 onto the substrate lies between the orthographic projections of the first connecting line 31 and the second connecting line 32 onto the substrate; and the orthographic projection of the third line segment 43 onto the substrate lies between the orthographic projections of the third sub-pin 21 and the fourth sub-pin 22 onto the substrate. That is, the first lead 40 is routed in the regions between the first sub-pin 11 and the second sub-pin 12, the regions between the first connecting line 31 and the second connecting line 32, and the regions between the third sub-pin 21 and the fourth sub-pin 22. In this embodiment of the invention, the number of first leads 40 arranged between the first sub-pin 11 and the second sub-pin 12 is not limited; it can be one, two, or more. Figure 2 The diagram only shows the arrangement of 8 first lead wires 40.

[0021] In this embodiment of the invention, the first lead 40 is routed in the area where the first dummy pin 13 is set, the area between the first connecting line 31 and the second connecting line 32, and the area between the third sub-pin 21 and the fourth sub-pin 22. This can reduce the lateral misalignment distance between the first pin 10 and the second pin 20 that are adjacent to and correspondingly connected to the first lead 40. Figure 2 The diagram illustrates that the misalignment distance between the corresponding second sub-pin 12 and the fourth sub-pin 22 in the first direction x is L1.

[0022] Figure 3 This is a partial schematic diagram of another display panel in the related technology. Figure 3 It indicates that Figure 2 They are roughly in the same position. Figure 3 A first connecting line 31 connects the first sub-pin 11 and the third sub-pin 21, and a second connecting line 32 connects the second sub-pin 12 and the fourth sub-pin 22. Five first dummy pins 13 are provided between the first sub-pin 11 and the second sub-pin 12, and the third sub-pin 21 and the fourth sub-pin 22 are adjacent to each other. Figure 3 Related technologies and Figure 2 The difference in the embodiments is that, Figure 3 The first lead 40 in this embodiment of the invention is not provided. Figure 3 Multiple connecting lines 30 are sequentially connected to multiple second pins 20 arranged along the first direction x. The second sub-pin 12 and the fourth sub-pin 22 connected to it are offset by a distance L0 in the first direction x.

[0023] exist Figure 2 and Figure 3In the embodiment where the plurality of first pins 10 have the same size and the same arrangement pitch, and the plurality of second pins 20 have the same size and the same arrangement pitch, it can be seen that in the related art, about 6 second pins 20 are arranged between the misalignment distance in the first direction x of the second sub-pin 12 and the fourth sub-pin 22 connected thereto, while in the embodiment of the present invention, about 4 second pins 20 are arranged between the misalignment distance in the first direction x of the correspondingly connected second sub-pin 12 and fourth sub-pin 22. That is, L1<L0. After adopting the design of the embodiment of the present invention, the misalignment distance in the first direction x between the correspondingly connected first pin 10 and second pin 20 is significantly reduced.

[0024] In the embodiment of the present invention, the first lead 40 is routed using the region where the first dummy pin 13 is disposed in the plurality of first pins 10 (i.e., the region between the first sub-pin 11 and the second sub-pin 12), the region between the first connection line 31 and the second connection line 32, and the region between the third sub-pin 21 and the fourth sub-pin 22. The connection lines 30 on the left and right sides are separated by the first lead 40, so that the position of the second pin 20 located on at least one side of the first lead 40 can be appropriately adjusted, and the misalignment distance in the first direction x between the correspondingly connected first pin 10 and second pin 20 located on at least one side of the first lead 40 in the first direction x is reduced, thereby shortening the length of the connection line 30 located on at least one side of the first lead 40 in the first direction x, reducing the impedance of the connection line 30, and making the impedance of the connection line 30 meet the requirements. The embodiment of the present invention can avoid the risk of signal loss caused by excessive impedance of the connection line 30, and can avoid poor display of the panel caused by signal loss.

[0025] Exemplarily, Figure 4 is another partial schematic view of the display surface provided by the embodiment of the present invention. As shown in Figure 4 , the display panel further includes third pins 50 located on one side of the substrate, the plurality of third pins 50 are arranged along the first direction x, and the third pins 50 are located on the side of the first pins 10 away from the second pins 20. The third pins 50 are used for bonding and connection with the output pins of the driving chip, that is, the first pins 10 are input pins, and the third pins 50 are output pins. Figure 4 schematically illustrates the display area AA and the non-display area NA, and the first pins 10, the second pins 20 and the third pins 50 are all located in the non-display area NA.

[0026] Exemplarily, as shown in Figure 4 , a circuit area 70 adjacent to the display area AA is further disposed in the non-display area NA, a plurality of demultiplexing circuits can be arranged in the circuit area 70, and the data lines in the display area AA are electrically connected to the demultiplexing circuits.

[0027] As shown in Figure 4As shown, the non-display area NA is also provided with signal lines 80. Signal lines 80 are wound around both sides of a plurality of first pins 10 and extend to a first edge Y extending along a first direction x of the display panel. A plurality of second pins 20 are located on the side of the plurality of first pins 10 closest to the first edge Y. The first edge Y can be a cut edge of the display panel. Signal lines 80 include at least signal lines for transmitting a constant high level, signal lines for transmitting a constant low level, and signal lines required to drive peripheral driving circuitry. Signal lines 80 include at least a first signal line 81, one end of which is connected to a third pin 50. The first signal line 81 is wound around the outside of the plurality of first pins 10 and extends to the first edge Y along the extension direction of the connecting line 30. For example, both the signal lines for transmitting a constant high level and the signal lines for transmitting a constant low level are first signal lines 81. The first signal line 81 may also include signal lines for transmitting other signals, which will not be exemplified here.

[0028] In this embodiment of the invention, the first lead 40 originally also needed to be wound around the left and right sides of the first pin 10, just like the signal line 80. That is, in related technologies, some signal lines that transmit the same signal as the first lead 40 of this application would be like... Figure 4 Similar to the schematic signal line 80, the wiring is concentrated on both sides of the first lead 40 and then extends to the first edge Y. The design of this embodiment is equivalent to moving some of the signal lines that were originally wound around the left and right sides of the first pin 10 to be routed among multiple connecting lines 30, thus separating the connecting lines 30 on the left and right sides. This arrangement does not increase the space occupied by the wiring. Furthermore, for some traces that need to extend from the pin arrangement area (i.e., the first pin, second pin, and third pin arrangement area) to the circuit area 70, setting this part of the trace as the first lead 40 can also reduce the winding length of the lead, reduce the overall impedance of the lead, and reduce the risk of electrostatic discharge damage to the lead.

[0029] For example, such as Figure 4As shown, the display panel also includes a third pin 50 and a second lead 61 located on one side of the substrate. Multiple third pins 50 are arranged along a first direction x, and the third pins 50 are located on the side of the first pin 10 away from the second pin 20. Each third pin 50 includes multiple third dummy pins 51, and at least one third dummy pin 51 is provided in the dummy pin area 50Z. The third dummy pin 51 is a third pin that does not have signal transmission function. The second lead 61 extends along a second direction y and crosses the dummy pin area 50Z. The first lead 40 includes at least one first sub-lead 40-1, and one end of the second lead 61 is connected to the first sub-lead 40-1. Optionally, the second lead 61 extends along the second direction y to the circuit area 70 and is electrically connected to the circuit within the circuit area 70. Optionally, the second lead 61 includes at least one first signal lead, which transmits the control signals required by the multiplexer; the second lead 61 includes at least one second signal lead, which transmits the switching signals that control the operation of the short-circuit bar; the second lead 61 includes data signal leads, which transmit the data signals of the red, green and blue sub-pixels required for the lighting test, and there are generally three data signal leads.

[0030] In this embodiment of the invention, a second lead 61 is connected to a first sub-lead 40-1 in the first lead 40. The second lead 61 extends along the second direction y and crosses the dummy pin area 50Z. The second lead 61 can be a lead that provides a signal to the circuit in the circuit area 70. In this embodiment of the invention, the first lead 40 is routed in the area between the first sub-pin 11 and the second sub-pin 12, the area between the first connecting line 31 and the second connecting line 32, and the area between the third sub-pin 21 and the fourth sub-pin 22. This reduces the wiring length of the first lead 40, eliminates the need for the first lead 40 to be wound on both sides of the first pin 10, reduces the impedance of the first lead 40, and also reduces the risk of electrostatic discharge damage to the first lead 40.

[0031] For example, such as Figure 4 As shown, the second lead 61 includes at least one first signal lead 611, which transmits control signals required for the operation of the multiplexer. The first signal lead 611 is also connected to the third pin 50 via a connecting trace 63, which is located between multiple first pins 10 and multiple third pins 50.

[0032] For example, such as Figure 4 As shown, the display panel also includes a third lead 62 located on one side of the substrate, between a plurality of first pins 10 and a plurality of third pins 50. The first lead 40 includes at least one second sub-lead 40-2, one end of the third lead 62 is connected to the second sub-lead 40-2, and the other end is coupled to the third pin 50. Figure 4The diagram illustrates that the third lead 62 is connected to the third pin 50 via the functional circuit 64. In this embodiment, the first lead 40 is routed in the regions between the first sub-pin 11 and the second sub-pin 12, between the first connecting line 31 and the second connecting line 32, and between the third sub-pin 21 and the fourth sub-pin 22. This reduces the wiring length of the first lead 40, eliminates the need for the first lead 40 to be wound around the left and right sides of the first pin 10, reduces the impedance of the first lead 40, and also reduces the risk of electrostatic discharge damage to the first lead 40.

[0033] In some implementations, such as Figure 2 As shown, the third segment 43 of the first lead 40 is routed between the third sub-pin 21 and the fourth sub-pin 22. And by... Figure 2 As can be seen from the top view, the second pin 20 is not set in the area where the third line segment 43 is arranged, that is, the second pin 20 is not set between the third sub-pin 21 and the fourth sub-pin 22.

[0034] In other embodiments, a dummy pin is provided between the third sub-pin 21 and the fourth sub-pin 22. For example, Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 5 As shown, the plurality of second pins 20 include second dummy pins 23, and at least one second dummy pin 23 is disposed between the third sub-pin 21 and the fourth sub-pin 22. In this embodiment, the second dummy pin 23 is also disposed in the area where the first lead 40 is arranged between the third sub-pin 21 and the fourth sub-pin 22, which can facilitate the regular arrangement of the second pins 20 in the first direction x, thereby ensuring the uniformity of stress distribution in the bonding process between the display panel and the flexible circuit board, preventing the bonding delamination problem, and improving the bonding yield.

[0035] For example, by Figure 5 As can be seen from the top view, along the plane perpendicular to the substrate, at least one third segment 43 of the first lead 40 overlaps and is at least partially insulated from the second dummy pin 23. In this embodiment of the invention, the second dummy pin 23 is provided between the third sub-pin 21 and the fourth sub-pin 22, which ensures the regularity of the arrangement of the second pins 20 in the first direction x, improving the bonding yield. When arranging the first lead 40 in the area where the second dummy pin 23 is provided, ensuring that the third segment 43 and the second dummy pin 23 overlap with insulated material at the point of intersection avoids adverse effects on the transmission of electrical signals on the first lead 40.

[0036] For example, by Figure 5As can be seen from the top view, along the plane perpendicular to the substrate, at least one third segment 43 of the first lead 40 does not overlap with the second pin 20. In this embodiment of the invention, a second dummy pin 23 is provided between the third sub-pin 21 and the fourth sub-pin 22, which ensures the regularity of the arrangement of the second pins 20 in the first direction x, improving bonding yield. In the area where the second dummy pin 23 is arranged, whether the third segment 43 overlaps with the second dummy lead 23 is related to the width and spacing of the second dummy pins 23 in the first direction x, and the width and spacing of the third segment 43 in the first direction x. In some embodiments, there may be situations where at least one third segment 43 of the first lead 40 does not overlap with the second pin 20, and at least one third segment 43 of the first lead 40 overlaps with the second dummy pin 23 with at least partial insulation.

[0037] For example, Figure 6 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 7 for Figure 6 A schematic diagram of a cross-section at the location of the midtangent AA′. (Combined with...) Figure 6 and Figure 7 The third sub-pin 21 and the fourth sub-pin 22 respectively include a first metal portion 201 and a second metal portion 202 disposed in different layers. Along the plane direction e perpendicular to the substrate 00, the first metal portion 201 and the second metal portion 202 overlap and are electrically connected. The second dummy pin 23 includes a third metal portion 203, which is located on the same layer as one of the first metal portion 201 and the second metal portion 202. Figure 7 The diagram illustrates the second metal portion 202 located on the side of the first metal portion 201 furthest from the substrate 00, and also shows the third metal portion 203 and the second metal portion 202 located on the same layer. This embodiment, by including two metal portions on different layers for the third sub-pin 21 and the fourth sub-pin 22, reduces the impedance of the second pin 20. Furthermore, by positioning the third metal portion 203 of the second dummy pin 23 on the same layer as either the first metal portion 201 or the second metal portion 202, the second dummy pin 23 can reuse the original manufacturing process of the display panel. This ensures the regularity of the pin arrangement within the second pin 20 arrangement area without increasing the manufacturing process, guarantees uniform stress distribution during the bonding process, and thus ensures a high bonding yield.

[0038] For example, such as Figure 7As shown, the third segment 43 of the first lead 40 is located on the same layer as the first metal part 201, that is, the third segment 43 and the second dummy pin 23 are set on different layers, which can ensure that the third segment 43 and the second dummy pin 23 are insulated from each other. Furthermore, in the area where the second dummy pin 23 is set, the second dummy pin 23 is made of a single layer of metal. The third segment 43 arranged in this area can also cooperate with the second dummy pin 23 to make the height difference between this area and the height of the second pins 20, which are made of double layers of metal, such as the third sub-pin 21 and the fourth sub-pin 22, smaller. This can improve the uniformity of stress distribution at the positions of multiple second pins 20 in the bonding process.

[0039] For example, such as Figure 6 and Figure 7 As shown, the display panel includes a first metal layer M1 and a second metal layer M2 located on a substrate 00, with the second metal layer M2 located on the side of the first metal layer M1 away from the substrate 00. Specifically, the first metal portion 201 of the third sub-pin 21 and the fourth sub-pin 22, and the third segment 43 of the first lead 40 are located on the first metal layer M1; the second metal portion 202 of the third sub-pin 21 and the fourth sub-pin 22, and the third metal portion 203 of the second dummy pin 23 are located on the second metal layer M2.

[0040] Optionally, the material of the first metal layer M1 includes molybdenum, and the material of the second metal layer M2 includes aluminum and / or titanium.

[0041] For example, such as Figure 6 As shown, the first lead 40 is located in the first metal layer M1, and the connecting line 30 is located in the second metal layer M2. The first lead 40 and the connecting line 30 are located in different layers. This arrangement can reduce signal interference between the first lead 40 and the connecting line 30.

[0042] For example, such as Figure 6 As shown, the line width of the first lead 40 is smaller than that of the connecting line 30. The connecting line 30 is used to electrically connect the first pin 10 and the second pin 20. The impedance of the connecting line 30 has a significant impact on the connection impedance between the first pin 10 and the second pin 20. In turn, the connection impedance between the pins affects the signal transmission performance between the flexible circuit board and the driver chip. Therefore, the connecting line 30 is designed to have a relatively large line width, which helps to reduce the impedance of the connecting line 30, lower the connection impedance between the pins, and ensure that the signal transmission meets the requirements.

[0043] For example, by Figure 6As can be seen from the top view, along the direction perpendicular to the plane of the substrate, at least one first segment 41 of the first lead 40 and the first dummy pin 13 are at least partially insulated and overlap. In this embodiment of the invention, the first dummy pin 13 is provided between the first sub-pin 11 and the second sub-pin 12, which can ensure the regularity of the arrangement of the first pins 10 in the first direction x and improve the bonding yield. Arranging the first lead 40 in the area where the first dummy pin 13 is provided, and providing insulation overlap between the first segment 41 and the first dummy pin 13 at the overlapping position, can avoid adverse effects on the transmission of electrical signals on the first lead 40.

[0044] For example, by Figure 6 As can be seen from the top view, along the plane perpendicular to the substrate, at least one first line segment 41 of the first lead 40 does not overlap with the first pin 10. In this embodiment of the invention, a first dummy pin 13 is provided between the first sub-pin 11 and the second sub-pin 12, which can ensure the regularity of the arrangement of the first pins 10 in the first direction x, improving bonding yield. In the area where the first dummy pin 13 is arranged, whether the first line segment 41 overlaps with the first dummy pin 13 is related to the width and spacing of the first dummy pin 13 in the first direction x, and the width and spacing of the first line segment 41 in the first direction x. In some embodiments, there may be situations where at least one first line segment 41 of the first lead 40 does not overlap with the first dummy pin 13, and at least one first line segment 41 of the first lead 40 overlaps with the first dummy pin 13 with at least partial insulation.

[0045] For example, such as Figure 4 As shown, the display panel includes a first edge Y extending along a first direction x, and a plurality of second pins 20 located on the side of a plurality of first pins 10 near the first edge Y; wherein the first edge Y exposes the end of a first lead 40. The first lead 40 is used at least for performing a power-on test on the display panel, after which the display panel is cut. The first edge Y is the cut edge of the display panel, so the first lead 40 is exposed at the edge position after the display panel is cut along the cut edge. In this embodiment of the invention, at least a portion of the leads used for lighting tests are moved to the area where the first dummy pin 13 is located for routing between the connecting lines 30. The first lead 40 is set to pass through the area where the first pin 10 is located, the area where the connecting line 30 is located, and the area where the second pin 20 is located in the second direction y. The first lead 40 is used to separate the connecting lines 30 on the left and right sides, thereby allowing the position of the second pin 20 located on at least one side of the first lead 40 to be appropriately adjusted. This reduces the misalignment distance of the corresponding first pin 10 and second pin 20 on at least one side of the first lead 40 in the first direction x, thereby shortening the length of the connecting line 30 located on at least one side of the first lead 40 in the first direction x, thus reducing the impedance of the connecting line 30 and ensuring that the impedance of the connecting line 30 meets the requirements.

[0046] Figure 4 A schematic diagram illustrating COG technology is provided. Embodiments of this invention can also be applied to COP technology. For example, Figure 8 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8 As shown, the display panel includes a display area AA and a non-display area NA. The non-display area NA also includes a bending area Q. In the second direction y, the third pin 50, the first pin 10, and the second pin 20 are all located on the side of the bending area Q away from the display area AA. Figure 8 The diagram illustrates the bending area Q in a flattened state. When the bending area Q is in a bent state, the third pin 50, the first pin 10, and the second pin 20 are placed on the side of the display panel away from the light-emitting surface. Figure 8 Some structures and labels can be referenced. Figure 4 The embodiments are explained in detail here and will not be repeated.

[0047] Based on the same inventive concept, embodiments of the present invention also provide a display module. Figure 9 This is a schematic diagram of a display module provided in an embodiment of the present invention. Figure 9 As shown, the display module includes a driver chip 200, a flexible circuit board 300, and a display panel 100 provided in any embodiment of the present invention. The driver chip 200 is bonded to the first pin 10, and the flexible circuit board 300 is bonded to the second pin 20. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. Using the display panel 100 provided in the embodiments of the present invention can shorten the length of the connection line between the first pin 10 and the second pin 20, reduce the impedance of the connection line, avoid the risk of signal loss due to excessive impedance of the connection line, and prevent poor panel display caused by signal loss.

[0048] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 10 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 10 As shown, the display device includes a display module 1000 provided in any embodiment of the present invention. The display module 1000 includes a display panel provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product.

[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a substrate, and a first pin, a second pin, a connecting line, and a first lead located on one side of the substrate; one end of the connecting line is connected to at least one first pin, and the other end is connected to at least one second pin; The plurality of first pins and the plurality of second pins are arranged along a first direction, the first pins being located on one side of the second pins in a second direction, and the second direction intersecting the first direction; The plurality of first pins include a first sub-pin, a second sub-pin, and a first dummy pin, and at least one first dummy pin is provided between the first sub-pin and the second sub-pin; the plurality of second pins include a third sub-pin and a fourth sub-pin, and the connecting line includes an adjacent first connecting line and a second connecting line; the first connecting line is connected between the first sub-pin and the third sub-pin, and the second connecting line is connected between the second sub-pin and the fourth sub-pin; The first lead includes a first segment, a second segment, and a third segment, with the two ends of the second segment connected to the first segment and the third segment, respectively. The first line segment's orthographic projection on the substrate is located between the orthographic projections of the first sub-pin and the second sub-pin on the substrate; the second line segment's orthographic projection on the substrate is located between the orthographic projections of the first connecting line and the second connecting line on the substrate; and the third line segment's orthographic projection on the substrate is located between the orthographic projections of the third sub-pin and the fourth sub-pin on the substrate.

2. The display panel according to claim 1, characterized in that, The plurality of second pins include a second dummy pin, and at least one second dummy pin is disposed between the third sub-pin and the fourth sub-pin.

3. The display panel according to claim 2, characterized in that, Along a direction perpendicular to the plane of the substrate, at least one third segment of the first lead overlaps with the second dummy pin in at least partially insulated manner.

4. The display panel according to claim 2, characterized in that, Along a direction perpendicular to the plane of the substrate, at least one third segment of the first lead does not overlap with the second pin.

5. The display panel according to claim 2, characterized in that, The third sub-pin and the fourth sub-pin respectively include a first metal part and a second metal part disposed in different layers. Along the plane perpendicular to the substrate, the first metal part and the second metal part overlap and are electrically connected. The second dummy pin includes a third metal portion, which is located on the same layer as one of the first metal portion and the second metal portion.

6. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the plane of the substrate, at least one segment of the first lead overlaps and is at least partially insulated from the first dummy pin.

7. The display panel according to claim 6, characterized in that, Along a direction perpendicular to the plane of the substrate, at least one first segment of the first lead does not overlap with the first pin.

8. The display panel according to claim 1, characterized in that, The first lead and the connecting line are located on different layers.

9. The display panel according to claim 1, characterized in that, The width of the first lead is smaller than the width of the connecting line.

10. The display panel according to claim 1, characterized in that, The display panel further includes a third pin and a second lead located on one side of the substrate, a plurality of the third pins are arranged along the first direction, and the third pins are located on the side of the first pin away from the second pin; the third pins include a plurality of third dummy pins, and at least one third dummy pin is provided in the dummy pin area; The second lead extends along the second direction and crosses the dummy pin area; The first lead includes at least one first sub-lead, and one end of the second lead is connected to the first sub-lead.

11. The display panel according to claim 10, characterized in that, The display panel further includes a third lead located on one side of the substrate, the third lead being located between a plurality of first pins and a plurality of third pins; The first lead includes at least one second sub-lead, and one end of the third lead is connected to the second sub-lead and the other end is coupled to the third pin.

12. The display panel according to claim 1, characterized in that, The display panel includes a first edge extending along the first direction, and a plurality of second pins are located on the side of the plurality of first pins near the first edge; The first edge exposes the end of the first lead.

13. A display module, characterized in that, The device includes a driver chip, a flexible circuit board, and a display panel as described in any one of claims 1 to 12, wherein the driver chip is bonded to the first pin and the flexible circuit board is bonded to the second pin.

14. A display device, characterized in that, Includes the display module as described in claim 13.

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