Display device and method for testing binding impedance of the same, display panel

Abstract

The application provides a display device, a display panel and a binding impedance test method of the display device. The display device comprises a display panel, a flexible circuit board and a display driving chip. The flexible circuit board comprises an FPC gasket group comprising N FPC gaskets, and N is greater than or equal to 5. The display panel comprises a panel FPC gasket group and a panel ILB gasket group. The panel FPC gasket group comprises N panel FPC gaskets, and the N panel FPC gaskets comprise a first short circuit group and a second short circuit group. The first short circuit group comprises two short-circuited panel FPC gaskets, and the second short circuit group comprises two panel FPC gaskets. The N panel FPC gaskets are in one-to-one binding connection with the N FPC gaskets. The panel ILB gasket group comprises M panel ILB gaskets, and M is greater than or equal to 3. The two panel FPC gaskets in the second short circuit group are connected with the same panel ILB gasket. The display driving chip comprises a DDCI gasket group comprising M DDCI gaskets. Adjacent two DDCI gaskets are short-circuited. The M DDCI gaskets are in one-to-one binding connection with the M panel ILB gaskets.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display device and its bonding impedance testing method and display panel. Background Technology

[0002] Micro-OLED, also known as silicon-based OLED (Organic Light-Emitting Diode), is a new type of OLED display device using a silicon substrate. Silicon-based OLEDs are characterized by their small size and high resolution. They are fabricated using mature integrated circuit CMOS (Complementary Metal Oxide Semiconductor) technology, enabling active pixel addressing and incorporating various circuits such as TCON (Timing Controller) and OCP (Over-Current Protection). This results in lightweight design and widespread application in near-eye displays and virtual reality (VR) and augmented reality (AR) fields, particularly in VR / AR head-mounted displays. In VR / AR head-mounted displays, users will be exposed to various environments, making the reliability and lifespan of the silicon-based OLED display device crucial.

[0003] In silicon-based OLED display devices, bonding impedance affects display quality and signal transmission. The bonding impedance result seriously affects module characteristics and reliability. How to test the bonding impedance of silicon-based OLED display devices in order to optimize the bonding impedance is an urgent problem to be solved. Summary of the Invention

[0004] This invention provides a display device and its bonding impedance testing method, as well as a display panel, to solve the problem of how to test the bonding impedance of a display device.

[0005] To solve the above-mentioned technical problems, the present invention is implemented as follows:

[0006] In a first aspect, embodiments of the present invention provide a display device, comprising: a display panel, a flexible circuit board bonded to the display panel, and a display driver chip;

[0007] The flexible circuit board includes: an FPC pad group, wherein the FPC pad group includes N FPC pads, where N is an integer greater than or equal to 5;

[0008] The display panel includes: a panel FPC pad group and a panel ILB pad group. The panel FPC pad group includes N panel FPC pads, among which there are a first shorting group and a second shorting group. The first shorting group includes two shorted panel FPC pads, and the second shorting group includes two panel FPC pads. The N panel FPC pads in the panel FPC pad group are bonded one-to-one with the N FPC pads in the FPC pad group. The panel ILB pad group includes M panel ILB pads, where M is an integer greater than or equal to 3. The two panel FPC pads in the second shorting group are connected to the same panel ILB pad.

[0009] The display driver chip includes: a DDCI pad group, the DDCI pad group includes M DDCI pads, two adjacent DDCI pads in the M DDCI pads are shorted, and the M DDCI pads in the DDCI pad group are bonded to the M panel ILB pads in the panel ILB pad group one by one.

[0010] The FPC pad group, panel FPC pad group, panel ILB pad group and DDCI pad group together form an impedance test pad group, and the display device includes at least one impedance test pad group.

[0011] Optionally, the impedance test pad set further includes:

[0012] A test pad group is disposed on the flexible circuit board or the display panel. The test pad group includes N test pads, and the N test pads in the test pad group are connected one-to-one with the N FPC pads in the FPC pad group or the panel FPC pad group or the panel FPC pad.

[0013] Optionally, the display device further includes:

[0014] A removable cover film is used to cover the test pad.

[0015] Optionally, the DDCI pad is an inner lead-bonded ILB pad or an outer lead-bonded OLB pad.

[0016] Optionally, the impedance test pad set further includes:

[0017] The first connection trace is disposed on the display panel and is used to connect the panel FPC pad and the panel ILB pad;

[0018] The second connection trace is disposed on the display driver chip and is used to connect two adjacent DDCI pads.

[0019] Optionally, the display device includes multiple impedance test pad groups, wherein the first connection traces in the multiple impedance test pad groups have the same impedance.

[0020] Optionally, the display panel includes: a substrate, a pixel driving circuit, a light-emitting device, and a thin film encapsulation layer disposed on the substrate, the pixel driving circuit including a gate metal layer and a source / drain metal layer, and the two panel FPC pads in the first shorting group are shorted through the pattern of the gate metal layer or the pattern of the source / drain metal layer.

[0021] Secondly, embodiments of the present invention provide a display panel, including:

[0022] The panel FPC gasket group and the panel ILB gasket group are provided. The panel FPC gasket group includes N panel FPC gaskets, which include a first shorting group and a second shorting group. The first shorting group includes two shorted panel FPC gaskets, and the second shorting group includes two panel FPC gaskets. The N panel FPC gaskets in the panel FPC gasket group are bonded to each other in the FPC gasket group. The panel ILB gasket group includes M panel ILB gaskets, where M is an integer greater than or equal to 3. The two panel FPC gaskets in the second shorting group are connected to the same panel ILB gasket.

[0023] Optionally, the display panel further includes:

[0024] The first connection trace is used to connect the panel FPC pad and the panel ILB pad;

[0025] The display panel includes multiple pairs of panel FPC pad groups and panel ILB pad groups, and the impedance of the first connection traces in different pairs of panel FPC pad groups and panel ILB pad groups is the same.

[0026] Optionally, the display panel further includes:

[0027] A substrate, a pixel driving circuit, a light-emitting device and a thin film encapsulation layer disposed on the substrate, the pixel driving circuit including a gate metal layer and a source / drain metal layer, the two panel FPC pads in the first shorting group being shorted through the pattern of the gate metal layer or the pattern of the source / drain metal layer.

[0028] Thirdly, embodiments of the present invention provide a method for testing the bonding impedance of a display device, applied to the display device described in the first aspect above, the method comprising:

[0029] The FOC bonding impedance is tested using two shorted FPC pads in the first shorting group of the panel FPC pad group, where the FOC bonding impedance is the bonding impedance between the flexible circuit board and the display panel.

[0030] and / or

[0031] The COC bonding impedance is tested using four panel FPC pads in the panel FPC pad group. The COC bonding impedance is the bonding impedance between the display panel and the display driver chip. The four panel FPC pads include a first panel FPC pad, a second panel FPC pad, a third panel FPC pad, and a fourth panel FPC pad. The second panel FPC pad and the third panel FPC pad belong to the same second shorting group. A voltage is input to the first panel FPC pad and the second panel FPC pad, and the current is tested at the third panel FPC pad and the fourth panel FPC pad. The COC bonding impedance is determined by the tested current value. Alternatively, a current is input to the first panel FPC pad and the second panel FPC pad, and the voltage is tested at the third panel FPC pad and the fourth panel FPC pad. The COC bonding impedance is determined by the tested voltage value.

[0032] and / or

[0033] The overall bonding impedance is determined based on the FOC bonding impedance and the COC bonding impedance.

[0034] Optionally, the FOC bonding impedance is the difference between the FOC test impedance and the FOC trace impedance, which is tested using two shorted panel FPC pads in the first shorting group of the panel FPC pad group.

[0035] and / or

[0036] The COC bonding impedance is the difference between the COC test impedance and the COC trace impedance, which are tested using the four panel FPC pads in the panel FPC pad group.

[0037] In this embodiment of the invention, by using the pad design on the display panel, flexible circuit board and display driver chip, the bonding impedance between the display panel and flexible circuit board, the bonding impedance between the display panel and display driver chip, and the overall bonding impedance of the display panel, flexible circuit board and display driver chip can be tested separately. Based on the test results, each bonding impedance can be optimized, thereby improving the reliability of the display device. Attached Figure Description

[0038] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0039] Figure 1 This is one of the structural schematic diagrams of the display device according to an embodiment of the present invention;

[0040] Figure 2 This is a second schematic diagram of the structure of the display device according to an embodiment of the present invention;

[0041] Figure 3 This is the third schematic diagram of the structure of the display device according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram illustrating the testing of FOC bonding impedance according to an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram illustrating the testing of COC binding impedance according to an embodiment of the present invention;

[0044] Figure 6 This is the fourth schematic diagram of the structure of the display device according to an embodiment of the present invention;

[0045] Figure 7 This is the fifth schematic diagram of the structure of the display device according to an embodiment of the present invention;

[0046] Figure 8 This is a sixth schematic diagram of the structure of the display device according to an embodiment of the present invention;

[0047] Figure 9 This is a schematic diagram of the wiring structure of the display device according to an embodiment of the present invention;

[0048] Figure 10 This is one of the structural schematic diagrams of a silicon-based OLED display device according to an embodiment of the present invention;

[0049] Figure 11 This is a second schematic diagram of the silicon-based OLED display device according to an embodiment of the present invention;

[0050] Figure 12 This is a schematic diagram of the structure of a silicon-based OLED display panel according to an embodiment of the present invention;

[0051] Figure 13 and Figure 14 This is a schematic diagram of the impedance test loop path and impedance splitting results in an embodiment of the present invention. Detailed Implementation

[0052] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0053] Please refer to Figure 1 This invention provides a display device, including: a display panel 10, a flexible printed circuit (FPC) 20 bonded to the display panel 10, and a display driver integrated circuit (DDIC) 30;

[0054] The flexible circuit board 20 includes: an FPC pad group, wherein the FPC pad group includes N FPC pads 21, where N is an integer greater than or equal to 5; Figure 1 In the embodiment shown, the FPC gasket assembly includes five FPC gaskets 21.

[0055] The display panel 10 includes: a panel FPC pad group and a panel ILB (Input Lead Bonding) pad group. The panel FPC pad group includes N panel FPC pads 11, among which there are a first shorting group D1 and a second shorting group D2. The first shorting group D1 includes two shorted panel FPC pads 11, and the second shorting group D2 includes two panel FPC pads 11. The N panel FPC pads 11 in the panel FPC pad group are bonded one-to-one with the N FPC pads 21 in the FPC pad group. The panel ILB pad group includes M panel ILB pads 12, where M is an integer greater than or equal to 3. The two panel FPC pads 11 in the second shorting group D2 are connected to the same panel ILB pad 12. Figure 1 In the illustrated embodiment, the panel FPC gasket assembly includes five panel FPC gaskets 11, and the five panel FPC gaskets 11 include a first shorting group D1, which includes two panel FPC gaskets 11 (i.e., Figure 1 The fourth and fifth panel FPC pads 11), the second shorting group D2 includes two panel FPC pads 11 (i.e. Figure 1 The second and third panel FPC pads 11 are connected to the same panel ILB pad 12.

[0056] The display driver chip 30 includes a DDCI pad group, which includes M DDCI pads 31. Two adjacent DDCI pads 31 are shorted together. The M DDCI pads 31 in the DDCI pad group are bonded to the M panel ILB pads 12 in the panel ILB pad group. Figure 1 In the illustrated embodiment, the DDCI pad assembly includes three DDCI pads 31, wherein the first and second DDCI pads 31 are shorted together, and the second and third DDCI pads 31 are shorted together.

[0057] In this embodiment of the invention, since the two panel FPC pads 11 in the first shorting group D1 of the display panel 10 are shorted, a loop circuit can be formed, which can be used to test the bonding impedance (also known as FOC (FPC on chip or flex on chip) bonding impedance) between the flexible circuit board 20 and the display panel 10. When testing the bonding impedance, voltage or current can be input to one of the panel FPC pads 11 in the first shorting group D1, and current or voltage can be monitored from the other panel FPC pad 11 in the first shorting group D1, thereby obtaining the FOC bonding impedance.

[0058] In this embodiment of the invention, since the two panel FPC pads 11 in the second shorting group D2 of the display panel 10 are connected to the same panel ILB pad 12, and the DDCI pads 31 in the display driver chip 30 are shorted in pairs, a loop circuit can be formed, which can be used for the bonding impedance (also called COC (chip-on-chip) bonding impedance) between the display driver chip 30 and the display panel 10. When testing the bonding impedance, four panel FPC pads 11 can be used to test the COC bonding impedance. Figure 1 For example, voltage can be input to the first and second panel FPC pads 11, and the current can be tested on the third and fourth panel FPC pads 11. The COC bonding impedance can be determined by the tested current value. Alternatively, current can be input to the first and second panel FPC pads 11, and the voltage can be tested on the third and fourth panel FPC pads 11. The COC bonding impedance can be determined by the tested voltage value.

[0059] It should be noted that if the panel FPC gasket group contains only 5 panel FPC gaskets 11, then the panel FPC gasket group can only have one first shorting group D1 and one second shorting group D2. The minimum number of panel FPC gaskets 11 in the panel FPC gasket group is 5 to complete the FOC bonding impedance test and COC bonding impedance test. The number of panel FPC gaskets 11 in the panel FPC gasket group can also be more than 5, for example, 6. If the number of panel FPC gaskets 11 is 6, the panel FPC gasket group can have two first shorting groups D1. Please refer to [reference needed]. Figure 2 The third and fourth panel FPC pads 11 form a first shorting group D1, and the fifth and sixth panel FPC pads 11 form a first shorting group D1. The FOC bonding impedance can be tested using two first shorting groups D1 respectively.

[0060] In this embodiment of the invention, the FPC pad group, the panel FPC pad group, the panel ILB pad group and the DDCI pad group constitute an impedance test pad group, and the display device includes at least one impedance test pad group.

[0061] The display device may include two or more impedance test pad sets. Please refer to [reference needed]. Figure 3 , Figure 3 In the illustrated embodiment, the display device includes two impedance test pad groups, with the dashed box indicating one impedance test pad group. The FOC bonding impedance and COC bonding impedance can be tested using these multiple impedance test pad groups, allowing for cross-verification of multiple test results and improving test accuracy.

[0062] In this embodiment of the invention, by using the pad design on the display panel, flexible circuit board and display driver chip, the bonding impedance between the display panel and flexible circuit board, the bonding impedance between the display panel and display driver chip, and the overall bonding impedance of the display panel, flexible circuit board and display driver chip can be tested separately. Based on the test results, each bonding impedance can be optimized, thereby improving the reliability of the display device.

[0063] In some embodiments, optionally, the impedance test pad group further includes a test pad group disposed on the flexible circuit board 20, the test pad group including N test pads, and the N test pads in the test pad group being connected one-to-one with the N FPC pads 21 in the FPC pad group.

[0064] Alternatively, in some other embodiments, the impedance test pad group further includes: a test pad group disposed on the display panel 10, the test pad group including N test pads, and the N test pads in the test pad group being connected one-to-one with the N panel FPC pads 11 in the panel FPC pad group.

[0065] The test pad is used to input current or voltage, or to detect voltage or current.

[0066] Figure 1 In the embodiment shown, the test pad group is disposed on the flexible circuit board 20. The test pad group includes 5 test pads, namely TP1, TP2, TP3, TP4 and TP5, which are connected to 5 FPC pads 21 in a one-to-one correspondence.

[0067] Please refer to Figure 4 When testing the FOC bonding impedance, one probe can be placed on TP4 and another probe on TP5. TP4, the 4th FPC pad 21, the 5th FPC pad 21, the 4th panel FPC pad 11, the 5th panel FPC pad 11, and TP5 can form a loop. Current or voltage is input into one probe, and the voltage or current is detected by the other probe. The measured value can be used to determine the FOC bonding impedance.

[0068] Please refer to Figure 5 When testing the COC binding impedance, four probes can be attached to TP1, TP2, TP3, and TP4 respectively. Current or voltage is input into the probes of TP1 and TP2, and the voltage or current is detected through the probes of TP3 and TP4. The measured values ​​can be used to determine the COC binding impedance. TP4 can also be replaced by TP5.

[0069] In this embodiment of the invention, optionally, the display device further includes: a removable cover film for covering the test pad to protect the test pad and avoid ESD (Electro-Static discharge) damage. When in use, the removable cover film can be removed to test the bonding impedance.

[0070] In this embodiment of the invention, optionally, the display driver chip 30 may include an inner lead-bonded (ILB) pad and an outer lead-bonded (OLB) pad, wherein the OLB pad is used to output control signals, and the ILB pad is used to input signals (such as power) from the display panel. In this embodiment of the invention, optionally, the DDCI pad 31 may be either an inner lead-bonded (ILB) pad or an outer lead-bonded (OLB) pad. That is, either an OLB pad or an ILB pad can be used for bonding impedance testing.

[0071] As improved in the above embodiments, the display device of the present invention may include multiple impedance test pad groups, each impedance test pad group including: an FPC pad group located on the flexible circuit board 20, a panel FPC pad group and a panel ILB pad group located on the display panel 10, and a DDIC pad group located on the display driver chip 30. The following example illustrates the arrangement of each impedance test pad group when the display device may include multiple impedance test pad groups.

[0072] Please refer to Figure 6 , Figure 6 In the illustrated embodiment, the display device may include two impedance test pad groups, located on the left and right sides respectively. The first shorting group in the panel FPC pad group of the two impedance test pad groups is asymmetrically arranged. That is, the first shorting group in the first and second impedance test pad groups is the fourth and fifth panel FPC pads 11 shorted.

[0073] Please refer to Figure 7 , Figure 7 In the illustrated embodiment, the display device may include two impedance test pad groups, located on the left and right sides respectively. The first shorting group in the panel FPC pad group of the two impedance test pad groups is symmetrically arranged. That is, the first shorting group in the first impedance test pad group is the shorting of the first and second panel FPC pads 11, and the first shorting group in the second impedance test pad group is the shorting of the fourth and fifth panel FPC pads 11.

[0074] Please refer to Figure 8 , Figure 8 In the illustrated embodiment, the display device may include two impedance test pad groups, located on the left and right sides respectively. The first shorting group in the panel FPC pad group of the two impedance test pad groups is symmetrically arranged. That is, the first shorting group in the first impedance test pad group is the shorting of the first and second panel FPC pads 11, and the first shorting group in the second impedance test pad group is the shorting of the fourth and fifth panel FPC pads 11. Figure 8 The illustrated embodiments and Figure 7 The difference between the embodiments shown is that: Figure 7 In the illustrated embodiment, the DDIC pad 31 in the DDIC pad group of the display driver chip 30 is an ILB pad, while... Figure 8 In the embodiment shown, the DDIC pad 31 in the DDIC pad group of the display driver chip 30 is an OLB pad.

[0075] Of course, it should be noted that the display device in this embodiment of the invention may also include more impedance test pad groups, such as three, with two located on the left and right sides and one located in the middle. The testing of multiple impedance test pad groups does not affect each other, and each can be independently tested for bonding impedance.

[0076] Please refer to Figure 9 In this embodiment of the invention, optionally, the impedance test pad assembly further includes:

[0077] The first connecting trace S1 is disposed on the display panel and is used to connect the panel FPC pad 11 and the panel ILB pad 12.

[0078] The second connection trace S2 is disposed on the display driver chip 30 and is used to connect two adjacent DDCI pads 31.

[0079] In an embodiment of the present invention, optionally, the display device includes a plurality of impedance test pad groups, wherein the first connection traces in the plurality of impedance test pad groups have the same impedance.

[0080] Figure 9 In the illustrated embodiment, the display device includes multiple impedance test pad groups. A second connection trace S2 connects adjacent DDCI pads 31 to form a loop. The second connection traces S2 in the left and right impedance test pad groups have an asymmetrical design; however, the impedances of the second connection traces S2 in different impedance test pad groups must be equal. A first connection trace S1 connects the panel FPC pad 11 and the panel ILB pad 12, thereby connecting the display panel and the display driver chip. The first connection traces S1 in the left and right impedance test pad groups can also have an asymmetrical design; however, the impedances of the first connection traces S1 in different impedance test pad groups must be equal.

[0081] The display device in the embodiments of the present invention may be an OLED display device, or more specifically, a silicon-based OLED display device. Of course, other types of display devices are also not excluded.

[0082] Please refer to Figure 10 This invention provides a silicon-based OLED display device, comprising: a display panel 10, a flexible circuit board 20 bonded to the display panel 10, and a display driver chip. Figure 10 (Not shown). The display panel 10 includes a silicon-based backplane 101 and an OLED light-emitting device disposed on the silicon-based backplane 101. Figure 10(Not shown) and a cover glass (CG) 102 for covering the OLED light-emitting device. The silicon-based backplate 101 integrates a pixel driving circuit to drive the OLED light-emitting device, which is used to realize the light-emitting display function. The cover glass 102 is set corresponding to the OLED light-emitting device, and the cover glass 102 functions to allow light to pass through and protect the OLED light-emitting device. In this embodiment of the invention, the cover glass 102 is slightly larger than the OLED light-emitting device and slightly smaller than the silicon-based backplate 101, with a certain distance left on all four sides to realize the positioning and fixation of the silicon-based OLED display device. A flexible circuit board 20 is connected to one side of the silicon-based backplate 101. The flexible circuit board 20 is used to realize electrical connection and external signal transmission.

[0083] The specific structure of the display panel in the embodiments of the present invention will be described below.

[0084] Please refer to Figure 11 and Figure 12The display panel of this embodiment is fabricated using a multi-layer stacked structure. The display panel 10 includes a silicon-based backplane 101, and an anode 103, an organic light-emitting layer 104, a cathode 105, a first thin-film encapsulation layer 106, an RGB color thin-film layer (CF) 107, a second thin-film encapsulation layer 108, and a cover glass 102 disposed on the silicon-based backplane 101. The silicon-based backplane 101 may include a silicon substrate and a pixel driving circuit disposed on the silicon substrate. The anode 103, organic light-emitting layer 104, and cathode 105 belong to OLED light-emitting devices. The anode 103 serves as the first electrode of the organic light-emitting layer 104, and the cathode 105 serves as the second electrode. The organic light-emitting layer 103 is typically made of organic materials. Utilizing the light-emitting characteristics of organic materials, holes and electrons are excited under the influence of voltage or current to form excitons, thereby achieving light emission. Optionally, the anode 103 can be made of ITO (indium tin oxide) material, which has high transmittance and high work function. The cathode 105 can be made of one or more alloy materials selected from Mg / Ag. The RGB color thin film layer (CF) 107 is located between the first thin film encapsulation layer 106 and the second thin film encapsulation layer 108, and is positioned corresponding to the organic light-emitting layer 104 to achieve colorized light emission. The first thin film encapsulation layer 106 and the second thin film encapsulation layer 108 are used together to achieve effective encapsulation of the device, effectively blocking water vapor and oxygen, thereby protecting the device and extending its lifespan. The first thin film encapsulation layer 106 and the second thin film encapsulation layer 108 can be made of one or more organic or inorganic materials with good sealing properties, preferably silicon oxide or silicon nitride, to protect the OLED light-emitting device and achieve a good sealing effect. The first thin film encapsulation layer 106 and the second thin film encapsulation layer 108 can also protect the RGB color thin film layer 107. The cover glass 102 can be made of glass or other materials.

[0085] In this embodiment of the invention, the pixel driving circuit may include film layers such as a gate metal layer, an active layer, and a source / drain metal layer, thereby constituting devices such as thin-film transistors and capacitors.

[0086] In this embodiment of the invention, optionally, the display panel includes: a substrate, a pixel driving circuit, a light-emitting device, and a thin-film encapsulation layer disposed on the substrate. The pixel driving circuit includes a gate metal layer and a source / drain metal layer. The two panel FPC pads in the first shorting group are shorted through the pattern of the gate metal layer or the pattern of the source / drain metal layer. By using the pattern of the gate metal layer or the pattern of the source / drain metal layer for shorting, ITO (anode or cathode) material is usually not used for shorting, thereby reducing impedance.

[0087] This invention also provides a display panel, comprising:

[0088] The panel FPC gasket group and the panel ILB gasket group are provided. The panel FPC gasket group includes N panel FPC gaskets, which include a first shorting group and a second shorting group. The first shorting group includes two shorted panel FPC gaskets, and the second shorting group includes two panel FPC gaskets. The N panel FPC gaskets in the panel FPC gasket group are bonded to each other in the FPC gasket group. The panel ILB gasket group includes M panel ILB gaskets, where M is an integer greater than or equal to 3. The two panel FPC gaskets in the second shorting group are connected to the same panel ILB gasket.

[0089] Optionally, the display panel further includes:

[0090] The first connection trace is used to connect the panel FPC pad and the panel ILB pad;

[0091] The display panel includes multiple pairs of panel FPC pad groups and panel ILB pad groups, and the impedance of the first connection traces in different pairs of panel FPC pad groups and panel ILB pad groups is the same.

[0092] Optionally, the display panel further includes:

[0093] A substrate, a pixel driving circuit, a light-emitting device, and a thin film encapsulation layer disposed on the substrate, the pixel driving circuit including a gate metal layer and a source / drain metal layer, the two panel FPC pads in the first shorting group being shorted through the pattern of the gate metal layer or the pattern of the source / drain metal layer.

[0094] This invention also provides a method for testing the bonding impedance of a display device, applicable to the display device described in any of the above embodiments, the method comprising:

[0095] The FOC bonding impedance is tested using two shorted FPC pads in the first shorting group of the panel FPC pad group, where the FOC bonding impedance is the bonding impedance between the flexible circuit board and the display panel.

[0096] and / or

[0097] The COC bonding impedance is tested using four panel FPC pads in the panel FPC pad group. The COC bonding impedance is the bonding impedance between the display panel and the display driver chip. The four panel FPC pads include a first panel FPC pad, a second panel FPC pad, a third panel FPC pad, and a fourth panel FPC pad. The second panel FPC pad and the third panel FPC pad belong to the same second shorting group. A voltage is input to the first panel FPC pad and the second panel FPC pad, and the current is tested at the third panel FPC pad and the fourth panel FPC pad. The COC bonding impedance is determined by the tested current value. Alternatively, a current is input to the first panel FPC pad and the second panel FPC pad, and the voltage is tested at the third panel FPC pad and the fourth panel FPC pad. The COC bonding impedance is determined by the tested voltage value.

[0098] and / or

[0099] The overall bonding impedance is determined based on the FOC bonding impedance and the COC bonding impedance.

[0100] In some embodiments, optionally, the FOC bonding impedance is the difference between the FOC test impedance and the FOC trace impedance tested using two shorted panel FPC pads in the first shorting group of the panel FPC pad group.

[0101] and / or

[0102] The COC bonding impedance is the difference between the COC test impedance and the COC trace impedance, which are tested using the four panel FPC pads in the panel FPC pad group.

[0103] The following simulation experiment illustrates the testing process of the binding impedance in this embodiment of the invention.

[0104] Please refer to Figure 13 and Figure 14 , Figure 13 and Figure 14 This is a schematic diagram of the impedance test loop path and impedance decomposition results according to an embodiment of the present invention. In this embodiment, the overall impedance test result of the display device includes COC bonding impedance + FOC bonding impedance + routing impedance (PFC routing impedance + panel routing impedance). Please refer to [the relevant documentation]. Figure 14 The FOC pad allows for individual analysis of FOC bonding impedance. For example, if the PFC routing impedance is approximately 0.5Ω, the FOC test impedance is approximately 2Ω, and the FOC bonding impedance is 1.5Ω. The total FOC test impedance for the entire loop is 4Ω. Additionally, please refer to... Figure 13For example, the COC test impedance is approximately 2.5Ω, of which the panel routing impedance is approximately 0.55Ω, and the COC bonding impedance is 1.95Ω, making the total COC test impedance in the entire loop 5Ω. The overall FOC test impedance + COC test impedance result is the sum of the panel routing impedance + FOC test impedance + COC test impedance, with an estimated total impedance of approximately 9Ω. This allows for the separation of impedance test results for each segment, enabling design optimization of the routing, layout improvement and verification, and simultaneous optimization of the bonding process, such as COC bonding conditions and parameters, FOC bonding conditions, batch monitoring and analysis, and interception of defects such as black screens and wire defects. Figure 13 and Figure 14 In this context, panel COC pad refers to the panel ILB pad in the above embodiments, and panel pad refers to the panel PFC pad in the above embodiments.

[0105] The embodiments of the present invention have been described above with reference to the accompanying drawings. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of the present invention without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of the present invention.

Claims

1. A display device, characterized in that, include: Display panel, flexible circuit board bonded to the display panel, and display driver chip; The flexible circuit board includes: an FPC pad group, wherein the FPC pad group includes N FPC pads, where N is an integer greater than or equal to 5; The display panel includes: a panel FPC pad group and a panel ILB pad group. The panel FPC pad group includes N panel FPC pads, among which there are a first shorting group and a second shorting group. The first shorting group includes two shorted panel FPC pads, and the second shorting group includes two panel FPC pads. The N panel FPC pads in the panel FPC pad group are bonded one-to-one with the N FPC pads in the FPC pad group. The panel ILB pad group includes M panel ILB pads, where M is an integer greater than or equal to 3. The two panel FPC pads in the second shorting group are connected to the same panel ILB pad. The display driver chip includes: a DDCI pad group, the DDCI pad group includes M DDCI pads, two adjacent DDCI pads in the M DDCI pads are shorted, and the M DDCI pads in the DDCI pad group are bonded to the M panel ILB pads in the panel ILB pad group one by one. The FPC pad group, panel FPC pad group, panel ILB pad group and DDCI pad group together form an impedance test pad group, and the display device includes at least one impedance test pad group.

2. The display device according to claim 1, characterized in that, The impedance test pad assembly also includes: A test pad group is disposed on the flexible circuit board or the display panel. The test pad group includes N test pads, and the N test pads in the test pad group are connected one-to-one with the N FPC pads in the FPC pad group or the panel FPC pad group or the panel FPC pad.

3. The display device according to claim 2, characterized in that, Also includes: A removable cover film is used to cover the test pad.

4. The display device according to claim 1, characterized in that, The DDCI pad is either an inner lead-bonded ILB pad or an outer lead-bonded OLB pad.

5. The display device according to claim 1, characterized in that, The impedance test pad assembly also includes: The first connection trace is disposed on the display panel and is used to connect the panel FPC pad and the panel ILB pad; The second connection trace is disposed on the display driver chip and is used to connect two adjacent DDCI pads.

6. The display device according to claim 5, characterized in that, The display device includes multiple impedance test pad groups, and the first connection traces in the multiple impedance test pad groups have the same impedance.

7. The display device according to claim 1, characterized in that, The display panel includes: a substrate, a pixel driving circuit, a light-emitting device, and a thin film encapsulation layer disposed on the substrate. The pixel driving circuit includes a gate metal layer and a source / drain metal layer. The two panel FPC pads in the first shorting group are shorted through the pattern of the gate metal layer or the pattern of the source / drain metal layer.

8. A display panel, characterized in that, include: The panel FPC gasket group and the panel ILB gasket group are provided. The panel FPC gasket group includes N panel FPC gaskets, which include a first shorting group and a second shorting group. The first shorting group includes two shorted panel FPC gaskets, and the second shorting group includes two panel FPC gaskets. The N panel FPC gaskets in the panel FPC gasket group are bonded to each other in the FPC gasket group. The panel ILB gasket group includes M panel ILB gaskets, where M is an integer greater than or equal to 3. The two panel FPC gaskets in the second shorting group are connected to the same panel ILB gasket.

9. The display panel according to claim 8, characterized in that, Also includes: The first connection trace is used to connect the panel FPC pad and the panel ILB pad; The display panel includes multiple pairs of panel FPC pad groups and panel ILB pad groups, and the impedance of the first connection traces in different pairs of panel FPC pad groups and panel ILB pad groups is the same.

10. The display panel according to claim 8, characterized in that, Also includes: A substrate, a pixel driving circuit, a light-emitting device, and a thin film encapsulation layer disposed on the substrate, the pixel driving circuit including a gate metal layer and a source / drain metal layer, the two panel FPC pads in the first shorting group being shorted through the pattern of the gate metal layer or the pattern of the source / drain metal layer.

11. A method for testing the binding impedance of a display device, characterized in that, Applied to the display device as described in any one of claims 1-7, the method comprises: The FOC bonding impedance is tested using two shorted FPC pads in the first shorting group of the panel FPC pad group, where the FOC bonding impedance is the bonding impedance between the flexible circuit board and the display panel. and / or The COC bonding impedance is tested using four panel FPC pads in the panel FPC pad group. The COC bonding impedance is the bonding impedance between the display panel and the display driver chip. The four panel FPC pads include a first panel FPC pad, a second panel FPC pad, a third panel FPC pad, and a fourth panel FPC pad. The second panel FPC pad and the third panel FPC pad belong to the same second shorting group. A voltage is input to the first panel FPC pad and the second panel FPC pad, and the current is tested at the third panel FPC pad and the fourth panel FPC pad. The COC bonding impedance is determined by the tested current value. Alternatively, a current is input to the first panel FPC pad and the second panel FPC pad, and the voltage is tested at the third panel FPC pad and the fourth panel FPC pad. The COC bonding impedance is determined by the tested voltage value. and / or The overall bonding impedance is determined based on the FOC bonding impedance and the COC bonding impedance.

12. The method according to claim 11, characterized in that, The FOC bonding impedance is the difference between the FOC test impedance and the FOC trace impedance, which is measured using two shorted panel FPC pads in the first shorting group of the panel FPC pad group. and / or The COC bonding impedance is the difference between the COC test impedance and the COC trace impedance, which are tested using the four panel FPC pads in the panel FPC pad group.

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