Detection control circuit, display panel and display driving method

Abstract

The application belongs to the technical field of display driving, and particularly relates to a detection control circuit, a display panel and a display driving method. The detection control circuit comprises a first threshold generation module, a second threshold generation module, a window comparison module and a logic output module. The window comparison module is configured to charge a charging node when a real-time common voltage is greater than a first threshold voltage or smaller than a second threshold voltage. The logic output module is configured to output a trigger signal to a timing controller when a cumulative voltage on the charging node exceeds a preset reference threshold. Therefore, the real-time detection of the common electrode voltage, the discrimination of the coupling direction and the output of the trigger signal are integrated to form an accurate detection control mode through the cooperation between the first threshold generation module, the second threshold generation module, the window comparison module and the logic output module, so that the crosstalk caused by the polarity asymmetry of a small range and a scattered area can be effectively detected.

Description

Technical Field

[0001] This disclosure belongs to the field of display driver technology, specifically relating to a detection and control circuit, a display panel, and a display driving method. Background Technology

[0002] In a liquid crystal display panel, the constant jumps in the data line voltage are coupled to the common electrode through parasitic capacitance, causing fluctuations in the common voltage. When the number of positive and negative polarities in the display screen is significantly different, the common electrode coupling becomes severe, causing color distortion or horizontal crosstalk.

[0003] Currently, related technologies detect images through algorithms within the timing controller. For large areas of data with asymmetrical positive and negative polarities, crosstalk is avoided by changing the polarity driving method. For example, the horizontal polarity can be switched from "+-+-+-……" to "+--++--+……", so that the number of positive and negative polarities in a row is the same, and the coupling effect cancels each other out. However, this algorithm detection method is only effective for regular patterns of a specific area. For cases with very small areas or even only some rows of data with asymmetrical positive and negative polarities, the image detection capability of the timing controller's internal algorithm cannot cover them, and crosstalk problems still exist.

[0004] Therefore, how to detect and improve crosstalk caused by the asymmetry of positive and negative polarity of data in a small area has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a detection control circuit, a display panel, and a display driving method. By cooperating with a first threshold generation module, a second threshold generation module, a window comparison module, and a logic output module, this application integrates the real-time detection of the common electrode voltage, the determination of the coupling direction, and the output of the trigger signal to form an accurate detection control method, which can effectively detect crosstalk caused by polarity asymmetry in small, scattered areas.

[0006] In a first aspect, this application provides a detection and control circuit applied to a display panel, the display panel including a timing controller and a source driver chip, the detection and control circuit including: a first threshold generation module connected to the timing controller, configured to: generate a first threshold voltage according to a first pulse width modulation signal output by the timing controller; a second threshold generation module connected to the timing controller, configured to: generate a second threshold voltage according to a second pulse width modulation signal output by the timing controller; a window comparison module connected to the first threshold generation module, the second threshold generation module, the common electrode of the display panel and a charging node respectively, configured to: compare the real-time common voltage on the common electrode with the first threshold voltage and the second threshold voltage respectively, and charge the charging node when the real-time common voltage is greater than the first threshold voltage or less than the second threshold voltage; a logic output module connected to the charging node and the timing controller respectively, configured to: output a trigger signal to the timing controller when the accumulated voltage on the charging node exceeds a preset reference threshold, so that the timing controller controls the source driver chip to switch polarity reversal mode.

[0007] Secondly, this application provides a display panel, the display panel comprising: an array substrate including multiple data lines, multiple scan lines, multiple pixel units arranged in an array, and a common electrode; a source driver chip connected to the multiple data lines for outputting pixel voltages to the data lines of the array substrate; a timing controller connected to the source driver chip for providing polarity control signals to the source driver chip; and a detection control circuit connected to the timing controller, the source driver chip, and the common electrode respectively for detecting the real-time common voltage on the common electrode and outputting a trigger signal to the timing controller when the real-time common voltage exceeds a preset range, so that the timing controller controls the source driver chip to switch to a polarity reversal mode.

[0008] Thirdly, this application provides a display driving method applied to a display panel. The display driving method includes: a first threshold generation module generating a first threshold voltage based on a first pulse width modulation signal output by a timing controller; a second threshold generation module generating a second threshold voltage based on a second pulse width modulation signal output by the timing controller; a window comparison module acquiring the real-time common voltage on the common electrode of the display panel in real time, and comparing the real-time common voltage with the first threshold voltage and the second threshold voltage respectively; when the real-time common voltage is greater than the first threshold voltage or less than the second threshold voltage, the window comparison module charging the charging node; when the accumulated voltage on the charging node exceeds a preset reference threshold, a logic output module outputting a trigger signal to the timing controller; and the timing controller responding to the trigger signal controlling the source driver chip to switch to a polarity reversal mode.

[0009] The technical solution provided in this application has at least the following beneficial effects:

[0010] (1) This application generates a first threshold voltage based on the first pulse width modulation signal output by the timing controller through the first threshold generation module and generates a second threshold voltage based on the second pulse width modulation signal output by the timing controller, thereby realizing independently adjustable and flexibly configurable upper and lower limit detection thresholds, which can be adapted to the electrical characteristics of different display panels.

[0011] (2) This application compares the real-time common voltage on the common electrode with the first threshold voltage and the second threshold voltage through the window comparison module. When the real-time common voltage is greater than the first threshold voltage or less than the second threshold voltage, the charging node is charged, realizing bidirectional real-time detection of the common electrode voltage. Regardless of whether the coupling direction is positive or negative, it can be accurately captured, overcoming the defect in the related technology that unidirectional detection cannot fully cover the coupling direction.

[0012] (3) This application outputs a trigger signal to the timing controller only when the accumulated voltage at the charging node exceeds the preset reference threshold through the logic output module, thereby filtering out instantaneous noise. Only continuous abnormal coupling can trigger subsequent actions, thus avoiding polarity switching jitter caused by frequent false triggers and ensuring the stability and reliability of the system.

[0013] Therefore, this application integrates the real-time detection of the common electrode voltage, the determination of the coupling direction, and the output of the trigger signal through the cooperation between the first threshold generation module, the second threshold generation module, the window comparison module, and the logic output module to form an accurate detection and control method, which can effectively detect crosstalk caused by polarity asymmetry in small and scattered areas. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0015] Figure 1 The diagram shown is a polarity reversal schematic provided in an embodiment of this application.

[0016] Figure 2 The image shown is a schematic diagram of a V-strip screen display in a column reversal mode according to an embodiment of this application.

[0017] Figure 3 The diagram shown is a comparison of the polarity of a row of pixels before and after polarity switching in an alternating bright and dark scene, according to an embodiment of this application.

[0018] Figure 4 The diagram shown is a schematic diagram of a detection control circuit provided in an embodiment of this application.

[0019] Figure 5 The diagram shown is a circuit diagram of a detection control circuit provided in an embodiment of this application.

[0020] Figure 6 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application.

[0021] Figure 7 The diagram shown is a flowchart of a display driving method provided in an embodiment of this application.

[0022] Explanation of reference numerals in the attached figures: 100. Detection and control circuit; 110. First threshold generation module; 120. Second threshold generation module; 130. Window comparison module; 140. Logic output module; 150. Reset module; 200. Timing controller; 300. Source driver chip; 400. Array substrate; Q1, first transistor; Q2, second transistor; Q3, third transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; R5, fifth resistor; R6, sixth resistor; R7, seventh resistor; R8, eighth resistor; R9, ninth resistor; R10, tenth resistor; OP1, first comparator; OP2, second comparator; OP3, third comparator; D1, first diode; D2, second diode; C1, first capacitor; C2, second capacitor; C3, third capacitor; A, charging node; B, intermediate node; CFCOM, common electrode. Detailed Implementation

[0023] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0024] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0025] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0026] TFT LCD (Thin Film Transistor Liquid Crystal Display) uses the electric field created by the voltage difference between the pixel electrode and the common electrode to deflect liquid crystal molecules at different angles, achieving different transmittance and thus displaying different gray levels. However, because the voltage of the source line is constantly refreshed to update the image, and to prevent liquid crystal polarization, a method of continuously switching between positive and negative polarities is typically used to drive the liquid crystal deflection. The reference potential for the positive and negative polarities is the common electrode VCOM (Common Voltage).

[0027] The constant fluctuations in data line voltage can couple voltage to the common electrode through parasitic capacitance coupling, causing fluctuations in the common electrode voltage. Under certain regular image patterns, when the difference in the number of positive and negative polarities is significant, the common electrode becomes severely coupled, leading to abnormal display phenomena such as color distortion or crosstalk. Vertical polarity reversal is typically column reversal, while horizontal polarity reversal is dot reversal; their polarity distribution is illustrated in the diagram below. Figure 1 As shown.

[0028] The principle of capacitive coupling is further explained below: In a TFT LCD panel, parasitic capacitance exists between the data lines and the common electrode (including parasitic capacitance between the data lines and pixel electrodes, and storage capacitance between the pixel electrodes and the common electrode). When the voltage on the data lines changes abruptly, the charging and discharging effect of the parasitic capacitance induces a corresponding voltage change on the common electrode. The change in common electrode voltage ΔVCOM can be expressed as: ΔVCOM = C_coupling / C_total × ΔV_data_line; where C_coupling is the coupling capacitance between the data lines and the common electrode, C_total is the total capacitance of the common electrode to ground, and ΔV_data_line is the change in data line voltage. Since the data line voltage undergoes polarity switching and grayscale voltage updates in each scan cycle, when multiple data lines simultaneously experience voltage changes in the same direction, the charge coupled to the common electrode accumulates, causing a significant shift in the common electrode voltage. The common electrode serves as the common reference voltage for all pixels in the screen. If its potential deviates from the design value, it will directly cause the effective voltage difference between the pixel electrode and the common electrode to change. This will cause the actual deflection angle of the liquid crystal molecules to deviate from the target value, ultimately resulting in the brightness of the pixel in that row not matching the target grayscale, i.e., generating horizontal crosstalk (H-Crosstalk).

[0029] If the currently displayed image is a vertical stripe image with alternating columns of bright and dark pixels, this image is usually called a V-strip image. Figure 2 This is a schematic diagram of the V-strip display in column reversal mode, showing the grayscale voltage distribution for each row. Figure 2 As shown, the number of bright positive grayscale levels (grayscale levels corresponding to positive polarity voltage) fed into each row is twice the number of bright negative grayscale levels (grayscale levels corresponding to negative polarity voltage). Due to the capacitive coupling effect, the voltage of CFCOM (i.e., VCOM, common voltage) will shift towards the positive polarity after being coupled, resulting in an increase in the voltage difference across the liquid crystal capacitor of each bright pixel, which will cause color shift in the entire image (most typical of green sub-pixels).

[0030] When a V-strip image is not displayed across the entire surface, but only in a portion of it, crosstalk occurs in the corresponding horizontal areas. For V-strip images of a specific area, relevant technologies use algorithms within the TCON IC (Timing Controller Integrated Circuit) to detect the image and avoid crosstalk by changing the polarity driving mode. Specifically, the polarity driving mode is typically switched from horizontal "+-+-+-…" to "+--++--+…". This polarity switching balances the image polarity that previously caused CFCOM coupling, thus eliminating coupling. Figure 3The diagram shows a comparison of the polarity of a row of pixels before and after switching in a scene with alternating brightness and darkness. Before the switch, the horizontal polarity is "+-+-+-……". Within a row, the number of bright positive polarities is significantly greater than the number of bright negative polarities, and CFCOM couples towards the positive polarity. After the switch, the polarity sequence is "+--++--+……". At this time, the number of bright positive and negative polarities within a row is the same, and the coupling effect cancels each other out, thus avoiding the occurrence of horizontal crosstalk.

[0031] However, for situations with very small areas or even just asymmetrical positive and negative polarities in some rows of data, the TCON algorithm's screen detection capability cannot cover them, and crosstalk still occurs. This situation typically occurs when displaying certain English letters or when Excel table borders are set to dashed lines. To mitigate crosstalk caused by text or dashed table borders, the inventors of this application attempted to add a VCOM compensation circuit to the circuit. The basic idea is to detect voltage fluctuations in the CFCOM circuit and use an inverting operational amplifier to output a compensation voltage with the opposite polarity to the CFCOM coupling voltage to cancel the CFCOM coupling within the panel. However, this method has the following problems: (1) The resistance of the CFCOM trace in the panel is relatively large. When the compensation voltage is transmitted along the CFCOM trace, there is a voltage drop. Only the panel area close to the PCBA (Printed Circuit Board Assembly) compensation circuit has a compensation effect, while the panel area far from the compensation circuit has a poor compensation effect. (2) When the refresh rate is high, the response speed of the operational amplifier is difficult to keep up with the speed of coupling change between rows during the line-by-line scanning process, resulting in poor dynamic compensation effect; (3) Using VCOM compensation circuit will cause the power consumption of the operational amplifier to increase significantly and the device temperature to rise under the severe CFCOM coupling, which will affect the system reliability.

[0032] To address the aforementioned problems, this application provides a detection and control circuit, specifically including the following embodiments: Figure 4 The diagram shown is a schematic representation of a detection and control circuit according to an embodiment of this application. Figure 4 As shown, the detection and control circuit 100 of this embodiment is applied to a display panel, which typically includes a timing controller 200 and a source driver chip 300. It should be noted that the timing controller 200 in this embodiment has a multi-channel pulse width modulation signal output function and an external trigger signal detection function; the source driver chip 300 in this embodiment has a polarity inversion control pin SQINV, and the polarity inversion mode of the output to the data line can be controlled by the level state of this pin.

[0033] like Figure 4As shown, the detection control circuit 100 in this embodiment includes a first threshold generation module 110, connected to the timing controller 200, and configured to generate a first threshold voltage based on the first pulse width modulation signal output by the timing controller 200. Specifically, the first pulse width modulation signal output by the timing controller 200 is a square wave signal with a high level of 3.3V. This signal cannot be directly used as the reference threshold of the comparator because the actual required reference threshold is usually higher than 3.3V. The first threshold generation module 110 converts the pulse width modulation signal into the required DC reference voltage by converting the duty cycle of the pulse width modulation signal. In this embodiment, the first threshold voltage V1 is used as an upper limit threshold to detect whether the voltage of the common electrode CFCOM is over-coupled in the positive polarity direction; when the voltage of the common electrode CFCOM is higher than V1, it indicates that the positive polarity coupling degree has exceeded the acceptable range.

[0034] like Figure 4 As shown, the detection and control circuit 100 in this embodiment further includes a second threshold generation module 120, which is connected to the timing controller 200 and configured to generate a second threshold voltage based on the second pulse width modulation signal output by the timing controller 200. It should be noted that the working principle of the second threshold generation module 120 is basically the same as that of the first threshold generation module 110, the difference being the input pulse width modulation signal and the output reference voltage value. The second threshold voltage V2 serves as a lower threshold, and its value is typically lower than the normal operating voltage range of the common electrode CFCOM, used to detect whether the voltage of the common electrode CFCOM is excessively coupled towards the negative polarity. When the voltage of the common electrode CFCOM is lower than V2, it indicates that the degree of negative polarity coupling has exceeded the acceptable range.

[0035] In this embodiment, the first threshold voltage V1 and the second threshold voltage V2 together constitute a detection window. That is, the voltage range between the second threshold voltage V2 and the first threshold voltage V1 is the normal operating voltage range of the common electrode CFCOM. By setting two thresholds, this application achieves full coverage detection of coupling in both positive and negative directions. Regardless of whether the common electrode CFCOM shifts positively or negatively due to any polarity imbalance, it can be captured by the window comparison module 130.

[0036] In this embodiment, the detection control circuit 100 further includes a window comparison module 130, which is connected to the first threshold generation module 110, the second threshold generation module 120, the common electrode CFCOM of the display panel, and the charging node A, respectively. It is configured to compare the real-time common voltage on the common electrode CFCOM with the first threshold voltage V1 and the second threshold voltage V2, respectively. When the real-time common voltage is greater than the first threshold voltage V1 or less than the second threshold voltage V2, the charging node A is charged.

[0037] The main function of the window comparison module 130 is to determine whether the input voltage falls within a preset voltage window. In this embodiment, the lower limit of the window is the second threshold voltage V2, and the upper limit is the first threshold voltage V1. The normal operating voltage of the common electrode CFCOM should be between the second threshold voltage V2 and the first threshold voltage V1. Specifically: (1) When the real-time common voltage on the common electrode CFCOM is greater than the first threshold voltage V1, it indicates that the voltage of the common electrode CFCOM is too positively offset, that is, the common electrode CFCOM is severely affected by positive polarity coupling. At this time, the window comparison module 130 generates a valid charging signal and starts charging the charging node A.

[0038] (2) When the real-time common voltage on the common electrode CFCOM is less than the second threshold voltage V2, it indicates that the negative offset of the common electrode CFCOM voltage is too low, that is, the common electrode CFCOM is severely affected by negative polarity coupling. At this time, the window comparison module 130 also generates a valid charging signal and starts charging the charging node A.

[0039] (3) When the voltage of the common electrode CFCOM is between the second threshold voltage V2 and the first threshold voltage V1, it indicates that the voltage of the common electrode CFCOM is within the normal range, and the window comparison module 130 does not generate a valid charging signal.

[0040] like Figure 4 As shown, the detection and control circuit 100 in this embodiment also includes a logic output module 140, which is connected to the charging node A and the timing controller 200 respectively, and is configured to output a trigger signal to the timing controller 200 when the accumulated voltage on the charging node A exceeds a preset reference threshold, so that the timing controller 200 controls the source driver chip 300 to switch the polarity reversal mode.

[0041] The voltage coupling on the common electrode CFCOM may experience transient spike interference. If each transient coupling triggers a polarity switch, it will cause the timing controller 200 to switch frequently and the source driver chip 300 to repeatedly adjust the output polarity, which will not only affect the display stability but may also shorten the chip's lifespan. This problem can be effectively solved by the charge accumulation mechanism of the logic output module 140 in this embodiment. The specific working process is as follows: (1) The output of the window comparison module 130 is connected to the charging node A via a charging path. The charging node A is connected to a grounding capacitor. When the window comparison module 130 determines that the voltage of the common electrode CFCOM is outside the normal range, its output terminal outputs a valid charging signal. This signal charges the capacitor on the charging node A via the charging path, and the voltage on the charging node A gradually increases over time. This charging process has an integral characteristic—only a coupling anomaly of sufficient duration can charge the voltage of the charging node A to the preset reference threshold, while a brief spike interference, due to insufficient duration, cannot charge the voltage of the charging node A to the trigger threshold.

[0042] (2) When the accumulated voltage of charging node A exceeds the preset reference threshold, the logic output module 140 outputs a trigger signal to the timing controller 200. This trigger signal is a standard logic level signal and can be directly recognized by the general-purpose input / output interface of the timing controller 200. After receiving the trigger signal, the timing controller 200 immediately controls the SQINV pin of the source driver chip 300 through its internal logic to switch the polarity reversal mode of the source driver chip 300, thereby eliminating the voltage coupling condition on the common electrode CFCOM.

[0043] In summary, the detection control circuit 100 of this application has the following technical effects: (1) This application generates a first threshold voltage V1 by the first threshold generation module 110 based on the first pulse width modulation signal output by the timing controller 200, and generates a second threshold voltage V2 by the second threshold generation module 120 based on the second pulse width modulation signal output by the timing controller 200. This realizes independently adjustable and flexibly configurable upper and lower limit detection thresholds, which can be specifically adapted according to the differences in electrical characteristics of different display panels, thus overcoming the shortcomings of the narrow applicability of fixed threshold circuits.

[0044] (2) This application compares the real-time common voltage on the common electrode CFCOM with the first threshold voltage V1 and the second threshold voltage V2 through the window comparison module 130. When the real-time common voltage is greater than the first threshold voltage V1 or less than the second threshold voltage V2, the charging node A is charged, realizing bidirectional real-time detection of the voltage of the common electrode CFCOM. Regardless of whether the coupling direction is positive or negative, it can be accurately captured, overcoming the defect of unidirectional detection in related technologies that cannot fully cover the coupling direction. At the same time, a hardware comparator is used for real-time comparison, and the response speed reaches the nanosecond level, which is far superior to the traditional timing controller algorithm based on frame period detection method.

[0045] (3) This application outputs a trigger signal to the timing controller 200 only when the accumulated voltage on the charging node A exceeds the preset reference threshold by the logic output module 140. This achieves the filtering of instantaneous noise. Only continuous abnormal coupling can trigger subsequent actions, thereby avoiding polarity switching jitter caused by frequent false triggers and ensuring the stability and reliability of the system.

[0046] (4) This application uses the collaborative working mechanism between the window comparison module 130 and the logic output module 140 to split the abnormal detection and judgment of the common electrode CFCOM voltage into two independent links: real-time comparison and cumulative judgment. This ensures that abnormal coupling is not missed while suppressing noise interference to the greatest extent.

[0047] Therefore, this application integrates the real-time detection of the common electrode CFCOM voltage, the determination of the coupling direction, and the output of the trigger signal through the cooperation between the first threshold generation module 110, the second threshold generation module 120, the window comparison module 130, and the logic output module 140, forming an accurate detection and control method that can effectively detect crosstalk caused by polarity asymmetry in small and scattered areas.

[0048] In one embodiment, such as Figure 4 As shown, the detection control circuit 100 also includes a reset module 150, which is connected to the timing controller 200 and the charging node A respectively, and is configured to discharge the charging node A in response to the reset signal output by the timing controller 200 so that the accumulated voltage on the charging node A is restored to the initial state.

[0049] When the window comparison module 130 detects that the voltage of the common electrode CFCOM exceeds the normal range, it charges the charging node A, causing the voltage on the charging node A to gradually accumulate. When the accumulated voltage exceeds a preset reference threshold, the logic output module 140 outputs a trigger signal to complete a trigger action. However, after the trigger action is completed, the charging node A still retains the accumulated charge, and the voltage of the charging node A is at a high level. If the charge on the charging node A cannot be cleared, the circuit will not be able to respond to subsequent common electrode CFCOM coupling, and the subsequent charging signal output by the window comparison module 130 will not be able to raise the voltage of the charging node A further to the trigger threshold.

[0050] In this embodiment, the reset module 150 establishes a controllable discharge path between charging node A and timing controller 200. When a reset is required, timing controller 200 outputs a reset signal, the discharge path is activated, and the charge on charging node A is released. After the reset is completed, the discharge path is disconnected, charging node A returns to a rechargeable state, and detection control circuit 100 then begins a new round of detection.

[0051] In practical applications, the timing controller 200 can output a reset signal at preset fixed frame intervals after outputting a trigger signal and completing polarity switching. For example, it can be set to output a reset pulse every 60 frames, causing the detection control circuit 100 to periodically reset and restart detection. This periodic reset mechanism ensures that the detection control circuit 100 maintains effective monitoring capability throughout the entire operation of the display panel.

[0052] Figure 5 The diagram shown is a schematic representation of a detection control circuit according to an embodiment of this application. Figure 5 As shown, the first threshold generation module 110 in this embodiment includes a first transistor Q1, a first resistor R1, a second resistor R2, and a first capacitor C1. Specifically, the control terminal of the first transistor Q1 is connected to the first pulse width modulation terminal of the timing controller 200, and the first terminal of the first transistor Q1 is grounded; the first terminal of the first resistor R1 is connected to the second terminal of the first transistor Q1, and the second terminal of the first resistor R1 is connected to the power supply terminal VCC; the first terminal of the second resistor R2 is connected to the second terminal of the first transistor Q1, and the second terminal of the second resistor R2 serves as the output terminal of the first threshold generation module 110; the first terminal of the first capacitor C1 is connected to the second terminal of the second resistor R2, and the second terminal of the first capacitor C1 is grounded.

[0053] The basic working principle of the first threshold generation module 110 in this embodiment is as follows: The first pulse width modulation (PWM) signal output by the timing controller 200 is a square wave signal with a high level of 3.3V and a low level of 0V. When the first PWM signal is high, the first transistor Q1 is turned on, and the voltage at its second terminal is close to 0V. When the first PWM signal is low, the first transistor Q1 is turned off, and the voltage at its second terminal is pulled up to near the power supply voltage VCC through the first resistor R1. Therefore, a pulse signal with the opposite logic to the first PWM signal is generated at the second terminal of the first transistor Q1—this node is low when the first PWM signal is high, and high when the first PWM signal is low. The amplitude of this pulse signal is the power supply voltage VCC, and its duty cycle is complementary to that of the first PWM signal. For example, when the duty cycle of the first PWM signal is 30%, the high-level duty cycle at the second terminal of the first transistor Q1 is 70%.

[0054] The pulse signal at the second terminal of the first transistor Q1 is filtered by a first-order low-pass filter composed of the second resistor R2 and the first capacitor C1. The AC component of the pulse signal is filtered out, while the DC component is retained. After filtering, a stable DC voltage, namely the first threshold voltage V1, is obtained across the first capacitor C1. The value of this DC voltage is the average value of the pulse signal at the second terminal of the first transistor Q1, which is equal to the power supply voltage VCC multiplied by the high-level duty cycle at this node, i.e., V1 = VCC × (1 - PWM1 duty cycle). Taking a power supply voltage VCC = 15V as an example, when the duty cycle of the first pulse width modulation signal is 30%, the theoretical output value of the first threshold voltage V1 is 15 × (1 - 30%) = 10.5V; when the duty cycle is 50%, the first threshold voltage V1 is 7.5V.

[0055] Therefore, in this embodiment, by adjusting the internal register of the timing controller 200 to change the duty cycle of the first pulse width modulation signal, the voltage value of the first threshold voltage V1 can be linearly adjusted without changing any external hardware, so that the same circuit can be adapted to display panels of different specifications.

[0056] like Figure 5 As shown, the second threshold generation module 120 in this embodiment includes a second transistor Q2, a third resistor R3, a fourth resistor R4, and a second capacitor C2. Specifically, the control terminal of the second transistor Q2 is connected to the second pulse width modulation terminal of the timing controller 200, and the first terminal of the second transistor Q2 is grounded; the first terminal of the third resistor R3 is connected to the second terminal of the second transistor Q2, and the second terminal of the third resistor R3 is connected to the power supply terminal VCC; the first terminal of the fourth resistor R4 is connected to the second terminal of the second transistor Q2, and the second terminal of the fourth resistor R4 serves as the output terminal of the second threshold generation module 120; the first terminal of the second capacitor C2 is connected to the second terminal of the fourth resistor R4, and the second terminal of the second capacitor C2 is grounded.

[0057] The working principle of the second threshold generation module 120 in this embodiment is basically the same as that of the first threshold generation module 110. The second pulse width modulation signal output by the timing controller 200 is a square wave signal with a high level representing a logic voltage and a low level representing 0V. When the signal is high, the second transistor Q2 is turned on, and its second terminal is pulled low to near ground potential; when the signal is low, the second transistor Q2 is turned off, and its second terminal is pulled up to near the power supply voltage VCC through the third resistor R3. As a result, a pulse signal with the opposite logic to the second pulse width modulation signal is generated at the second terminal of the second transistor Q2. The amplitude of this pulse signal is the power supply voltage VCC, and its duty cycle is complementary to that of the second pulse width modulation signal.

[0058] After the pulse signal is filtered by a first-order low-pass filter consisting of the fourth resistor R4 and the second capacitor C2, the AC component is removed, while the DC component is retained, resulting in a stable DC voltage across the second capacitor C2, which is the second threshold voltage V2. This DC voltage is equal to the power supply voltage VCC multiplied by the high-level duty cycle of the pulse signal at the second terminal of the second transistor Q2, i.e., V2 = VCC × (1 - PWM2 duty cycle). Taking a power supply voltage VCC = 15V as an example, when the duty cycle of the second pulse width modulation signal is 30%, the theoretical output value of the second threshold voltage V2 is 10.5V; when the duty cycle is 50%, the second threshold voltage V2 is 7.5V.

[0059] In this embodiment, the second threshold voltage V2 and the first threshold voltage V1 together constitute a complete detection window. The first threshold voltage V1 is typically set to an upper limit higher than the normal operating voltage of the common electrode CFCOM, and the second threshold voltage V2 is typically set to a lower limit lower than the normal operating voltage of the common electrode CFCOM. These are used to detect the coupling offset of the common electrode CFCOM in the positive and negative polarity directions, respectively. Through the independent configuration of the two threshold generation modules, the upper and lower thresholds can be adjusted independently without interference, providing a flexible and adjustable reference voltage source for the window comparison module 130.

[0060] like Figure 5 As shown, the window comparison module 130 of this embodiment includes a first comparator OP1, a second comparator OP2, a first diode D1, a second diode D2, a fifth resistor R5, and a third capacitor C3. The inverting input terminal of the first comparator OP1 is connected to the output terminal of the first threshold generation module 110, and the non-inverting input terminal of the first comparator OP1 is connected to the common electrode CFCOM. The inverting input terminal of the second comparator OP2 is connected to the common electrode CFCOM, and the non-inverting input terminal of the second comparator OP2 is connected to the output terminal of the second threshold generation module 120. The anode of the first diode D1 is connected to the output terminal of the first comparator OP1, and the cathode of the first diode D1 is connected to the intermediate node B. The anode of the second diode D2 is connected to the output terminal of the second comparator OP2, and the cathode of the second diode D2 is connected to the intermediate node B. The first terminal of the fifth resistor R5 is connected to the intermediate node B, and the second terminal of the fifth resistor R5 is connected to the charging node A. The first terminal of the third capacitor C3 is connected to the charging node A, and the second terminal of the third capacitor C3 is grounded.

[0061] The working principle of the window comparison module 130 in this embodiment is as follows: (1) When the voltage of the common electrode CFCOM is within the normal range, that is, the voltage of the common electrode CFCOM is lower than the first threshold voltage V1 and higher than the second threshold voltage V2. For the first comparator OP1, the voltage at its non-inverting input terminal is lower than the voltage at its inverting input terminal, and the output terminal is at a low level. For the second comparator OP2, the voltage at its inverting input terminal is higher than the voltage at its non-inverting input terminal, and the output terminal is also at a low level. At this time, both the first diode D1 and the second diode D2 are in the off state, the intermediate node B is at a low level, there is no charging current at the charging node A, and the voltage across the third capacitor C3 remains unchanged.

[0062] (2) When the voltage of the common electrode CFCOM is higher than the first threshold voltage V1, that is, the voltage of the common electrode CFCOM is too far forward. For the first comparator OP1, the voltage at its non-inverting input terminal is higher than the voltage at its inverting input terminal, and the output terminal flips to a high level. This high level is transmitted to the intermediate node B through the first diode D1. For the second comparator OP2, its output terminal is still at a low level, and the second diode D2 is in the off state. The high level at the intermediate node B charges the third capacitor C3 through the fifth resistor R5, and the voltage at the charging node A gradually increases.

[0063] (3) When the voltage of the common electrode CFCOM is lower than the second threshold voltage V2, that is, the negative offset of the voltage of the common electrode CFCOM is too large. For the second comparator OP2, the voltage of its inverting input terminal is lower than the voltage of its non-inverting input terminal, and the output terminal flips to a high level. This high level is transmitted to the intermediate node B through the second diode D2. For the first comparator OP1, its output terminal is at a low level, and the first diode D1 is in the off state. The high level of the intermediate node B charges the third capacitor C3 through the fifth resistor R5, and the voltage of the charging node A gradually increases.

[0064] In this embodiment, the first diode D1 and the second diode D2 act as a logical "OR" in the circuit—regardless of whether the first comparator OP1 or the second comparator OP2 outputs a high level, the high level can be transmitted to the intermediate node B through the corresponding diode. Furthermore, the outputs of the two comparators are isolated from each other by diodes, preventing one comparator from pulling down the high level output of the other when one outputs a low level. The fifth resistor R5 and the third capacitor C3 form a charging time constant network, determining the rise rate of the voltage at charging node A. The resistance value of the fifth resistor R5 and the capacitance value of the third capacitor C3 together determine the charging speed—the larger the resistance or capacitance value, the slower the charging; conversely, the smaller the resistance or capacitance value, the faster the charging.

[0065] like Figure 5As shown, the logic output module 140 of this embodiment includes a third comparator OP3, a sixth resistor R6, and a seventh resistor R7. The inverting input of the third comparator OP3 is connected to a preset reference threshold, and the non-inverting input of the third comparator OP3 is connected to charging node A. The first terminal of the sixth resistor R6 is connected to the output of the third comparator OP3, and the second terminal of the sixth resistor R6 is connected to the trigger terminal of the timing controller 200. The first terminal of the seventh resistor R7 is connected to the first terminal of the sixth resistor R6, and the second terminal of the seventh resistor R7 is grounded.

[0066] The working principle of the logic output module 140 in this embodiment is as follows: The voltage at charging node A gradually increases over time. When the voltage at charging node A is lower than a preset reference threshold, the voltage at the non-inverting input of the third comparator OP3 is lower than the voltage at the inverting input, and the output is low. At this time, the resistor network composed of the sixth resistor R6 and the seventh resistor R7 outputs this low level to the trigger terminal of the timing controller 200, and the trigger terminal remains in a low-level state, so the timing controller 200 does not operate. When the voltage at charging node A gradually increases due to continuous charging until it exceeds the preset reference threshold, the voltage at the non-inverting input of the third comparator OP3 is higher than the voltage at the inverting input, and the output flips to a high level. This high level generates a high-level signal that meets the logic level requirements at the trigger terminal of the timing controller 200 through the voltage divider network of the sixth resistor R6 and the seventh resistor R7. When the timing controller 200 detects this high level, it responds and performs a polarity switching action.

[0067] Resistors R6 and R7 form a voltage divider network, whose main function is to adapt the voltage amplitude. Since the theoretical high-level output of the third comparator OP3 is the power supply voltage VCC, and the general-purpose input / output interface of the timing controller 200 can typically only withstand a logic level of 3.3V, directly connecting the VCC high level to the timing controller 200 could damage its interface. By using resistors R6 and R7 to divide the voltage, the high-level output of the third comparator OP3 can be reduced to a voltage range that the timing controller 200 can safely accept, while also meeting the logic level discrimination threshold requirements.

[0068] Furthermore, such as Figure 5 As shown, the logic output module 140 also includes an eighth resistor R8 and a ninth resistor R9. The first terminal of the eighth resistor R8 serves as a preset reference threshold terminal, and the second terminal of the eighth resistor R8 is connected to the power supply terminal VCC. The first terminal of the ninth resistor R9 is connected to the first terminal of the eighth resistor R8, and the second terminal of the ninth resistor R9 is grounded.

[0069] The eighth resistor R8 and the ninth resistor R9 form a voltage divider network. The power supply voltage VCC is divided by the eighth resistor R8 and the ninth resistor R9 in series, generating a DC voltage at the preset reference threshold that is proportional to the power supply voltage VCC. This voltage value is determined by the resistance ratio of the eighth resistor R8 to the ninth resistor R9, i.e., preset reference threshold = VCC × R9 / (R8 + R9). Taking a power supply voltage VCC = 15V and the resistance values ​​of the eighth resistor R8 and the ninth resistor R9 being equal as an example, the preset reference threshold is 7.5V.

[0070] Furthermore, such as Figure 5 As shown, the reset module 150 in this embodiment includes a third transistor Q3 and a tenth resistor R10. The control terminal of the third transistor Q3 is connected to the reset terminal of the timing controller 200, the first terminal of the third transistor Q3 is grounded, and the second terminal of the third transistor Q3 is connected to the charging node A. The first terminal of the tenth resistor R10 is connected to the control terminal of the third transistor Q3, and the second terminal of the tenth resistor R10 is grounded.

[0071] The working principle of the reset module 150 is as follows: Under normal detection conditions, the reset terminal of the timing controller 200 outputs a low level, the gate of the third transistor Q3 is at a low level, the third transistor Q3 is in the off state, and a high impedance is presented between its second terminal and its first terminal. The charging node A is isolated from ground, and the third capacitor C3 on the charging node A can normally accumulate charge. The tenth resistor R10 is connected between the control terminal of the third transistor Q3 and ground. Its function is to reliably pull the control terminal of the third transistor Q3 low to ground potential when the reset terminal of the timing controller 200 is in a high impedance state or the output signal is unstable, ensuring that the third transistor Q3 remains off and avoiding false turn-on caused by the control terminal being floating.

[0072] When the timing controller 200 determines that the detection state needs to be reset, its reset terminal outputs a high-level reset signal. This high level is applied to the control terminal of the third transistor Q3, turning on the third transistor Q3 and creating a low-impedance path between its second and first terminals. At this time, charging node A is directly grounded through the conduction path of the third transistor Q3, and the charge stored in the third capacitor C3 is quickly discharged to ground through this path. The voltage of charging node A rapidly drops to near zero potential, thus returning to the initial state.

[0073] After the reset is complete, the timing controller 200 pulls the reset signal back to a low level, the third transistor Q3 returns to the off state, and charging node A is isolated from ground again. The detection control circuit 100 then begins a new round of detection. The timing controller 200 should pull the reset signal low promptly after completing the reset; otherwise, the third transistor Q3 will remain on, charging node A will be grounded for an extended period, and the circuit will be unable to detect the common electrode CFCOM coupling again.

[0074] Figure 6 The diagram shown is a structural schematic of a display panel provided in an embodiment of this application. Figure 6 As shown, the display panel includes an array substrate 400, a source driver chip 300, a timing controller 200, and the detection and control circuit 100 described in the foregoing embodiment.

[0075] Specifically, the array substrate 400 includes multiple data lines, multiple scan lines, multiple pixel units arranged in an array, and a common electrode CFCOM. The source driver chip 300 is connected to the multiple data lines and outputs pixel voltages to the data lines of the array substrate 400. The timing controller 200 is connected to the source driver chip 300 and provides polarity control signals to the source driver chip 300. The detection control circuit 100 is connected to the timing controller 200, the source driver chip 300, and the common electrode CFCOM, respectively, and detects the real-time common voltage on the common electrode CFCOM. When the real-time common voltage exceeds a preset range, it outputs a trigger signal to the timing controller 200, causing the timing controller 200 to control the source driver chip 300 to switch to a polarity reversal mode.

[0076] The display panel in this embodiment, through the integrated detection and control circuit 100, can monitor the voltage status of the common electrode CFCOM in real time and automatically trigger polarity switching when abnormal coupling is detected. This effectively improves the crosstalk problem caused by the asymmetry of positive and negative polarities of data in small and scattered areas, and enhances the image quality performance and system reliability of the display panel in various complex display scenarios.

[0077] In one embodiment, this application provides a display driving method, specifically including the following embodiments: Figure 7 The diagram shown is a flowchart of a display driving method provided in an embodiment of this application; as follows: Figure 7 As shown, the display driver method specifically includes the following steps: Step S100: The first threshold generation module generates a first threshold voltage based on the first pulse width modulation signal output by the timing controller, and the second threshold generation module generates a second threshold voltage based on the second pulse width modulation signal output by the timing controller.

[0078] Step S200: The window comparison module acquires the real-time common voltage on the common electrode of the display panel in real time, and compares the real-time common voltage with the first threshold voltage and the second threshold voltage respectively.

[0079] Step S300: When the real-time common voltage is greater than the first threshold voltage or less than the second threshold voltage, the window comparison module charges the charging node.

[0080] Step S400: When the accumulated voltage on the charging node exceeds the preset reference threshold, the logic output module outputs a trigger signal to the timing controller.

[0081] In step S500, the timing controller responds to the trigger signal and controls the source driver chip to switch the polarity reversal mode.

[0082] It should be noted that the working process of the display driving method in this embodiment is the same as the working principle of the detection and control circuit described above, and will not be repeated here.

[0083] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0084] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0085] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A detection and control circuit, characterized in that, Applied to a display panel, the display panel includes a timing controller and a source driver chip, and the detection and control circuit includes: The first threshold generation module, connected to the timing controller, is configured to generate a first threshold voltage based on the first pulse width modulation signal output by the timing controller. The second threshold generation module, connected to the timing controller, is configured to generate a second threshold voltage based on the second pulse width modulation signal output by the timing controller. The window comparison module, which is connected to the first threshold generation module, the second threshold generation module, the common electrode of the display panel, and the charging node, is configured to: compare the real-time common voltage on the common electrode with the first threshold voltage and the second threshold voltage, respectively; and charge the charging node when the real-time common voltage is greater than the first threshold voltage or less than the second threshold voltage. The logic output module, which is connected to the charging node and the timing controller respectively, is configured to: when the accumulated voltage on the charging node exceeds a preset reference threshold, output a trigger signal to the timing controller so that the timing controller controls the source driver chip to switch the polarity reversal mode.

2. The detection and control circuit according to claim 1, characterized in that, The detection and control circuit also includes: The reset module, connected to both the timing controller and the charging node, is configured to discharge the charging node in response to a reset signal output by the timing controller, so that the accumulated voltage on the charging node is restored to its initial state.

3. The detection and control circuit according to claim 1, characterized in that, The first threshold generation module includes: A first transistor, wherein the control terminal of the first transistor is connected to the first pulse width modulation terminal of the timing controller, and the first terminal of the first transistor is grounded; A first resistor, the first end of which is connected to the second end of the first transistor, and the second end of which is connected to the power supply. The second resistor has its first end connected to the second end of the first transistor, and the second end of the second resistor serves as the output terminal of the first threshold generation module. A first capacitor, the first terminal of which is connected to the second terminal of the second resistor, and the second terminal of the first capacitor is grounded.

4. The detection and control circuit according to claim 1, characterized in that, The second threshold generation module includes: The second transistor has its control terminal connected to the second pulse width modulation terminal of the timing controller, and its first terminal is grounded. The third resistor has a first end connected to the second end of the second transistor, and the second end of the third resistor is connected to the power supply terminal. The fourth resistor has its first end connected to the second end of the second transistor, and the second end of the fourth resistor serves as the output terminal of the second threshold generation module. The second capacitor has its first terminal connected to the second terminal of the fourth resistor, and its second terminal is grounded.

5. The detection and control circuit according to claim 1, characterized in that, The window comparison module includes: A first comparator, wherein the inverting input of the first comparator is connected to the output of the first threshold generation module, and the non-inverting input of the first comparator is connected to the common electrode; The second comparator has its inverting input connected to the common electrode and its non-inverting input connected to the output of the second threshold generation module. The first diode has its anode connected to the output terminal of the first comparator and its cathode connected to the intermediate node. The second diode has its anode connected to the output terminal of the second comparator and its cathode connected to the intermediate node. The fifth resistor has its first end connected to the intermediate node and its second end connected to the charging node. The third capacitor has its first terminal connected to the charging node and its second terminal grounded.

6. The detection and control circuit according to claim 1, characterized in that, The logic output module includes: The third comparator has its inverting input connected to a preset reference threshold and its non-inverting input connected to the charging node. The sixth resistor has its first end connected to the output of the third comparator and its second end connected to the trigger terminal of the timing controller. The seventh resistor has its first end connected to the first end of the sixth resistor, and its second end grounded.

7. The detection and control circuit according to claim 6, characterized in that, The logic output module also includes: The eighth resistor has its first end serving as the preset reference threshold terminal, and its second end connected to the power supply terminal. The ninth resistor has its first end connected to the first end of the eighth resistor, and its second end grounded.

8. The detection and control circuit according to any one of claims 2-7, characterized in that, The reset module includes: The third transistor has its control terminal connected to the reset terminal of the timing controller, its first terminal grounded, and its second terminal connected to the charging node. The tenth resistor has its first end connected to the control terminal of the third transistor, and its second end grounded.

9. A display panel, characterized in that, The display panel includes: The array substrate includes multiple data lines, multiple scan lines, multiple pixel units arranged in an array, and a common electrode; A source driver chip, connected to the multiple data lines, is used to output pixel voltage to the data lines of the array substrate; A timing controller, connected to the source driver chip, is used to provide a polarity control signal to the source driver chip; The detection and control circuit according to any one of claims 1-8 is connected to the timing controller, the source driver chip and the common electrode respectively, for detecting the real-time common voltage on the common electrode, and outputting a trigger signal to the timing controller when the real-time common voltage exceeds a preset range, so that the timing controller controls the source driver chip to switch the polarity reversal mode.

10. A display driving method, characterized in that, The display driving method, applied to the display panel of claim 9, comprises: The first threshold generation module generates a first threshold voltage based on the first pulse width modulation signal output by the timing controller, and the second threshold generation module generates a second threshold voltage based on the second pulse width modulation signal output by the timing controller. The window comparison module acquires the real-time common voltage on the common electrode of the display panel in real time, and compares the real-time common voltage with the first threshold voltage and the second threshold voltage respectively; When the real-time common voltage is greater than the first threshold voltage or less than the second threshold voltage, the window comparison module charges the charging node; When the accumulated voltage on the charging node exceeds a preset reference threshold, the logic output module outputs a trigger signal to the timing controller; The timing controller responds to the trigger signal and controls the source driver chip to switch to polarity reversal mode.

Images