Data transmitting and receiving apparatus and display apparatus including the same

Abstract

Disclosed are a data transmitting and receiving apparatus and a display apparatus including the same. The data transmitting and receiving apparatus includes a transmitting apparatus, a plurality of receiving apparatuses, a first communication line configured to connect the receiving apparatuses to the transmitting apparatus on a one-to-one basis, and a second communication line configured to connect the transmitting apparatus and the receiving apparatuses between a first terminal and a second terminal of the transmitting apparatus. The second communication line includes a forward wire connected between the first terminal of the transmitting apparatus and a first receiving apparatus, a feedback wire connected between an nth receiving apparatus and the second terminal of the transmitting apparatus, and an intermediate wire connected between the first receiving apparatus and the nth receiving apparatus. The transmitting apparatus is configured to transmit a first ID code to the first receiving apparatus via the forward wire and receive an ID assignment acknowledgement signal via the feedback wire connected to the nth receiving apparatus.

Description

Technical Field

[0001] The implementation relates to a technique for assigning an ID to identify each integrated circuit (IC). Background Technology

[0002] The display panel comprises multiple pixels arranged in a matrix. Each pixel can have a color such as red (R), green (G), and blue (B) and displays an image on the display panel while emitting light in grayscale levels according to the image data.

[0003] Image data is transferred from a data processing device, such as a timing controller, to a data driving device, such as a source driver IC. The image data is sent as a digital value, and the data driving device converts the image data into analog voltages to drive the individual pixels. Summary of the Invention

[0004] To enable bidirectional communication between a data processing device and multiple data driving devices, a method is needed to identify each data driving device. An embodiment provides a data transmission and reception device capable of automatically assigning an ID for identifying the source driver IC to each integrated circuit (IC) on a per-IC basis, and a display device including such a device.

[0005] The problems addressed by this disclosure are not limited to those described above, and those skilled in the art will clearly understand from the following description other problems not described.

[0006] A data transmission and reception apparatus according to one embodiment includes: a transmission device; a plurality of receiving devices; a first communication line configured to connect the receiving devices to the transmission device on a one-to-one basis; and a second communication line configured to connect the transmission device and the receiving devices between a first terminal and a second terminal of the transmission device. The second communication line includes: a forward conductor connected between the first terminal of the transmission device and a first receiving device; a feedback conductor connected between an nth receiving device and the second terminal of the transmission device (where n is a natural number equal to or greater than 3); and one or more intermediate conductors configured to connect adjacent receiving devices between the first receiving device and the nth receiving device. The transmission device is configured to transmit a first ID code to the first receiving device via the forward conductor and to receive an ID allocation confirmation signal via the feedback conductor connected to the nth receiving device.

[0007] The transmitting device can output clock training signals, control data, and image data after receiving the ID allocation confirmation signal.

[0008] The signal transmission speed of the second communication line can be lower than that of the first communication line.

[0009] The first receiving device can generate a second ID code in response to the first ID code, and send the second ID code to the nth receiving device via the intermediate wire. The nth receiving device can send the ID allocation confirmation signal to the sending device via the feedback wire in response to the second ID code.

[0010] The first receiving device can generate a second ID code by adding or subtracting a preset increment to the first ID code. The nth receiving device is configured to generate an ID allocation confirmation signal by adding or subtracting an increment to the second ID code.

[0011] The transmitting device can send a start code to the first receiving device via the forward conductor before the first ID code, and receive the start code from the nth receiving device via the feedback conductor.

[0012] The first receiving device can transmit the start code received via the forward conductor to the nth receiving device via the intermediate conductor, and then change the voltage of the intermediate conductor to a first voltage. The nth receiving device can transmit the start code received via the intermediate conductor to the transmitting device via the feedback conductor, and then change the voltage of the feedback conductor to the first voltage.

[0013] The transmitting device may send a preset preamble to the first receiving device via the forward conductor before the start code.

[0014] The transmitting device can send a stop code to the first receiving device via the positive wire after receiving the ID allocation confirmation signal, and receive the stop code from the nth receiving device via the feedback wire.

[0015] The first receiving device can transmit the stop code received via the forward wire to the nth receiving device via the intermediate wire. The nth receiving device is configured to transmit the stop code received via the intermediate wire to the transmitting device via the feedback wire.

[0016] The first receiving device can output the stop code to the intermediate conductor, and then change the voltage of the intermediate conductor to a second voltage. The nth receiving device can output the stop code to the feedback conductor, and then change the voltage of the feedback conductor to the second voltage.

[0017] The transmitting device can send clock training signals, control data, and image data to the receiving device via a first communication line through unidirectional communication. The transmitting device and the receiving device can perform bidirectional communication via a second communication line.

[0018] A display device according to one embodiment includes: a display panel having data lines connected to pixels therein; a plurality of driver ICs electrically connected to the data lines and configured to provide data voltages corresponding to image data to the data lines; and a timing controller connected to the driver ICs via a first communication line and a second communication line, configured to assign an ID to the driver ICs via the second communication line and then send the image data to the driver ICs via the first communication line. The first communication line is configured to connect the timing controller and the driver ICs on a one-to-one basis. The second communication line is configured to cascade the timing controller and the driver ICs. The timing controller is configured to send a first ID code to one of the driver ICs.

[0019] The driver IC may include: a first driver IC configured to generate an (n-1)th ID code (where n is a natural number equal to or greater than 3) by adding a preset increment or decrement to the first ID code received from the timing controller via the second communication line; an (n-1)th driver IC configured to generate an nth ID code by adding the increment or decrement to the (n-1)th ID code received via the second communication line; and an nth driver IC configured to generate an ID allocation confirmation signal by adding the increment or decrement to the nth ID code received via the second communication line, and to send the ID allocation confirmation signal to the timing controller.

[0020] According to one or more implementations, a unique ID can be assigned to each data drive device (RX system) via a communication channel transmission path that is cascaded between a data processing device (TX system) and multiple data drive devices (RX systems).

[0021] According to one or more implementations, the TX system can use the unique ID assigned to each IC chip in the RX system to set up test, debug, or transport channel environment construction for each IC in the RX system.

[0022] According to one or more implementations, the TX system may be allowed to use the ID of each IC chip assigned to the RX system to request the status information of each IC in the RX system, determine whether the IC is functioning properly based on the status information received from the IC, and define and perform subsequent operations.

[0023] The effects of this disclosure are not limited to those described above, and other effects not described will be understood by those skilled in the art based on the following description and the appended claims. Attached Figure Description

[0024] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is a configuration diagram of a display device according to an embodiment of the present disclosure; Figure 2 This is a configuration diagram of a data processing apparatus and a data driving apparatus according to embodiments of the present disclosure; Figure 3 This is a diagram illustrating a first main communication portion and a second main communication portion according to an embodiment of the present disclosure; Figure 4 This is a diagram showing the signal transmission line between the data processing apparatus and the data driving apparatus according to an embodiment of the present disclosure; Figure 5 This is a flowchart illustrating the control process of the ID allocation steps according to embodiments of this disclosure; and Figure 6 This is a waveform diagram showing the IDs sequentially assigned to the source driver IC in the ID allocation step according to an embodiment of the present disclosure. Detailed Implementation

[0025] The advantages and features of this disclosure, as well as methods of implementing them, will be apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings. However, this disclosure is not limited to the following embodiments, which may be implemented in various different forms; rather, these embodiments are provided to complete the disclosure and to allow those skilled in the art to fully understand the scope of this disclosure, which is limited only to the scope of the appended claims.

[0026] The shapes, dimensions, scales, angles, quantities, etc., shown in the drawings for the purpose of describing embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted so as not to unnecessarily obscure the subject matter of this disclosure.

[0027] The following implementations can be combined or associated with each other, in whole or in part, and various types of interlocks and drives are technically possible. These implementations can be implemented independently of each other or together in an interrelated relationship.

[0028] Various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0029] Figure 1 This is a configuration diagram of a display device according to an embodiment.

[0030] Reference Figure 1 The display device 100 may include a data processing device 110, a data driving device 120, a display panel 130, a gating driving device 140, etc. The data processing device 110 can be interpreted as a transmitting system (TX system) or device. The data driving device 120 can be interpreted as a receiving system (RX system) or device.

[0031] The data processing device 110 can receive image data from another device. The other device is the device that generates the image data, and may be a host system connected to the video source.

[0032] The data processing device 110 can process image data received from another device to suit the data driving device 120, and can send the processed image data to the data driving device 120. The data processing device 110 can perform gamma correction processing on the grayscale values ​​of each pixel included in the image data, or can perform compensation processing to suit the characteristics of each pixel. The data processing device 110 can be a timing controller.

[0033] The data driving device 120 can receive image data from the data processing device 110, generate a data voltage VD based on the grayscale values ​​of the pixels included in the image data, and provide the data voltage VD to the pixel P. The data driving device 120 may include multiple source driver ICs that are electrically connected to data lines DL of the display panel 130.

[0034] Multiple pixels P can be set in the display panel 130. Each pixel P can be connected to the data drive device 120 via the data line DL, and can be connected to the gating drive device 140 via the gating line GL.

[0035] The display panel 130 may be a panel of a flat panel display such as a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an organic light-emitting display (OLED), or a non-organic light-emitting display.

[0036] A transistor can be disposed in each pixel P. The gate terminal of the transistor can be connected to the gate line GL, and the source terminal of the transistor can be connected to the data line DL. When the gate driving device 140 provides the scan signal SCN to the gate line GL, the transistor is turned on, and the data line DL is connected to pixel P. After the data line DL is connected to pixel P, the data voltage VD provided from the data driving device 120 is transmitted to pixel P.

[0037] The data processing device 110 sends timing control signals to the gating drive device 140 and the data drive device 120 to synchronize the gating drive device 140 and the data drive device 120, and controls the operation timing of each of the gating drive device 140 and the data drive device 120.

[0038] The data processing device 110 can send a gating timing control signal to the gating drive device 140. The gating drive device 140 can generate a scan signal SCN according to the gating timing control signal, and can provide the scan signal SCN to the pixel P through the gating line GL.

[0039] At least two types of communication lines LN1 and LN2 can be provided between the data processing device 110 and the data driving device 120. The data processing device 110 can send a first signal via the first communication line LN1 and can send or receive a second signal via the second communication line LN2.

[0040] The first communication line LN1 can form a one-way high-speed communication channel, and the second communication line LN2 can form a two-way low-speed communication line. The first communication line LN1 can be interpreted as the main communication line or main channel. The second communication line LN2 can be interpreted as an auxiliary communication line, auxiliary channel, etc. The first signal can be interpreted as the main communication signal, while the second signal can be interpreted as an auxiliary communication signal.

[0041] In display mode, the data processing device 110 can send control data and image data to the data driving device 120 via the first communication line LN1. The control data may include timing control information and option information for the data driving device 120 and the gating driving device 140. In the ID allocation data before entering display mode, the data driving device 120 receives and stores the ID code received via the second communication line LN2. Multiple source driver ICs constituting the data driving device 120 are sequentially assigned IDs according to the ID code received via the second communication line LN2, and the last source driver IC can store its own ID code and then send a signal indicating the end of ID allocation to the data processing device 110 via the second communication line LN2.

[0042] Figure 2This is a configuration diagram of a data processing apparatus and a data driving apparatus according to embodiments of the present disclosure. Figure 3 This is a diagram illustrating the first main communication portion and the second main communication portion according to an embodiment of the present disclosure.

[0043] Reference Figure 2 and Figure 3 The data processing device 110 may include a transmission controller 111, a first main communication section 112, a first auxiliary communication section 113, etc. The data driving device 120 may include a receiving controller 121, a second main communication section 122, a second auxiliary communication section 123, etc.

[0044] The first main communication section 112 and the second main communication section 122 can be connected via the first communication line LN1. In display mode, the first main communication section 112 can send control data, image data, etc. to the second main communication section 122 via the first communication line LN1.

[0045] The first main communication unit 112 can send a clock training signal for clock and data recovery (CDR) training of the data driving device 120 to the second main communication unit 122 via the first communication line LN1. The clock training step can be performed between the ID allocation step and the display mode, in which the clock training signal is sent to the data driving device 120. The clock training signal can be sent to the data driving device 120 via the first communication line LN1. When the data processing unit 110 receives a signal indicating a lock failure state of the data driving device 120, the data processing unit 110 sends the clock training signal to the first communication line LN1 to restart CDR.

[0046] The first auxiliary communication section 113 and the second auxiliary communication section 123 can be connected via the second communication line LN2. In the ID allocation step, the first auxiliary communication section 113 can send the ID code to the second auxiliary communication section 123 via the second communication line LN2.

[0047] The first main communication section 112 may include a scrambler 112A, an encoder 112B, a parallel-to-serial (P2S) converter 112C, a transmitter 112D, etc. The second main communication section 122 may include a receiver 122D, a serial-to-parallel (S2P) converter 122C, a decoder 122B, a descrambler 122A, etc.

[0048] The image data is scrambled by scrambler 112A. Scrambling is a process of scrambling each bit of the data to be transmitted, thereby preventing the same bit from appearing consecutively K times (where K is a natural number equal to or greater than 2) or more in the data transmission stream. Since scrambling can be performed according to pre-arranged rules, descrambling unit 122A can perform the function of restoring the scrambled stream to the data in its initial state.

[0049] Encoder 112B can encode P bits in the data transport stream into Q bits. P can be, for example, 8, and Q can be, for example, 10. Encoding 8 bits of data into 10 bits of data is defined as 8B10B encoding. 8B10B encoding is an encoding method using DC balanced codes. According to this implementation, data recovery rate can be improved, thereby improving image defects, by encoding not only image data but also control data for a horizontal row.

[0050] Encoder 112B can encode data, increasing the number of bits in the transport stream. The encoded data can be decoded by decoder 122B using DC balanced codes (e.g., 8B10B). Alternatively, the encoded data can be recovered to its original bits by decoder 122B.

[0051] Encoder 112B may use finite run-length code (LRLC) when encoding data. "Run length" means that identical bits are placed consecutively, and LRLC controls specific bits in the data such that the "run length" does not exceed a given size in the data. When encoder 112B encodes data using LRLC, decoder 122B may decode the data according to the LRLC scheme used by encoder 112B.

[0052] The P2S converter 112C converts data from a parallel system into data for a serial transmission system, enabling signal transmission via a small number of wires in the first communication line LN1. The transmitter 112D can serially transmit data input from the P2S converter 112C via the first communication line LN1. The data transmitted via the first communication line LN1 can be a differential signal. In this case, the first communication line LN1 may include wires for transmitting positive signals and wires for transmitting negative signals.

[0053] The S2P converter 122C converts received serial data into parallel data. The S2P converter 122C may include a clock recovery section 122C-1. The clock recovery section 122C-1 receives a clock training signal, performs clock training such that the phase of the clock detected from the input signal is stably fixed, and then samples the data bits using the clock recovered in this way to recover control data and image data. The clock recovery section 122C-1 can recover the clock using a phase-locked loop (PLL) method, but embodiments of this disclosure are not limited thereto. For example, the clock recovery section can recover the clock using a delay-locked loop (DLL) method.

[0054] The transmit controller 111 may include a memory 114. The memory 114 may store the ID code of the first source driver IC that will be assigned an ID among the plurality of source driver ICs in the data drive device 120.

[0055] Each source driver IC's receive controller 121 includes a memory 124. The memory 124 stores received ID codes, specifically the ID codes received by the first source driver IC from the data processing device 110. Each source driver IC other than the first source driver IC receives ID codes from another source driver IC that was previously assigned an ID, and stores these ID codes in its memory.

[0056] Figure 4 This is a diagram illustrating the signal transmission wires between the data processing apparatus and the data driving apparatus according to an embodiment of the present disclosure. Figure 4 In the above, the third source driver IC 120c can be the (n-1)th source driver IC, and the fourth source driver IC 120d can be the nth source driver IC.

[0057] Reference Figure 4 The data driving device may include multiple source driver ICs 120a, 120b, 120c and 120d. The data processing device 110 may be connected one-to-one to the source driver ICs 120a, 120b, 120c and 120d via a first communication line LN1.

[0058] The first communication line LN1 can also consist of m electrically insulated lines (m being a natural number). Each pair of lines can be paired, and low-voltage differential signaling (LVDS) communication can be performed on each pair.

[0059] The data processing device 110 and the source driver ICs 120a, 120b, 120c and 120d can be connected in a cascaded or serial manner between the first terminal and the second terminal of the data processing device 110 via the second communication line LN2.

[0060] The second communication line LN2 may include a forward conductor (LN2a), n intermediate conductors (LN2b, LN2c, and LN2d, where n is a natural number equal to or greater than 2), and a feedback conductor LN2e. Figure 4 The example shown is for n=3, but the embodiments of this disclosure are not limited to this. Because adjacent source driver ICs are connected via intermediate wires, the number of intermediate wires becomes larger as the number of source driver ICs increases.

[0061] The first source driver IC 120a is connected to the first terminal of the data processing device 110 via a positive wire LN2a. The first source driver IC 120a and the second source driver IC 120b are connected to each other via a first intermediate wire LN2b. The second source driver IC 120b and the third source driver IC 120c are connected to each other via a second intermediate wire LN2c. The third source driver IC 120c and the fourth source driver IC 120d are connected to each other via a third intermediate wire LN2d. The fourth source driver IC 120d is connected to the second terminal of the data processing device 110 via a feedback wire LN2e.

[0062] In the clock training step, the data processing device 110 (e.g., a timing controller) can send a clock training signal to source driver ICs 120a, 120b, 120c, and 120d via a first communication line LN1. When a first voltage of the lock signal is received via the positive conductor LN2a, and the phase of the clock recovered by the first source driver IC 120a performing clock training is fixed, a lock signal can be output at the first voltage. The first voltage of the lock signal output from the first source driver IC 120a is transmitted (propagated) to the second source driver IC 120b via the first intermediate conductor LN2b. When the phase of the clock recovered by the second source driver IC 120b performing clock training is fixed, a lock signal can be output at the first voltage. The first voltage of the lock signal output from the second source driver IC 120b is transmitted to the third source driver IC 120c via the second intermediate conductor LN2c. When the phase of the clock recovered by the third source driver IC 120c performing clock training is fixed, a lock signal can be output at the first voltage. The first voltage of the lock signal output from the third source driver IC 120c is transmitted to the fourth source driver IC 120d via the third intermediate wire LN2d. When the phase of the clock recovered by the fourth source driver IC 120d, which performs clock training, is fixed, the lock signal can be output at the first voltage. The first voltage of the lock signal output from the fourth source driver IC 120d is transmitted to the data processing device 110 via the feedback wire LN2e. When the phase of the recovered clock is unlocked in any of the source driver ICs 120a, 120b, 120c, and 120d, the lock signal is inverted at a second voltage to indicate a lock failure state and is sent to the data processing device 110. The lock failure state refers to the state where the clock in the source driver ICs 120a, 120b, 120c, and 120d has not recovered normally. When the lock signal received via the feedback wire LN2e is at a first voltage, the data processing device 110 can enter the display mode, and when the lock signal is at a second voltage, the data processing device 110 can send a clock training signal to the source driver ICs 120a, 120b, 120c, and 120d. The first voltage of the lock signal can be a high voltage (High or H) of the digital signal, and the second voltage can be a low voltage (Low or L) of the digital signal, but the embodiments of this disclosure are not limited thereto.

[0063] In the ID allocation step, by sequentially sending ID codes to source driver ICs 120a, 120b, 120c, and 120d via the second communication line LN2, IDs can be sequentially assigned to source driver ICs 120a, 120b, 120c, and 120d, and each IC can be assigned a unique ID. The following will combine... Figure 4 , Figure 5 and Figure 6Describe the ID allocation steps in detail.

[0064] Figure 5 This is a flowchart illustrating the control process of the ID allocation steps according to embodiments of this disclosure. Figure 5 In this context, "TCON" refers to a timing controller, which is an example of a data processing device 110. Figure 6 This is a waveform diagram showing the IDs sequentially assigned to the source driver IC in the ID allocation step according to an embodiment of the present disclosure.

[0065] Reference Figure 4 , Figure 5 and Figure 6 When power is applied to the display device, the timing controller TCON and the source driver ICs 120a, 120b, 120c and 120d are driven. Immediately after power is applied to the display device, the timing controller TCON can enter the ID allocation step (S01, S02).

[0066] The ID allocation process can be divided into the following time periods: the first time period IDP1, during which the ID allocation start protocol is executed for the source driver ICs 120a, 120b, 120c and 120d (S03); the second time period IDP2, during which the IDs are sequentially allocated to the source driver ICs 120a, 120b, 120c and 120d (S04); and the third time period IDP3, during which the ID allocation stop protocol is executed for the source driver ICs 120a, 120b, 120c and 120d (S05).

[0067] When the first time period IDP1 begins, the timing controller TCON sends the start code ID START to the first source driver IC 120a via the positive wire LN2a. The start code ID START is digital data defined in the ID allocation start protocol. Before the start code ID START, a preamble PRE can be sent to the first source driver IC 120a. The preamble PRE may include a pulse generated at a specific voltage (e.g., high voltage H), or a pulse that triggers one or more times and reverses the voltage one or more times. In the communication link between the timing controller TCON and the first source driver IC 120a, the preamble PRE can improve the recognition rate of the start code ID START in the first source driver IC 120a. After the first source driver IC 120a receives the start code ID START, the start code ID START is sequentially transmitted (propagated) to the other source driver ICs 120b, 120c, and 120d.

[0068] The first source driver IC 120a sends the start code ID START received from the timing controller TCON to the second source driver IC 120b via the first intermediate wire LN2b, and then changes the voltage of the first intermediate wire LN2b from low voltage L to high voltage H. The second source driver IC 120b sends the start code ID START received from the first source driver IC 120a to the third source driver IC 120c via the second intermediate wire LN2c, and then changes the voltage of the second intermediate wire LN2c from low voltage L to high voltage H. The third source driver IC 120c sends the start code ID START received from the second source driver IC 120b to the fourth source driver IC 120d via the third intermediate wire LN2d, and then changes the voltage of the third intermediate wire LN2d from low voltage L to high voltage H. The fourth source driver IC 120d sends the start code ID START received from the third source driver IC 120c to the timing controller TCON via the feedback line LN2e, and then changes the voltage of the feedback line LN2e from low voltage L to high voltage H.

[0069] When the start code ID START is received from the fourth source driver IC 120d via the feedback wire LN2e, the timing controller TCON determines that the ID allocation start protocol has been executed normally and enters the ID allocation step. The ID allocation step (S04) is executed in the second time period IDP2. In the ID allocation step, the first source driver IC 120a can generate a second ID code in response to the first ID code received from the timing controller TCON. The nth source driver IC can generate an ID allocation confirmation signal in response to the nth ID code received from the (n-1)th source driver IC, and can provide the ID allocation confirmation signal to the timing controller TCON.

[0070] When the second time period IDP2 begins, the timing controller TCON sends the first ID code ID1 to the first source driver IC 120a via the positive wire LN2a. The timing controller TCON can apply a high voltage H to the positive wire LN2a after sending the first ID code ID1 to the first source driver IC 120a. The first ID code ID1 is digital data defined in the ID allocation protocol. The first source driver IC 120a stores the first ID code ID1 received via the positive wire LN2a in memory 124, assigns the first ID code ID1 as its ID, and generates a second ID code ID2 by adding a preset increment or decrement to the first ID code ID1. The first source driver IC 120a sends the second ID code ID2 to the second source driver IC 120b via the first intermediate wire LN2b. The second source driver IC 120b stores the second ID code ID2 received via the first intermediate wire LN2b in the memory 124, assigns the second ID code ID2 as the ID of the second source driver IC 120b, and generates a third ID code ID3 by adding or subtracting an amount to the second ID code ID2. The second source driver IC 120b sends the third ID code ID3 to the third source driver IC 120c via the second intermediate wire LN2c. The third source driver IC 120c stores the third ID code ID3 received via the second intermediate wire LN2c in the memory 124, assigns the third ID code ID3 as the ID of the third source driver IC 120c, and generates a fourth ID code ID4 by adding or subtracting an amount to the third ID code ID3. The third source driver IC 120c sends the fourth ID code ID4 to the fourth source driver IC 120d via the third intermediate wire LN2d. The fourth source driver IC 120d stores the fourth ID code ID4 received via the third intermediate wire LN2d in memory 124, assigns the fourth ID code ID4 as the ID of the fourth source driver IC 120d, and generates a fifth ID code ID5 by adding or subtracting an amount to the fourth ID code ID4. The fifth ID code ID5 can be interpreted as an ID assignment confirmation signal. The fourth source driver IC 120d sends the fifth ID code ID5 to the timing controller TCON via the feedback wire LN2e. In the ID assignment step, each of the source driver ICs 120a, 120b, 120c, and 120d can apply a high voltage H to the corresponding wires in wires LN2b, LN2c, LN2d, and LN2e after outputting the internally generated ID code to transmit the ID code. The increment or decrement of the ID code added to each source driver IC 120a, 120b, 120c and 120d can be the same value in each IC, for example, "+1", but the embodiments of this disclosure are not limited thereto.For example, when ID1=1, the ID codes generated in the source driver ICs 120a, 120b, 120c and 120d can be ID2=ID1+1=2, ID3=ID2+1=3, ID4=ID3+1=4, and ID5=ID4+1=5.

[0071] When the fifth ID code ID5 is received from the fourth source driver IC 120d via the feedback wire LN2e, the timing controller TCON determines that the ID allocation protocol has been executed normally and enters the ID allocation stop step to end the ID allocation (S05).

[0072] In the third time period IDP3, the ID allocation stop step is executed. The timing controller TCON can determine the number of source driver ICs 120a, 120b, 120c, and 120d that have been assigned IDs, and can also verify whether the ID allocation was executed correctly based on the data value of the fifth ID code ID5 received via the feedback line LN2e. For example, the timing controller TCON can confirm whether the ID allocation protocol was executed correctly by comparing the fifth ID code ID5 stored in memory 114 with the fifth ID code ID5 received via the feedback line LN2e. When the fifth ID code ID5 received via the feedback line LN2e does not match the fifth ID code ID5 stored in memory 114, the timing controller TCON can execute the ID allocation step S04 again.

[0073] When the third period IDP3 begins, the timing controller TCON sends a stop code ID STOP to the first source driver IC 120a via the positive wire LN2a. The stop code ID STOP is digital data defined in the ID allocation stop protocol. After outputting the stop code ID STOP, the timing controller TCON can control the voltage of the positive wire LN2a to the voltage defined in the ID allocation stop protocol, such as a high voltage H or a low voltage L. After the first source driver IC 120a receives the stop code ID STOP, the stop code ID STOP is sequentially transmitted (propagated) to the other source driver ICs 120b, 120c, and 120d.

[0074] The first source driver IC 120a sends the stop code ID STOP received from the timing controller TCON to the second source driver IC 120b via the first intermediate wire LN2b, and then changes the voltage of the first intermediate wire LN2b from high voltage H to low voltage L. The second source driver IC 120b sends the stop code ID STOP received from the first source driver IC 120a to the third source driver IC 120c via the second intermediate wire LN2c, and then changes the voltage of the second intermediate wire LN2c from high voltage H to low voltage L. The third source driver IC 120c sends the stop code ID STOP received from the second source driver IC 120b to the fourth source driver IC 120d via the third intermediate wire LN2d, and then changes the voltage of the third intermediate wire LN2d from high voltage H to low voltage L. The fourth source driver IC 120d sends the stop code ID STOP received from the third source driver IC 120c to the timing controller TCON via the feedback line LN2e, and then changes the voltage of the feedback line LN2e from high voltage H to low voltage L.

[0075] When the stop code ID STOP is received from the fourth source driver IC 120d via the feedback wire LN2e, the timing controller TCON determines that the ID allocation stop protocol has been executed normally, and performs clock training steps (S06, S07) to establish communication links with the source driver ICs 120a, 120b, 120c and 120d.

[0076] During the clock training step, the timing controller TCON sends clock training signals to the source driver ICs 120a, 120b, 120c, and 120d via the first communication line LN1, performs monitoring via the feedback line LN2e, and enters the display mode (S08, S09) upon successful locking. In display mode, the timing controller TCON sends control data and image data to the source driver ICs 120a, 120b, 120c, and 120d.

[0077] In steps S04 and S05, the timing controller TCON can monitor the voltage received via the feedback line LN2e. If no voltage signal as defined in the ID allocation protocol and ID allocation stop protocol is received within a preset threshold time and the ID allocation is not confirmed (S10), the timing controller TCON can perform ID allocation again (S03, S04, S05). If the ID allocation is not confirmed until the threshold time has passed, the timing controller TCON will not perform ID allocation again (S03, S04, S05), but will instead proceed to the clock training step (S11).

[0078] After unique IDs are assigned to each of the source driver ICs 120a, 120b, 120c, and 120d, the timing controller TCON can use the unique ID assigned to each IC chip to access the source driver ICs 120a, 120b, 120c, and 120d separately. By distinguishing the source driver ICs 120a, 120b, 120c, and 120d, the timing controller TCON can use the IDs to perform tests, debugs, or transport channel environment construction individually. For example, the timing controller TCON can send a status information request command along with a second ID code ID2 via the positive wire LN2a. In this case, the second source driver IC 120b of the source driver ICs 120a, 120b, 120c, and 120d acknowledges the received second ID code ID2 and, in response to the command from the timing controller TCON, outputs the status information of the second source driver IC 120b via the third intermediate wire LN2d. The timing controller TCON can receive status information from the second source driver IC 120b via the feedback wire LN2e.

[0079] As an example of constructing a transmission channel environment, the timing controller TCON can, in conjunction with the ID code, perform equalizer (EQ) settings in each of the source driver ICs 120a, 120b, 120c, and 120d to improve the quality of the transmitted signal, or set channel coding selection and the number of channels. Channel coding may include scrambling code selection, CDR settings, etc.

[0080] The first communication line LN1 is a high-speed communication channel transmission path between the timing controller TCON and the source driver ICs 120a, 120b, 120c, and 120d. Conversely, the second communication line LN2 is a low-speed communication channel transmission path between the timing controller TCON and the source driver ICs 120a, 120b, 120c, and 120d. The communication channel via the second communication line LN2 can support a much lower transmission speed than the first communication line LN1, for example, a transmission speed of 1 Mbps to 800 Mbps. In the above embodiment, because the ID is assigned to the source driver ICs 120a, 120b, 120c, and 120d using a low-speed communication channel transmission path, ID assignment can be stable with almost no communication errors.

[0081] The objectives to be achieved by this disclosure, the means to achieve these objectives, and the effects of this disclosure as described above do not limit the essential features of the claims. Therefore, the scope of the claims is not limited to the content of this disclosure.

[0082] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all respects and do not limit the present disclosure.

[0083] Cross-reference to related applications

[0084] This application claims priority and benefit to Korean Patent Application No. 10-2025-0052062, filed in Korea on April 22, 2025, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A data transmitting and receiving apparatus, the data transmitting and receiving apparatus comprising: Transmitting device; Multiple receiving devices; A first communication line is configured to connect the plurality of receiving devices to the transmitting device on a one-to-one basis. as well as A second communication line is configured to connect the transmitting device and the receiving device between a first terminal and a second terminal of the transmitting device. The second communication line includes: A forward conductor, the forward conductor being connected between the first terminal of the transmitting device and the first receiving device; A feedback wire, the feedback wire being connected between the second terminal of the nth receiving device and the transmitting device, wherein n is a natural number equal to or greater than 3; and One or more intermediate wires are configured to connect adjacent receiving devices between the first receiving device and the nth receiving device, and The transmitting device is configured to transmit a first ID code to the first receiving device via the forward conductor, and to receive an ID allocation confirmation signal via the feedback conductor connected to the nth receiving device.

2. The data transmission and reception apparatus according to claim 1, wherein, The transmitting device is configured to output a clock training signal, control data, and image data after receiving the ID allocation confirmation signal.

3. The data transmission and reception apparatus according to claim 1, wherein, The signal transmission speed of the second communication line is lower than that of the first communication line.

4. The data transmission and reception apparatus according to claim 1, wherein, The first receiving device is configured to generate a second ID code in response to the first ID code, and to transmit the second ID code to the nth receiving device via the intermediate wire. The nth receiving device is configured to send the ID allocation confirmation signal to the transmitting device via the feedback wire in response to the second ID code.

5. The data transmission and reception apparatus according to claim 1, wherein, The transmitting device is configured to transmit a start code to the first receiving device via the forward conductor before the first ID code, and to receive the start code from the nth receiving device via the feedback conductor. The first receiving device is configured to transmit the start code received via the forward conductor to the nth receiving device via the intermediate conductor, and then change the voltage of the intermediate conductor to a first voltage. The nth receiving device is configured to transmit the start code received via the intermediate wire to the transmitting device via the feedback wire, and then change the voltage of the feedback wire to the first voltage.

6. The data transmission and reception apparatus according to claim 5, wherein, The transmitting device is configured to transmit a preset preamble to the first receiving device via the forward conductor before the start code.

7. The data transmission and reception apparatus according to claim 6, wherein, The transmitting device is configured to send a stop code to the first receiving device via the forward conductor after receiving the ID allocation confirmation signal, and to receive the stop code from the nth receiving device via the feedback conductor. The first receiving device is configured to transmit the stop code received via the forward wire to the nth receiving device via the intermediate wire. The nth receiving device is configured to transmit the stop code received via the intermediate wire to the transmitting device via the feedback wire. The first receiving device is configured to output the stop code to the intermediate conductor, then change the voltage of the intermediate conductor to a second voltage, and The nth receiving device is configured to output the stop code to the feedback line and then change the voltage of the feedback line to the second voltage.

8. A display device, the display device comprising: The display panel has data cables that connect to the pixels. Multiple driver ICs are electrically connected to the data line and configured to provide a data voltage corresponding to the image data to the data line; as well as A timing controller, connected to the driver IC via a first communication line and a second communication line, is configured to assign an ID to the driver IC via the second communication line and then send the image data to the driver IC via the first communication line. The first communication line is configured to connect the timing controller and the driver IC on a one-to-one basis. The second communication line is configured to cascade the timing controller and the driver IC, and The timing controller is configured to send a first ID code to one of the driver ICs.

9. The display device according to claim 8, wherein, The driver IC includes: A first driver IC is configured to generate an (n-1)th ID code by adding a preset increment or decrement to the first ID code received from the timing controller via the second communication line, where n is a natural number equal to or greater than 3. The (n-1)th driver IC is configured to generate the nth ID code by adding the increment or decrement to the (n-1)th ID code received via the second communication line; and The nth driver IC is configured to generate an ID allocation confirmation signal by adding the increment or decrement to the nth ID code received via the second communication line, and to send the ID allocation confirmation signal to the timing controller.

10. The display device according to claim 9, wherein, The second communication line includes: A positive wire, wherein the positive wire is connected between the first terminal of the timing controller and the first driver IC; Feedback wire, the feedback wire being connected between the nth driver IC and the second terminal of the timing controller; and One or more intermediate wires are configured to connect adjacent driver ICs between the first driver IC and the nth driver IC, and The timing controller is configured to send the first ID code to the first driver IC via the positive wire, and to receive the ID allocation confirmation signal via the feedback wire connected to the nth driver IC.

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