Gamma voltage generation circuit and source driver circuit including the same

Abstract

Disclosed are a gamma voltage generation circuit and a source driver circuit including the same. The gamma voltage generation circuit includes a first voltage divider configured to output a plurality of voltages having different levels between a high potential reference voltage and a low potential reference voltage; a multiplexer part configured to select an upper gamma reference voltage and a lower gamma reference voltage from among the divided voltages; a first buffer part configured to transfer the upper gamma reference voltage and the lower gamma reference voltage; a second voltage divider configured to output voltages having different levels between the upper gamma reference voltage and the lower gamma reference voltage; a second buffer part configured to transfer a gamma reference voltage; and a third voltage divider configured to output gradation voltages having different voltage levels between the gamma reference voltages. The second buffer part includes a stabilizer configured to generate a sink current or a source current at an N-1 intermediate voltage division node and an N+1 intermediate voltage division node whenever an input image changes.

Description

Technical Field

[0001] Embodiments of the present invention relate to a gamma voltage generation circuit and a source driver circuit including the same. Background Technology

[0002] With the development of the information technology society, the demand for display devices for displaying images is increasing in various forms, and in recent years, various types of display devices, such as liquid crystal display (LCD) and organic light-emitting display (OLED), have been utilized.

[0003] The display device includes a display panel with multiple pixels, a panel driver for driving the display panel, etc. The panel driver includes a data driver for supplying data voltage to the display panel and a gating driver for supplying gating signals to the display panel.

[0004] The panel driver also includes a gamma voltage generation circuit for supplying a gamma reference voltage to the data driver. Since the gamma voltage output from the gamma voltage generation circuit varies according to the input image, the gamma voltage fluctuates significantly whenever the input image changes, which in turn prolongs the settling time of the output signal. Summary of the Invention

[0005] This disclosure is intended to address the aforementioned needs and / or problems.

[0006] Embodiments of this disclosure may provide a gamma voltage generation circuit and a source driver circuit including the same.

[0007] The problems to be solved by this disclosure are not limited to the above-described objectives, and other objectives not mentioned will be clearly understood by those skilled in the art from the following description.

[0008] A gamma voltage generation circuit according to an embodiment of the present disclosure includes: a first voltage divider configured to output a plurality of voltages having different voltage levels between a high-potential reference voltage and a low-potential reference voltage; a multiplexer section configured to select an upper gamma reference voltage and a lower gamma reference voltage from the voltages divided by the first voltage divider; a first buffer section configured to transmit the upper gamma reference voltage and the lower gamma reference voltage selected by the multiplexer section; and a second voltage divider configured to output the upper gamma reference voltage transmitted by the first buffer section. The input image includes a voltage with a different voltage level between the input image and the gamma reference voltage; a second buffer portion configured to transmit the gamma reference voltage from the voltage divided by the second voltage divider; and a third voltage divider configured to output a grayscale voltage with a different voltage level between the gamma reference voltages transmitted by the second buffer portion, wherein the second buffer portion may include a stabilizer configured to generate a sink current or a source current at the (N-1)th intermediate voltage divider node and the (N+1)th intermediate voltage divider node relative to the Nth voltage divider node of the output Nth gamma reference voltage whenever the input image changes.

[0009] The second buffer section may further include an output section configured to output an Nth gamma reference voltage through a first output node connected to the Nth voltage divider node using a pull-up transistor controlled by a first control voltage and a pull-down transistor controlled by a second control voltage. The stabilizer may include: a first transistor and a second transistor configured to generate a sink current or a source current through a second output node connected to the (N-1)th intermediate voltage divider node; and a third transistor and a fourth transistor configured to generate a sink current or a source current through a third output node connected to the (N+1)th intermediate voltage divider node.

[0010] The pull-up transistor, the first transistor, and the third transistor can be p-channel transistors, and the pull-down transistor, the second transistor, and the fourth transistor can be n-channel transistors.

[0011] The stabilizer may further include: a first comparator configured to convert a first control voltage into a first pulse wave and apply the converted first pulse wave to a first transistor and a third transistor; and a second comparator configured to convert a second control voltage into a second pulse wave and apply the converted second pulse wave to a second transistor and a fourth transistor. The first and second comparators may be Schmitt triggers.

[0012] The first transistor may include a gate electrode to which a first pulse wave is applied, a first electrode to which a high potential voltage is applied, and a second electrode connected to a second output node. The second transistor may include a gate electrode to which a second pulse wave is applied, a first electrode connected to a second output node, and a second electrode to which a low potential voltage is applied. The third transistor may include a gate electrode to which a first pulse wave is applied, a first electrode to which a high potential voltage is applied, and a second electrode connected to a third output node. The fourth transistor may include a gate electrode to which a second pulse wave is applied, a first electrode connected to a third output node, and a second electrode to which a low potential voltage is applied.

[0013] The (N-1)th intermediate voltage divider node can be located between the Nth voltage divider node and the (N-1)th voltage divider node that outputs the (N-1)th gamma voltage, and the (N+1)th intermediate voltage divider node can be located between the Nth voltage divider node and the (N+1)th voltage divider node that outputs the (N+1)th gamma voltage.

[0014] When the grayscale of the input image decreases, the stabilizer can generate sink current at each of the (N-1)th intermediate voltage divider node and the (N+1)th intermediate voltage divider node.

[0015] As the grayscale of the input image increases, the stabilizer can generate source current at each of the (N-1)th and (N+1)th intermediate voltage divider nodes.

[0016] A source driver circuit according to an embodiment of the present disclosure includes: a data driver configured to convert source data into a data voltage based on a gamma voltage; and a gamma voltage generation circuit configured to generate the gamma voltage, wherein the gamma voltage generation circuit includes: a first voltage divider configured to output a plurality of voltages having different voltage levels between a high-potential reference voltage and a low-potential reference voltage; a multiplexer section configured to select an upper gamma reference voltage and a lower gamma reference voltage from the voltages divided by the first voltage divider; and a first buffer section configured to transmit the upper gamma reference voltage and the lower gamma reference voltage selected by the multiplexer section. A second voltage divider configured to output a voltage with different voltage levels between the upper gamma reference voltage and the lower gamma reference voltage transmitted by the first buffer portion; a second buffer portion configured to transmit a gamma reference voltage from the voltage divided by the second voltage divider; and a third voltage divider configured to output a grayscale voltage with different voltage levels between the gamma reference voltages transmitted by the second buffer portion, wherein the second buffer portion may include a stabilizer configured to generate a sink current or a source current at the (N-1)th intermediate voltage divider node and the (N+1)th intermediate voltage divider node relative to the Nth voltage divider node of the output Nth gamma reference voltage whenever the input image changes.

[0017] According to this disclosure, by generating source current or sink current at the (N-1)th intermediate voltage divider node and the (N+1)th intermediate voltage divider node relative to the Nth voltage divider node of the output gamma reference voltage, the settling time for the Nth gamma reference voltage to return to its original voltage is shortened according to the change of the input image, and therefore, the settling time for the output voltage can also be shortened.

[0018] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other effects not mentioned in the claims. Attached Figure Description

[0019] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein: Figure 1 This is a block diagram illustrating a display device according to one embodiment of the present disclosure; Figure 2 It is shown Figure 1 A block diagram showing the circuit configuration of the data driver; Figure 3 yes Figure 1The circuit configuration diagram of the gamma voltage generator shown is as follows. Figure 4 It is shown Figure 3 The equivalent circuit diagram of the circuit configuration of the second buffer section shown; and Figures 5 to 8 It is used for explanation Figure 4 The diagram shows the operating principle of the stabilizer. Detailed Implementation

[0020] The advantages and features of this disclosure, as well as methods of implementing them, will become clear from the following detailed description of the embodiments taken in conjunction with the accompanying drawings. This disclosure is not limited to the following embodiments, which may be implemented in various different forms; rather, these embodiments are provided to make the disclosure complete and to allow those skilled in the art to fully understand the scope of this disclosure, and this disclosure is limited only by the scope of the appended claims.

[0021] To describe embodiments of this disclosure, the shapes, dimensions, proportions, angles, quantities, etc., shown in the accompanying drawings are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0022] Terms such as “including,” “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless these terms are used only with the term “only.” Unless otherwise expressly stated, references to the singular should be interpreted as including the plural.

[0023] In the explanation of the components, they are interpreted as including error tolerance, even if not explicitly stated.

[0024] When describing the location or interconnection between two components, such as “on top of,” “above,” “below,” “next to,” “connected to,” “cross,” or “intersect,” one or more other components may be inserted between them, unless “immediately adjacent” or “directly” is used.

[0025] When describing temporal contexts such as “after,” “following,” “next,” or “before,” they may not be continuous in time scale unless “immediately” or “directly” is used.

[0026] Components may be distinguished by using ordinal numbers, such as "first," "second," etc., before their names, but their function or structure is not limited by such ordinal numbers or component names. For ease of description, the ordinal numbers placed before the names of the same components may differ between implementations.

[0027] The following implementations can be combined or associated with each other, in whole or in part, and various types of interlocks and drives are technically possible. Implementations can be implemented independently of each other or together in an interrelated relationship.

[0028] Various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0029] In the following embodiments, a transistor is a three-electrode device comprising a gate, a source, and a drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-channel transistor, current flows from the drain to the source. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, current flows from the source to the drain because holes flow from the source to the drain. The source and drain of a transistor are not fixed. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0030] Figure 1 This is a block diagram illustrating a display device according to one embodiment of the present disclosure.

[0031] Reference Figure 1 According to one embodiment of the present disclosure, a display device includes a display panel 100 and a display panel driving circuit, which is used to write source data of an input image into pixels of the display panel 100. The source data can be interpreted as pixel data.

[0032] The display panel 100 may include multiple gate lines GL1 to GLm and multiple data lines DL1 to DLn, which are arranged to intersect each other to define multiple pixel regions. The display panel 100 may also include pixels P respectively disposed in the multiple pixel regions. Each pixel P may include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light for color implementation. Each pixel P may also include a white sub-pixel. In a liquid crystal display device, a pixel includes a liquid crystal cell. In an electroluminescent display device, a pixel includes a light-emitting element such as an OLED. Each sub-pixel includes pixel circuitry for driving the liquid crystal cell or the light-emitting element.

[0033] The display panel driving circuit, under the control of the timing controller 140, writes the source data of the input image into the pixels of the display panel 100. The display panel driving circuit includes a source driver circuit for converting the source data into a data voltage, and a gating driver 110. The source driver circuit includes a gamma voltage generator 130 and a data driver 120.

[0034] The gating driver 110 may be located on one side of the display panel 100, such as the left side, but in some embodiments, it may be located on both the opposite sides of the display panel 100, such as both the left and right sides. The gating driver 110 may include a plurality of gating driver ICs (gating driver integrated circuits, not shown).

[0035] The strobe driver 110 may be in the form of a packaged strobe driver IC, but is not necessarily limited to this, and the strobe driver IC may be directly mounted on the display panel 100.

[0036] The data driver 120 can receive source data of the input image as a digital signal from the timing controller 140 and output a data voltage. The data driver 120 can use a DAC (digital-to-analog converter) to convert the source data of the input image into a gamma voltage and output a data voltage.

[0037] The data driver 120 may be disposed on one side of the display panel 100, such as the top side, but in some embodiments, it may be disposed on both the opposite sides of the display panel 100, such as the top and bottom sides. Furthermore, the data driver 120 may be in the form of a package that mounts an active driver IC, but is not necessarily limited to this.

[0038] The gamma voltage generator 130 can generate multiple gamma voltages with different voltage levels, use the generated gamma voltages to generate grayscale voltages, and provide the grayscale voltages to the data driver 120. The gamma voltages can be interpreted as gamma reference voltages.

[0039] The timing controller 140 can receive various timing signals from the host system 150, including vertical synchronization signals (Vsync), horizontal synchronization signals (Hsync), data enable signals (DE), and clock signals (CLK), and can generate data control signals (DCS) for controlling the data driver 120 and gating control signals (GCS) for controlling the gating driver 110. Additionally, the timing controller 140 can receive image data (RGB) from the host system 150, convert it to a form that can be processed by the data driver 120, and output it as image data (RGB').

[0040] The data control signal (DCS) may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE). The gating control signal (GCS) may include a gating start pulse (GSP), a gating shift clock (GSC), and a gating output enable signal (GOE).

[0041] The host system 150 can be implemented as any of the following: a navigation system, a set-top box, a DVD (Digital Multifunction Disc) player, a Blu-ray player, a personal computer (PC), a home theater system, a broadcast receiver, and a telephone system.

[0042] The host system 150 may include a SoC (System-on-a-Chip) with a built-in scaler and can convert digital image data (RGB) of the input image into a format suitable for display on the display panel 100. The host system 150 can transmit the digital image data (RGB) and timing signals to the timing controller 140.

[0043] Figure 2 yes Figure 1 The diagram shows the circuit configuration of the data driver.

[0044] Reference Figure 2 According to embodiments of the present disclosure, the data driver 120 may include a receiver 121, a logic controller 122, a shift register 123, a latch 124, a DAC 125, and an output buffer 126.

[0045] Receiver 121 can receive data serially provided from the timing controller, recover the clock from the received data, and use the recovered clock to sample control data and source data of the input image from the data.

[0046] The logic controller 122 can rearrange the source data on a sub-pixel basis. The logic controller 122 can use clock and control data to control the output timing of the shift register and latch.

[0047] Shift register 123 can shift the clock input from the timing controller to generate a sampling clock, and can sequentially output the generated sampling clock to a latch (LAT).

[0048] The latch 124 can sample and store source data according to the timing of the sequentially input sampling clock, and can output all stored source data at the same time.

[0049] DAC 125 can select a grayscale voltage corresponding to the grayscale value of the source data input from latch 124 and output it as a data voltage. The grayscale voltage can be interpreted as a gamma compensation voltage for each grayscale level and can be provided from gamma voltage generator 130.

[0050] Output buffer 126 amplifies the data voltage input from DAC 125 and outputs the amplified data voltage Vdata to the data line. The data voltage can increase as the grayscale of the source data increases and decrease as the grayscale of the source data decreases.

[0051] Figure 3 yes Figure 1 The diagram shows the circuit configuration of the gamma voltage generator.

[0052] Reference Figure 3 According to embodiments of the present disclosure, the gamma voltage generator 130 may include a first voltage divider 131, a multiplexer (MUX) section 132, a first buffer section 133, a second voltage divider 134, a second buffer section 135, and a third voltage divider 136.

[0053] In this configuration, when implementing the gamma voltage generation circuit for each color, the gamma voltage generator 130 may include, but is not limited to, a first gamma voltage generator 130R, a second gamma voltage generator 130G, and a third gamma voltage generator 130B. The first gamma voltage generator 130R outputs a gamma voltage for generating the data voltage applied to the red sub-pixel. The second gamma voltage generator 130G outputs a gamma voltage for generating the data voltage applied to the green sub-pixel. The third gamma voltage generator 130B outputs a gamma voltage for generating the data voltage applied to the blue sub-pixel.

[0054] The first voltage divider 131 can divide the voltage between the high-potential reference voltage VREF_H and the low-potential reference voltage VREF_L to output voltages with different voltage levels. For example, the first voltage divider 131 may include multiple resistors connected in series.

[0055] The first voltage divider 131 divides the voltage between the high-potential reference voltage VREF_H and the low-potential reference voltage VREF_L through the voltage divider node, thereby generating voltages with different voltage levels.

[0056] MUX section 132 can select the upper gamma reference voltages V0 and V1 and the lower gamma reference voltage V11 from the voltages divided by the first voltage divider 131. For example, MUX section 132 can be implemented as multiplexers MUX1, MUX2 and MUX3.

[0057] The first buffer section 133 can transmit the upper and lower gamma reference voltages V0, V1, and V11 selected by the MUX section 132. For example, the first buffer section 133 can be implemented as buffers BUF11, BUF12, and BUF13, which are composed of an operating amplification section. The first buffer section 133 includes a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal.

[0058] The second voltage divider 134 can divide the voltage between the upper gamma reference voltage V1 and the lower gamma reference voltage V11 from the first buffer section 133 through the voltage divider node, thereby outputting gamma reference voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, V10 and V11 with different voltage levels.

[0059] The second buffer section 135 can be implemented as buffers BUF21, BUF22, BUF23, BUF24, BUF25, BUF26, BUF27, BUF28 and BUF29, and can transmit the gamma reference voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, V10 and V11 output from the second voltage divider 134.

[0060] The third voltage divider 136 can divide the voltage between the gamma reference voltages V1, V2, V3, V4, V5, V6, V7, V8, V9, V10 and V11 output from the second buffer section 135 through the voltage divider node, thereby outputting a gamma compensation voltage for each grayscale, i.e., the grayscale voltage.

[0061] Figure 4 It is shown Figure 3 The equivalent circuit diagram of the circuit configuration of the second buffer section is shown.

[0062] Reference Figure 4 According to embodiments of the present disclosure, the second buffer portion 135 may include an input portion 135a, an amplification portion 135b, an output portion 135c, and a stabilizer 135d.

[0063] The input section 135a may include an eleventh PMOS transistor PM11, a twelfth PMOS transistor PM12, an eleventh NMOS transistor NM11, a twelfth NMOS transistor NM12, a thirteenth PMOS transistor PM13, and a thirteenth NMOS transistor NM13.

[0064] The eleventh PMOS transistor PM11 is controlled by the output voltage Vout1 and includes a gate electrode to which the output voltage Vout1 is applied, a first electrode connected to the first node N1, and a second electrode connected to the third node N3.

[0065] The twelfth PMOS transistor PM12 is controlled by the input voltage Vin and includes a gate electrode to which the input voltage Vin is applied, a first electrode connected to the first node N1, and a second electrode connected to the fourth node N4.

[0066] When the eleventh PMOS transistor PM11 is turned on by the output voltage Vout1, it supplies a high potential voltage AVDDH to the third node N3, and when the twelfth PMOS transistor PM12 is turned on by the input voltage Vin, it supplies a high potential voltage AVDDH to the fourth node N4.

[0067] The eleventh NMOS transistor NM11 is controlled by the output voltage Vout1 and includes a gate electrode to which the output voltage Vout1 is applied, a first electrode connected to the fifth node N5, and a second electrode connected to the second node N2.

[0068] The twelfth NMOS transistor NM12 is controlled by the input voltage Vin and includes a gate electrode to which the input voltage Vin is applied, a first electrode connected to the sixth node N6, and a second electrode connected to the second node N2.

[0069] When the eleventh NMOS transistor NM11 is turned on by the output voltage Vout1, it discharges the fifth node N5 to the low potential voltage VSS, and when the twelfth NMOS transistor NM12 is turned on by the input voltage Vin, it discharges the sixth node N6 to the low potential voltage VSS.

[0070] The thirteenth PMOS transistor PM13 is controlled by a first bias voltage VB1 and includes a gate electrode to which the first bias voltage VB1 is applied, a first electrode to which a high potential voltage AVDDH is applied, and a second electrode connected to the first node N1.

[0071] The thirteenth NMOS transistor NM13 is controlled by a second bias voltage VB2 and includes a gate electrode to which the second bias voltage VB2 is applied, a first electrode connected to the second node N2, and a second electrode to which a low potential voltage VSS is applied.

[0072] When the thirteenth PMOS transistor PM13 is turned on by the first bias voltage VB1, it supplies the high potential voltage AVDDH to the first node N1, and when the thirteenth NMOS transistor NM13 is turned on by the second bias voltage VB2, it supplies the low potential voltage VSS to the second node N2.

[0073] The amplification section 135b can amplify the current at the third node N3 to the sixth node N6 based on the difference between the input voltage Vin and the output voltage Vout1, and can generate the first control voltage HIP and the second control voltage HIN at the tenth node N10 and the eighth node N8, respectively. The amplification section 135b may include the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the sixth PMOS transistor PM6, the seventh PMOS transistor PM7, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the fourth NMOS transistor NM4, the fifth NMOS transistor NM5, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, and the ninth NMOS transistor NM9.

[0074] The fourth PMOS transistor PM4 is controlled by the voltage at the ninth node N9 and includes a gate electrode connected to the ninth node N9, a first electrode to which a high potential voltage AVDDH is applied, and a second electrode connected to the fifth node N5.

[0075] The fifth PMOS transistor PM5 is controlled by the voltage at the ninth node N9 and includes a gate electrode connected to the ninth node N9, a first electrode to which a high potential voltage AVDDH is applied, and a second electrode connected to the sixth node N6.

[0076] The sixth PMOS transistor PM6 is controlled by a third bias voltage VB3 and includes a gate electrode to which the third bias voltage VB3 is applied, a first electrode connected to the fifth node N5, and a second electrode connected to the ninth node N9.

[0077] The seventh PMOS transistor PM7 is controlled by a third bias voltage VB3 and includes a gate electrode to which the third bias voltage VB3 is applied, a first electrode connected to the sixth node N6, and a second electrode connected to the tenth node N10.

[0078] The eighth PMOS transistor PM8 is controlled by a fifth bias voltage VB5 and includes a gate electrode to which the fifth bias voltage VB5 is applied, a first electrode connected to the ninth node N9, and a second electrode connected to the seventh node N7.

[0079] The ninth PMOS transistor PM9 is controlled by the seventh bias voltage VB7 and includes a gate electrode to which the seventh bias voltage VB7 is applied, a first electrode connected to the tenth node N10, and a second electrode connected to the eighth node N8.

[0080] The fourth NMOS transistor NM4 is controlled by the voltage at the seventh node N7 and includes a gate electrode connected to the seventh node N7, a first electrode connected to the third node N3, and a second electrode to which a low potential voltage VSS is applied.

[0081] The fifth NMOS transistor NM5 is controlled by the voltage at the seventh node N7 and includes a gate electrode connected to the seventh node N7, a first electrode connected to the fourth node N4, and a second electrode to which a low potential voltage VSS is applied.

[0082] The sixth NMOS transistor NM6 is controlled by a fourth bias voltage VB4 and includes a gate electrode to which the fourth bias voltage VB4 is applied, a first electrode connected to the seventh node N7, and a second electrode connected to the third node N3.

[0083] The seventh NMOS transistor NM7 is controlled by a fourth bias voltage VB4 and includes a gate electrode to which the fourth bias voltage VB4 is applied, a first electrode connected to the eighth node N8, and a second electrode connected to the fourth node N4.

[0084] The eighth NMOS transistor NM8 is controlled by the sixth bias voltage VB6 and includes a gate electrode to which the sixth bias voltage VB6 is applied, a first electrode connected to the ninth node N9, and a second electrode connected to the seventh node N7.

[0085] The ninth NMOS transistor NM9 is controlled by the eighth bias voltage VB8 and includes a gate electrode to which the eighth bias voltage VB8 is applied, a first electrode connected to the tenth node N10, and a second electrode connected to the eighth node N8.

[0086] The output section 135c can perform pull-up and pull-down operations according to the first control voltage HIP and the second control voltage HIN, thereby outputting the output voltage Vout1, which follows the input voltage Vin, to the first output node OUT1. The output section 135c may include a tenth PMOS transistor PM10, a tenth NMOS transistor NM10, a first capacitor C1, and a second capacitor C2.

[0087] The tenth PMOS transistor PM10 is a pull-up transistor controlled by the voltage at the tenth node N10, and includes a gate electrode connected to the tenth node N10, a first electrode to which a high potential voltage AVDDH is applied, and a second electrode connected to the first output node OUT1.

[0088] The tenth NMOS transistor NM10 is a pull-down transistor controlled by the voltage at the eighth node N8, and includes a gate electrode connected to the eighth node N8, a first electrode connected to the first output node OUT1, and a second electrode to which a low potential voltage VSS is applied.

[0089] The first capacitor C1 is connected between the sixth node N6 and the first output node OUT1. The second capacitor C2 is connected between the fourth node N4 and the first output node OUT1. The first capacitor C1 and the second capacitor C2 stabilize the output voltage Vout1 output through the first output node OUT1 so that it does not oscillate when the output voltage Vout1 rises or falls.

[0090] Stabilizer 135d can quickly stabilize fluctuations in the gamma reference voltage due to changes in the input voltage Vin. Stabilizer 135d may include a first comparator COM1, a second comparator COM2, an eleventh PMOS transistor PM11, an eleventh NMOS transistor NM11, a twelfth PMOS transistor PM12, and a twelfth NMOS transistor NM12.

[0091] The first comparator COM1 senses the voltage at the tenth node N10, i.e., the first control voltage HIP, and converts it into a first pulse wave HIP_EN for output. The first comparator COM1 can be connected between the tenth node N10 and the gate electrode of the eleventh PMOS transistor PM11.

[0092] The second comparator COM2 senses the voltage at the eighth node N8, i.e., the second control voltage HIN, and converts it into a second pulse wave HIN_EN for output. The second comparator COM2 can be connected between the eighth node N8 and the gate electrode of the eleventh NMOS transistor NM11.

[0093] The first comparator COM1 and the second comparator COM2 can be comparators with hysteresis characteristics, and can output a logic high voltage when the input voltage is equal to or greater than a predetermined threshold voltage, and output a logic low voltage when the input voltage is less than the threshold voltage. The first comparator COM1 and the second comparator COM2 can be implemented as, for example, Schmitt flip-flops, but are not limited thereto.

[0094] The eleventh PMOS transistor PM11 is a pull-up transistor controlled by the voltage of the first pulse wave (HIP_EN) output from the first comparator COM1, and includes a gate electrode connected to the tenth node N10, a first electrode to which a high potential voltage AVDDH is applied, and a second electrode connected to the second output node OUT2, through which the output voltage Vout2 is output.

[0095] The eleventh NMOS transistor NM11 is a pull-down transistor controlled by the voltage of the second pulse wave HIN_EN output from the second comparator COM2, and includes a gate electrode connected to the eighth node N8, a first electrode connected to the second output node OUT2, and a second electrode to which a low potential voltage VSS is applied.

[0096] The twelfth PMOS transistor PM12 is a pull-up transistor controlled by the voltage of the first pulse wave HIP_EN output from the first comparator COM1, and includes a gate electrode connected to the tenth node N10, a first electrode to which a high potential voltage AVDDH is applied, and a second electrode connected to the third output node OUT3, through which the output voltage Vout3 is output.

[0097] The twelfth NMOS transistor NM12 is a pull-down transistor controlled by the voltage of the second pulse wave HIN_EN output from the second comparator COM2, and includes a gate electrode connected to the eighth node N8, a first electrode connected to the third output node OUT3, and a second electrode to which a low potential voltage VSS is applied.

[0098] Figures 5 to 8 It is used for explanation Figure 4 The diagram shows the operating principle of the stabilizer.

[0099] Reference Figure 5 and Figure 6 When the grayscale of the input image decreases, the input voltage VIN drops and becomes lower than the output voltage Vout1, which causes the gamma reference voltage to swing in the positive (+) direction, thereby increasing the second control voltage HIN to be applied as the gate turn-on voltage.

[0100] During this period, in stabilizer 135d, the pull-up transistors (i.e., the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12) are turned off, while the pull-down transistors (i.e., the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12) are turned on to perform a pull-down operation, so that the voltage at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1) is reduced relative to the Nth voltage divider node DN(N) of the output Nth gamma reference voltage Vn, thereby reducing the output voltage.

[0101] The (N-1)th intermediate voltage divider node IDN(N-1) is located between the (N-1)th voltage divider node DN(N-1) and the Nth voltage divider node DN(N), and the (N+1)th intermediate voltage divider node IDN(N+1) is located between the Nth voltage divider node DN(N) and the (N+1)th voltage divider node DN(N+1).

[0102] In other words, when the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 are turned on, sink current is generated at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1), so that the voltages Vn-1 and Vn+1 at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1) decrease.

[0103] Therefore, due to the voltage changes at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1), the settling time for the Nth gamma reference voltage Vn to return to its original voltage is shortened, which in turn shortens the settling time for the output voltage Vout1.

[0104] For example, such as Figure 6 As shown, the settling time for the Nth gamma reference voltage Vn is shortened from t4 to t3, and the settling time for the output voltage Vout1 is also shortened from t4 to t3.

[0105] Reference Figure 7 and Figure 8 From time t1 to time t2, as the grayscale of the input image increases, the input voltage VIN rises and becomes greater than the output voltage Vout1. This causes the gamma reference voltage to swing in the negative (-) direction, thereby reducing the first control voltage HIP to be applied as the gate turn-on voltage.

[0106] During this period, in stabilizer 135d, the pull-down transistors (i.e., the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12) are turned off, while the pull-up transistors (i.e., the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12) are turned on to perform a pull-up operation, so that the voltage at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1) increases relative to the Nth voltage divider node DN(N) of the output Nth gamma reference voltage Vn, thereby increasing the output voltage.

[0107] In other words, when the eleventh PMOS transistor PM11 and the twelfth PMOS transistor PM12 are turned on, source currents are generated at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1), so that the voltage at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1) increases.

[0108] Therefore, due to the voltage changes at the (N-1)th intermediate voltage divider node IDN(N-1) and the (N+1)th intermediate voltage divider node IDN(N+1), the settling time for the Nth gamma reference voltage Vn to return to its original voltage is shortened, which in turn shortens the settling time for the output voltage Vout1.

[0109] For example, such as Figure 8 As shown, the settling time for the Nth gamma reference voltage Vn is shortened from time t4 to time t3, and the settling time for the output voltage Vout1 is also shortened from time t4 to time t3.

[0110] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to such embodiments and can be modified in various ways within its scope without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed in this specification are provided not to limit the technical spirit of the present disclosure, but to describe it, and the scope of the technical spirit of the present disclosure is not limited by these embodiments. Therefore, the above embodiments should be understood in all respects as illustrative rather than restrictive. The scope of protection of this disclosure should be interpreted by the claims, and all technical ideas within the scope of their equivalents should be interpreted as being within the scope of the rights of this disclosure.

[0111] Cross-reference to related applications

[0112] This application claims priority and benefit to Korean Patent Application No. 10-2025-0051749, filed on April 21, 2025, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A gamma voltage generating circuit, the gamma voltage generating circuit comprising: A first voltage divider is configured to output multiple voltages with different voltage levels between a high-potential reference voltage and a low-potential reference voltage. The multiplexer section is configured to select an upper gamma reference voltage and a lower gamma reference voltage from the voltage divided by the first voltage divider; A first buffer section is configured to transmit the upper gamma reference voltage and the lower gamma reference voltage selected by the multiplexer section; A second voltage divider is configured to output a voltage with different voltage levels between the upper gamma reference voltage and the lower gamma reference voltage transmitted by the first buffer portion. The second buffer section is configured to transfer a gamma reference voltage from the voltage divided by the second voltage divider; as well as A third voltage divider is configured to output grayscale voltages with different voltage levels between the gamma reference voltages transmitted by the second buffer section. The second buffer portion includes a stabilizer configured to generate a sink current or a source current at the (N-1)th and (N+1)th intermediate voltage divider nodes relative to the Nth gamma reference voltage output whenever the input image changes, where N is a natural number.

2. The gamma voltage generating circuit according to claim 1, wherein, The second buffer section further includes an output section configured to output the Nth gamma reference voltage through a first output node connected to the Nth voltage divider node, using a pull-up transistor controlled by a first control voltage and a pull-down transistor controlled by a second control voltage. The stabilizer includes: A first transistor and a second transistor, configured to generate the sink current or the source current through a second output node connected to the (N-1)th intermediate voltage divider node; and The third and fourth transistors are configured to generate the sink current or the source current through a third output node connected to the (N+1)th intermediate voltage divider node.

3. The gamma voltage generating circuit according to claim 2, wherein, The pull-up transistor, the first transistor, and the third transistor are p-channel transistors, and the pull-down transistor, the second transistor, and the fourth transistor are n-channel transistors.

4. The gamma voltage generating circuit according to claim 2, wherein, The stabilizer also includes: A first comparator, configured to convert the first control voltage into a first pulse wave, and apply the converted first pulse wave to the first transistor and the third transistor; and A second comparator is configured to convert the second control voltage into a second pulse wave and apply the converted second pulse wave to the second transistor and the fourth transistor.

5. The gamma voltage generating circuit according to claim 4, wherein, The first comparator and the second comparator are Schmitt triggers.

6. The gamma voltage generating circuit according to claim 4, wherein, The first transistor includes a gate electrode to which the first pulse wave is applied, a first electrode to which a high potential voltage is applied, and a second electrode connected to the second output node. The second transistor includes a gate electrode to which the second pulse wave is applied, a first electrode connected to the second output node, and a second electrode to which a low potential voltage is applied. The third transistor includes a gate electrode to which the first pulse wave is applied, a first electrode to which the high potential voltage is applied, and a second electrode connected to the third output node. The fourth transistor includes a gate electrode to which the second pulse wave is applied, a first electrode connected to the third output node, and a second electrode to which the low potential voltage is applied.

7. The gamma voltage generating circuit according to claim 1, wherein, The (N-1)th intermediate voltage divider node is located between the Nth voltage divider node and the (N-1)th voltage divider node that outputs the (N-1)th gamma voltage, and The (N+1)th intermediate voltage divider node is located between the Nth voltage divider node and the (N+1)th voltage divider node that outputs the (N+1)th gamma voltage.

8. The gamma voltage generating circuit according to claim 1, wherein, When the grayscale of the input image decreases, the stabilizer generates the sink current at each of the (N-1)th intermediate voltage divider node and the (N+1)th intermediate voltage divider node.

9. The gamma voltage generating circuit according to claim 1, wherein, As the grayscale of the input image increases, the stabilizer generates the source current at each of the (N-1)th intermediate voltage divider node and the (N+1)th intermediate voltage divider node.

10. A source driver circuit, the source driver circuit comprising: A data driver configured to convert source data into a data voltage based on gamma voltage; as well as A gamma voltage generation circuit, configured to generate the gamma voltage. The gamma voltage generation circuit includes: A first voltage divider is configured to output multiple voltages with different voltage levels between a high-potential reference voltage and a low-potential reference voltage. The multiplexer section is configured to select an upper gamma reference voltage and a lower gamma reference voltage from the voltage divided by the first voltage divider. A first buffer section is configured to transmit the upper gamma reference voltage and the lower gamma reference voltage selected by the multiplexer section; A second voltage divider is configured to output a voltage with different voltage levels between the upper gamma reference voltage and the lower gamma reference voltage transmitted by the first buffer portion. The second buffer section is configured to transfer a gamma reference voltage from the voltage divided by the second voltage divider; and A third voltage divider is configured to output grayscale voltages with different voltage levels between the gamma reference voltages transmitted by the second buffer section. The second buffer portion includes a stabilizer configured to generate a sink current or a source current at the (N-1)th and (N+1)th intermediate voltage divider nodes relative to the Nth gamma reference voltage output whenever the input image changes, where N is a natural number.

11. The source driver circuit according to claim 10, wherein, The second buffer section further includes an output section configured to output the Nth gamma reference voltage through a first output node connected to the Nth voltage divider node, using a pull-up transistor controlled by a first control voltage and a pull-down transistor controlled by a second control voltage. The stabilizer includes: A first transistor and a second transistor, configured to generate the sink current or the source current through a second output node connected to the (N-1)th intermediate voltage divider node; and The third and fourth transistors are configured to generate the sink current or the source current through a third output node connected to the (N+1)th intermediate voltage divider node.

12. The source driver circuit according to claim 11, wherein, The stabilizer also includes: A first comparator, configured to convert the first control voltage into a first pulse wave, and apply the converted first pulse wave to the first transistor and the third transistor; and A second comparator is configured to convert the second control voltage into a second pulse wave and apply the converted second pulse wave to the second transistor and the fourth transistor.

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