Shifting register circuit, display panel and display device

Abstract

The application provides a shift register circuit, a display panel and a display device, relates to the technical field of display, and can reduce power consumption. The shift register circuit comprises a shift register, which comprises: a first transistor, which is connected with a clock end, an input end and a first node, is turned on in response to a first level of the clock end, and writes a signal of the input end into the first node; a first module, which writes a first level or a second level into a second node in response to a signal of the first node, and the second node and the first node have opposite levels at the same time; a second transistor, which is connected with the second node, a first signal line and the first node, is turned on in response to a second level of the second node, and writes a first level of the first signal line into the first node; and an output module, which is connected with the second node, a first potential line, a second potential line and an output end, writes a first level of the first potential line into the output end in response to the second level of the second node, and writes a second level provided by the second potential line into the output end in response to a first level of the second node.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a shift register circuit, a display panel, and a display device. Background Technology

[0002] The display panel is equipped with a shift register. During operation, the shift register outputs scan signals step by step. The scan signals are transmitted to the pixel circuit through the scan lines to control the conduction and cutoff of the transistors in the pixel circuit, thereby completing the row-by-row selection drive of the pixel rows.

[0003] However, traditional shift register architectures consume a lot of power, which can lead to a series of problems such as panel overheating and increased overall power consumption, thus hindering the optimization and improvement of the display panel's overall performance. Summary of the Invention

[0004] This invention provides a shift register circuit, a display panel, and a display device to reduce the power consumption of the shift register circuit.

[0005] In a first aspect, embodiments of the present invention provide a shift register circuit, including multiple cascaded shift registers, wherein the shift registers include: The first transistor is electrically connected to the clock terminal, the input terminal, and the first node, and is configured to turn on in response to a first level provided by the clock terminal, and to write the signal from the input terminal into the first node. The first module is configured to respond to a signal from the first node by writing either the first level or the second level to the second node, such that the level states of the second node and the first node are opposite at the same time, wherein the level states of the second level and the first level are opposite. The second transistor, which is electrically connected to the second node, the first signal line and the first node respectively, is configured to turn on in response to the second level of the second node and write the first level provided by the first signal line into the first node; The output module is electrically connected to the second node, the first potential line, the second potential line, and the output terminal, respectively. It is configured to write the first level provided by the first potential line to the output terminal in response to the second level of the second node, and to write the second level provided by the second potential line to the output terminal in response to the first level of the second node.

[0006] Secondly, based on the same inventive concept, embodiments of the present invention also provide a display panel, including: Pixel circuit; In the aforementioned shift register circuit, the shift register is electrically connected to the pixel circuit.

[0007] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the aforementioned display panel.

[0008] The technical solution provided by the embodiments of the present invention has the following beneficial effects: Due to the threshold voltage, relying solely on the conduction of the first transistor is insufficient to fully transmit the first voltage level provided by the input terminal to the first node. For example, if the first transistor is a P-type transistor, it cannot fully transmit the low potential provided by the input terminal to the first node when it is turned on; if the first transistor is an N-type transistor, it cannot fully transmit the high potential provided by the input terminal to the first node when it is turned on, resulting in a decrease in the signal quality output by the output module.

[0009] To address this issue, related technologies typically employ a parallel transmission gate structure with complementary clock control, consisting of a P-type transistor and an N-type transistor. In this structure, the first terminals of both the P-type and N-type transistors are connected to the input, and their second terminals are both connected to the first node. The gate of the P-type transistor is connected to the first clock input, and the gate of the N-type transistor is connected to the second clock input. Simultaneously, the signal levels provided by the first and second clock inputs are opposite, allowing both transistors to conduct synchronously when the input signal needs to be written to the first node. This enables the complete writing of the input signal to the first node based on one of the transistor types. However, this architecture requires each shift register to be connected to two clock inputs, resulting in high power consumption during clock flips and increased overall circuit power consumption. Furthermore, it is prone to abnormal output due to timing differences between the two clock signals.

[0010] In this embodiment of the invention, a second transistor is configured, with its gate connected to a second node. By controlling the complementary voltage levels of the second node and the first node, the second transistor can be synchronously turned on in response to a second voltage level when the first transistor turns on in response to a first voltage level and the input terminal provides a first voltage level. This allows for a more complete writing of the first voltage level into the first node through the synergistic effect of different types of transistors. This design utilizes an internal node to drive the second transistor, eliminating the need for an additional clock input for the second transistor. The shift register requires only a single external clock input, thus effectively reducing power consumption and eliminating abnormal output problems caused by timing differences between different clocks.

[0011] Furthermore, in this embodiment of the invention, the second transistor is connected to a separate first signal line. The voltage value of the first level provided by the first signal line can be the same as or different from the voltage value of the first level provided by the input terminal. This allows for more flexible control of the potential of the first node. For example, when the first node needs to be set low, the second transistor can be used to completely write a lower potential into the first node, pulling its potential down further. Or, when the first node needs to be set high, the second transistor can be used to completely write a higher potential into the first node, raising its potential up further. This helps to further optimize the quality of the signal output by the output module. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a shift register circuit provided in an embodiment of the present invention; Figure 2 A schematic diagram of a shift register provided in an embodiment of the present invention; Figure 3 for Figure 2 A corresponding timing diagram; Figure 4 Another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 5 for Figure 4 A corresponding timing diagram; Figure 6 This is another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 7 This is yet another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 8 Another schematic diagram of the shift register circuit provided in an embodiment of the present invention; Figure 9 This is yet another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 10 This is yet another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 11 This is yet another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 12 This is yet another schematic diagram of a shift register provided in an embodiment of the present invention; Figure 13 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 14 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0014] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0015] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0016] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” used in the embodiments of this invention are also intended to include the plural forms unless the context clearly indicates otherwise.

[0017] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0018] This invention provides a shift register circuit. Figure 1 This is a schematic diagram of a shift register circuit provided in an embodiment of the present invention, such as... Figure 1 As shown, the shift register circuit includes multiple cascaded shift registers 1. Shift register 1 is electrically connected to the pixel circuit via scan lines, and its effective output level is used to control the conduction of the transistors connected to it in the pixel circuit, thereby controlling the pixel circuit to perform operations such as reset or charging.

[0019] Figure 2 This is a schematic diagram of a shift register provided in an embodiment of the present invention. Figure 3 for Figure 2 A corresponding timing diagram, Figure 4 This is another schematic diagram of a shift register provided in an embodiment of the present invention. Figure 5 for Figure 4 A corresponding timing diagram, such as Figures 2-5 As shown, shift register 1 includes a first transistor T1, a second transistor T2, a first module 2, and an output module 3.

[0020] In this configuration, the first transistor T1 is electrically connected to the clock terminal CK, the input terminal IN, and the first node N1, and is configured to turn on in response to the first level provided by the clock terminal CK, writing the signal at the input terminal IN into the first node N1. (See also...) Figure 1 In the two adjacent shift registers 1, the clock terminal CK of the first shift register 1 is electrically connected to the first clock line ck1, and the clock terminal CK of the other shift register 1 is electrically connected to the second clock line ck2.

[0021] The first module 2 is configured to respond to a signal from the first node N1 by writing a first level or a second level to the second node N2, such that the level states of the second node N2 and the first node N1 are opposite at the same time, wherein the second level and the first level are opposite in level state. Alternatively, in another embodiment, the first module 2 is configured to write a second level to the second node N2 when the first node N1 is at the first level, and to write a first level to the second node N2 when the first node N1 is at the second level.

[0022] The second transistor T2 is electrically connected to the second node N2, the first signal line L1, and the first node N1, and is configured to conduct in response to the second level of the second node N2, writing the first level provided by the first signal line L1 into the first node N1. That is, the second transistor T2 and the first transistor T1 are transistors of different types; the first transistor T1 conducts in response to the first level, and the second transistor T2 conducts in response to the second level.

[0023] Output module 3 is electrically connected to the second node N2, the first potential line VG1, the second potential line VG2 and the output terminal OUT, respectively. It is configured to write the first level provided by the first potential line VG1 to the output terminal OUT in response to the second level of the second node N2, and to write the second level provided by the second potential line VG2 to the output terminal OUT in response to the first level of the second node N2.

[0024] It should be noted that the "first level" and "second level" in this invention are only used to indicate the logic state (high or low) of the signal, and do not represent the actual voltage value. The "first level" related to the clock terminal CK, the first module 2, the first signal line L1, and the first potential line VG1 all indicate that their respective signals are in a high-level logic state (or a low-level logic state) at the current moment, but the voltage value of their respective signals in this logic state may be different. Similarly, the "second level" related to the clock terminal CK, the first module 2, and the second potential line VG2 all indicate that their respective signals are in a low-level logic state (or a high-level logic state) at the current moment, but the voltage value of their respective signals in this logic state may be different.

[0025] In one architecture, the first voltage level is low, and the second voltage level is high. See also Figure 2 The first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. The first potential line VG1 is a low potential line VGL used to provide a low level, the second potential line VG2 is a high potential line VGH used to provide a high level, and the first signal line L1 is used to provide a low level.

[0026] Taking the input terminal IN as an example with a high potential of VGH and a low potential of VGL. The first transistor T1 is a P-type transistor. When the first transistor T1 turns on in response to the low level provided by the clock terminal CK, and the input terminal IN provides a low potential VGL, due to the influence of the threshold voltage, the P-type first transistor T1 can only pull the potential of the first node N1 to VGL-Vth, and cannot completely transfer the low potential VGL provided by the input terminal IN to the first node N1. However, at the same time, the first node N1 triggers the first module 2 to write a high level to the second node N2, controlling the second transistor T2 to turn on synchronously. The second transistor T2 is an N-type transistor. The N-type transistor has no threshold voltage drop when outputting a low potential. Therefore, the second transistor T2 can completely write the low potential provided by the first signal line L1 to the first node N1, pulling the potential of the first node N1 low, so that the first node N1 can reach a sufficiently low potential when set low. Furthermore, the first node N1 better triggers the first module 2 to write a high level to the second node N2, further controlling the output module 3 to better output the low potential VGL provided by the first potential line VG1, improving the quality of the low level output by the shift register 1 circuit. Moreover, when the shift register 1 outputs a low level, the P-type transistors driven by it in the pixel circuit can be more fully turned on, optimizing the reset and charging processes of the pixel circuit. When the shift register 1 outputs a high level, the N-type transistors driven by it in the pixel circuit can be more fully turned off, suppressing leakage current.

[0027] Alternatively, in another architecture, the first level is high and the second level is low. See also Figure 4 The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor. The first potential line VG1 is a high-potential line VGH used to provide a high level, the second potential line VG2 is a low-potential line VGL used to provide a low level, and the first signal line L1 is used to provide a high level.

[0028] Taking the example of input terminal IN providing a high potential of VGH and a low potential of VGL, the first transistor T1 is an N-type transistor. When the first transistor T1 turns on in response to the high level provided by the clock terminal CK, and the input terminal IN provides a high potential VGH, due to the influence of the threshold voltage, the N-type first transistor T1 can only pull the potential of the first node N1 to VGH-Vth, and cannot completely transfer the high potential VGH provided by the input terminal IN to the first node N1. However, at the same time, the first node N1 triggers the first module 2 to write a low level to the second node N2, controlling the second transistor T2 to turn on synchronously. The second transistor T2 is a P-type transistor. P-type transistors have no threshold voltage drop when outputting a high potential. Therefore, the second transistor T2 can completely write the high potential provided by the first signal line L1 into the first node N1, raising the potential of the first node N1 so that the first node N1 can reach a sufficiently high potential when set high. Furthermore, the first node N1 better triggers the first module 2 to write a low level to the second node N2, further controlling the output module 3 to better output the high potential VGH provided by the first potential line VG1, improving the high-level output quality of the shift register 1 circuit. Moreover, when the shift register 1 outputs a high level, the N-type transistors driven by it in the pixel circuit can be more fully turned on, optimizing the reset and charging processes of the pixel circuit. When the shift register 1 outputs a low level, the P-type transistors driven by it in the pixel circuit can be more fully turned off, suppressing leakage current.

[0029] Due to the threshold voltage, relying solely on the conduction of the first transistor T1 is insufficient to fully transmit the first level provided by the input terminal IN to the first node N1. For example, as mentioned earlier, when the first transistor T1 is a P-type transistor, it cannot fully transmit the low potential provided by the input terminal IN to the first node N1 when it is turned on; when the first transistor T1 is an N-type transistor, it cannot fully transmit the high potential provided by the input terminal IN to the first node N1 when it is turned on, resulting in a decrease in the signal quality output by the output module 3.

[0030] To address this issue, related technologies typically employ a parallel transmission gate structure with complementary clock control, consisting of a P-type transistor and an N-type transistor. In this structure, the first terminals of both the P-type and N-type transistors are connected to the input, and their second terminals are both connected to the first node. The gate of the P-type transistor is connected to the first clock input, and the gate of the N-type transistor is connected to the second clock input. Simultaneously, the signal levels provided by the first and second clock inputs are opposite, allowing both transistors to conduct synchronously when the input signal needs to be written to the first node. This enables the complete writing of the input signal to the first node based on one of the transistor types. However, this architecture requires each shift register to be connected to two clock inputs, resulting in high power consumption during clock flips and increased overall circuit power consumption. Furthermore, it is prone to abnormal output due to timing differences between the two clock signals.

[0031] In this embodiment of the invention, a second transistor T2 is configured, with its gate connected to a second node N2. By controlling the complementary levels of the second node N2 and the first node N1, when the first transistor T1 responds to the first level and its input terminal IN provides the first level, the second transistor T2 is controlled to synchronously turn on in response to the second level. This allows for a more complete writing of the first level to the first node N1 through the synergistic effect of different types of transistors. This design utilizes an internal node to drive the second transistor T2, eliminating the need for an additional clock terminal CK for T2. The shift register 1 requires only a single external clock input, thus effectively reducing power consumption and eliminating abnormal output problems caused by timing differences between different clocks.

[0032] Furthermore, in this embodiment of the invention, the second transistor T2 is connected to a separate first signal line L1. The voltage value of the first level provided by the first signal line L1 can be the same as or different from the voltage value of the first level provided by the input terminal IN. This allows for more flexible control of the potential of the first node N1. For example, when the first node N1 needs to be set low, the second transistor T2 can be used to completely write a lower potential into the first node N1, pulling its potential to a lower level. Or, when the first node N1 needs to be set high, the second transistor T2 can be used to completely write a higher potential into the first node N1, raising its potential to a higher level. This helps to further optimize the quality of the signal output by the output module 3.

[0033] In some implementations, combined again Figure 2 and Figure 3 or combine again Figure 4 and Figure 5 The operation of shift register 1 includes a first time period t1, a second time period t2, a third time period t3, and a fourth time period t4.

[0034] During the first time period t1, the input terminal IN provides the first level, the clock terminal CK provides the second level, the first transistor T1 is turned off, the first node N1 maintains the second level, the second node N2 maintains the first level, and the output module 3 writes the second level provided by the second potential line VG2 into the output terminal OUT.

[0035] During the second time period t2, the input terminal IN provides a first level. During at least a portion of the time period, the clock terminal CK provides a first level. The first transistor T1 is turned on and writes the first level provided by the input terminal IN to the first node N1. The first module 2 writes a second level to the second node N2. The second transistor T2 is turned on and writes the first level provided by the first signal line L1 to the first node N1. The output module 3 writes the first level provided by the first potential line VG1 to the output terminal OUT.

[0036] The duration of the second time period t2 can be adjusted based on the number of first levels of the clock terminal CK it covers. For example, the second time period t2 can cover only one first level of the clock terminal CK to make the second time period t2 have a shorter duration, or the second time period t2 can cover only multiple first levels of the clock terminal CK to make the second time period t2 have a longer duration.

[0037] During the third time period t3, the input terminal IN provides the second level, the clock terminal CK provides the second level, the first transistor T1 is turned off, the first node N1 maintains the first level, the second node N2 maintains the second level, and the output module 3 writes the first level provided by the first potential line VG1 into the output terminal OUT.

[0038] During the fourth time period t4, the input terminal IN provides a second level. During at least a portion of the time period, the clock terminal CK provides a first level. The first transistor T1 is turned on, writing the second level provided by the input terminal IN to the first node N1. The first module 2 writes the first level to the second node N2. The second transistor T2 is turned off, and the output module 3 writes the second level provided by the second potential line VG2 to the output terminal OUT.

[0039] The duration of the fourth time period t4 can be adjusted based on the number of first levels of the clock terminal CK it covers. For example, the fourth time period t4 can cover only one first level of the clock terminal CK to make the fourth time period t4 have a shorter duration, or the fourth time period t4 can cover only multiple first levels of the clock terminal CK to make the fourth time period t4 have a longer duration.

[0040] Combination Figure 2 and Figure 3 In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, taking the input terminal IN with a high potential of VGH and a low potential of VGL as an example: During the first time period t1, the input terminal IN provides a low level, and the clock terminal CK provides a high level. The first transistor T1 is turned off, the first node N1 remains at a high level, the second node N2 remains at a low level, and the output module 3 continues to write the high level provided by the high potential line VGH to the output terminal OUT.

[0041] During the second time period t2, the input terminal IN provides a low level. When the clock terminal CK provides a low level, the first transistor T1 turns on, the potential of the first node N1 goes low, and its potential is VGL-Vth. The first module 2 responds to the low level of the first node N1 by writing a high level to the second node N2. The second transistor T2 turns on, writing the low level provided by the first signal line L1 to the first node N1, pulling the potential of the first node N1 low. The second node N2 is pulled high again, and the first node N1 and the second node N2 are clamped together. The output module 3 responds to the high level of the second node N2 by outputting the low level provided by the low potential line VGL more completely to the output terminal OUT. When the clock terminal CK provides a high level, the first transistor T1 turns off, the first node N1 remains low, the second node N2 remains high, and the output module 3 maintains a low output level.

[0042] During the third time period t3, the input terminal IN is provided with a high level, and the clock terminal CK is provided with a high level. The first transistor T1 is cut off, the first node N1 remains low, the second node N2 remains high, and the output module 3 maintains a low output level.

[0043] During the fourth time period t4, the input terminal IN provides a high level. When the clock terminal CK provides a low level, the first transistor T1 turns on, outputting the high level provided by the input terminal IN to the first node N1. The first module 2 responds to the high level of the first node N1 by writing a low level to the second node N2. The second transistor T2 turns off, and the output module 3 responds to the low level of the second node N2 by outputting the high level provided by the high-potential line VGH to the output terminal OUT. When the clock terminal CK provides a high level, the first transistor T1 turns off, the first node N1 remains high, the second node N2 remains low, and the output module 3 maintains a high output level.

[0044] Combination Figure 4 and Figure 5 In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, taking the input terminal IN with a high potential of VGH and a low potential of VGL as an example: During the first time period t1, the input terminal IN provides a high level, and the clock terminal CK provides a low level. The first transistor T1 is turned off, the first node N1 remains low, the second node N2 remains high, and the output module 3 continues to write the low level provided by the low potential line VGL to the output terminal OUT.

[0045] During the second time period t2, the input terminal IN provides a high level. When the clock terminal CK provides a high level, the first transistor T1 turns on, and the potential of the first node N1 becomes high, with its potential being VGH-Vth. The first module 2 responds to the high level of the first node N1 by writing a low level to the second node N2. The second transistor T2 turns on, writing the high level provided by the first signal line L1 to the first node N1, raising the potential of the first node N1. The first module 2 then pulls the second node N2 back down to a low potential, clamping the first node N1 and the second node N2 together. The output module 3 responds to the low level of the second node N2 by outputting the high level provided by the high potential line VGH more completely to the output terminal OUT. When the clock terminal CK provides a low level, the first transistor T1 turns off, the first node N1 remains high, the second node N2 remains high, and the output module 3 maintains a high output level.

[0046] During the third time period t3, the input terminal IN is provided with a low level, and the clock terminal CK is provided with a low level. The first transistor T1 is turned off, the first node N1 remains at a high level, the second node N2 remains at a low level, and the output module 3 maintains a high output level.

[0047] During the fourth time period t4, the input terminal IN provides a low level. When the clock terminal CK provides a high level, the first transistor T1 turns on, outputting the low level provided by the input terminal IN to the first node N1. The first module 2 responds to the low level of the first node N1 by writing a high level to the second node N2. The second transistor T2 turns off, and the output module 3 responds to the high level of the second node N2 by outputting the low level provided by the low potential line VGL to the output terminal OUT. When the clock terminal CK provides a low level, the first transistor T1 turns off, the first node N1 remains low, the second node N2 remains high, and the output module 3 maintains a low output level.

[0048] In some implementations, see again Figure 2 The first level is low, and the second level is high. The first transistor T1 is a P-type transistor, the second transistor T2 is an N-type transistor, and the first signal line L1 is used to provide a low-level signal.

[0049] As previously analyzed, the P-type transistor is affected by the threshold voltage, and cannot fully write the low potential provided by the input terminal IN to the first node N1 when it is turned on. To address this, this embodiment of the invention configures an N-type second transistor T2, and based on internal node control, the second transistor T2 and the first transistor T1 are synchronously turned on. When the N-type transistor outputs a low potential, it is not affected by the threshold voltage and can fully output the low potential provided by the first signal line L1 to the first node N1, pulling the potential of the first node N1 low. This triggers the second node N2 to be pulled high again, forming a mutual clamping between the first node N1 and the second node N2. The internal node potential is written more fully, which helps to make the circuit output a more reliable low level. In this structure, each stage of shift register 1 only needs to correspond to one clock terminal CK, which can effectively reduce power consumption.

[0050] In some implementations, see again Figure 4 The first level is high, and the second level is low. The first transistor T1 is an N-type transistor, the second transistor T2 is a P-type transistor, and the first signal line L1 is used to provide a high-level signal.

[0051] As analyzed above, the N-type transistor is affected by the threshold voltage and cannot fully write the high potential provided by the input terminal IN to the first node N1 when it is turned on. To address this, this embodiment of the invention configures a P-type second transistor T2, and based on internal node control, the second transistor T2 and the first transistor T1 are turned on synchronously. When the P-type transistor outputs a high potential, it is not affected by the threshold voltage and can fully output the high potential provided by the first signal line L1 to the first node N1, raising the potential of the first node N1. This triggers the second node N2 to be pulled low again, forming a mutual clamping between the first node N1 and the second node N2. The internal node potential is written more fully, contributing to a more reliable high-level output. In this structure, each stage of shift register 1 only needs to correspond to one clock terminal CK, effectively reducing power consumption.

[0052] In some implementations, see again Figure 1 In two adjacent shift register stages 1, the output terminal OUT of the preceding shift register 1 can be connected to the input terminal IN of the following shift register 1. This means the output signal of the preceding shift register 1 is multiplexed as the input signal of the following shift register 1. At this time, the voltage value of the first level provided by the input terminal IN is equal to the voltage value of the first level provided by the first potential line VG1, and the voltage value of the second level provided by the input terminal IN is equal to the voltage value of the first level provided by the second potential line VG2.

[0053] In some implementations, see again Figure 2 and Figure 4 The first potential line VG1 is multiplexed as the first signal line L1.

[0054] See Figure 2 In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first signal line L1 is a low-potential line VGL. When the first transistor T1 is turned on and its input terminal IN provides a low potential VGL, the first transistor T1 can only pull the potential of the first node N1 to VGL-Vth, while the second transistor T2 can completely write the low potential VGL provided by the low-potential line VGL into the first node N1, causing the potential of the first node N1 to be pulled down to be equal to VGL.

[0055] Or, see Figure 4 In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the first signal line L1 is a high-potential line VGH. When the first transistor T1 is turned on and its input terminal IN provides a high potential VGH, the first transistor T1 can only pull the potential of the first node N1 to VGH-Vth, while the second transistor T2 can completely write the high potential VGH provided by the high-potential line VGH into the first node N1, raising the potential of the first node N1 to equal VGH.

[0056] In the above structure, the signal line connected to the second transistor T2 is multiplexed with the signal line connected to the output module 3. The second transistor T2 does not need to be configured with additional signal lines, and the connection and wiring of the shift register 1 is simpler.

[0057] In some implementations, the first voltage level provided by the first potential line VG1 is V1, the first voltage level provided by the first signal line L1 is V2, and |V2|>V1.

[0058] Understandably, when the first level is low, the voltage value of the first level is negative, and |V2| > V1 means that the low-level voltage value provided by the first signal line L1 is more negative. When the first level is high, the voltage value of the first level is positive, and |V2| > V1 means that the high-level voltage value provided by the first signal line L1 is higher.

[0059] Figure 6 This is another schematic diagram of the shift register provided in an embodiment of the present invention, as shown below. Figure 6 As shown, in an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor: the low potential LVGL(V2) provided by the first signal line L1 is lower than the low potential VGL(V1) provided by the low potential line VGL. When the first transistor T1 is turned on and the input terminal IN provides a low potential VGL, the second transistor T2 can pull the potential of the first node N1 to a more negative LVGL(V2), making the potential of the first node N1 even lower, thereby better triggering the first module 2 to write a high level to the second node N2.

[0060] Figure 7 This is another schematic diagram of a shift register provided in an embodiment of the present invention, as shown below. Figure 7 As shown, in an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor: the high potential HVGL (V2) provided by the first signal line L1 is greater than the high potential VGH (V1) provided by the high potential line VGH. When the first transistor T1 is turned on and its input terminal IN provides a high potential VGH, the second transistor T2 can raise the potential of the first node N1 to a higher HVGL (V2), making the potential of the first node N1 reach a higher level, thereby better triggering the first module 2 to write a low level to the second node N2.

[0061] In some implementations, see again Figure 2 and Figure 4 , or see again Figure 6 and Figure 7 The first module 2 is electrically connected to the first node N1, the first signal line L1, the second potential line VG2, and the second node N2, respectively. It is configured to write the second level provided by the second potential line VG2 into the second node N2 in response to the first level of the first node N1, and to write the first level of the first signal line L1 into the second node N2 in response to the second level of the first node N1.

[0062] The first module 2 may specifically include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 is a P-type transistor, and the sixth transistor T6 is an N-type transistor. The gates of both transistors are electrically connected to the first node N1, and the second terminals of both transistors are also electrically connected to the first node N1. In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first terminal of the fifth transistor T5 is electrically connected to the second potential line VG2, and the first terminal of the sixth transistor T6 is electrically connected to the first signal line L1. In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the first terminal of the fifth transistor T5 is electrically connected to the first signal line L1, and the first terminal of the sixth transistor T6 is electrically connected to the second potential line VG2.

[0063] Output module 3 may specifically include a seventh transistor T7 and an eighth transistor T8, where the seventh transistor T7 is a P-type transistor and the eighth transistor T8 is an N-type transistor. The gates of both the seventh transistor T7 and the eighth transistor T8 are electrically connected to the second node N2, and the second terminals of both are electrically connected to the output terminal OUT. In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first terminal of the seventh transistor T7 is electrically connected to the second potential line VG2, and the first terminal of the eighth transistor T8 is electrically connected to the first potential line VG1. In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the first terminal of the seventh transistor T7 is electrically connected to the first potential line VG1, and the first terminal of the eighth transistor T8 is electrically connected to the second potential line VG2.

[0064] In this structure, the first module 2 is connected to the signal lines required by the second transistor T2 and the output module 3. The first module 2 does not need to be configured with an additional constant voltage line, and the connection wiring of the shift register 1 is simpler.

[0065] In particular, when the voltage of the first level provided by the first potential line VG1 is V1, the voltage of the first level provided by the first signal line L1 is V2, and |V2| > V1: See Figure 6 In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor: the low potential LVGL (V2) provided by the first signal line L1 is lower than the low potential VGL (V1) provided by the low potential line VGL. The sixth transistor T6 is electrically connected to the first signal line L1 and can completely output LVGL to the second node N2 when it is turned on, pulling the potential of the second node N2 down to less than VGL. At this time, the gate-source voltage VGS of the N-type eighth transistor T8 is LVGL-VGL, which is much smaller than Vth. The eighth transistor T8 can be turned off more completely, avoiding leakage current between the seventh transistor T7 and the eighth transistor T8, making the signal output at the output terminal OUT more complete.

[0066] See Figure 7 In the architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor: the high potential HVGL (V2) provided by the first signal line L1 is greater than the high potential VGH (V1) provided by the high potential line VGH. The fifth transistor T5 is electrically connected to the first signal line L1 and can completely output HVGL to the second node N2 when it is turned on, raising the potential of the second node N2 to be greater than VGH. At this time, the gate-source voltage VGS of the P-type seventh transistor T7 is HVGL - VGH, which is much greater than Vth. The seventh transistor T7 can be turned off more completely, avoiding leakage current between the seventh transistor T7 and the eighth transistor T8, making the signal output at the output terminal OUT more complete.

[0067] In some implementations... Figure 8 This is another schematic diagram of the shift register circuit provided in an embodiment of the present invention. Figure 9 This is another schematic diagram of a shift register provided in an embodiment of the present invention. Figure 10 This is another schematic diagram of a shift register provided in an embodiment of the present invention, as shown below. Figures 8-10 As shown, the shift register 1 also includes a shift module 4. The shift module 4 is electrically connected to the second node N2, the second signal line L2, the second potential line VG2, and the shift terminal CR. It is configured to respond to the signal from the second node N2 by writing a first level provided by the second signal line L2 or a second level provided by the second potential line VG2 to the shift terminal CR, so that the shift terminal CR and the output terminal OUT have the same level at the same time. In another embodiment, the shift module 4 is configured to respond to the first level of the second node N2 by writing a second level provided by the second potential line VG2 to the shift terminal CR, and to respond to the second level of the second node N2 by writing a first level provided by the second signal line L2 to the shift terminal CR.

[0068] In two adjacent shift registers 1, the shift terminal CR of the previous shift register 1 is electrically connected to the input terminal IN of the next shift register 1.

[0069] The first voltage level provided by the first potential line VG1 is V1, and the first voltage level provided by the second signal line L2 is V3, where |V3|>V1.

[0070] Understandably, when the first level is low, its voltage value is negative, and |V3| > V1 means that the low-level voltage provided by the second signal line L2 is even more negative. When the first level is high, its voltage value is positive, and |V2| > V1 means that the high-level voltage provided by the second signal line L2 is even higher.

[0071] This structure has a separate shift module 4 configured in shift register 1. The signal output by the output terminal OUT of shift register 1 is only used as the driving signal of the pixel circuit. In two adjacent shift registers 1, the signal output by the shift terminal CR of the previous shift register 1 is used as the signal of the input terminal IN of the next shift register 1.

[0072] The shift module 4 specifically includes a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 is a P-type transistor, and the tenth transistor T10 is an N-type transistor. The gates of both the ninth and tenth transistors are electrically connected to the second node N2, and the second terminals of both transistors are electrically connected to the shift terminal CR. In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the first terminal of the ninth transistor T9 is electrically connected to the second potential line VG2, and the first terminal of the tenth transistor T10 is electrically connected to the second signal line L2. In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, the first terminal of the ninth transistor T9 is electrically connected to the second signal line L2, and the first terminal of the tenth transistor T10 is electrically connected to the second potential line VG2.

[0073] In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor: the low potential provided by the second signal line L2, LVGL' (V3), is lower than the low potential VGL (V1) provided by the low potential line VGL. When the tenth transistor T10 responds to the high level of the second node N2, it can completely output the more negative LVGL' (V3) to the shift terminal CR, serving as the low potential of the input terminal IN of the next-stage shift register 1. Thus, when the first transistor T1 is turned on in the next-stage shift register 1 and the input terminal IN provides the low potential LVGL' (V3), even if the first transistor T1 cannot completely output LVGL' (V3) to the first node N1, it can still make the potential of the first node N1 reach a lower level to some extent.

[0074] In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor: the high potential provided by the second signal line L2, HVGH' (V3), is greater than the high potential provided by the first potential line VG1, VGH (V1). When the ninth transistor T9 responds to the low level of the second node N2 and turns on, it can completely output the higher high potential HVGH' to the shift terminal CR, serving as the high potential of the input terminal IN of the next-stage shift register 1. Therefore, when the first transistor T1 is turned on in the next-stage shift register 1 and the input terminal IN provides the high potential HVGH', even if the first transistor T1 cannot completely output the high potential HVGH' to the first node N1, it can still make the potential of the first node N1 reach a higher level to a certain extent.

[0075] Furthermore, the first signal line L1 provides a first-level voltage of V2, |V2|>V1, and V3=V2. That is, the second signal line L2 provides the same first-level voltage as the first signal line L1, and the first signal line L1 can be reused as the second signal line L2, simplifying the wiring design.

[0076] In some implementations... Figure 11 This is another schematic diagram of a shift register provided in an embodiment of the present invention. Figure 12 This is another schematic diagram of a shift register provided in an embodiment of the present invention, as shown below. Figure 11 and Figure 12 As shown, a third transistor T3 is connected in series between the second transistor T2 and the first signal line L1. The third transistor T3 is also electrically connected to the second node N2 and is configured to conduct in response to a second level of the second node N2, writing the first level provided by the first signal line L1 into the second transistor T2. That is, the third transistor T3 and the second transistor T2 are transistors of the same type.

[0077] There is a third node N3 between the second transistor T2 and the third transistor T3.

[0078] The shift register 1 also includes a second module 5, which is electrically connected to the first node N1, the second potential line VG2 and the third node N3 respectively, and is configured to respond to the second level of the first node N1 by writing the second level provided by the second potential line VG2 into the third node N3.

[0079] The second module 5 may specifically include a fourth transistor T4, which is the same type of transistor as the second transistor T2. The gate of the fourth transistor T4 is electrically connected to the first node N1, the first terminal is electrically connected to the second potential line VG2, and the second terminal is electrically connected to the third node N3.

[0080] See Figure 11 In an architecture where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor: When the first transistor T1 is turned on and its input terminal IN provides a low level, the first module 2 writes a high level to the second node N2. The third transistor T3 and the second transistor T2 are simultaneously turned on. Since both the third transistor T3 and the second transistor T2 are N-type transistors, their low-level outputs are not affected by the threshold voltage, thus allowing the low potential provided by the first signal line L1 to be completely written to the first node N1. When the first transistor T1 is turned on and its input terminal IN provides a high level, the first module 2 writes a low level to the second node N2, the second transistor T2 is turned off, and the third transistor T3 responds to the high level of the first node N1 and turns on, writing the high level provided by the high-potential line VGH to the third node N3. This ensures that the gate-source voltage VGS of the second transistor T2 is less than Vth and is completely turned off, preventing leakage between the first node N1 and the second node N2 due to the negative drift of the second transistor T2, and keeping the potentials of the first node N1 and the second node N2 intact.

[0081] Or see Figure 12In an architecture where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor: When the first transistor T1 is turned on and its input terminal IN provides a high level, the first module 2 writes a low level to the second node N2. The third transistor T3 and the second transistor T2 are simultaneously turned on. Since both the third transistor T3 and the second transistor T2 are P-type transistors, their high output levels are not affected by the threshold voltage, thus allowing the high level provided by the first signal line L1 to be completely written to the first node N1. When the first transistor T1 is turned on and its input terminal IN provides a low level, the first module 2 writes a high level to the second node N2, the second transistor T2 is turned off, and the third transistor T3 responds to the low level of the first node N1 and turns on, writing the low level provided by the low potential line VGL to the third node N3. This ensures that the gate-source voltage VGS of the second transistor T2 is greater than Vth and is completely turned off, preventing leakage between the first node N1 and the second node N2 due to positive drift of the second transistor T2, and keeping the potentials of the first node N1 and the second node N2 intact.

[0082] Based on the same concept, embodiments of the present invention also provide a display panel. Figure 13 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 13 As shown, the display panel includes a pixel circuit 100 and the aforementioned shift register circuit 200, with the shift register 1 in the shift register circuit 200 electrically connected to the pixel circuit 100.

[0083] The pixel circuit 100 includes a driving module, a gate reset module, an anode reset module, and a data writing module. The gate reset module performs a gate reset operation on the driving module, the anode reset module performs a reset operation on the anode of the light-emitting element, and the data writing module performs a charging operation. The shift register 1 can be electrically connected to the gate reset module, the anode reset module, or the data writing module.

[0084] The following is a schematic illustration using one circuit structure as an example: Figure 14 A schematic diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 14 As shown, the pixel circuit includes: The driving transistor 101 has its gate electrically connected to node O1, its first electrode electrically connected to node O2, and its second electrode electrically connected to node O3.

[0085] The gate reset transistor 102 has its gate electrically connected to the first scan line G1, its first electrode electrically connected to the first reset line Ref1, and its second electrode electrically connected to node O1.

[0086] The data writing transistor 103 has its gate electrically connected to the second scan line G2, its first electrode electrically connected to the data line Data, and its second electrode electrically connected to node O1.

[0087] The light-emitting control transistor 104 has its gate electrically connected to the light-emitting control line EM, its first electrode electrically connected to the first power supply line ELVDD, and its second electrode electrically connected to node O2.

[0088] The anode reset transistor 105 has its gate electrically connected to the third scan line G3, its first electrode electrically connected to the second reset line Ref2, and its second electrode electrically connected to node O3. Node O3 is electrically connected to the anode of the light-emitting element 300, and the cathode of the light-emitting element 300 is electrically connected to the second power supply line ELVSS.

[0089] The first capacitor C1 is electrically connected between node O1 and node O3.

[0090] The second capacitor C2 is electrically connected between node O3 and the cathode of the light-emitting element 300.

[0091] All of the aforementioned transistors can be N-type transistors. Shift register 1 can be electrically connected to the first scan line G1, the second scan line G2, or the third scan line G3.

[0092] Based on the same concept, embodiments of the present invention also provide a display device. Figure 15 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 15 As shown, the display device includes the aforementioned display panel 1000. Of course, Figure 15 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0094] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shift register circuit, characterized in that, This includes multiple cascaded shift registers, wherein the shift registers include: The first transistor is electrically connected to the clock terminal, the input terminal, and the first node, and is configured to turn on in response to a first level provided by the clock terminal, and to write the signal from the input terminal into the first node. The first module is configured to respond to a signal from the first node by writing either the first level or the second level to the second node, such that the level states of the second node and the first node are opposite at the same time, wherein the level states of the second level and the first level are opposite. The second transistor, which is electrically connected to the second node, the first signal line and the first node respectively, is configured to turn on in response to the second level of the second node and write the first level provided by the first signal line into the first node; The output module is electrically connected to the second node, the first potential line, the second potential line, and the output terminal, respectively. It is configured to write the first level provided by the first potential line to the output terminal in response to the second level of the second node, and to write the second level provided by the second potential line to the output terminal in response to the first level of the second node.

2. The shift register circuit according to claim 1, characterized in that, The operation of the shift register includes a first time period, a second time period, a third time period, and a fourth time period; During the first time period, the input terminal provides the first level, the clock terminal provides the second level, the first transistor is turned off, the first node maintains the second level, the second node maintains the first level, and the output module writes the second level provided by the second potential line to the output terminal; During the second time period, the input terminal provides the first level, and during at least a portion of the time period, the clock terminal provides the first level. The first transistor is turned on, and the first level provided by the input terminal is written to the first node. The first module writes the second level to the second node, and the second transistor is turned on, and the first level provided by the first signal line is written to the first node. The output module writes the first level provided by the first potential line to the output terminal. During the third time period, the input terminal provides the second level, the clock terminal provides the second level, the first transistor is turned off, the first node maintains the first level, the second node maintains the second level, and the output module writes the first level provided by the first potential line to the output terminal. During the fourth time period, the input terminal provides the second level, and for at least a portion of the time period, the clock terminal provides the first level. The first transistor is turned on, and the second level provided by the input terminal is written to the first node. The first module writes the first level to the second node, the second transistor is turned off, and the output module writes the second level provided by the second potential line to the output terminal.

3. The shift register circuit according to claim 1, characterized in that, The first level is a low level, and the second level is a high level; The first transistor is a P-type transistor, the second transistor is an N-type transistor, and the first signal line is used to provide a low-level signal.

4. The shift register circuit according to claim 1, characterized in that, The first level is a high level, and the second level is a low level; The first transistor is an N-type transistor, the second transistor is a P-type transistor, and the first signal line is used to provide a high-level signal.

5. The shift register circuit according to claim 1, characterized in that, The first potential line is multiplexed as the first signal line.

6. The shift register circuit according to claim 1, characterized in that, The voltage of the first level provided by the first potential line is V1, and the voltage of the first level provided by the first signal line is V2, where |V2|>V1.

7. The shift register circuit according to claim 1, characterized in that, The first module is electrically connected to the first node, the first signal line, the second potential line, and the second node, respectively, and is configured to write the second level provided by the second potential line to the second node in response to the first level of the first node, and to write the first level of the first signal line to the second node in response to the second level of the first node.

8. The shift register circuit according to claim 1, characterized in that, The shift register further includes a shift module, which is electrically connected to the second node, the second signal line, the second potential line, and the shift terminal, respectively. The shift module is configured to respond to the signal of the second node by writing the first level provided by the second signal line or the second level provided by the second potential line into the shift terminal, so that the shift terminal and the output terminal have the same level at the same time. In two adjacent shift registers, the shift terminal of the previous shift register is electrically connected to the input terminal of the next shift register. The voltage of the first level provided by the first potential line is V1, and the voltage of the first level provided by the second signal line is V3, where |V3|>V1.

9. The shift register circuit according to claim 8, characterized in that, The voltage of the first level provided by the first signal line is V2, |V2|>V1, and V3=V2.

10. The shift register circuit according to claim 1, characterized in that, A third transistor is connected in series between the second transistor and the first signal line. The third transistor is also electrically connected to the second node and is configured to turn on in response to the second level of the second node, writing the first level provided by the first signal line into the second transistor. A third node is present between the second transistor and the third transistor; The shift register further includes a second module, which is electrically connected to the first node, the second potential line, and the third node, and is configured to write the second level provided by the second potential line to the third node in response to the second level of the first node.

11. A display panel, characterized in that, include: Pixel circuit; The shift register circuit according to any one of claims 1 to 10, wherein the shift register in the shift register circuit is electrically connected to the pixel circuit.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

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