Display device and driving method thereof

Abstract

Disclosed are a display device and a driving method thereof, the display device including a display panel on which pixels are disposed, a data driver integrated circuit including output buffers connected to output channels and configured to output data voltages to the pixels through data lines, and a multiplexer connected between the output channels and the data lines and including switching elements controlled by a multiplexing control signal.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0049646, filed on April 16, 2025, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0002] This disclosure relates to a display device and a driving method thereof. Background Technology

[0003] With the development of an information-oriented society, the demand for display devices for displaying images has increased, and various types of display devices, such as liquid crystal displays (LCDs), plasma display panels (PDPs), and organic light-emitting diodes (OLEDs), have been used.

[0004] Typical display devices do not restrict viewing angles. However, due to privacy and information protection reasons, it has recently become necessary to restrict the viewing angle of display devices. For example, when a display device is used as an information medium inside a vehicle to provide high-definition images to passengers in the front passenger seat, the viewing angle needs to be limited to the driver for driving safety. Summary of the Invention

[0005] Embodiments of this disclosure provide a display device and its driving method capable of displaying private images and shared images respectively in multiple areas on a display panel.

[0006] Embodiments of this disclosure provide a display device and a driving method thereof, wherein the display device provides virtual data voltage to some sub-pixels according to a privacy mode or a sharing mode and disables an output buffer or a data driver integrated circuit connected to the sub-pixels providing the virtual data voltage.

[0007] Embodiments of this disclosure provide a display device and a driving method thereof including a data driver integrated circuit, wherein the output channel of the data driver integrated circuit is connected to a ground voltage.

[0008] Embodiments of this disclosure provide a display device and a driving method thereof. The display device includes a multiplexer with a virtual switching element configured to connect virtual voltage lines and data lines to each other in response to a virtual multiplexing control signal. One embodiment is a display device comprising: a display panel having pixels disposed thereon; a data driver integrated circuit including an output buffer connected to an output channel and configured to output data voltages to the pixels via data lines; and a multiplexer connected between the output channel and the data lines and including a switching element controlled by a multiplexing control signal.

[0009] A pixel may include: a first sub-pixel connected to a first data line; and a second sub-pixel connected to a second data line and displaying the same color as the first sub-pixel.

[0010] The data driver integrated circuit can be configured to: when the pixel operates in a first mode, output a first data voltage corresponding to the first image to a first sub-pixel and output a virtual data voltage to a second sub-pixel; and when the pixel operates in a second mode, output a virtual data voltage to the first sub-pixel and output a second data voltage corresponding to the second image to the second sub-pixel.

[0011] The output channel can also be connected to ground voltage.

[0012] The output channel can be configured such that when the pixel operates in the first mode, a first data voltage output from the output buffer is output to the first sub-pixel and a ground voltage is output to the second sub-pixel, and when the pixel operates in the second mode, a ground voltage is output to the first sub-pixel and a second data voltage output from the output buffer is output to the second sub-pixel.

[0013] The output buffer can be enabled based on a source output enable signal at the on level input from an external device, and the source output enable signal can be applied at the off level while the ground voltage is output from the output channel.

[0014] The multiplexer may include: a first switching element configured to be turned on according to a first multiplexing control signal and to connect an output channel to a first sub-pixel; a second switching element configured to be turned on according to a second multiplexing control signal and to connect an output channel to a second sub-pixel; a first virtual switching element configured to be turned on according to a first virtual multiplexing control signal and to connect a virtual voltage line receiving a virtual data voltage and a first data line to each other; and a second virtual switching element configured to be turned on according to a second virtual multiplexing control signal and to connect the virtual voltage line and the second data line to each other.

[0015] Virtual data voltage can be a voltage corresponding to black grayscale.

[0016] When the pixel operates in the first mode, a second virtual multiplexing control signal at the on level can be applied, and when the pixel operates in the second mode, a first virtual multiplexing control signal at the on level can be applied.

[0017] The data driver integrated circuit can be enabled based on a data driver enable signal input from an external device, and a data driver enable signal at the off level can be applied in response to a first virtual multiplexing control signal at the on level or a second virtual multiplexing control signal at the on level.

[0018] The display panel may include: a first unit pixel and a second unit pixel, each of the first unit pixel and the second unit pixel comprising two or more pixels.

[0019] The multiplexer may include: a first switching element configured to be turned on according to a (1-1) multiplexing control signal and to connect an output channel to a first sub-pixel of a first unit pixel; a second switching element configured to be turned on according to a (2-1) multiplexing control signal and to connect an output channel to a second sub-pixel of the first unit pixel; a third switching element configured to be turned on according to a (1-2) multiplexing control signal and to connect an output channel to a first sub-pixel of a second unit pixel; and a fourth switching element configured to be turned on according to a (2-2) multiplexing control signal and to connect an output channel to a second sub-pixel of a second unit pixel.

[0020] The display panel may include: a first region, wherein a first image is displayed via a first subpixel; and a second region, wherein a second image different from the first image is displayed via a second subpixel, and the first and second regions may be variable when the display panel is driven.

[0021] The first sub-pixel and the second sub-pixel can have the same pixel structure, and the first sub-pixel and the second sub-pixel can have a mirror shape along the pixel column direction.

[0022] The display device may also include a lens component disposed on the display panel and comprising a plurality of lenses.

[0023] The lens component may include: a first lens disposed in a first light-emitting region of a first sub-pixel; and a second lens disposed in a second light-emitting region of a second sub-pixel and having a shape different from that of the first lens.

[0024] The first lens can be configured to control the emission of light emitted from the first light-emitting region at a first viewing angle, and the second lens can be configured to control the emission of light emitted from the second light-emitting region at a second viewing angle that is wider than the first viewing angle.

[0025] Another embodiment is a method for driving a display device, comprising: outputting a data voltage to a first sub-pixel by a data driver integrated circuit during a first time period within a horizontal time period; and outputting a data voltage to a second sub-pixel by the data driver integrated circuit during a second time period within a horizontal time period.

[0026] When the pixel operates in the first mode, outputting a data voltage to the first sub-pixel may include: outputting a first data voltage from the output buffer to the output channel, and when the pixel operates in the first mode, outputting a data voltage to the second sub-pixel may include: outputting a ground voltage to the output channel.

[0027] When the pixel operates in the second mode, outputting a data voltage to the first sub-pixel may include: outputting a ground voltage to the output channel, and when the pixel operates in the second mode, outputting a data voltage to the second sub-pixel may include: outputting a second data voltage from the output buffer to the output channel.

[0028] Outputting the data voltage to the first sub-pixel may further include enabling the output buffer in response to a source output enable signal at an on level, and outputting the data voltage to the second sub-pixel may further include disabling the output buffer in response to a source output enable signal at an off level.

[0029] When the pixel operates in the first mode, outputting a data voltage to the first sub-pixel may include: in response to a first multiplexing control signal at an on level, connecting an output buffer to a first data line via a multiplexer; and when the pixel operates in the first mode, outputting a data voltage to the second sub-pixel may include: in response to a second virtual multiplexing control signal at an on level, connecting a virtual voltage line to a second data line via a multiplexer.

[0030] When the pixel operates in the second mode, outputting a data voltage to the first sub-pixel may include: in response to a first virtual multiplexing control signal at an on level, connecting a virtual voltage line to a first data line via a multiplexer; and when the pixel operates in the second mode, outputting a data voltage to the second sub-pixel may include: in response to a second multiplexing control signal at an on level, connecting an output buffer to a second data line via a multiplexer.

[0031] Outputting the data voltage to the first sub-pixel may further include: enabling the data driver integrated circuit in response to a data driver enable signal at an on level, and outputting the data voltage to the second sub-pixel may further include: disabling the data driver integrated circuit in response to a data driver enable signal at an off level.

[0032] The display device and its driving method according to the embodiments can freely and easily change the size and shape of the area displaying private images and shared images.

[0033] The display device and driving method according to the embodiments can reduce the power consumption and latency degradation of the components by disabling the data driver integrated circuit or output buffer when providing virtual data voltage to the sub-pixel.

[0034] The display device and driving method according to the embodiments can reduce the number of data driver integrated circuits and lines, and achieve a thinner and smaller display device by connecting an output channel to multiple pixel units via a multiplexer.

[0035] The display device and its driving method according to the embodiments can effectively implement privacy mode and sharing mode in various usage environments. Attached Figure Description

[0036] Figure 1 This is a block diagram of a display device according to an embodiment.

[0037] Figure 2 This is a block diagram illustrating the configuration of a data driver integrated circuit according to an embodiment.

[0038] Figure 3 This is a diagram illustrating a method for driving a display panel according to an embodiment.

[0039] Figure 4 This is a diagram illustrating the configuration of pixels according to an embodiment.

[0040] Figure 5 This is an example showing an image displayed in the display panel.

[0041] Figure 6 This is a diagram illustrating the connection relationship between the pixels and the data driver integrated circuit according to the first embodiment.

[0042] Figure 7 Is applied to Figure 6 The waveform diagram of the control and drive signals of the display device.

[0043] Figure 8 This is a diagram illustrating the connection relationship between the pixels and the data driver integrated circuit according to the second embodiment.

[0044] Figure 9 Is applied to Figure 8 The waveform diagram of the control and drive signals of the display device.

[0045] Figure 10 This is a diagram illustrating the connection relationship between the pixels and the data driver integrated circuit according to the third embodiment.

[0046] Figure 11 Is applied to Figure 10 The waveform diagram of the control and drive signals of the display device.

[0047] Figure 12 This is a circuit diagram of the pixel according to an embodiment.

[0048] Figure 13 It is shown Figure 12 The diagram shows a planar layout of the pixels.

[0049] Figure 14 This is a plan view showing a unit pixel according to an embodiment.

[0050] Figure 15 It is shown schematically. Figure 14 The view shown is of the first lens.

[0051] Figure 16 It shows relative to Figure 15 A view of the optical profile of the first lens from its angle of view.

[0052] Figure 17 It is shown schematically. Figure 14 The view of the second lens shown.

[0053] Figure 18 It shows relative to Figure 17 A view showing the optical profile of the second lens from its angle of view.

[0054] Figure 19 This is a schematic cross-sectional view of the display area of ​​the display panel according to an embodiment.

[0055] Figure 20 This is a view showing an example of a display device according to an embodiment. Detailed Implementation

[0056] In the following description, embodiments will be described with reference to the accompanying drawings. In this specification, when a component (or region, layer, portion, etc.) is referred to as "on another component," "connected to another component," or "combined to another component," the component may be directly on, connected to, or combined to another component, or a third component may be present therein.

[0057] The same reference numerals always refer to the same elements. Additionally, in the drawings, the thickness, scale, and dimensions of parts may be exaggerated for ease of description and clarity. The term "and / or" includes any and all combinations of one or more associated listed items.

[0058] It should be understood that when the terms “first” and “second” are used herein to describe various components, those components should not be limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component without departing from the scope of this disclosure, and vice versa. Unless the context clearly indicates otherwise, the singular expressions and terms used herein also cover or include plural expressions and terms.

[0059] Furthermore, terms such as “below,” “lower side,” “upper,” and “upper side” are used to describe the relationships of the configurations shown in the accompanying drawings. These terms are described as relative concepts based on the directions shown in the figures.

[0060] In various embodiments of this disclosure, the terms "comprising" or "including" may refer to an attribute, a fixed quantity, a step, a process, a component, or a combination thereof, but do not exclude other attributes, fixed quantities, steps, processes, components, or combinations thereof.

[0061] Figure 1 This is a block diagram of a display device according to an embodiment.

[0062] refer to Figure 1 The display device 1 includes a timing controller 10, a gate driver 20, a data driver 30, a multiplexer 31 (or demultiplexer), a power supply unit 40, and a display panel 50.

[0063] The timing controller 10 can receive image signals RGB and control signals CS from an external host system, etc. The image signal RGB may include multiple grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0064] The timing controller 10 processes the image signal RGB and the control signal CS to suit the operating conditions of the display panel 50, and can generate and output image data DATA, gate drive control signal CONT1, transmit drive control signal CONT2, data drive control signal CONT3 and power control signal CONT4.

[0065] Gate driver 20 may include scan driver 20A, which is configured to generate scan signals based on gate drive control signal CONT1 input from timing controller 10. Scan driver 20A can provide the generated scan signals to pixel PX via multiple scan lines GL. In an embodiment, a pixel PX can be configured to receive multiple scan signals with different waveforms. In such an embodiment, scan driver 20A can provide multiple scan signals to pixel PX in its corresponding pixel row via scan lines GL.

[0066] The gate driver 20 may further include a light-emitting driver 20B, which is configured to generate a light-emitting control signal based on an emission drive control signal CONT2 input from the timing controller 10. The light-emitting driver 20B can provide the generated light-emitting control signal to the pixel PX of its corresponding pixel row via the light-emitting line EL.

[0067] The gate driver 20 can be configured to be mounted as a gate-in-panel on the display panel 50. As shown, the gate driver 20 can be disposed on one side of the display panel 50, or on both sides of the display panel 50 (e.g., left and right). Depending on the driving method, panel design, etc., the gate driver 20 can be disposed on both sides of the display panel 50 (e.g., left and right), or it can be connected to two or more of the four side surfaces of the display panel 50.

[0068] The data driver 30 can generate a data signal based on the data drive control signal CONT3 output from the timing controller 10 and the image data DATA. The data driver 30 can provide the generated data signal to the pixel PX through multiple data lines DL.

[0069] Data driver 30 may include multiple data driver integrated circuits DIC1, DIC2, and DIC3. Each of the data driver integrated circuits DIC1, DIC2, and DIC3 can be connected to two or more data lines DL via a multiplexer 31, which will be described below. For example, when the total number of data lines DL is m, each of the data driver integrated circuits DIC1, DIC2, and DIC3 can be sequentially connected to m / 3 of the data lines DL. Such data driver integrated circuits DIC1, DIC2, and DIC3 can be partially or fully enabled based on a data driver enable signal SD applied from the timing controller 10. Figure 1 The example shown is a data driver 30 including three data driver integrated circuits DIC1, DIC2 and DIC3; however, the number is not limited to this and more or fewer data driver integrated circuits DIC1, DIC2 and DIC3 may be provided.

[0070] In an embodiment, the display device 1 may include a multiplexer 31 connected between the data driver 30 and the pixel PX and configured to time-division drive the data lines DL. The multiplexer 31 connects each output channel of the data driver integrated circuits DIC1, DIC2, and DIC3 to two or more data lines DL. Furthermore, the multiplexer 31 can reduce the number of output channels of the data driver integrated circuits DIC1, DIC2, and DIC3 by time-divisionally distributing the data voltages output from the output channels of the data driver integrated circuits DIC1, DIC2, and DIC3 to the data lines DL.

[0071] In an embodiment, multiplexer 31 may include multiple switching elements connected between the output channels of data driver integrated circuits DIC1, DIC2, and DIC3 and the data lines DL. For example, multiplexer 31 may be a 1:n multiplexer, in which one output channel is connected to i (where i is an integer greater than 1) data lines DL via a switching element.

[0072] The power supply unit 40 can generate a high-level driving voltage VDD and a low-level driving voltage VSS based on the power control signal CONT4 to supply to the display panel 50. The power supply unit 40 can provide the generated driving voltages VDD and VSS to the pixel PX through the corresponding voltage lines PL1 and PL2. In addition, the power supply unit 40 can also generate a reference voltage Vref required to drive the pixel PX and provide it to the pixel PX through the corresponding voltage line VrefL.

[0073] Multiple pixels PX (or subpixels) can be disposed on the display panel 50. Pixels PX can be disposed on the display panel 50, for example, in a matrix configuration. Pixels PX disposed in a pixel row are connected to the same scan line GL and light emission line EL, and pixels PX disposed in a pixel column are connected to the same data line DL. Pixels PX can emit light with a brightness corresponding to the data signal and scan signal provided by the scan line GL and data line DL in response to an emission control signal applied through the light emission line EL.

[0074] In one embodiment, each pixel PX can display one of the colors red, green, and blue. In another embodiment, each pixel PX can display one of the colors cyan, magenta, and yellow. In various embodiments, each pixel PX can display one of the colors red, green, blue, and white.

[0075] Figure 2 This is a block diagram illustrating the configuration of a data driver integrated circuit according to an embodiment.

[0076] refer to Figure 2 The data driver integrated circuit (DIC) may include a register unit 36, a latch unit 32, a digital-to-analog converter (DAC) 33, and an output buffer 34.

[0077] Register unit 36 ​​uses the timing controller 10 ( Figure 1 The received data drives the control signal CONT3 to generate a sampling signal, and provides the generated sampling signal to the latch unit 32.

[0078] The latch unit 32 latches the image data DATA received from the timing controller 10 and outputs the image data DATA to the DAC 33 in response to the sampling signal received from the register unit 36.

[0079] DAC 33 can convert the image data DATA received from latch unit 32 into a gamma-compensated voltage to generate a data voltage.

[0080] The output buffer 34 outputs the data voltage from the DAC 33 to the data line DL through the output channel CH according to the source output enable signal SOE received from the timing controller 10.

[0081] In this embodiment, the data driver integrated circuit (DIC) may further include a power management circuit 35. The power management circuit 35 may generate a bias current Ibias based on a power control signal PWRC received from the timing controller 10 and apply the bias current Ibias to the output buffer 34. The power management circuit 35 can control the magnitude of the data voltage output from the data driver integrated circuit (DIC) and manage the power consumption of the data driver integrated circuit (DIC) by changing the magnitude of the bias current Ibias according to a pattern indicated by the power control signal PWRC.

[0082] Meanwhile, the data driver integrated circuit (DIC) may include at least one or more output buffers 34. Each output buffer 34 can be connected to a corresponding data line DL via a corresponding output channel CH. In such an embodiment, the power consumption of the data driver integrated circuit (DIC) can correspond to the sum of the power consumption of each output buffer 34.

[0083] Figure 3 This is a diagram illustrating a method for driving a display panel according to an embodiment.

[0084] refer to Figure 3 The display panel 50 may include a display area AA for displaying an image and a non-display area NA surrounding the display area AA. The display area AA may have a generally rectangular shape as shown in the figure, but is not limited thereto, and may be adapted to the display device 1. Figure 1 The type of area is formed as a polygon, circle, ellipse or polygon shape, with at least one edge formed as a curve, etc. The non-display area NA can be set to surround the display area AA, and can be formed to follow the shape of the display area AA or have an independent shape.

[0085] The display area AA can be divided into a first area A1 and a second area A2. The second area A2 is, for example, the area where a second image is displayed, and can be driven to display a shared image visible to all viewers. Here, viewers can be, for example, the driver and a fellow passenger, and in this case, the second area A2 may include, but is not limited to, the area adjacent to the driver's seat.

[0086] For example, a first area A1 is an area that displays a first image that is different from the second image, and can be driven to display a private image that is visible only to a certain viewer. Here, the viewer may be, for example, a fellow passenger, and in this case, the first area A1 may include, but is not limited to, the area of ​​the seat arrangement adjacent to the passenger in front.

[0087] The display panel 50 can be controlled so that the first area A1 operates in a first mode and the second area A2 operates in a second mode. For example, the second area A2 can operate in the second mode with a wider viewing angle than the first area A1, and the first area A1 can operate in the first mode with a narrower viewing angle than the second area A2.

[0088] In other words, the second area A2 can operate in a second mode, where the viewpoint is expanded so that the image is visible to other viewers or all viewers, i.e., a shared mode, and the first area A1 can operate in a first mode, where the viewpoint is restricted so that the image is visible only to a certain viewer (e.g., the driver), i.e., a privacy mode.

[0089] The position, size, and shape of the first area A1 and the second area A2 are not limited. In an embodiment, the position, size, and shape of the first area A1 and the second area A2 can change during operation of the display panel 50. For example, when the vehicle is in motion, the area adjacent to the front passenger seat can be assigned as the first area A1 and can be configured to operate in a privacy mode that restricts viewing of the driver, and when the vehicle is not in motion, the area adjacent to the front passenger seat can be assigned as the second area A2 and can be configured to operate in a shared mode that allows viewing of the driver. In this case, when the vehicle is not in motion, the second area A2 can become the entire area of ​​the display panel 50.

[0090] Meanwhile, in the illustrated embodiment, the area of ​​the second region A2 may be smaller than the area of ​​the first region A1. However, the embodiment is not limited to this.

[0091] Figure 4 This is a diagram illustrating the configuration of pixels according to an embodiment.

[0092] refer to Figure 4 According to the embodiment, pixel PX is configured to include a plurality of sub-pixels SP1 and SP2. For example, pixel PX may be configured to include a first sub-pixel SP1 and a second sub-pixel SP2.

[0093] Each of sub-pixels SP1 and SP2 may include control circuitry CC for controlling a light-emitting diode (LED) LD and the amount of drive current to be applied to the LED LD. Control circuitry CC may include at least one transistor and a capacitor.

[0094] The control circuits CC of sub-pixels SP1 and SP2 that constitute a pixel PX can be configured with the same or different circuits. For example, the control circuits CC of sub-pixels SP1 and SP2 can have the same circuit structure and can be set to have a mirror shape, but are not limited to this.

[0095] A light-emitting diode (LED) can display one of the colors red, green, and blue. In another embodiment, the LED can display one of the colors cyan, magenta, and yellow. In yet another embodiment, the LED can display one of the colors red, green, blue, and white.

[0096] The light-emitting diodes (LDs) that make up sub-pixels SP1 and SP2 of a pixel PX can display the same color. For example, the LDs of sub-pixels SP1 and SP2 included in a red pixel PX can display red, the LDs of sub-pixels SP1 and SP2 included in a green pixel PX can display green, and the LDs of sub-pixels SP1 and SP2 included in a blue pixel PX can display blue.

[0097] Three pixels PX displaying red, green, and blue respectively can form a single pixel unit. However, this embodiment is not limited to this. As described above, when pixel PX displays cyan, magenta, and yellow, three pixels PX displaying cyan, magenta, and yellow respectively can form a single pixel unit. Alternatively, when pixel PX displays red, green, blue, and white, four pixels PX displaying red, green, blue, and white respectively can form a single pixel unit. Alternatively, two or more pixels PX displaying the same color can be included in a single pixel unit.

[0098] In an embodiment, subpixels SP1 and SP2 included in a pixel PX can be driven to display different images. For example, the first subpixel SP1 can display a reference. Figure 3 The first image described is a privacy image, and the second sub-pixel SP2 can be used to display a reference. Figure 3 The second image (shared image) is described. When pixel PX is assigned to the first region A1 and driven in the first mode, the first sub-pixel SP1 can be driven to display the first image, and when pixel PX is assigned to the second region A2 and driven in the second mode, the second sub-pixel SP2 can be driven to display the second image.

[0099] Simultaneously, when pixel PX is driven in the first mode, the second sub-pixel SP2 can be driven to display a predetermined virtual image. The virtual image can be, for example, a black and white image, but is not limited to this. Conversely, when pixel PX is driven in the second mode, the first sub-pixel SP1 can be driven to display a predetermined virtual image.

[0100] As described above, the position, size, and shape of the first region A1 and the second region A2 can be varied. That is, when the display device 1 ( Figure 1 When driven, pixel PX can operate in a first mode during a first time period and in a second mode during a second time period. In this embodiment, during the first time period, the first sub-pixel SP1 can display a first image, and the second sub-pixel SP2 can display a virtual image. Furthermore, during the second time period, the second sub-pixel SP2 can display a second image, while the first sub-pixel SP1 can display a virtual image.

[0101] Figure 5 This is an example showing an image displayed in the display panel. More specifically, Figure 5 The left side of the image shows the first sub-pixel SP1, which is configured to display a privacy image. Figure 4 The image shown in ). Figure 5 The right side of the image shows the second sub-pixel SP2, which is configured to display a shared image. Figure 4 The image shown in ). Figure 5 The lower side of the image shows the entire image displayed in the display area AA through the first sub-pixel SP1 and the second sub-pixel SP2.

[0102] The display area AA can be divided into a first area A1 and a second area A2. The first area A1 is the area where a first image, intended as a private image, is displayed, and the second area A2 is the area where a second image, intended as a shared image, is displayed. In the illustrated embodiment, the second area A2 is located in area B, which is driven by the first data driver integrated circuit DIC1.

[0103] The first sub-pixel SP1, located in the first region A1, can display a privacy image in various shades of gray, and the first sub-pixel SP1, located in the second region A2, can display a predetermined virtual image, such as a black image. Conversely, the second sub-pixel, located in the first region A1, can display a black image, and the second sub-pixel SP2, located in the second region A2, can display a shared image in various shades of gray.

[0104] As shown in the figure, when the area of ​​the second region A2 is set to a small value, only some second sub-pixels SP2 display various grayscale levels, and most second sub-pixels SP2 display virtual images. In such an embodiment, when all data driver integrated circuits DIC1, DIC2, and DIC3 are enabled for the second sub-pixels SP2 and configured to output data voltage, unnecessary power consumption may occur, and the degradation of data driver integrated circuits DIC1, DIC2, and DIC3 may be accelerated.

[0105] Figure 6This is a diagram illustrating the connection relationship between the pixels and the data driver integrated circuit according to the first embodiment.

[0106] refer to Figure 6 The data driver integrated circuit (DIC) may include multiple output channels CH1, CH2, and CH3, respectively connected to multiple output buffers 341, 342, and 343. Each of the output channels CH1, CH2, and CH3 may output a data voltage applied from the output buffers 341, 342, and 343 connected thereto.

[0107] In this embodiment, each output channel CH1, CH2, and CH3 may be further connected to the ground voltage GND. In this embodiment, when the data voltage is not output from the plurality of output buffers 341, 342, and 343, the output channels CH1, CH2, and CH3 may be further controlled to output the ground voltage GND.

[0108] Each of the output channels CH1, CH2, and CH3 can be connected to a corresponding pixel PX1, PX2, and PX3 via multiplexer 31. For example, the first output channel CH1 can be connected to the first pixel PX1, the second output channel CH2 can be connected to the second pixel PX2, and the third output channel CH3 can be connected to the third pixel PX3.

[0109] The multiplexer 31 includes multiple switching elements M1, M2, M3, M4, M5, and M6. Each of the switching elements M1, M2, M3, M4, M5, and M6 can be connected to one of the output channels CH1, CH2, and CH3 of the data driver integrated circuit DIC.

[0110] In this configuration, two or more switching elements M1, M2, M3, M4, M5, and M6 can be connected to an output channel CH1, CH2, and CH3. For example, the first switching element M1 and the second switching element M2 can be connected to the first output channel CH1, the third switching element M3 and the fourth switching element M4 can be connected to the second output channel CH2, and the fifth switching element M5 and the sixth switching element M6 can be connected to the third output channel CH3.

[0111] The switching elements M1, M2, M3, M4, M5, and M6 can be switched on and off via the timing controller 10. Figure 1The multiplexer is controlled by multiplexing control signals MUX1 and MUX2 provided by the multiplexer. For example, the first switching element M1, the third switching element M3, and the fifth switching element M5 are controlled according to the first multiplexing control signal MUX1, and the second switching element M2, the fourth switching element M4, and the sixth switching element M6 are controlled according to the second multiplexing control signal MUX2. Here, because the switching elements M1, M2, M3, M4, M5, and M6 are controlled by two or more multiplexing control signals MUX1 and MUX2, the multiplexer 31 can be referred to as a 2MUX structure.

[0112] Display panel 50 includes a plurality of pixels PX1, PX2, and PX3 arranged in a matrix. Figure 6 The image shows, representatively, pixels PX1, PX2, and PX3, each displaying a first color, a second color, and a third color, respectively. Here, the first color can be red, the second color can be green, and the third color can be blue. However, the embodiment is not limited to this. The first to third pixels PX1, PX2, and PX3 displaying the first to third colors can constitute a unit pixel PXU.

[0113] Each of pixels PX1, PX2, and PX3 includes a first sub-pixel and a second sub-pixel, namely SP11 and SP12 of PX1, SP21 and SP22 of PX2, and SP31 and SP32 of PX3. Each of sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 is driven to display either a first image (shared image) or a second image (privacy image), as shown in the reference. Figure 4 As stated above.

[0114] Subpixels SP11, SP12, SP21, SP22, SP31, and SP32 can be connected to scan lines GL1 and GL2, as well as light-emitting lines (not shown). For example, the first subpixels SP11, SP21, and SP31 can be connected to scan line GLo, and the second subpixels SP12, SP22, and SP32 can be connected to scan line GLe. Here, scan line GLo can be an odd-numbered scan line, and scan line GLe can be an even-numbered scan line.

[0115] Subpixels SP11, SP12, SP21, SP22, SP31, and SP32 can be further connected to data lines DL1, DL2, DL3, DL4, DL5, and DL6 corresponding to subpixels SP11, SP12, SP21, SP22, SP31, and SP32. Each of the switching elements M1 to M6 of the multiplexer 31 can be connected to each input terminal of data lines DL1, DL2, DL3, DL4, DL5, and DL6, respectively.

[0116] In this configuration, sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 constituting one of pixels PX1, PX2, and PX3 can be connected to an output channel CH1, CH2, and CH3 via switching elements M1, M2, M3, M4, M5, and M6. For example, sub-pixels SP11 and SP12 constituting the first pixel PX1 can be connected to the first output channel CH1 via the first switching element M1 and the second switching element M2; sub-pixels SP21 and SP22 constituting the second pixel PX2 can be connected to the second output channel CH2 via the third switching element M3 and the fourth switching element M4; and sub-pixels SP31 and SP32 constituting the third pixel PX3 can be connected to the third output channel CH3 via the fifth switching element M5 and the sixth switching element M6.

[0117] When switching elements M1, M2, M3, M4, M5, and M6 are turned on according to multiplexing control signals MUX1 and MUX2, data voltages can be applied to the data lines DL1, DL2, DL3, DL4, DL5, and DL6 connected to the corresponding switching elements M1, M2, M3, M4, M5, and M6. More specifically, when the first switching element M1, the third switching element M3, and the fifth switching element M5 are turned on by the first multiplexing control signal MUX1, data voltages can be applied to the first sub-pixels SP11, SP21, and SP31 of each pixel PX1, PX2, and PX3 connected to the first data line DL1, the third data line DL3, and the fifth data line DL5. Additionally, when the second switching element M2, the fourth switching element M4, and the sixth switching element M6 are turned on by the second multiplexing control signal MUX2, data voltage can be applied to the second sub-pixels SP12, SP22, and SP32 of each pixel PX1, PX2, and PX3 connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6.

[0118] In one embodiment, switching elements M1, M2, M3, M4, M5, and M6 can be configured as transistors. In the illustrated embodiment, switching elements M1, M2, M3, M4, M5, and M6 are PMOS transistors. In such an embodiment, the on-level of multiplexing control signals MUX1 and MUX2 can be low. However, in another embodiment, switching elements M1, M2, M3, M4, M5, and M6 can be NMOS transistors. In such an embodiment, the on-level of multiplexing control signals MUX1 and MUX2 can be high.

[0119] In this embodiment, output buffers 341, 342, and 343 can output data voltages corresponding to the first image synchronously with a first multiplexing control signal MUX1 at an on level, and can output data voltages corresponding to the second image synchronously with a second multiplexing control signal MUX2 at an on level. Then, when the first multiplexing control signal MUX1 is applied, the data voltages corresponding to the first image can be applied to the first sub-pixels SP11, SP21, and SP31, and when the second multiplexing control signal MUX2 is applied, the data voltages corresponding to the second image can be applied to the second sub-pixels SP12, SP22, and SP32. Therefore, the first sub-pixels SP11, SP21, and SP31 can emit light with brightness corresponding to the first image, and the second sub-pixels SP12, SP22, and SP32 can emit light with brightness corresponding to the second image.

[0120] If the first image to be displayed in the first sub-pixels SP11, SP21, and SP31 does not exist in a certain frame (e.g., pixels PX1, PX2, and PX3 operate in the second mode in the corresponding frame), then the output buffers 341, 342, and 343 (or the data driver integrated circuit DIC that includes the output buffers 341, 342, and 343) can be controlled to be disabled during the first time period t1. Conversely, the ground voltage GND can be output through the output channels CH1, CH2, and CH3.

[0121] Conversely, if the second image to be displayed in the second sub-pixels SP12, SP22, and SP32 does not exist in a certain frame (for example, pixels PX1, PX2, and PX3 operate in the first mode in the corresponding frame), then output buffers 341, 342, and 343 can be disabled in the second time period t2, and the ground voltage GND can be output through output channels CH1, CH2, and CH3. Here, the ground voltage GND can be the voltage corresponding to a black image, i.e., black grayscale.

[0122] In the above embodiments, the output channels CH1, CH2, and CH3 of the data driver integrated circuit DIC, and the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 have a 1:n, or 1:2, connection relationship. That is, one output channel CH1, CH2, and CH3 is connected via multiplexer 31 to the first sub-pixels SP11, SP21, and SP31 and the second sub-pixels SP12, SP22, and SP32, which constitute one of pixels PX1, PX2, and PX3 in a 1:n relationship. However, the embodiments are not limited to this. In various embodiments, one output channel CH1, CH2, and CH3 can be connected via multiplexer 31 to three or more sub-pixels disposed in two or more pixels.

[0123] Figure 7 Is applied to Figure 6 The waveform diagram of the control and drive signals of the display device. More detailed... Figure 7 It is shown in order to show Figure 5 The control and drive signals applied are shown in the image.

[0124] Let's refer to each other. Figures 5 to 7 It can drive the display device 1 on a frame-by-frame basis. Figure 1 A frame can be divided into a first time period t1 and a second time period t2.

[0125] In the first time period t1, the first data voltage Vdata1 can be applied to the first sub-pixels SP11, SP21 and SP31 to display the first image (privacy image), while in the second time period t2, the second data voltage Vdata2 can be applied to the second sub-pixels SP12, SP22 and SP32 to display the second image (shared image).

[0126] More specifically, during the first time period t1, a scan signal at the on level can be sequentially applied to scan line GLo in response to the first gate start signal VST1. Additionally, during the second time period t2, a scan signal at the on level can be applied to scan line GLe in response to the second gate start signal VST2.

[0127] Data driver integrated circuits DIC1, DIC2, and DIC3 can be enabled based on data driver enable signals SD1, SD2, and SD3. Output buffers 341, 342, and 343 within each of the data driver integrated circuits DIC1, DIC2, and DIC3 can output data voltages with respect to sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 in synchronization with the scan signal.

[0128] For example, each of the output buffers 341, 342 and 343 can output a first data voltage Vdata1 to be applied to the first sub-pixels SP11, SP21 and SP31 in the first time period t1, and can output a second data voltage Vdata2 to be applied to the second sub-pixels SP12, SP22 and SP32 in the second time period t2.

[0129] Timer controller 10 ( Figure 1 A frame can be time-divided, and multiplexing control signals MUX1 and MUX2 are provided sequentially during the time-division periods t1 and t2, thereby sequentially turning on the switching elements M1 to M6 of the multiplexer 31.

[0130] During the first time period t1, the first multiplexing control signal MUX1, which is at the on level, is applied to the multiplexer 31. Then, the first switching element M1, the third switching element M3, and the fifth switching element M5 are turned on, and the first data voltage Vdata1 output from the output buffers 341, 342, and 343 can be applied to the first sub-pixels SP11, SP21, and SP31.

[0131] During the second time period t2, the second multiplexing control signal MUX2, which is at the on level, is applied to the multiplexer 31. Then, the second switching element M2, the fourth switching element M4, and the sixth switching element M6 are turned on, and the second data voltage Vdata2 output from the output buffers 341, 342, and 343 can be applied to the second sub-pixels SP12, SP22, and SP32.

[0132] In this way, when image data in the first mode or the second mode is applied relative to pixel PX, the first area A1 of the display panel 50 displaying the first image can be freely changed. Figure 3 ) and the second region A2 displaying the second image Figure 3 (size and shape)

[0133] Depending on the driving mode, at least some of sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 can display virtual images. For example, in Figure 5 In the illustrated embodiment, most of the second sub-pixels SP12, SP22, and SP32 can be configured to display virtual images. In this embodiment, unnecessary power consumption can occur when control is activated to enable all data driver integrated circuits DIC1, DIC2, and DIC3 throughout the entire frame period and when a predetermined second data voltage Vdata2 is output to the second sub-pixels SP12, SP22, and SP32. To prevent this problem, output buffers 341, 342, and 343 connected to the second sub-pixels SP12, SP22, and SP32 can be disabled when displaying virtual images.

[0134] For example, during the second time period t2, the second sub-pixels SP12, SP22, and SP32 located in area A can display virtual images. That is, it is not necessary to provide the controlled second data voltage Vdata2 to the second sub-pixels SP12, SP22, and SP32 located in area A.

[0135] Therefore, when a scan signal is applied to the second sub-pixels SP12, SP22, and SP32 located in region A, the output buffers 342, 342, and 343 in all data driver integrated circuits DIC1, DIC2, and DIC3 can be disabled. For example, a source output enable signal SOE at a shutdown level (e.g., high level) can be applied from timing controller 10 to all data driver integrated circuits DIC1, DIC2, and DIC3. Therefore, the second data voltage Vdata2 may not be output from output buffers 341, 342, and 343.

[0136] Conversely, the ground voltage GND connected to each output channel CH1, CH2, and CH3 can be provided to data lines DL1 to DL6. Then, a virtual data voltage (also called a “predetermined data voltage”), such as the ground voltage GND, can be applied to the second sub-pixels SP12, SP22, and SP32 located in area A, and a predetermined virtual image corresponding to the ground voltage GND can be displayed.

[0137] Since the second data voltage Vdata2 is not output from the output buffers 341, 342, and 343, the power consumption of the data driver integrated circuits DIC1, DIC2, and DIC3 can be reduced. Furthermore, when the data driver integrated circuits DIC1, DIC2, and DIC3 are idle, the performance of the circuit elements can be restored, and the rate of degradation can be slowed.

[0138] When output buffers 341, 342, and 343 are disabled, the image data DATA( Figure 1 It is not necessary to use the timer controller 10 ( Figure 1 The power consumption of data driver integrated circuits DIC1, DIC2, and DIC3 can be further reduced using this configuration.

[0139] During the second time period t2, the second sub-pixels SP12, SP22, and SP32 located in region B and connected to the first data driver integrated circuit DIC1 can display a predetermined grayscale according to the second image. That is, the predetermined controlled second data voltage Vdata2 must be provided to the second sub-pixels SP12, SP22, and SP32 through the first data driver integrated circuit DIC1.

[0140] Therefore, when a scan signal is applied to the second sub-pixels SP12, SP22, and SP32 located in region B, the output buffers 341, 342, and 343 located in the first data driver integrated circuit DIC1 can be enabled. For example, the first source output enable signal SOE1, which is at an on level (e.g., low level), can be activated from the timing controller 10. Figure 1 The data is applied to the first data driver integrated circuit DIC1.

[0141] The timing controller 10 provides image data DATA to the enabled first data driver integrated circuit DIC1, and the first data driver integrated circuit DIC1 converts the image data DATA to generate a second data voltage Vdata2. The second data voltage Vdata2 can be provided to the second sub-pixels SP12, SP22 and SP32 through output buffers 341, 342 and 343.

[0142] Meanwhile, when the first data driver integrated circuit DIC1 is enabled, the output buffers 341, 342, and 343 in the second data driver integrated circuit DIC2 and the third data driver integrated circuit DIC3, which are connected to the second sub-pixels SP12, SP22, and SP32 that display the virtual image, can be controlled to remain disabled.

[0143] During the second time period t2, the second sub-pixels SP12, SP22, and SP32 located in region C display the virtual image. That is, it is not necessary to provide the controlled second data voltage Vdata2 to the second sub-pixels SP12, SP22, and SP32 located in region A. Therefore, when the scan signal is applied to the second sub-pixels SP12, SP22, and SP32 located in region C, the output buffers 341, 342, and 343 in all data driver integrated circuits DIC1, DIC2, and DIC3 can be disabled.

[0144] Figure 8 This is a diagram illustrating the connection relationship between the pixels and the data driver integrated circuit according to the second embodiment.

[0145] and Figure 6 Compared to the embodiments in the previous embodiment, the multiplexer 31 according to the embodiment may also include a plurality of virtual switching elements S1 to S6.

[0146] Each of the virtual switch elements S1 to S6 can be connected to one of the data lines DL1 to DL6 respectively. For example, the first virtual switch element S1 can be connected to the first data line DL1, the second virtual switch element S2 can be connected to the second data line DL2, the third virtual switch element S3 can be connected to the third data line DL3, the fourth virtual switch element S4 can be connected to the fourth data line DL4, the fifth virtual switch element S5 can be connected to the fifth data line DL5, and the sixth virtual switch element S6 can be connected to the sixth data line DL6.

[0147] The virtual switching elements S1 to S6 can be turned on and off by the timing controller 10. Figure 1 The virtual multiplexing control signals DMUX1 and DMUX2 provided are used for control. For example, the first, third, and fifth virtual switching elements S1, S3, and S5 can be controlled according to the first virtual multiplexing control signal DMUX1, and the second, fourth, and sixth virtual switching elements S2, S4, and S6 can be controlled according to the second virtual multiplexing control signal DMUX2.

[0148] Each of the virtual switching elements S1 to S6 can be further connected to virtual voltage lines SRGB and PRGB. The virtual voltage lines SRGB and PRGB can be connected from the power supply unit 40 ( Figure 1 The device receives a predetermined virtual data voltage, such as a black / grayscale voltage. The black / grayscale voltage can be, for example, a DC voltage of 0V, but is not limited to this.

[0149] When virtual switch elements S1 to S6 are turned on according to virtual multiplexing control signals DMUX1 and DMUX2, data lines DL1 to DL6 connected to the corresponding virtual switch elements S1 to S6 can be electrically connected to the virtual voltage lines SRGB and PRGB. Therefore, black grayscale voltage can be applied to data lines DL1 to DL6.

[0150] More specifically, when the first, third, and fifth virtual switch elements S1, S3, and S5 are turned on by the first virtual multiplexing control signal DMUX1, a black grayscale voltage can be applied to the first sub-pixels SP11, SP21, and SP31 of pixels PX1, PX2, and PX3 connected to the first, third, and fifth data lines DL1, DL3, and DL5. Furthermore, when the second virtual switch element S2, the fourth virtual switch element S4, and the sixth virtual switch element S6 are turned on by the second virtual multiplexing control signal DMUX2, a black grayscale voltage can be applied to the second sub-pixels SP12, SP22, and SP32 of pixels PX1, PX2, and PX3 connected to the second data line DL2, the fourth data line DL4, and the sixth data line DL6.

[0151] In one embodiment, the virtual switching elements S1 to S6 can be formed of transistors. In the illustrated embodiment, the virtual switching elements S1 to S6 are PMOS transistors. In such an embodiment, the on-state levels of the virtual multiplexing control signals DMUX1 and DMUX2 can be low. However, in another embodiment, the virtual switching elements S1 to S6 can be NMOS transistors. In such an embodiment, the on-state levels of the virtual multiplexing control signals DMUX1 and DMUX2 can be high.

[0152] Figure 9 Is applied to Figure 8 The waveform diagram of the control and drive signals of the display device. More detailed... Figure 9 It is shown in order to show Figure 5 The control and drive signals applied are shown in the image.

[0153] Let's refer to each other. Figure 5 , Figure 8 and Figure 9 It can drive the display device 1 on a frame-by-frame basis. Figure 1 A frame can be divided into a first time period t1 and a second time period t2.

[0154] In the first time period t1, the first data voltage Vdata1 can be applied to the first sub-pixels SP11, SP21 and SP31 to display the first image (privacy image), while in the second time period t2, the second data voltage Vdata2 can be applied to the second sub-pixels SP12, SP22 and SP32 to display the second image (shared image).

[0155] Depending on the driving mode, at least some of sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 can display virtual images. For example, in Figure 5 In the illustrated embodiment, most of the second sub-pixels SP12, SP22, and SP32 can be configured to display virtual images. In this embodiment, unnecessary power consumption may occur when the control enables all data driver integrated circuits DIC1, DIC2, and DIC3 throughout the entire frame period and outputs a predetermined second data voltage Vdata2 to the second sub-pixels SP12, SP22, and SP32. To prevent this, the data driver integrated circuits DIC1, DIC2, and DIC3 connected to the second sub-pixels SP12, SP22, and SP32 can be disabled when displaying virtual images.

[0156] For example, during the second time period t2, the second sub-pixels SP12, SP22, and SP32 located in area A can display a virtual image. That is, it is not necessary to provide the controlled second data voltage Vdata2 to the second sub-pixels SP12, SP22, and SP32 located in area A.

[0157] Therefore, when a scan signal is applied to the second sub-pixels SP12, SP22, and SP32 located in region A, all data driver integrated circuits DIC1, DIC2, and DIC3 can be disabled. For example, data driver enable signals SD1, SD2, and SD3 at a shutdown level (e.g., high level) can be activated from timing controller 10. Figure 1 The second data voltage Vdata2 is applied to all data driver ICs DIC1, DIC2, and DIC3. Therefore, the second data voltage Vdata2 may not be output from any of the data driver ICs DIC1, DIC2, and DIC3. Furthermore, a second multiplexing control signal MUX2 at a shutdown level can be applied, which prevents unwanted voltage from being output from the disabled data driver ICs DIC1, DIC2, and DIC3 to data lines DL2, DL4, and DL6.

[0158] Conversely, a second virtual multiplexing control signal DMUX2 at an on-level (e.g., low level) can be applied from the timing controller 10. Then, the second virtual switch element S2, the fourth virtual switch element S4, and the sixth virtual switch element S6 can be turned on, and the second virtual voltage line PRGB and the second data line DL2, the fourth data line DL4, and the sixth data line DL6 can be electrically connected. The black-grayscale voltage applied to the second virtual voltage line PRGB can be applied to the second sub-pixels SP12, SP22, and SP32 via the second data line DL2, the fourth data line DL4, and the sixth data line DL6. Subsequently, a virtual image corresponding to the black-grayscale can be displayed in the second sub-pixels SP12, SP22, and SP32 located in area A.

[0159] When data driver integrated circuits DIC1, DIC2, and DIC3 are disabled, their power consumption can be reduced. Additionally, when DIC1, DIC2, and DIC3 are idle, the circuit elements can be regenerated, and the rate of degradation can be slowed.

[0160] When the data driver integrated circuits DIC1, DIC2, and DIC3 are disabled, the image data DATA( Figure 1 The power consumption of the display device 1 can be further reduced by not applying power from the timing controller 10 to the data driver integrated circuits DIC1, DIC2, and DIC3.

[0161] During the second time period t2, the second sub-pixels SP12, SP22, and SP32 located in region B and connected to the first data driver integrated circuit DIC1 can display a predetermined grayscale according to the second image. That is, the predetermined controlled second data voltage Vdata2 must be provided to the second sub-pixels SP12, SP22, and SP32 through the first data driver integrated circuit DIC1.

[0162] Therefore, when a scan signal is applied to the second sub-pixels SP12, SP22, and SP32 located in region B, the first data driver integrated circuit DIC1 can be enabled. For example, a first data driver enable signal SD1 at an on level (e.g., low level) can be applied to the first data driver integrated circuit DIC1 from the timing controller 10.

[0163] The timing controller 10 provides image data DATA to the enabled first data driver integrated circuit DIC1, and the first data driver integrated circuit DIC1 converts the image data DATA to generate a second data voltage Vdata2. The second data voltage Vdata2 can be provided to the second sub-pixels SP12, SP22, and SP32 through output buffers 341, 342, and 343. A second multiplexing control signal MUX2 at the on level can be applied so that the second data voltage Vdata2 output from the first data driver integrated circuit DIC1 can be provided to data lines DL2, DL4, and DL6.

[0164] Meanwhile, when the first data driver integrated circuit DIC1 is enabled, the second data driver integrated circuit DIC2 and the third data driver integrated circuit DIC3, which are connected to the second sub-pixels SP12, SP22 and SP32 that display the virtual image, can be controlled to remain disabled.

[0165] During the second time period t2, the second sub-pixels SP12, SP22, and SP32 located in region C display the virtual image. That is, it is not necessary to provide the controlled second data voltage Vdata2 to the second sub-pixels SP12, SP22, and SP32 located in region A. Therefore, when the scan signal is applied to the second sub-pixels SP12, SP22, and SP32 located in region C, all data driver integrated circuits DIC1, DIC2, and DIC3 can be disabled.

[0166] Meanwhile, the method for reducing power consumption while displaying the image in the second region A2 is as described above. However, the above embodiments can also be applied equivalently to the case of displaying the image in the first region A1.

[0167] Figure 10 This is a diagram illustrating the connection relationship between the pixels and the data driver integrated circuit according to the third embodiment.

[0168] and Figure 8 Compared to the embodiments in the text, in Figure 10 In the embodiments described, each of the output channels CH1, CH2, and CH3 can be connected to pixels PX1, PX2, and PX3 in multiple unit pixels PXU1 and PXU2 via multiplexer 31. For example, the first output channel CH1 can be connected to the first pixel PX1 of the first unit pixel PXU1 and the second unit pixel PXU2, the second output channel CH2 can be connected to the second pixel PX2 of the first unit pixel PXU1 and the second unit pixel PXU2, and the third output channel CH3 can be connected to the third pixel PX3 of the first unit pixel PXU1 and the second unit pixel PXU2. Thus, when one output channel CH1, CH2, and CH3 are connected to multiple unit pixels PXU1 and PXU2, the number of data driver integrated circuits DIC and the configuration of data driver 30 ( Figure 1 The number of lines is reduced, and a miniaturized display device 1 can be achieved. Figure 1 ).

[0169] Multiplexer 31 may include multiple switching elements M1 to M12. Each of switching elements M1 to M12 may be connected to one of the output channels CH1, CH2, and CH3 of data driver 30. In this case, two or more switching elements M1 to M12 may be connected to one output channel CH1, CH2, and CH3. The switching elements M1 to M12 can be turned on and off by the timing controller 10. Figure 1 The multiplexing control signals MUX11, MUX12, MUX21 and MUX22 provided by the controller are used for control.

[0170] The display panel 50 includes a plurality of pixels PX1 and PX2 arranged in a matrix. Each unit pixel PXU1 and PXU2 includes a plurality of pixels PX1, PX2 and PX3. Each of the pixels PX1, PX2 and PX3 constituting one of the unit pixels PXU1 and PXU2 includes a first sub-pixel and a second sub-pixel, namely SP11 and SP12 of PX1, SP21 and SP22 of PX2, and SP31 and SP32 of PX3.

[0171] Sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 of unit pixels PXU1 and PXU2 can be connected to their corresponding data lines DL1 to DL12. Switching elements M1 to M12 of multiplexer 31 can be connected to the input terminals of data lines DL1 to DL12 respectively.

[0172] In this configuration, each of the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 included in the multiple unit pixels PXU1 and PXU2 can be connected to one of the output channels CH1, CH2, and CH3 via switching elements M1 to M12. For example, the first sub-pixel SP11 of the first pixel PX1 of unit pixels PXU1 and PXU2 can be connected to the first output channel CH1 via the first switching element M1 and the seventh switching element M7, respectively, and its second sub-pixel SP12 can be connected to the first output channel CH1 via the second switching element M2 and the eighth switching element M8, respectively.

[0173] The first sub-pixel SP21 of the second pixel PX2 of unit pixels PXU1 and PXU2 can be connected to the second output channel CH2 through the third switch element M3 and the ninth switch element M9, respectively, and its second sub-pixel SP22 can be connected to the second output channel CH2 through the fourth switch element M4 and the tenth switch element M10, respectively. The first sub-pixel SP31 of the third pixel PX3 of unit pixels PXU and PXU2 can be connected to the third output channel CH3 through the fifth switch element M5 and the eleventh switch element M11, respectively, and its second sub-pixel SP32 can be connected to the third output channel CH3 through the sixth switch element M6 and the twelfth switch element M12, respectively.

[0174] The multiplexer 31 may further include multiple virtual switching elements S1 to S12. Virtual switching elements S1 to S12 may be connected to one of the data lines DL1 to DL12 respectively. Virtual switching elements S1 to S12 may be further connected to virtual voltage lines SRGB and PRGB. Virtual voltage lines SRGB and PRGB may receive voltages corresponding to predetermined virtual data voltages, for example, from the power supply unit 40. Figure 1 The black grayscale voltage, etc. The black grayscale voltage can be, for example, a DC voltage of 0V, but is not limited to this.

[0175] It can be controlled from the timer controller 10 ( Figure 1 The virtual multiplexing control signals DMUX1 and DMXU2, provided by [various sources], control the on / off state of virtual switching elements S1 to S12. When virtual switching elements S1 to S12 are turned on according to the virtual multiplexing control signals DMUX1 and DMUX2, the data lines DL1 to DL12 connected to the corresponding virtual switching elements S1 to S12 can be electrically connected to the virtual voltage lines SRGB and PRGB. Therefore, black grayscale voltage can be applied to the data lines DL1 to DL12.

[0176] Figure 11 Is applied to Figure 10 The waveform diagram of the control and drive signals of the display device. More detailed... Figure 11 It is shown in order to show Figure 5 The control and drive signals applied are shown in the image.

[0177] Let's refer to each other. Figure 5 , Figure 10 and Figure 11 It can drive the display device 1 on a frame-by-frame basis. Figure 1 A frame can be divided into a first time period t1 and a second time period t2.

[0178] In the first time period t1, the first data voltage Vdata1 can be applied to the first sub-pixels SP11, SP21 and SP31 to display the first image (privacy image), while in the second time period t2, the second data voltage Vdata2 can be applied to the second sub-pixels SP12, SP22 and SP32 to display the second image (shared image).

[0179] More specifically, during the first time period t1, scan signals at the on level can be sequentially applied to scan line GLo in response to the first gate start signal VST1. Additionally, during the second time period t2, scan signals at the on level can be sequentially applied to scan line GLe in response to the second gate start signal VST2. Each scan signal can be applied at the on level during a horizontal time period 1H.

[0180] Timer controller 10 ( Figure 1 A frame can be time-divided, and multiplexing control signals MUX11, MUX12, MUX21 and MUX22 are sequentially provided to time-division periods t1 and t2, thereby sequentially turning on the switching elements M1 to M12 of the multiplexer 31.

[0181] The first multiplexing control signals MUX11 and MUX12, which are at the on level, can be applied to the multiplexer 31 during the first time period t1. Here, the (1-1) multiplexing control signal MUX11 and the (1-2) multiplexing control signal MUX12 can be applied sequentially over a horizontal time period 1H. The first data voltage Vdata1 output from the output buffers 341, 342, and 343 can be applied to the first sub-pixels SP11, SP21, and SP31, which are included in the plurality of unit pixels PXU1 and PXU2, in response to the sequentially on first multiplexing control signals MUX11 and MUX12.

[0182] Similarly, the second multiplexing control signals MUX21 and MUX22, which are at the on level, can be applied to the multiplexer 31 during the second time period t2. Here, the (2-1) multiplexing control signal MUX21 and the (2-2) multiplexing control signal MUX22 can be applied sequentially by time-division of a horizontal time period 1H. The second data voltage Vdata2 output from the output buffers 341, 342, and 343 can be applied to the second sub-pixels SP12, SP22, and SP32, which are included in the plurality of unit pixels PXU1 and PXU2, in response to the sequentially on second multiplexing control signals MUX21 and MUX22.

[0183] Figure 12 This is a circuit diagram of the pixel according to an embodiment. Figure 13 It is shown Figure 12 The diagram shows a planar layout of the pixels.

[0184] Let's refer to each other. Figure 12 and Figure 13 The display panel 50 may include a first scan line GL1, a second scan line GL2, and a light-emitting line EL extending in the row direction, and may also include a high-potential driving voltage line PL1, a low-potential driving voltage line PL2, a data line DL, and a reference voltage line VrefL extending in the column direction substantially perpendicular to the row direction. A sub-pixel SP1 and SP2 may be formed in the area where the first scan line GL1, the second scan line GL2, the light-emitting line EL, the high-potential driving voltage line PL1, the low-potential driving voltage line PL2, and the data line DL intersect each other.

[0185] Two sub-pixels SP1 and SP2 that are adjacent to each other in the row direction can form a pixel PX. The sub-pixels SP1 and SP2 that form a pixel PX can be formed using the same or different circuits. When the sub-pixels SP1 and SP2 that form a pixel PX are formed using the same circuit, the sub-pixels SP1 and SP2 can have a layout in which the sub-pixels SP1 and SP2 are mirror images of each other based on the column direction. More specifically, the two sub-pixels SP1 and SP2 that are adjacent to each other and form a pixel PX can have a layout in which they are mirror images of each other based on a high-potential driving voltage line PL1. However, this embodiment is not limited to this.

[0186] In this embodiment, two adjacent sub-pixels SP1 and SP2 may share at least one of a high-potential driving voltage line PL1, a low-potential driving voltage line PL2, a data line DL, and a reference voltage line VrefL. For example, two sub-pixels SP1 and SP2 included in a pixel PX may share a high-potential driving voltage line PL1. Furthermore, for example, two or more pixels PS may share a low-potential driving voltage line PL2 and / or a reference voltage line VrefL. In this case, to connect the reference voltage line VrefL extending along the column direction to sub-pixels SP1 and SP2, a connection line CL extending along the row direction can be formed by passing through sub-pixels SP1 and SP2. However, this embodiment is not limited to this.

[0187] The configuration of subpixels SP1 and SP2 will be described below based on the first subpixel SP1.

[0188] According to an embodiment, the first sub-pixel SP1 may include a driving transistor DT, a light-emitting diode LD connected to the driving transistor DT, and control circuitry configured to control the amount of driving current applied to the driving transistor DT through the driving transistor DT. For example, the control circuitry may include first transistors T1 through fifth transistors T5 and a capacitor Cst. In such an embodiment, a pixel PX may have a 12T2C structure.

[0189] The first electrode of the driving transistor DT is configured to receive a high-potential driving voltage VDD (connected to the high-potential driving voltage line PL1), and its second electrode is connected to the second node N2. The gate electrode of the driving transistor DT is connected to the first node N1. The driving transistor DT can be turned on according to the voltage applied to the first node N1, and the amount of driving current flowing to the light-emitting diode LD can be controlled.

[0190] In this embodiment, the driving transistor DT can be formed by two auxiliary driving transistors DT1 and DT2 connected in series as shown. In this case, the first auxiliary driving transistor DT1 can be connected between the high-potential driving voltage VDD and the second auxiliary driving transistor DT2, and the second auxiliary driving transistor DT2 can be connected between the first auxiliary driving transistor DT1 and the first node N1. The gate electrodes of the first auxiliary driving transistor DT1 and the second auxiliary driving transistor DT2 can be connected to the first node N1. However, the embodiment is not limited to this.

[0191] The first electrode of the first transistor T1 is connected to the data line DL, and its second electrode is indirectly connected to the gate electrode of the driving transistor DT through the third node N3. The gate electrode of the first transistor T1 can be connected to the first scan line GL1 and can receive the first scan signal SC1. The first transistor T1 can be turned on according to the first scan signal SC1 applied to the first scan line GL1, and transmit the data voltage Vdata applied to the data line DL to the third node N3. Such a first transistor T1 can be called a switching transistor.

[0192] The first electrode of the second transistor T2 is connected to the gate electrode of the driving transistor DT through a first node N1, and its second electrode is connected to the second electrode of the driving transistor DT through a second node N2. The gate electrode of the second transistor T2 can be connected to the second scan line GL2 and can receive the second scan signal SC2. The second transistor T2 can be turned on according to the second scan signal SC2 applied to the second scan line GL2, and the gate electrode and the second electrode of the driving transistor DT can be electrically connected to each other.

[0193] The first electrode of the third transistor T3 is configured to receive a reference voltage Vref (connected to the reference voltage line VrefL), and its second electrode is connected to the third node N3. The gate electrode of the third transistor T3 can be connected to the light-emitting line EL and can receive a light-emitting signal EM. The third transistor T3 can be turned on according to the light-emitting signal EM applied to the light-emitting line EL, and can apply the reference voltage Vref to the third node N3. Such a third transistor T3 can be called an initialization transistor.

[0194] The first electrode of the fourth transistor T4 is connected to the driving transistor DT through the second node N2, and its second electrode is connected to the light-emitting diode LD through the fourth node N4. The gate electrode of the fourth transistor T4 can be connected to the light-emitting line EL and can receive the light-emitting signal EM. The fourth transistor T4 can be turned on according to the light-emitting signal EM applied to the light-emitting line EL, and can connect the driving transistor DT and the light-emitting diode LD. When the fourth transistor T4 is turned on, a current path is formed between the high-potential driving voltage VDD and the low-potential driving voltage VSS, and the light-emitting diode LD can emit light. Such a fourth transistor T4 can be called a light-emitting transistor.

[0195] The first electrode of the fifth transistor T5 is configured to receive a reference voltage Vref (connected to the reference voltage line VrefL), and its second electrode is connected to the anode electrode of the light-emitting diode LD via the fourth node N4. The gate electrode of the fifth transistor T5 can be connected to the second scan line GL2 and can receive the second scan signal SC2. The fifth transistor T5 can be turned on according to the second scan signal SC2 applied to the second scan line GL2, and can transmit the reference voltage Vref to the anode electrode of the light-emitting diode LD. Such a fifth transistor T5 can be referred to as an anode initialization transistor.

[0196] A capacitor Cst can be connected between the first node N1 and the third node N3. The capacitor Cst can store a voltage corresponding to the potential difference between the first node N1 and the third node N3.

[0197] The anode of the light-emitting diode (LD) can be connected to the fourth node N4, and its cathode can be connected to the low-potential drive voltage VSS. When the driving transistor DT and the fourth transistor T4 are turned on, a current path can be formed between the high-potential drive voltage VDD and the low-potential drive voltage VSS, and the drive current can flow to the LD. The LD can emit light with a brightness corresponding to the applied drive current.

[0198] exist Figure 12 In the illustrated embodiment, the pixel PX can be constructed from a low-temperature polycrystalline silicon (LTPS) thin-film transistor. An LTPS thin-film transistor includes a gate electrode, a source electrode, and a drain electrode. The LTPS thin-film transistor can have an active layer formed of polycrystalline silicon. This LTPS thin-film transistor can be formed from a p-type thin-film transistor or an n-type thin-film transistor. LTPS thin-film transistors have high electron mobility and therefore fast drive characteristics.

[0199] In another embodiment, the pixel PX can be formed of an oxide semiconductor thin-film transistor (OSB), or it can be a hybrid type including LTPS thin-film transistors and OSB thin-film transistors. The OSB thin-film transistor can include a gate electrode, a source electrode, and a drain electrode. The OSB thin-film transistor has an active layer formed of oxide semiconductor. Here, the oxide semiconductor can be configured as an amorphous oxide semiconductor or a crystalline oxide semiconductor. The OSB thin-film transistor can be configured as a p-type transistor or an n-type transistor. OSB thin-film transistors can be formed using low-temperature processes and have lower charge mobility than LTPS thin-film transistors. Such OSB thin-film transistors exhibit excellent cutoff current characteristics.

[0200] Figure 14 This is a plan view showing the unit pixels according to an embodiment. More specifically, Figure 14The upper plane of unit pixel PXU is shown when three pixels PX1, PX2, and PX3 are set in unit pixel PXU and each of pixels PX1, PX2, and PX3 includes two sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32.

[0201] Each of sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 includes a light-emitting diode (LD). Figure 12 A light-emitting diode (LD) includes an anode electrode (ANO).

[0202] Sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 each have a light-emitting region EA defined by a light-emitting diode (LD). The light-emitting region EA can be defined as the area where the anode electrode ANO is not covered by the upper insulating layer (e.g., the embankment described below) and is exposed on its upper side. The size and shape of the light-emitting regions EA of sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 can be the same as or different from each other. In an embodiment, the light-emitting regions EA of the first sub-pixels SP11, SP21, and SP31 can have a generally circular shape, and the light-emitting regions of the second sub-pixels SP12, SP22, and SP32 can have a generally quadrilateral shape, but are not limited thereto.

[0203] In this embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be a red pixel, a green pixel, and a blue pixel, respectively. Therefore, the light-emitting diodes (LDs) of the sub-pixels SP11 and SP12 of the first pixel PX1 can emit red light, the light-emitting diodes (LDs) of the sub-pixels SP21 and SP22 of the second pixel PX2 can emit green light, and the light-emitting diodes (LDs) of the sub-pixels SP31 and SP32 of the third pixel PX3 can emit blue light.

[0204] Each of the sub-pixels SP11, SP12, SP21, SP22, SP31, and SP32 is provided with a lens assembly comprising multiple lenses 501 and 502. The lens assembly may include a first lens 501 and a second lens 502, each lens providing a different viewing angle. For example, the first lens 501 may be disposed in the light-emitting region EA of the first sub-pixels SP11, SP21, and SP31, and the second lens 502 may be disposed in the light-emitting region EA of the second sub-pixels SP12, SP22, and SP32.

[0205] The size and shape of the first lens 501 or the second lens 502 can differ from each other to provide different viewing angles. For example, the first lens 501 can be a hemispherical lens having a flat lower surface and a spherical upper surface opposite to the lower surface. For example, the second lens 502 can be a semi-cylindrical lens having a flat lower surface and a semi-cylindrical upper surface opposite to the lower surface. However, the embodiments are not limited to these.

[0206] The viewing angle of the display panel 50 can be controlled by using a first lens 501 and a second lens 502, each with a different shape. More specifically, the viewing angle limiting directions of the first lens 501 and the second lens 502 are different from each other, and narrow and wide viewing angles can be achieved by selectively driving the sub-pixels SP11, SP12, SP21, SP22, SP31 and SP32 as described above.

[0207] Figure 15 It is shown schematically. Figure 14 The view shown is of the first lens. Figure 16 It shows relative to Figure 15 A view of the optical profile of the first lens from its angle of view. Figure 17 It is shown schematically. Figure 14 The view of the second lens shown. Figure 18 It shows relative to Figure 17 A view showing the optical profile of the second lens from its angle of view.

[0208] like Figure 15 As shown, the first lens 501 is a hemispherical lens and has a semi-circular cross-section in the X and Y directions. Therefore, the first lens 501 restricts the viewing angle in the X and Y directions.

[0209] On the contrary, such as Figure 17 As shown, the second lens 502 is a semi-cylindrical lens with a rectangular cross-section in the X direction and a semi-circular cross-section in the Y direction. Therefore, the second lens 502 restricts the viewing angle in the Y direction but does not restrict the viewing angle in the longitudinal direction of the first lens 501, i.e., the viewing angle in the X direction.

[0210] like Figure 16 As shown, the first sub-pixels SP11, SP21, and SP31 of the hemispherical first lens 501 are provided. Figure 14 The luminescent regions EA11, EA21 and EA31 of the ) Figure 14 It has a narrow viewing angle of approximately 30 degrees or less in both the left-right and vertical directions. Conversely, as... Figure 18 As shown, the second sub-pixels SP12, SP22, and SP32 of the semi-cylindrical second lens 502 are provided. Figure 14 The luminescent regions EA12, EA22 and EA32 of the light-emitting region are... Figure 14It has a wide viewing angle of about 60 degrees or more in the left and right directions.

[0211] Therefore, for the first image displayed in the first sub-pixels PS11, SP21 and SP31, a narrow viewing angle mode in the vertical direction and a narrow viewing angle mode in the left and right direction (i.e., privacy mode) can be implemented, and for the second image displayed in the second sub-pixels SP12, SP22 and SP32, a narrow viewing angle mode in the vertical direction and a wide viewing angle mode in the left and right direction (i.e., sharing mode) can be implemented.

[0212] Thus, display panel 50 ( Figure 1 It always has a narrow viewing angle in the vertical direction, and therefore, when applied in a vehicle, the display panel 50 can prevent images from being reflected on the vehicle's windshield and interrupting the driver's line of sight.

[0213] Figure 19 This is a cross-sectional schematic diagram of the display area of ​​the display panel according to an embodiment. Figure 19 The image shows a cross-section of two sub-pixels SP that are set adjacent to each other. Specifically, in Figure 19 The image shows a cross-section configured to display the first sub-pixel of the first image.

[0214] refer to Figure 19 The display panel 100 may include a substrate 101, a thin film transistor 120, a light-emitting diode LD, a packaging unit 170, and a touch unit 180.

[0215] The substrate 101 may include one or more plastic materials (such as polyimide) or glass materials. The substrate 101 may be a rigid substrate or a flexible substrate.

[0216] A buffer layer 102 may be disposed on the substrate 101. The buffer layer 102 can minimize or delay the dispersion of moisture or oxygen that permeates into the substrate 101. The buffer layer 102 can be formed by alternatingly stacking silicon nitride (SiNx) and silicon oxide (SiOx) at least once, but is not limited thereto. Figure 19 In the diagram, the buffer layer 102 is shown as a multi-structure layer with three layers, but the number of layers constituting the buffer layer 102 is not limited to this, and the buffer layer 102 can be formed as a single-structure layer.

[0217] A light-shielding layer 126 may be disposed on the buffer layer 102. A semiconductor layer 123 may be disposed overlapping the light-shielding layer 126. The light-shielding layer 126 prevents light from being transmitted into the semiconductor layer 123 of the thin-film transistor 120. The light-shielding layer 126 may be formed of a metallic material and may be a single-structure layer or a multi-structure layer formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto.

[0218] The first insulating layer 103 may be disposed on the light-shielding layer 126. The first insulating layer 103 may be formed of the same material as the buffer layer 102, but the embodiments of this disclosure are not limited thereto.

[0219] The thin-film transistor 120 may be disposed on the first isolation layer 103. The thin-film transistor 120 may include a source electrode 121, a gate electrode 122, a semiconductor layer 123, and a drain electrode 124.

[0220] Semiconductor layer 123 may be disposed on first isolation layer 103. Semiconductor layer 123 may include source region, drain region, and channel region between source region and drain region. Semiconductor layer 123 may include oxide semiconductors such as indium gallium zinc oxide (IGZO) and silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon, but embodiments of this disclosure are not limited thereto.

[0221] The second insulating layer 104 may be disposed on the semiconductor layer 123. The second insulating layer 104 may be formed of the same material as the first insulating layer 103; however, the embodiments of this disclosure are not limited thereto.

[0222] The gate electrode 122 may be disposed on the second insulating layer 104. The gate electrode 122 may be configured to overlap with the channel region of the semiconductor layer 123. The gate electrode 122 may be formed of a metallic material.

[0223] The third insulating layer 105 and the fourth insulating layer 106 can be disposed on the gate electrode 122. The source electrode 121 and the drain electrode 124 can be disposed on the fourth insulating layer 106. The source electrode 121 and the drain electrode 124 can be electrically connected to the semiconductor layer 123 through contact holes. The source electrode 121 and the drain electrode 124 can be formed of a metallic material.

[0224] The storage electrode 140 may be spaced apart from the first thin-film transistor 120. The storage electrode 140 may include a first storage electrode 141 and a second storage electrode 142.

[0225] The first storage electrode 141 may be disposed on the third insulating layer 105. The second storage electrode 142 may be disposed on the fourth insulating layer 106, overlapping the first storage electrode 141 in at least one region.

[0226] Thin-film transistor 120 can be a driving transistor DT ( Figure 12 Although not shown, the display panel 50 may also include other transistors.

[0227] The first protective layer 111 can be disposed on the source electrode 121 and the drain electrode 124. The first protective layer 111 can planarize the upper part of the thin-film transistor 120 and protect the thin-film transistor 120. The first protective layer 111 can be formed of an organic material. For example, the first protective layer 111 can be formed of an organic material including acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but is not limited thereto.

[0228] The second protective layer 112 may be disposed on the first protective layer 111. The second protective layer 112 may be formed of the same material as the first protective layer 111, but is not limited thereto.

[0229] The connecting electrode 145 can be disposed between the first protective layer 111 and the second protective layer 112. The connecting electrode 145 can electrically connect the thin film transistor 120 and the light-emitting diode LD.

[0230] A light-emitting diode (LD) can be disposed on the second protective layer 112. The LD may include an anode electrode 151, an organic layer 152, and a cathode electrode 153.

[0231] The anode electrode 151 may be disposed on the second protective layer 112. The anode electrode 151 may be electrically connected to the thin-film transistor 120 through contact holes formed on the first protective layer 111 and the second protective layer 112. The anode electrode 151 may be a reflective electrode that reflects light, but the embodiments of this disclosure are not limited thereto. The anode electrode 151 may comprise a metallic material with high reflectivity, such as a deposited structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a deposited structure of aluminum (Al) and ITO (ITO / Al / ITO), and an APC alloy, and may be formed as a single-layer structure or a multi-layer structure, but is not limited thereto.

[0232] A dam 154 may be formed to cover the edge of the anode electrode 151 and expose at least one area of ​​the anode electrode 151 upwards. The dam 154 is formed to define an opening (or a light-emitting area EA) for the sub-pixel SP. That is, the area of ​​the anode electrode 151 exposed but not covered by the dam 154 may define the light-emitting area of ​​the sub-pixel SP.

[0233] The embankment 154 may be formed of organic materials, such as materials including black pigments, benzocyclobutene resins, polyimide resins, acrylic resins, or photosensitive polymers, but the embodiments of this disclosure are not limited thereto.

[0234] Spacer 155 may be further provided on the embankment 154. Spacer 155 may be formed of the same material as the embankment 154, but embodiments of this disclosure are not limited thereto. Spacer 155 can suppress or prevent marking or scratch defects on the display panel 50 by preventing mask sagging during the masking process.

[0235] The organic layer 152 can be disposed on the exposed area of ​​the anode electrode 151 not covered by the dam. In other words, the organic layer 152 can be disposed on the exposed anode electrode 151 exposed by the dam 154. In another embodiment, the organic layer 152 can be disposed on the entire surface of the substrate.

[0236] The cathode electrode 153 may be disposed on the organic layer 152. The cathode electrode 153 may be a transparent electrode that transmits light, but is not limited thereto. For example, the cathode electrode 153 may include a transparent conductive material or metal, such as indium tin oxide (ITO) or indium zinc oxide (IZO), through which visible light is transmitted, but is not limited thereto.

[0237] A capping layer 156 may be further disposed on the cathode electrode 153. The capping layer 156 can minimize damage to the cathode electrode 153 of the light-emitting diode LD and the organic layer 152 beneath the cathode electrode 153 caused by external light sources. The capping layer 156 may be formed of an organic or inorganic film.

[0238] The encapsulation unit 170 may be disposed on the dam 154 or the light-emitting diode (LD). The encapsulation unit 170 may include one or more insulating layers. For example, the encapsulation unit 170 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172 disposed on the first inorganic encapsulation layer 171, and a second inorganic encapsulation layer 173 disposed on the organic encapsulation layer 172. The encapsulation unit 170 may include one or more inorganic material layers and one or more organic material layers. For example, the first inorganic encapsulation layer 171 and the second inorganic encapsulation layer 173 may include inorganic materials, and the organic encapsulation layer 172 may include organic materials, but is not limited thereto.

[0239] The touch unit 180 may be disposed on the packaging unit 170. The touch unit 180 may include a touch buffer layer 181, a first touch electrode 182, a first touch insulating layer 183, a black matrix BM, a second touch insulating layer 184, a second touch electrode 185, and a third touch insulating layer 186.

[0240] Touch buffer layer 181 may be disposed on encapsulation unit 170. Touch buffer layer 181 may be formed of the same material as buffer layer 102, but is not limited thereto.

[0241] The first touch electrode 182 can be disposed on the touch buffer layer 181. The first touch insulating layer 183 can be disposed on the first touch electrode 182.

[0242] The black matrix BM can be disposed on the first touch insulating layer 183. The black matrix BM may include a material capable of absorbing light.

[0243] The second touch insulating layer 184 may be disposed on the black matrix BM. The second touch insulating layer 184 may include an organic insulating material.

[0244] The second touch electrode 185 may be disposed on the second touch insulating layer 184. The first touch electrode 182 may be electrically connected to the second touch electrode 185 through a contact hole formed in the second touch insulating layer 184. The first touch electrode 182 and the second touch electrode 185 may comprise metallic materials.

[0245] The third touch insulating layer 186 may be disposed on the second touch electrode 185. The third touch insulating layer 186 may include, but is not limited to, the same material as the first touch insulating layer 183.

[0246] The microlens ML can be disposed on the third touch insulating layer 186. The microlens ML can be hemispherical or semi-circular, but is not limited to these. The shape of the microlens ML can vary according to the size and shape of the light-emitting area EA. By setting the microlens ML, a wide viewing angle characteristic can be ensured, brightness can be improved, and light leakage and reflection can be blocked, thereby preventing light leakage.

[0247] The center of the microlens ML can be aligned with the center of the corresponding light-emitting region EA. However, this embodiment is not limited to this. In another embodiment, the center of the microlens ML may not be aligned with the center of the light-emitting region EA. In such an embodiment, an optical component configured to output light emitted from the light-emitting diode LD in the direction of the microlens ML can also be provided. Alternatively, when some components of the light-emitting diode LD are tilted, light emitted from the light-emitting diode LD can be output in the direction of the microlens ML.

[0248] In the illustrated embodiment, the microlens ML is a first lens 501 with a hemispherical shape disposed in the first sub-pixel SP. Figure 14 However, the microlens ML is not limited to this, and the microlens ML can be configured as a second lens 502 with a semi-cylindrical shape disposed in the second sub-pixel SP. Figure 14 ).

[0249] A lens protective layer 190 may be disposed on the microlens ML. The lens protective layer 190 may include, but is not limited to, an organic insulating material. The lens protective layer 190 protects the microlens ML by covering it.

[0250] The refractive index of the lens protective layer 190 can be less than that of the microlens ML. Therefore, due to the difference between the refractive index of the microlens ML and the refractive index of the lens protective layer 190, light passing through the microlens ML can be prevented from being reflected in the direction of the substrate 101.

[0251] Figure 20 This is a view illustrating an example of a display device according to an embodiment. More specifically, Figure 20 The arrangement of the display device 1 in the vehicle is shown in more detail.

[0252] refer to Figure 20 The display device 1 may be disposed in at least some portions of the vehicle's dashboard. The vehicle's dashboard includes configurations disposed on the front surface of the vehicle's front seats (e.g., driver's seat and front passenger seat). For example, the vehicle's dashboard may include input configurations for operating various functions inside the vehicle (e.g., air conditioning, audio system, navigation system).

[0253] In an embodiment, the display device 1 may be disposed on the vehicle's dashboard and may operate as an input portion configured to manipulate at least some of the various functions of the vehicle. The display device 1 may provide various information related to the vehicle, such as vehicle driving information (e.g., current speed, remaining fuel, vehicle distance traveled) and information about vehicle components (e.g., the level of tire damage).

[0254] Display device 1 can be configured to extend across the driver's seat and front passenger seat located at the front of the vehicle, as shown in the figure. Users of display device 1 can include the driver and passenger sitting in the front passenger seat. That is, both the driver and passenger can use display device 1.

[0255] Figure 20 The display device 1 shown may correspond to the display panel 50 included in the display device 1. Figure 3 At least some of them. For example, Figure 20 The display device 1 shown can show the display area AA of the display panel 50. Figure 3 ) and non-display area NA ( Figure 2 At least some of them. In addition to the components of display device 1. Figure 20 Other components besides the one shown can be installed inside the vehicle.

[0256] Embodiments of this disclosure have been described with reference to the accompanying drawings. Those skilled in the art will recognize that this disclosure may be implemented in other specific forms without departing from the spirit or essential characteristics of this disclosure. The described embodiments are to be considered illustrative in all respects only and not restrictive. Therefore, the scope of this disclosure is indicated by the appended claims rather than by the foregoing description. All modifications within the meaning and scope of equivalents of the claims are to be included within the scope of this disclosure.

[0257] Figure Labels

[0258] 1: Display device

[0259] 10: Timer Controller

[0260] 20: Gate driver

[0261] 30: Data Driver

[0262] 31: Multiplexer

[0263] 40: Power Supply Unit

[0264] 50: Display panel

Claims

1. A display device, comprising: A display panel, wherein pixels are provided on the display panel; A data driver integrated circuit, the data driver integrated circuit including an output buffer connected to an output channel and configured to output a data voltage to the pixel via a data line; as well as A multiplexer connected between the output channel and the data line, and including a switching element controlled by a multiplexing control signal. The pixels include: A first sub-pixel, the first sub-pixel being connected to a first data line and configured to display a color; and The second sub-pixel, connected to the second data line and configured to display the same color as the first sub-pixel, When the pixel operates in the first mode, the data driver integrated circuit is configured to output a first data voltage corresponding to the first image to the first sub-pixel, and to output a predetermined data voltage to the second sub-pixel. When the pixel operates in the second mode, the data driver integrated circuit is configured to output the predetermined data voltage to the first sub-pixel and to output a second data voltage corresponding to the second image to the second sub-pixel, wherein the predetermined data voltage is different from the first data voltage and the second data voltage.

2. The display device according to claim 1, in, The output channel is also connected to the ground voltage.

3. The display device according to claim 2, in, When the pixel operates in the first mode, the output channel is configured to output the first data voltage from the output buffer to the first sub-pixel and output the ground voltage to the second sub-pixel. When the pixel operates in the second mode, the output channel is configured to output the ground voltage to the first sub-pixel and output the second data voltage output from the output buffer to the second sub-pixel.

4. The display device according to claim 3, in, The output buffer is enabled based on a source output enable signal at the on level input from an external device, and Specifically, while outputting the ground voltage from the output channel, the source output enable signal is applied at a shutdown level.

5. The display device according to claim 1, in, The multiplexer includes: A first switching element is configured to be turned on according to a first multiplexing control signal and to connect the output channel to the first sub-pixel; A second switching element is configured to be turned on according to a second multiplexing control signal and to connect the output channel to the second sub-pixel; A first virtual switching element, configured to be turned on according to a first virtual multiplexing control signal, and connecting a virtual voltage line receiving the predetermined data voltage and the first data line to each other; and A second virtual switch element is configured to be turned on according to a second virtual multiplexing control signal and to connect the virtual voltage line and the second data line to each other.

6. The display device according to claim 5, in, The predetermined data voltage is the voltage corresponding to black grayscale.

7. The display device according to claim 5, in, When the pixel operates in the first mode, a second virtual multiplexing control signal at the on level is applied, and When the pixel operates in the second mode, the first virtual multiplexing control signal, which is at the on level, is applied.

8. The display device according to claim 7, in, The data driver integrated circuit is enabled based on a data driver enable signal input from an external device, and The data driver enable signal is applied at the off level in response to either the first virtual multiplexing control signal at the on level or the second virtual multiplexing control signal at the on level.

9. The display device according to claim 1, in, The display panel includes: The first unit pixel and the second unit pixel, each comprising two or more pixels. The multiplexer includes: A first switching element is configured to be turned on according to a first-1 multiplexing control signal and to connect the output channel to the first sub-pixel of the first unit pixel; A second switching element is configured to be turned on according to a second-first multiplexing control signal and to connect the output channel to the second sub-pixel of the first unit pixel; A third switching element, configured to be turned on according to a first-second multiplexing control signal, and connecting the output channel to the first sub-pixel of the second unit pixel; and A fourth switching element is configured to be turned on according to the second-2 multiplexing control signal and to connect the output channel to the second sub-pixel of the second unit pixel.

10. The display device according to claim 1, in, The display panel includes: A first region, in which a first image is displayed via the first sub-pixel; and The second region, in which a second image different from the first image is displayed through the second sub-pixel, and The first region and the second region are variable when the display panel is driven.

11. The display device according to claim 1, in, The first sub-pixel and the second sub-pixel have the same pixel structure, and The first sub-pixel and the second sub-pixel have mirror shapes along the pixel column direction.

12. The display device according to claim 1, further comprising: A lens component, which is disposed on the display panel and includes multiple lenses. The lens component includes: A first lens, wherein the first lens is disposed in the first light-emitting region of the first sub-pixel; and The second lens is disposed in the second light-emitting region of the second sub-pixel and has a shape different from that of the first lens.

13. The display device according to claim 12, in, The first lens is configured to control the emission of light emitted from the first light-emitting region at a first viewing angle, and The second lens is configured to control the emission of light emitted from the second light-emitting region at a second viewing angle that is wider than the first viewing angle.

14. A method for driving a display device, the display device comprising: A display panel, wherein pixels are provided on the display panel; A data driver integrated circuit, the data driver integrated circuit including an output buffer connected to an output channel and configured to output a data voltage to the pixel via a data line; The method includes: a multiplexer connected between the output channel and the data line and including a switching element controlled by a multiplexing control signal; the pixel comprising: a first sub-pixel connected to a first data line and configured to display a color; and a second sub-pixel connected to a second data line and displaying the same color as the first sub-pixel; the method comprising: The data driver integrated circuit outputs the data voltage to the first sub-pixel during a first time period within a horizontal time period; and The data driver integrated circuit outputs the data voltage to the second sub-pixel during a second time period within the first horizontal time period.

15. The method for driving a display device according to claim 14, in, When the pixel operates in the first mode, outputting the data voltage to the first sub-pixel includes: The first data voltage output from the output buffer is output to the output channel, and Wherein, when the pixel operates in the first mode, outputting the data voltage to the second sub-pixel includes: Output ground voltage to the output channel.

16. The method for driving a display device according to claim 15, in, When the pixel operates in the second mode, outputting the data voltage to the first sub-pixel includes: The ground voltage is output to the output channel, and Wherein, when the pixel operates in the second mode, outputting the data voltage to the second sub-pixel includes: The second data voltage output from the output buffer is output to the output channel.

17. The method for driving a display device according to claim 15, in, Outputting the data voltage to the first sub-pixel further includes: The output buffer is enabled in response to a source output enable signal that is at the on level, and The method of outputting the data voltage to the second sub-pixel further includes: The output buffer is disabled in response to the source output enable signal being at the off level.

18. The method for driving a display device according to claim 14, in, When the pixel operates in the first mode, outputting the data voltage to the first sub-pixel includes: In response to a first multiplexing control signal at the on level, the output buffer is connected to the first data line via the multiplexer, and Wherein, when the pixel operates in the first mode, outputting the data voltage to the second sub-pixel includes: In response to a second virtual multiplexing control signal that is at the on level, the virtual voltage line is connected to the second data line via the multiplexer.

19. The method for driving a display device according to claim 18, in, When the pixel operates in the second mode, outputting the data voltage to the first sub-pixel includes: In response to a first virtual multiplexing control signal at an on level, the virtual voltage line is connected to the first data line via the multiplexer, and Wherein, when the pixel operates in the second mode, outputting the data voltage to the second sub-pixel includes: In response to a second multiplexing control signal at the on level, the output buffer is connected to the second data line via the multiplexer.

20. The method for driving a display device according to claim 18, in, Outputting the data voltage to the first sub-pixel further includes: The data driver integrated circuit is enabled in response to a data driver enable signal at the on level, and The method of outputting the data voltage to the second sub-pixel further includes: The data driver integrated circuit is disabled in response to the data driver enable signal being at the off level.

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