Pixel-level frequency encoding type naked eye 3D display driving system, display method and medium

Abstract

The application relates to a pixel-level frequency coding naked-eye 3D display driving system, a display method and a medium, and relates to the technical field of naked-eye 3D display, wherein the system comprises: a display substrate, which is electrically connected with a driving integrated circuit; a GOA driving array, which is used for row-by-row selection of a pixel array based on a GOA signal to obtain a selected row; a driving integrated circuit, which is used for generating a target light-emitting frequency coding signal and a target light-emitting brightness coding signal of each pixel in the selected row, and outputting the target light-emitting frequency coding signal and the target light-emitting brightness coding signal to a column-level time-division multiplexing network; the column-level time-division multiplexing network, which is used for receiving the target light-emitting frequency coding signal and the target light-emitting brightness coding signal and outputting the target light-emitting frequency coding signal and the target light-emitting brightness coding signal to a pixel driving unit of each pixel in the selected row; and a pixel array, which is composed of a plurality of pixel driving units and is integrated on the display substrate, and the pixel driving unit is used for light-emitting frequency control and light-emitting brightness control of the pixel. The application has the effect of realizing naked-eye 3D display without relying on additional hardware.

Description

Technical Field

[0001] This application relates to the field of naked-eye 3D display technology, specifically to a pixel-level frequency-coded naked-eye 3D OLED driving system, display method, and medium. Background Technology

[0002] Glasses-free 3D display refers to a display technology that allows the left and right eyes to see images from different perspectives without the need for 3D glasses or other auxiliary devices. It relies on the optical structure of the display screen itself and driving algorithms to synthesize stereoscopic images in the brain using binocular parallax. Glasses-free 3D display technology provides a stereoscopic visual effect without the need for special glasses and has broad application prospects in consumer electronics, automotive displays, medical devices, and industrial design.

[0003] Currently, mainstream naked-eye 3D technologies are mainly divided into optical beam splitting and time-division multiplexing. Optical beam splitting mainly projects different images to the left and right eyes through optical elements; time-division multiplexing mainly uses the persistence of vision in the human eye to form stereoscopic vision by rapidly alternating the display of images to the left and right eyes. This type of technology requires active shutter glasses. The above two methods require additional optical elements and special glasses to achieve naked-eye 3D display. How to get rid of the dependence on additional hardware to achieve naked-eye 3D display is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In order to achieve naked-eye 3D display without relying on additional hardware, this application provides a pixel-level frequency-coded naked-eye 3D OLED driving system, display method and medium.

[0005] The first aspect of this application provides a pixel-level frequency-coded naked-eye 3D display driving system, specifically comprising: The display substrate is electrically connected to the driving integrated circuit. A GOA driving array, integrated on the display substrate, is used to select the pixel array row by row based on the GOA signal when the GOA signal output by the driving integrated circuit is received, thereby obtaining the selected row. The driving integrated circuit is used to receive 3D frame data and depth map of the content to be displayed, generate target emission frequency encoding signal and target emission brightness encoding signal of each pixel in the selected path according to the 3D frame data and the depth map, and output the target emission frequency encoding signal and the target emission brightness encoding signal to the column-level time-division multiplexing network. The target emission frequency encoding signal is a first frequency emission frequency encoding signal or a second frequency emission frequency encoding signal. The first frequency is the frequency allocated to the left eye image pixels, and the second frequency is the frequency allocated to the right eye image pixels. The column-level time-division multiplexing network, composed of multiple single-channel units integrated on the display substrate, is used to receive the target emission frequency encoding signal and the target emission brightness encoding signal, and write them into the latch in the single-channel unit based on the decoder and transmission gate in the single-channel unit. Within a single row cycle, the latch outputs the target emission frequency encoding signal and the target emission brightness encoding signal to the pixel driving unit of the corresponding pixel in the selected row; the duration for which the latch stores data is the row cycle. The pixel array consists of multiple pixel driving units integrated on the display substrate. The pixel driving units are used for controlling the emission frequency and brightness of the pixels.

[0006] By adopting the above technical solution, this system relies on the GOA driving array integrated on the display substrate to work in conjunction with the driving integrated circuit. The GOA driving array receives the GOA signal output by the driving integrated circuit and completes row-by-row selection of the pixel array, accurately locking the currently selected row to be driven, providing a precise row scanning timing basis for pixel-level independent signal writing. The driving integrated circuit receives the 3D frame data to be displayed and the corresponding depth map, abandoning the traditional optical beam splitting imaging logic, and through data analysis and calculation, independently matching and generating a unique target emission frequency encoding signal and target emission brightness encoding signal for each pixel in the selected row. Among them, by distinguishing the first frequency corresponding to the left eye image pixel and the second frequency corresponding to the right eye image pixel, the pixel-level frequency differentiation encoding of the left and right eye images is completed, realizing the micro-pixel-level separation of the left and right eye parallax images. At the same time, the independent brightness encoding signal ensures that the display brightness of each pixel is accurately controllable. Furthermore, by integrating on the display substrate A column-level time-division multiplexing network, consisting of a decoder, multiple transmission gates, and D-type latches, latches and outputs the received frequency and brightness encoded signals in a time-division manner. The D-type latches can stably latch and continuously output pixel drive signals within a row cycle, ensuring stable and time-sequence-free output of pixel signals within a single row cycle. Finally, the precisely encoded frequency and brightness signals are synchronously transmitted to each pixel drive unit of the pixel array, and the pixel drive unit independently completes the precise control of the emission frequency and brightness of a single pixel. This invention relies entirely on the pixel-level frequency encoding drive mechanism of the GOA drive array, column-level time-division multiplexing network, and pixel drive circuit integrated on the display substrate. It uses pixel parallax differentiation in the frequency dimension to replace the optical beam splitting method of traditional physical gratings and lenses. It can accurately achieve the separation and imaging of left and right eye parallax images without adding any external optical films or beam splitting hardware, realizing high-performance naked-eye 3D display without additional hardware dependence.

[0007] In one embodiment, the single-channel unit includes a 4-to-16 decoder, 16 transmission gates, and 16 D-type latches. The input of the 4-to-16 decoder is connected to the column time slot encoding signal output by the main control module in the driver integrated circuit. The output of the 4-to-16 decoder is connected to the control terminal of each of the transmission gates. The input of each transmission gate is connected in parallel to the column output channel of the driver integrated circuit. The output of each transmission gate is connected to the data input terminal of the corresponding D-type latch. The output of each D-type latch is connected to the pixel driving unit of the corresponding pixel.

[0008] In one embodiment, when the pixel array is an OLED pixel array, the pixel driving unit includes: transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11, a storage capacitor C1, and an OLED device. The source of transistor T1 is connected to a data signal line, its gate is connected to a scan signal line, and its drain is connected to the gate of transistor T2. The source of transistor T2 is connected to a VDD power line, and its drain is connected to the source of transistor T3. The drain of transistor T3 is connected to the upper plate of the storage capacitor C1, and its gate is connected to the drain of transistor T10. The source of transistor T4 is connected to a Vinit power line, its gate is connected to a scan signal line, and its drain is connected to the gate of transistor T2. The source of transistor T5 is connected to a Vinit power line, and its gate is connected to... The source of transistor T6 is connected to the data signal line, its gate is connected to the scan signal line, and its drain is connected to the gate of transistor T7. The source of transistor T7 is connected to the Vinit power line, and its drain is connected to the source of transistor T8. The gate of transistor T8 is connected to the frequency encoding signal line, and its drain is connected to the source of transistor T9. The gate of transistor T9 is connected to the brightness encoding signal line, and its drain is connected to the anode of the OLED device. The source of transistor T10 is connected to the drain of transistor T3, its gate is connected to the scan signal line, and its drain is connected to the gate of transistor T3. The source of transistor T11 is connected to the VDD power line, its gate is connected to the gate of transistor T2, and its drain is connected to the anode of the OLED device. The lower plate of the storage capacitor C1 is connected to the VSS power line. The cathode of the OLED device is connected to the VSS power line. Transistors T1, T2, T3, T4, T5, T6, and T7 are all used for data writing, reset, and threshold voltage compensation; transistor T8 is used to control the pixel's emission frequency; transistor T9 is used to control the pixel's emission brightness; transistors T10 and T11 are both used for auxiliary driving and current compensation; the storage capacitor C1 is used to store pixel data; and the OLED device is used for emission display.

[0009] In one embodiment, the latch is a D-type latch.

[0010] In one embodiment, the driver integrated circuit includes: A global clock generator is used to generate the system clock signal and frequency reference signal. The 3D content processing module is used to receive 3D frame data and depth map of the content to be displayed, and extract depth information, motion vectors and viewpoint information from the 3D frame data and the depth map; The main control module is used to generate emission frequency encoding signals and emission brightness encoding signals for each pixel based on the depth information, the motion vector, and the viewpoint information. A global synchronization module is used to synchronize the operating timing according to the system clock signal and the frequency reference signal; A brightness correction module is used to perform Gamma correction and non-uniformity correction on the luminous brightness encoding signal to obtain a corrected luminous brightness encoding signal; The column-driven module is used to generate target emission frequency encoding signals and target emission brightness encoding signals for each pixel in the selected row based on all the emission frequency encoding signals and all the corrected emission brightness encoding signals, and output them to the column-level time-division multiplexing network. The GOA driver module is used to generate GOA information and output the GOA signal to the GOA driver array.

[0011] In one embodiment, the first frequency ranges from [50 Hz, 70 Hz], the second frequency ranges from [100 Hz, 140 Hz], and the ratio of the first frequency to the second frequency is 1:2.

[0012] In one embodiment, the GOA driving array adopts a shift register cascade structure, and the GOA driving array is distributed on both sides of the pixel array.

[0013] In one embodiment, the display substrate is a glass substrate or a flexible substrate. When the display substrate is a glass substrate, the pixel array, the column-level time-division multiplexing network, and the GOA driving array are all fabricated on the glass substrate, and the driving integrated circuit is bonded to the glass substrate using a COG process. When the display substrate is a flexible substrate, the pixel array, the column-level time-division multiplexing network, and the GOA driving array are all fabricated on a flexible substrate, and the driving integrated circuit is bonded to the flexible substrate using a COF process.

[0014] A second aspect of this application provides a pixel-level frequency-coded glasses-free 3D display method, specifically including: Based on the GOA signal output by the driver integrated circuit, the pixel array integrated on the display substrate is selected row by row through the GOA driver array to determine the selected row. The GOA driver array is integrated on the display substrate. When the driving integrated circuit receives 3D frame data and depth map of the content to be displayed, it generates a target emission frequency encoding signal and a target emission brightness encoding signal for each pixel in the selected passage based on the 3D frame data and the depth map; the target emission frequency encoding signal is an emission frequency encoding signal of a first frequency or an emission frequency encoding signal of a second frequency, wherein the first frequency is the frequency allocated to the left eye image pixel and the second frequency is the frequency allocated to the right eye image pixel. The target emission frequency encoding signal and the target emission brightness encoding signal are output to the column-level time-division multiplexing network. Based on the decoder and transmission gate in the single-channel unit of the column-level time-division multiplexing network, the target emission frequency encoding signal and the target emission brightness encoding signal are written into the latch in the single-channel unit. Within a single row cycle, the target emission frequency encoding signal and the target emission brightness encoding signal are output to the pixel driving unit of the corresponding pixel in the pixel array through the latch. The column-level time-division multiplexing network is composed of multiple single-channel units. The duration of the data stored in the latch is the row cycle. The column-level time-division multiplexing network is integrated on the display substrate. The pixel driving unit controls the emission frequency and emission brightness of the corresponding pixels according to the target emission frequency encoding signal and the target emission brightness encoding signal.

[0015] A third aspect of this application provides a computer-readable storage medium storing a computer program that, when loaded and executed by a processor, performs the steps of the method described in any one of the first aspects.

[0016] In summary, this application includes at least one of the following beneficial technical effects: Relying on the GOA driving array integrated on the display substrate and working in conjunction with the driving integrated circuit, the GOA driving array receives the GOA signal output by the driving integrated circuit and completes row-by-row selection of the pixel array, accurately locking the currently selected row to be driven, providing a precise row scanning timing basis for pixel-level independent signal writing; the driving integrated circuit receives the 3D frame data to be displayed and the corresponding depth map, abandoning the traditional optical beam splitting imaging logic, and through data parsing and calculation, independently matching and generating a dedicated target emission frequency encoding signal and target emission brightness encoding signal for each pixel in the selected row. Specifically, by distinguishing the first frequency corresponding to the left-eye image pixel and the second frequency corresponding to the right-eye image pixel, pixel-level frequency differentiation encoding of the left and right eye images is completed, achieving micro-pixel-level separation of the left and right eye parallax images. Simultaneously, the independent brightness encoding signal ensures precise and controllable display brightness of each pixel. In the embodiments of this application, the driving integrated circuit writes its dedicated control data for each pixel through a column-level time-division multiplexing network in each row cycle of each frame. For the left-eye pixel emitting light at a first frequency (e.g., 60 Hz), the "brightness encoding signal" in its control data is valid in odd-numbered frames and "off" (all 0s) in even-numbered frames. For the right-eye pixel emitting light at a second frequency (e.g., 120 Hz), its "brightness encoding signal" is valid in every frame. The latch receives new data in each frame, is fully compatible with the time slot mechanism, and simultaneously implements different valid emission frequencies. The driver integrated circuit generates an independent "target emission frequency encoding signal" and "target emission brightness encoding signal" for each pixel in each frame, and performs a gain compensation of 2 on the brightness encoding signal of the left-eye pixel (first frequency). In non-valid frames, the brightness encoding signal of the left-eye pixel outputs an "off" sequence (all 0s). The two signals are then output to the column-level time-division multiplexing network through a 16:1 time-division multiplexing.

[0017] Furthermore, a column-level time-division multiplexing network, integrated on the display substrate and consisting of a decoder, multiple transmission gates, and latches, is used to latch and output the received frequency and brightness encoded signals in a time-division manner. The latches can stably latch and continuously output pixel drive signals within a row cycle, ensuring stable and time-series-free output of pixel signals within a single row cycle. In the embodiments of this application, the column-level time-division multiplexing network adopts a 16:1 time-division multiplexing structure. Before the start of each time slot, the output node of the transmission gate (i.e., the input terminal of the latch) is pre-charged to an intermediate level (e.g., VDD / 2). When the transmission gate is turned on, the signal only needs to swing from the intermediate level to the final high or low level, with the swing amplitude halved, thereby significantly shortening the setup time and ensuring reliable data writing within 482 nanoseconds. In each row cycle of each frame, dedicated control data containing frequency and brightness information is written to each of the 16 columns of pixels.

[0018] Finally, the precisely encoded frequency and brightness signals are synchronously transmitted to each pixel driving unit of the pixel array, and the pixel driving unit independently completes the precise control of the emission frequency and brightness of a single pixel. In the embodiment of this application, the pixel driving unit receives the "frequency encoded signal" and "brightness encoded signal" from the latch, treats these two signals as two independent enable signals, and performs a logical AND operation on the two signals through an AND gate. The output of the AND gate controls the final emission path switch. Specifically, the "frequency encoded signal" controls one switch to determine whether the pixel is eligible to emit light in this frame; the "brightness encoded signal" (i.e., the original time slot PWM sequence) controls another switch to determine the specific emission duration and mode under the premise of being eligible to emit light. The pixel will only emit light when both signals are valid at the same time. In this way, frequency control and brightness control are logically decoupled, but physically achieve precise coordination through the AND gate, and retain the original 11T1C structure for stable output of drive current.

[0019] This invention relies entirely on the pixel-level frequency encoding driving mechanism of the GOA driving array, column-level time-division multiplexing network and pixel driving circuit integrated on the display substrate. It uses the pixel parallax differentiation in the frequency dimension to replace the optical beam splitting method of traditional physical gratings and lenses. It can accurately realize the separation and imaging of left and right eye parallax images without adding any external optical film or beam splitting hardware, thus realizing high-performance naked-eye 3D display without additional hardware dependence.

[0020] In the embodiments of this application, the driver integrated circuit writes dedicated control data for each pixel through a column-level time-division multiplexing network in each row cycle of each frame. For the left-eye pixel emitting light at a first frequency (e.g., 60 Hz), the "brightness encoding signal" in its control data is valid in odd-numbered frames and "off" (all 0) in even-numbered frames; for the right-eye pixel emitting light at a second frequency (e.g., 120 Hz), its "brightness encoding signal" is valid in every frame. The latch receives new data in each frame, fully compatible with the time slot mechanism, and simultaneously realizes different effective emission frequencies. The driver integrated circuit generates independent "target emission frequency encoding signal" and "target emission brightness encoding signal" for each pixel in each frame, and performs a gain compensation of 2 on the brightness encoding signal of the left-eye pixel (first frequency) to balance the average brightness of the left and right eyes. In non-effective frames, it outputs an "off" sequence (all 0) for the brightness encoding signal of the left-eye pixel, and then outputs the two signals to the column-level time-division multiplexing network through a 16:1 time-division multiplexing.

[0021] The column-level time-division multiplexing network employs a 16:1 time-division multiplexing structure and integrates a pre-charge circuit. Before the start of each time slot, the output node of the transmission gate (i.e., the input of the latch) is pre-charged to an intermediate level (e.g., VDD / 2). When the transmission gate is turned on, the signal only needs to swing from the intermediate level to the final high or low level, with the swing amplitude halved, thus significantly shortening the setup time and ensuring reliable data writing within 482 nanoseconds. In each row cycle of each frame, dedicated control data containing frequency and brightness information is written to each of the 16 columns of pixels.

[0022] The pixel driving unit receives a "frequency-encoded signal" and a "brightness-encoded signal" from the latch, treating these two signals as two independent enable signals. An AND gate is used to logically AND these two signals, and the output of the AND gate controls the final light-emitting path switch. Specifically, the "frequency-encoded signal" controls one switch, determining whether the pixel is eligible to emit light in this frame; the "brightness-encoded signal" (i.e., the original time-slot PWM sequence) controls another switch, determining the specific light-emitting duration and mode if the pixel is eligible. The pixel will only emit light when both signals are simultaneously valid. In this way, frequency control and brightness control are logically decoupled, but physically precisely coordinated through the AND gate, while retaining the original 11T1C structure for stable output of the drive current. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the pixel-level frequency-coded naked-eye 3D display driving system provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of a single-channel unit provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a pixel driving unit provided in an embodiment of this application; Figure 4 This is a schematic flowchart of a pixel-level frequency-encoded naked-eye 3D display method provided in an embodiment of this application. Detailed Implementation

[0024] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0025] In the description of the embodiments of this application, words such as "exemplarily," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of words such as "exemplarily," "for example," or "for instance" is intended to present the relevant concepts in a specific manner.

[0026] In the description of the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, B existing alone, or A and B existing simultaneously. Furthermore, unless otherwise stated, the term "multiple" means two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized.

[0027] See Figure 1 This application discloses a pixel-level frequency-coded naked-eye 3D display driving system, applied to a display device, the specific details of which are as follows: This system independently encodes the emission frequency and brightness of each pixel at the pixel level, emitting light at a first frequency for the left-eye image and a second frequency for the right-eye image, with the first and second frequencies being unequal. Utilizing the biological visual characteristic that the human eye can still produce differential neural responses to light signals of different frequencies within a frequency band above the critical flicker fusion frequency, the viewer's visual cortex assigns different frequency light signals from the same display panel to the left and right eye visual processing channels respectively, thus achieving naked-eye stereoscopic vision display without relying on any optical beam splitters or assistive glasses. The system as a whole includes a display substrate, a GOA driving array integrated on the display substrate, a driving integrated circuit electrically connected to the display substrate, a column-level time-division multiplexing network integrated on the display substrate, and a pixel array integrated on the display substrate. These components work together to complete the entire workflow from 3D content reception, signal processing, signal distribution to independent pixel emission control. Furthermore, the display device can be a mobile phone, tablet, or television.

[0028] The display substrate, serving as the physical platform for the entire system, is electrically connected to the driver integrated circuit (GIC) via conductive leads. It houses and integrates the pixel array, column-level time-division multiplexing (TDM) network, and GOA driver array. The display substrate can be either a glass substrate or a flexible substrate, depending on the product form factor. When the display substrate is glass, the pixel array, column-level TDM network, and GOA driver array are all fabricated on the glass substrate surface using low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) technology. The driver integrated circuit is bonded to the non-display area at the edge of the glass substrate using COG (Chip-on-Glass) technology. The output pads of the driver integrated circuit are connected to the input terminals of the column-level TDM network and the GOA driver array, respectively, via metal traces on the glass substrate. When the display substrate is flexible, the substrate material is PI (polyimide) flexible material. The pixel array, column-level TDM network, and GOA driver array are all fabricated on this flexible material. The driver integrated circuit is bonded to the flexible substrate using COF (Chip-on-Flass) technology. Both substrate solutions share the same driver integrated circuit design, with completely identical signal interface definitions. Switching between different substrate solutions can be achieved without any modifications to the driver circuit.

[0029] The GOA (Graphical Oscillator) driver array is integrated onto the display substrate. Its function is to select the pixel array row by row based on the GOA signal received from the driver integrated circuit. The internal structure of the GOA driver array adopts a cascaded shift register structure, consisting of multiple shift registers connected end to end, with each shift register corresponding to one row of pixels in the pixel array. The GOA signal output by the driver integrated circuit includes two types: the GOA clock signal and the GOA start signal. The GOA clock signal is a periodic pulse signal used to drive the shift registers to shift row by row. The GOA start signal is a trigger pulse generated at the beginning of each frame, used to activate the first-stage shift register to output a valid row selection level. During operation, the GOA start signal triggers the first-stage shift register to output a valid row selection level at the beginning of the frame. Subsequently, at each valid edge of the GOA clock signal, the valid row selection level of the current-stage shift register is passed to the next-stage shift register, while the current stage returns to an invalid level. This process is repeated row by row to achieve row-by-row selection of the pixel array from the first row to the last row. The GOA (Gateway Availability) drive array is distributed on both sides of the pixel array. Specifically, the GOA units on the left drive odd-numbered rows, and the GOA units on the right drive even-numbered rows, with both sides working alternately. This dual-sided distribution structure shortens the trace distance for the row gating signal to reach the center of each row of pixels, reduces the RC delay of the signal, and minimizes waveform distortion of the row gating signal. When a row is selected, the row gating signal for that row is at an active level for a duration equal to one row cycle. During this row cycle, the switching transistors connected to the scan signal lines in the pixel drive units of all pixels in that row remain on, allowing external control signals to be written to the functional nodes inside the pixels. After the row gating signal becomes inactive, the pixels in that row enter a data holding and illumination state until the row is selected again in the next frame. The selected row refers to the row of pixels whose row gating signal is active at the current moment during line-by-line scanning. All pixel drive units within a row in the selected state can receive external data writes. The row cycle refers to the duration for which the GOA drive array maintains an active gating level for a row of pixels in the pixel array. Within a single row cycle, all pixels in that row complete the entire process of receiving data and latching the signal.

[0030] The driver integrated circuit is electrically connected to the display substrate. Its core function is to receive 3D frame data and depth maps of the content to be displayed, generate target emission frequency encoding signals and target emission brightness encoding signals for each pixel in the selected row based on the 3D frame data and depth maps, and output the target emission frequency encoding signals and target emission brightness encoding signals to the column-level time-division multiplexing network. The driver integrated circuit contains the following functional modules: a global clock generator, a 3D content processing module, a main control module, a global synchronization module, a brightness correction module, a column driver module, and a GOA driver module. The global clock generator is used to generate a system clock signal and a frequency reference signal. The system clock signal provides a unified working clock reference for all modules within the entire driver integrated circuit, and the frequency reference signal provides a time reference for the generation of the first and second frequencies. It should be noted that the frequency reference signal consists of N pulse width modulated carrier signals of different frequencies. The N carrier signals are continuously output in parallel at different frequencies to form a frequency signal library; the column driver module selects the carrier signal of the corresponding frequency for each pixel from this frequency signal library as the target emission frequency encoding signal for that pixel. In this embodiment, N=16, and the frequencies of the 16 carrier signals are 1Hz, 2Hz, 5Hz, 10Hz, 15Hz, 20Hz, 30Hz, 48Hz, 60Hz, 72Hz, 90Hz, 120Hz, 144Hz, 165Hz, 240Hz and 480Hz, respectively, covering the complete frequency range from ultra-low power consumption to ultra-high refresh rate.

[0031] The 3D content processing module receives 3D frame data and depth maps of the content to be displayed from an external image source, and extracts depth information, motion vectors, and viewpoint information from them. The 3D frame data contains pixel grayscale information from the left and right eye images. The depth map is a grayscale image corresponding to the spatial location of the 3D frame data, with each pixel location corresponding to a depth value ranging from 0 to 255, where 0 represents the farthest depth of field and 255 represents the closest depth of field. The depth map can be pre-generated by 3D content creation tools during the content creation stage, calculated in real-time by a stereo matching algorithm using a binocular camera, or inferred from 2D images by a monocular depth estimation neural network. Motion vectors are the displacement information of each pixel between adjacent frames extracted from continuous 3D frame data using inter-frame differencing and block matching algorithms. Viewpoint information is the optimal viewing angle corresponding to each pixel, calculated based on the depth information and motion vectors through geometric projection relationships. The main control module generates emission frequency and emission brightness encoded signals for each pixel based on the depth, motion vector, and viewpoint information output by the 3D content processing module. Simultaneously, it generates column time slot encoded signals to control the timing switching of the column-level time-division multiplexing network. The column time slot encoded signal is a multi-bit binary signal generated by the main control module, indicating which time slot within the row cycle is currently in. This signal is input to the decoder of a single-channel unit, where it is decoded to generate a one-hot code. The corresponding transmission gates are then sequentially selected to complete the timing allocation of the data.

[0032] The main control module determines the specific rules for pixel frequency allocation as follows: based on the eye-specific markers of each pixel in the 3D frame data, pixels belonging to the left-eye image are assigned a first-frequency emission frequency encoding signal, and pixels belonging to the right-eye image are assigned a second-frequency emission frequency encoding signal. Specifically, the index numbers of the first and second frequencies in the frequency signal library are converted into 4-bit binary codes, ultimately forming the emission frequency encoding signal which is sent to the column driver module. The global synchronization module is used to synchronize the working timing of the column driver module and the GOA driver module according to the system clock signal and the frequency reference signal, ensuring that the column data output timing is precisely aligned with the row gating timing, so that each row pixel can accurately receive the control data belonging to that row within the selected row period. The brightness correction module is used to perform Gamma correction and non-uniformity correction on the emission brightness encoding signal generated by the main control module to obtain the corrected emission brightness encoding signal. Gamma correction converts linear grayscale values ​​according to the non-linear characteristics of human visual perception, making the visual transition of the displayed grayscale uniform and natural, with a correction index of 2.2. Non-uniformity correction is based on the brightness deviation compensation coefficient of each pixel, which is calibrated and stored point by point when the panel leaves the factory. The brightness data of each pixel is then multiplied and corrected point by point to eliminate the brightness inconsistency in different areas of the panel caused by manufacturing process fluctuations.

[0033] The column-driven module generates target luminous frequency encoding signals and target luminous brightness encoding signals for each pixel in the selected row based on all luminous frequency encoding signals and the corrected luminous brightness encoding signals. These signals are then output to the column-level time-division multiplexing network via the column output channel. Specifically, the generation of the target luminous frequency encoding signal involves the column-driven module selecting the carrier signal corresponding to the target frequency from a frequency signal library based on the luminous frequency number signal. Similarly, the generation of the target luminous brightness encoding signal involves the brightness correction module sequentially performing Gamma correction and panel non-uniformity correction on the original grayscale values ​​of each pixel extracted from the 3D frame data by the main control module, and then outputting the corrected luminous brightness encoding signal. In this embodiment, the corrected grayscale value is a 4-bit binary data, ranging from 0000 to 1111, corresponding to 16 brightness levels from decimal 0 to 15. The brightness pulse width modulator in the column-driven module receives the corrected grayscale value corresponding to the current pixel.

[0034] Step 2: Convert grayscale values ​​into a time slot occupancy sequence. The brightness pulse width modulator uses a time slot pulse width modulation method to generate the target luminance encoding signal. Within one line cycle, the line cycle is evenly divided into a preset number of time slots, each with an equal duration. In this embodiment, the preset number is 16. This value is determined based on the following: the number of time slots should be an integer power of 2 to facilitate binary decoding control, and the duration of a single time slot should not be shorter than the response time of the self-emissive device used to ensure that the device can complete the bright / dark state switching within that time. Taking 1080P resolution and a 120Hz frame refresh rate as an example, the frame cycle is approximately 8.333ms, each frame cycle contains 1080 line cycles, each line cycle is approximately 7.716μs, and the duration of each time slot is approximately 482.25ns. The response time of OLED devices is in the microsecond range, and the response time of Micro-LED devices is in the nanosecond range, both meeting the time slot control accuracy requirements. In other embodiments, the preset number can also be 8 or 32. If a higher brightness resolution is required, it can be achieved by increasing the frame refresh rate or increasing the number of time slots.

[0035] The brightness pulse width modulator internally employs a grayscale-time slot mapping lookup table, converting the corrected 4-bit grayscale value into a 16-bit high / low level sequence. Each bit in this sequence corresponds to a time slot; an active level indicates that the pixel should emit light within that time slot, while an inactive level indicates that it should be off. Pixels with different brightness levels occupy different numbers of active time slots, with the number of slots being linearly proportional to the grayscale value. Furthermore, the active time slots are uniformly distributed within the row period to avoid excessive instantaneous current and brightness flicker. For example: 100% luminance level (grayscale value 15) occupies all 16 time slots (time slots 0 to 15), with a sequence of 1111111111111111; 50% luminance level (grayscale value 8) occupies 8 time slots (time slots 0, 2, 4, 6, 8, 10, 12, 14), with a sequence of 1010101010101010; 25% luminance level (grayscale value 4) occupies 4 time slots (time slots 0, 4, 8, 12), with a sequence of 1000100010001000; 6.25% luminance level (grayscale value 1) occupies 1 time slot (time slot 0), with a sequence of 10000000000000000; 0% luminance level (grayscale value 0) does not occupy any time slots, with a sequence of 00000000000000000.

[0036] Step 3: Serial output according to time slot sequence. Within each row cycle, the brightness pulse width modulator, as the column time slot encoding signal increments slot by slot, sequentially extracts the level value of the corresponding bit of the current time slot number from the 16-bit level sequence corresponding to the pixel, as the target luminance encoding signal of the pixel in the current time slot.

[0037] In addition, the GOA driver module is also used to generate GOA signals and output them to the GOA driver array. The GOA signals include a GOA clock signal and a GOA start signal. It should be noted that the content to be displayed is the content that needs to be shown to the user through a display device.

[0038] Furthermore, regarding the specific signal form and operation mode of the target emission frequency encoding signal: The target emission frequency encoding signal is a periodic high-low level alternating signal generated by the driving integrated circuit based on the eye-specific information of the pixel. This signal is output to the pixel driving unit and applied to the gate of the frequency control transistor. When the signal is at an effective level, the frequency control transistor is turned on, the driving current path of the pixel is connected, and the pixel is ready to emit light; when the signal is at an ineffective level, the frequency control transistor is turned off, the driving current path is cut off, and the pixel is turned off. This signal is periodically flipped at the target frequency, causing the pixel to periodically alternate between bright and dark at that frequency. The target emission frequency encoding signal is either a first frequency emission frequency encoding signal or a second frequency emission frequency encoding signal. The target frequency is either the first frequency or the second frequency. The first frequency is the frequency allocated to the left-eye image pixel, and the second frequency is the frequency allocated to the right-eye image pixel. The value range of the first frequency is 50Hz to 70Hz, and the value range of the second frequency is 100Hz to 140Hz. The ratio of the first frequency to the second frequency is 1:2. The selection of the aforementioned frequency range is based on the following criteria: the lower limit is not lower than the critical flicker perception threshold of the human eye, ensuring that viewers will not perceive pixel flicker and experience visual discomfort; the upper limit does not exceed the upper limit of the frequency resolution capability of the human visual cortex, ensuring that the brain can effectively distinguish between the two frequencies of light signals. The 1:2 ratio gives the two frequencies a simple integer multiple rhythmic relationship in the time domain, which is beneficial for system timing synchronization and reducing inter-frame alignment errors. In a preferred embodiment, the first frequency is 60Hz and the second frequency is 120Hz. For example, for a left-eye image pixel, the frequency-encoded signal generates an effective level pulse approximately every 16.67ms, causing the pixel to emit light 60 times per second; for a right-eye image pixel, the frequency-encoded signal generates an effective level pulse approximately every 8.33ms, causing the pixel to emit light 120 times per second. It's important to note that the human visual system responds differently to flickering light of different frequencies: when the flickering frequency is below approximately 50Hz, the human eye will clearly perceive the flicker; when the frequency is between 50-140Hz, the human eye will not perceive the flicker, but the visual cortex of the brain can still distinguish signals of different frequencies and send them to the visual processing channels of the left and right eyes respectively; when the frequency is above 140Hz, the human eye cannot distinguish signals of different frequencies at all. Furthermore, the photoreceptor cells and optic nerves of the human eye are capable of distinguishing different flickering frequencies. When two sets of pixels alternately emit light at different fixed frequencies, the human eye forms a visual filtering effect: the left eye prioritizes capturing images of one frequency, and the right eye prioritizes capturing images of another frequency, achieving a natural separation of the left and right views. This replaces the beam splitting / time splitting function of traditional gratings and shutter glasses, providing users with a naked-eye 3D experience.

[0039] It should be noted that the target emission frequency encoding signal and the target emission brightness encoding signal are output synchronously on the column output channel in a time-division multiplexing manner. Within each time slot, the column output channel simultaneously carries both signals of the current pixel.

[0040] Furthermore, the column-level time-division multiplexing network consists of multiple single-channel units integrated on the display substrate and is located between the column output terminal of the driver integrated circuit and the pixel array. The single-channel unit includes a decoder, a preset number of transmission gates, and a preset number of latches. In this embodiment, the single-channel unit includes a 4-16 decoder, 16 transmission gates, and 16 D-type latches.

[0041] The column-level time-division multiplexing network receives the target emission frequency encoding signal and the target emission brightness encoding signal output from the driver integrated circuit and writes them into each D-type latch in the single-channel unit. Within a single row cycle, it outputs these signals to the pixel driving unit of each pixel in the selected row. The 4-to-16 decoder is a combinational logic circuit with 4-bit binary input and 16-bit one-hot code output. Its 4-bit input is connected to the column time slot encoding signal output by the main control module in the driver integrated circuit. The column time slot encoding signal is a 4-bit binary code, ranging from 0000 to 1111, corresponding to decimal 0 to 15, indicating the 0th to 15th time slot in a row cycle. Based on the input column time slot encoding signal, the 4-to-16 decoder sets one of its 16 outputs to an active level and the remaining 15 to an inactive level. The 16 outputs of the 4-to-16 decoder are connected to the control terminals of 16 transmission gates. The inputs of each transmission gate are connected in parallel to the same column output channel of the driver integrated circuit, meaning that the 16 transmission gates share the same data input source, which is the encoded signal data output by the driver integrated circuit through the column output channel in the current time slot. The output of each transmission gate is connected to the data input of its corresponding D-type latch. A transmission gate is an analog switch circuit; it conducts when its control terminal is at an active level, transmitting the signal from the input terminal to the output terminal without loss; when its control terminal is at an inactive level, it is cut off, maintaining a high-blocking open state between the input and output terminals. The output of each D-type latch is connected to the pixel driver unit of the corresponding pixel. A D-type latch is a sequential logic circuit; when its data input terminal receives data during the enable period, it latches the data and holds it continuously at the output terminal. Even if the data at the input terminal changes or the input path is disconnected, the data at the output terminal remains unchanged. The duration of data retention for each D-type latch is one row cycle. That is, after data is written at the beginning of a row cycle, the data is continuously and effectively output to the corresponding pixel throughout the entire row cycle, and is overwritten and updated by new data when the corresponding time slot of the next row cycle arrives.

[0042] The specific operation of the column-level time-division multiplexing network within one row cycle is as follows: The main control module first outputs the column time slot encoding signal 0000. The 4-16 decoder decodes this as output 0 being valid, and the 0th transmission gate is turned on. At this time, the driver IC outputs the target emission frequency encoding signal and target emission brightness encoding signal of the first column pixel corresponding to this single-channel unit through the column output channel. This data is written to the 0th D-type latch and latched through the turned-on 0th transmission gate. Subsequently, the main control module updates the column time slot encoding signal to 0001. After decoding by the 4-16 decoder, output 1 is valid, and the 1st transmission gate is turned on. At this time, the column output channel outputs the data of the second column pixel, which is written to the 1st D-type latch through the 1st transmission gate. This process continues. In the 15th time slot, the column time slot encoding signal is 1111, the 15th transmission gate is turned on, and the data of the 16th column pixel is written to the 15th D-type latch. During the sequential writing process described above, the D-type latches that have completed writing continue to hold the latched data after their corresponding transmission gates close, continuously providing stable control signals to the pixel driving unit of the corresponding pixel through their output terminals. After all 16 time slots are completed, the 16 D-type latches each hold independent control data for their respective column pixels, and all 16 columns of pixels are simultaneously under control. For the entire display panel, multiple single-channel units work in parallel, and all single-channel units receive the same set of column time slot encoding signals, thus switching synchronously. Data writing for all column pixels can be completed within one row cycle. For details, please refer to [link to documentation]. Figure 2 Taking 1920 columns of pixels as an example, a total of 120 single-channel units are required to work in parallel, each responsible for 16 columns. The column output channels of the 120 single-channel units are independent of each other, and each receives its own data from the 120 column output ports of the driver integrated circuit.

[0043] Furthermore, regarding the crucial role of column-level time-division multiplexing networks in achieving independent frequency control: without D-type latches, when the transmission gate switches from the current column to the next, the control signal for the current column immediately disappears, and the pixel, having lost its control signal, cannot emit light stably at the target frequency. The introduction of D-type latches solves this problem, ensuring that each pixel always obtains stable and independent frequency-coded and luminance-coded signals throughout the entire row cycle. For the left-eye pixel emitting light at the first frequency, the driver integrated circuit writes valid emission data to its corresponding D-type latch every two frame cycles, and writes extinguishing data in the frame cycle between the two writes, thereby enabling the pixel to emit light periodically at the first frequency; for the right-eye pixel emitting light at the second frequency, the driver integrated circuit writes valid emission data to its corresponding D-type latch in every frame cycle, enabling the pixel to emit light continuously at the second frequency.

[0044] The pixel array consists of multiple pixel driving units integrated on the display substrate. The pixel driving units are used for controlling the emission frequency and brightness of the pixels. When the pixel array is an OLED pixel array, each pixel driving unit adopts an 11T1C structure, including transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, a storage capacitor C1, and the OLED device. The specific connections of each component are as follows: the source of transistor T1 is connected to the data signal line, the gate is connected to the scan signal line, and the drain is connected to the gate of transistor T2; the source of transistor T2 is connected to the VDD power supply line, and the drain is connected to the source of transistor T3; the drain of transistor T3 is connected to the upper plate of storage capacitor C1, and the gate is connected to the drain of transistor T10; the source of transistor T4 is connected to the Vinit power supply line, the gate is connected to the scan signal line, and the drain is connected to the gate of transistor T2; the source of transistor T5 is connected to the Vinit power supply line, the gate is connected to the scan signal line, and the drain is connected to the gate of transistor T3; the source of transistor T6 is connected to the data signal line, the gate is connected to the scan signal line, and the drain is connected to... The gate of transistor T7 is connected; the source of transistor T7 is connected to the Vinit power supply line, and the drain is connected to the source of transistor T8; the gate of transistor T8 is connected to the frequency encoding signal line, and the drain is connected to the source of transistor T9; the gate of transistor T9 is connected to the brightness encoding signal line, and the drain is connected to the anode of the OLED device; the source of transistor T10 is connected to the drain of transistor T3, the gate is connected to the scan signal line, and the drain is connected to the gate of transistor T3; the source of transistor T11 is connected to the VDD power supply line, the gate is connected to the gate of transistor T2, and the drain is connected to the anode of the OLED device; the lower plate of storage capacitor C1 is connected to the VSS power supply line; the cathode of the OLED device is connected to the VSS power supply line. Transistors T1 to T7 work together for data writing, internal node reset, and threshold voltage compensation for the driving transistors. During the reset phase, the scan signal line is active, and transistors T1, T4, T5, T6, and T10 are turned on. The gates of transistors T2, T3, and T7, as well as the upper plate of storage capacitor C1, are reset to the Vinit voltage. During the data writing phase, brightness data output from the data signal line is written to the gate of T2 via T1, while frequency data is written to the gate of T7 via T6. T10 shorts the gate and drain of T3 to form a diode connection structure to achieve threshold voltage compensation. Transistor T8 is a frequency control transistor. Its gate is connected to the frequency encoding signal line, receiving the target emission frequency encoding signal output from the D-type latch. This signal controls T8 to periodically turn on and off at the target frequency, thereby controlling the pixel's emission frequency. Transistor T9 is a brightness control transistor. Its gate is connected to the brightness encoding signal line and receives the target light emission brightness encoding signal output from the D-type latch. The conduction time of T9 is controlled by this signal in each light emission cycle, thereby controlling the light emission brightness of the pixel.Transistors T10 and T11 are used for auxiliary driving and current compensation: T10 achieves self-compensation of the threshold voltage of T3 during the reset phase, and T11, as an auxiliary driving transistor, together with T2, provides a stable driving current for the OLED device. Storage capacitor C1 stores the pixel data voltage after row gating, maintaining the gate potential of T2 stable throughout the entire frame period. The OLED device, as a light-emitting element, emits light when it receives the driving current. During the light-emitting phase, the scan signal line becomes inactive, and T1, T4, T5, T6, and T10 are all turned off, allowing the pixel to enter an independent light-emitting state. At this time, the conduction and cutoff of T8 and T9 are entirely determined by the frequency encoding signal and the brightness encoding signal. T2 and T11 provide the driving current to the OLED device based on the voltage held on storage capacitor C1, and the OLED device emits light according to the target frequency and target brightness. See details below. Figure 3 , Figure 3 In this context, ELVDD stands for VDD power line, DATA stands for data signal line, Scan stands for scan signal line, Vinit stands for Vinit power line, ELVSS stands for VSS power line, Freq_Code stands for frequency encoding signal line, and Bright_Code stands for brightness encoding signal line.

[0045] When the pixel array is a Micro-LED pixel array, since Micro-LED devices are inorganic semiconductor devices, their threshold voltage consistency is better than that of OLED devices. Furthermore, they use a constant voltage driving method and do not require threshold voltage compensation or current compensation circuits. Therefore, the pixel driving unit is simplified to a 7T1C structure, omitting transistors T3, T10, and T11 from the aforementioned 11T1C structure. The OLED devices in the 11T1C structure are replaced with Micro-LED devices, and the connection relationships between the remaining transistors remain consistent with the 11T1C structure. Specifically, the structure includes transistors T1, T2, T4, T5, T6, T7, T8, T9, storage capacitor C1, and the Micro-LED device. For details, please refer to [link to relevant documentation]. Figure 3 This achieves compatibility with both OLED and Micro-LED, two mainstream self-emissive display technologies. For Micro-LED, the pixel circuit can be simplified to a 7T1C structure, further improving the aperture ratio and reducing costs; at the same time, utilizing the nanosecond-level response speed of Micro-LED, the crosstalk rate can be as low as below 0.05%, and the refresh rate can reach above 3840Hz, giving it an irreplaceable advantage in the AR / VR micro-display field.

[0046] In summary, this system receives 3D content through a driver integrated circuit and generates independent frequency and brightness encoding signals for each pixel. The data holding function of the D-type latch in the column-level time-division multiplexing network ensures that each pixel always receives a stable independent control signal throughout the row cycle. The series connection of the frequency control transistor and brightness control transistor in the pixel driver unit achieves decoupled control of frequency and brightness respectively. The row-by-row gating of the GOA driver array ensures that each row of pixels receives data sequentially. Through the coordinated operation of all parts, pixel-level frequency-independent encoding naked-eye 3D display is achieved. This system achieves naked-eye 3D display effects without relying on any optical beam splitters or auxiliary glasses, avoiding the resolution and brightness losses found in traditional solutions. The column-level time-division multiplexing network reduces the number of column output channels of the driver integrated circuit to one-sixteenth of the original number through 16:1 time-division multiplexing, reducing chip area and cost. The D-type latch maintains the control signal of each column pixel for an entire row cycle, providing hardware support for pixel-level frequency-independent encoding. The system is compatible with both glass substrates and flexible substrates.

[0047] In another embodiment, the driving system of the present invention supports not only pixel-level frequency-encoded 3D display mode, but also a global time-division alternating 3D display mode. This mode is suitable for 3D content sources with left and right eye separation format and no pixel-by-pixel depth map.

[0048] In the global time-division alternating 3D display mode, the system operates at a total refresh rate of 240Hz, and the working process is as follows: Frame 1 (0 to 1 / 240 seconds): The main control module generates a global left-eye identification signal, and the global clock generator sets the frame reference frequency to 240Hz. The driver IC sends the complete frame data of the left-eye image to the column driver module, which writes the complete frame data of the left-eye image into the pixel driver unit of all pixels through a column-level time-division multiplexing network. At this time, the gate of the frequency control transistor T8 receives a uniform high-level enable signal, and the T8 of all pixels is turned on simultaneously, so all pixels display the left-eye image in a uniform manner. Display result: The screen displays the complete left-eye view.

[0049] Frame 2 (1 / 240 to 2 / 240 seconds): The main control module immediately switches the global identifier signal to the global right-eye identifier signal. The driver IC sends the complete frame of right-eye image data to the column driver module, which writes the right-eye data into the pixel driver units of all pixels through the column-level time-division multiplexing network. All pixels display the right-eye image. Display result: The screen displays the complete right-eye view.

[0050] High-speed loop: The system continuously alternates in the above manner, displaying 240 frames per second, with 120 frames for the left eye and 120 frames for the right eye. Since the refresh rate of 120Hz per eye is far higher than the critical flicker fusion frequency of the human eye (typically 60-90Hz), the viewer will not perceive screen flicker. The visual cortex of the human brain fuses the continuous image streams received by the left and right eyes, thus producing a stereoscopic visual effect.

[0051] Comparison and complementarity between global time-division alternation mode and pixel-level frequency coding mode: The advantages of pixel-level frequency encoding mode are: different pixels can be independently assigned different emission frequencies, and the frequency and brightness of foreground and background pixels can be dynamically adjusted according to depth information. The 3D effect has high precision and low power consumption, making it suitable for high-quality 3D content with pixel-by-pixel depth maps.

[0052] The advantages of the global time-division alternation mode are: all pixels switch uniformly, the driving logic is simple, the left and right eye images are completely independent without crosstalk, it has strong compatibility with 3D content formats (only the left and right eye images are needed), it is suitable for traditional left and right eye separated format 3D video content, and the single eye frame rate is as high as 120Hz, which can obtain smoother motion pictures.

[0053] Both modes share the same hardware architecture, and can be dynamically switched between the two modes through the mode switching signal of the main control module without any hardware modification.

[0054] See Figure 4 This application discloses a flowchart of a pixel-level frequency-encoded glasses-free 3D display method, which can be implemented using a computer program. This computer program can be integrated into an application or run as a standalone utility application, specifically including: S1: Based on the GOA signal output by the driver integrated circuit, the pixel array integrated on the display substrate is selected row by row through the GOA driver array to determine the selected row.

[0055] S2: When the driver integrated circuit receives 3D frame data and depth map of the content to be displayed, it generates target emission frequency encoding signal and target emission brightness encoding signal of each pixel in the selected passage based on the 3D frame data and depth map.

[0056] S3: Output the target emission frequency encoding signal and the target emission brightness encoding signal to the column-level time-division multiplexing network, and write the target emission frequency encoding signal and the target emission brightness encoding signal into the latch in the single-channel unit based on the decoder and transmission gate in the single-channel unit within the column-level time-division multiplexing network. Within a single row cycle, output the target emission frequency encoding signal and the target emission brightness encoding signal to the pixel driving unit of the corresponding pixel in the pixel array through the latch.

[0057] S4: The pixel driving unit controls the emission frequency and emission brightness of the corresponding pixels according to the target emission frequency encoding signal and the target emission brightness encoding signal.

[0058] Specifically, the GOA driver module of the driver integrated circuit outputs a GOA start signal at the start of the frame to trigger the first-stage shift register in the GOA driver array to output a valid row strobe level, making the first row of the pixel array a strobe row. Subsequently, driven by the GOA clock signal, the strobe rows advance sequentially from the first row to the last row. The switching transistors connected to the scan signal lines in all pixel driver units within the strobe row remain on during the row cycle, allowing external signals to be written into the pixel.

[0059] Secondly, the driver integrated circuit receives 3D frame data and depth maps. The internal 3D content processing module extracts depth information, motion vectors, and viewpoint information. The main control module assigns a first-frequency emission frequency encoding signal to the left-eye pixels and a second-frequency emission frequency encoding signal to the right-eye pixels according to their eye-specific assignment. The preferred first frequency is 60Hz and the second frequency is 120Hz, with a 1:2 ratio for easy timing synchronization. The lower limit of the frequency is not lower than the human eye's critical flicker perception threshold, and the upper limit does not exceed the upper limit of the visual cortex's frequency resolution. After the brightness correction module performs Gamma correction and panel non-uniformity correction on the original grayscale values, the column driver module generates the target emission brightness encoding signal using a time-slot pulse width modulation method. The column driver module outputs the target emission frequency encoding signal and the target emission brightness encoding signal to the column-level time-division multiplexing network through the column output channel.

[0060] Furthermore, in this embodiment, within a single row cycle, the 4-16 decoders of each single-channel unit in the column-level time-division multiplexing network sequentially turn on transmission gates 0 to 15 according to the column time slot encoding signal output by the main control module, writing the data of the corresponding column pixels into the corresponding D-type latches. Each D-type latch latches the received data and maintains it at the output for an entire row cycle, converting the serial write into parallel output to the pixel driver unit of the corresponding pixel, so that the 16 columns of pixels simultaneously obtain their own independent control signals throughout the entire row cycle. All single-channel units share the same set of column time slot encoding signals and work synchronously and in parallel, completing the signal allocation of all column pixels within a single row cycle. Finally, the pixel driver unit that receives the target emission frequency encoding signal and the target emission brightness encoding signal controls the emission frequency and emission brightness of the corresponding pixel according to the target emission frequency encoding signal and the target emission brightness encoding signal. This is prior art and will not be described in detail here.

[0061] The implementation principle of a pixel-level frequency-encoded naked-eye 3D display method in this application is as follows: Relying on the collaborative work of a GOA driving array integrated on the display substrate and a driving integrated circuit, the GOA driving array receives the GOA signal output by the driving integrated circuit and completes row-by-row selection of the pixel array, accurately locking the currently selected row to be driven, providing a precise row scanning timing basis for writing pixel-level independent signals; the driving integrated circuit receives the 3D frame data to be displayed and the corresponding depth map, abandoning the traditional optical beam splitting imaging logic, and through data parsing and calculation, independently matching and generating a dedicated target emission frequency encoding signal and target emission brightness encoding signal for each pixel in the selected row. Specifically, by distinguishing the first frequency corresponding to the left-eye image pixel and the second frequency corresponding to the right-eye image pixel, pixel-level frequency differentiation encoding of the left and right eye images is completed, achieving micro-pixel-level separation of the left and right eye parallax images. Simultaneously, the independent brightness encoding signal ensures precise and controllable display brightness of each pixel; further... An integrated column-level time-division multiplexing network (TDN), consisting of a decoder, multiple transmission gates, and D-type latches, latches and outputs the received frequency and brightness encoded signals in a time-division manner. The D-type latches can stably latch and continuously output pixel drive signals within a row cycle, ensuring stable and time-sequence-free output of pixel signals within a single row cycle. Finally, the precisely encoded frequency and brightness signals are synchronously transmitted to each pixel drive unit of the pixel array, allowing the pixel drive unit to independently and precisely control the emission frequency and brightness of a single pixel. This invention relies entirely on the pixel-level frequency encoding drive mechanism of the GOA drive array, column-level time-division multiplexing network, and pixel drive circuit integrated on the display substrate. It uses pixel parallax differentiation in the frequency dimension to replace the optical beam splitting method of traditional physical gratings and lenses. It can accurately achieve the separation and imaging of left and right eye parallax images without adding any external optical films or beam splitting hardware, realizing high-performance naked-eye 3D display without additional hardware dependence.

[0062] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0063] This application also discloses a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements a pixel-level frequency-coded naked-eye 3D display method according to the above embodiments.

[0064] The computer program can be stored in a computer-readable medium. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or certain middleware. The computer-readable medium includes any entity or device capable of carrying computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the computer-readable medium includes, but is not limited to, the above-mentioned components.

[0065] The pixel-level frequency-coded naked-eye 3D display method of the above embodiment is stored in the computer-readable storage medium and loaded and executed on the processor to facilitate the storage and application of the above method.

[0066] This application also discloses a display device, which can be an electronic device such as a desktop computer, laptop computer, mobile phone, or television. The display device includes, but is not limited to, a processor and a memory. For example, the display device may also include input / output devices, network access devices, and buses.

[0067] The processor can be a central processing unit (CPU). Of course, depending on the actual use, it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), off-the-shelf programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc., and this application does not limit it.

[0068] The memory can be an internal storage unit of the display device, such as a hard disk or RAM of the display device, or an external storage device of the display device, such as a plug-in hard disk, smart memory card (SMC), secure digital card (SD), or flash memory card (FC) equipped on the display device. Furthermore, the memory can be a combination of an internal storage unit and an external storage device of the display device. The memory is used to store computer programs and other programs and data required by the display device. The memory can also be used to temporarily store data that has been output or will be output. This application does not limit this.

[0069] In this display device, a pixel-level frequency-encoded naked-eye 3D display method according to the above embodiment is stored in the memory of the display device and loaded and executed on the processor of the display device for convenient use.

[0070] The foregoing description is merely an exemplary embodiment of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A pixel-level frequency-encoded naked-eye 3D display driving system, applied to a display device, characterized in that, include: The display substrate is electrically connected to the driver integrated circuit. A GOA driving array, integrated on the display substrate, is used to select the pixel array row by row based on the GOA signal when the GOA signal output by the driving integrated circuit is received, thereby obtaining the selected row. The driving integrated circuit is used to receive 3D frame data and depth map of the content to be displayed, generate target emission frequency encoding signal and target emission brightness encoding signal of each pixel in the selected path according to the 3D frame data and the depth map, and output the target emission frequency encoding signal and the target emission brightness encoding signal to the column-level time-division multiplexing network. The target emission frequency encoding signal is a first frequency emission frequency encoding signal or a second frequency emission frequency encoding signal. The first frequency is the frequency allocated to the left eye image pixels, and the second frequency is the frequency allocated to the right eye image pixels. The column-level time-division multiplexing network, composed of multiple single-channel units integrated on the display substrate, is used to receive the target emission frequency encoding signal and the target emission brightness encoding signal, and write them into the latch in the single-channel unit based on the decoder and transmission gate in the single-channel unit. Within a single row cycle, the latch outputs the target emission frequency encoding signal and the target emission brightness encoding signal to the pixel driving unit of the corresponding pixel in the selected row; the duration for which the latch stores data is the row cycle. The pixel array consists of multiple pixel driving units integrated on the display substrate. The pixel driving units are used for controlling the emission frequency and brightness of the pixels.

2. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1, characterized in that, The single-channel unit includes a 4-to-16 decoder, 16 transmission gates, and 16 latches. The input of the 4-to-16 decoder is connected to the column time slot encoding signal output by the main control module in the driver integrated circuit. The output of the 4-to-16 decoder is connected to the control terminal of each transmission gate. The input of each transmission gate is connected in parallel to the column output channel of the driver integrated circuit. The output of each transmission gate is connected to the data input terminal of the corresponding latch. The output of each latch is connected to the pixel driving unit of the corresponding pixel.

3. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1, characterized in that, When the pixel array is an OLED pixel array, the pixel driving unit includes: transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, and T11, a storage capacitor C1, and an OLED device. The source of transistor T1 is connected to a data signal line, its gate is connected to a scan signal line, and its drain is connected to the gate of transistor T2. The source of transistor T2 is connected to the VDD power line, and its drain is connected to the source of transistor T3. The drain of transistor T3 is connected to the upper plate of the storage capacitor C1, and its gate is connected to the drain of transistor T10. The source of transistor T4 is connected to the Vinit power line, its gate is connected to a scan signal line, and its drain is connected to the gate of transistor T2. The source of transistor T5 is connected to the Vinit power line, and its gate is connected to the scan signal line. The source of transistor T6 is connected to the data signal line, the gate is connected to the scan signal line, and the drain is connected to the gate of transistor T7. The source of transistor T7 is connected to the Vinit power line, and the drain is connected to the source of transistor T8. The gate of transistor T8 is connected to the frequency encoding signal line, and the drain is connected to the source of transistor T9. The gate of transistor T9 is connected to the brightness encoding signal line, and the drain is connected to the anode of the OLED device. The source of transistor T10 is connected to the drain of transistor T3, the gate is connected to the scan signal line, and the drain is connected to the gate of transistor T3. The source of transistor T11 is connected to the VDD power line, the gate is connected to the gate of transistor T2, and the drain is connected to the anode of the OLED device. The lower plate of the storage capacitor C1 is connected to the VSS power line. The cathode of the OLED device is connected to the VSS power line. Transistors T1, T2, T3, T4, T5, T6, and T7 are all used for data writing, reset, and threshold voltage compensation; transistor T8 is used to control the pixel's emission frequency; transistor T9 is used to control the pixel's emission brightness; transistors T10 and T11 are both used for auxiliary driving and current compensation; the storage capacitor C1 is used to store pixel data; and the OLED device is used for emission display.

4. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1 or 2, characterized in that, The latch is a D-type latch.

5. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1, characterized in that, The driver integrated circuit includes: A global clock generator is used to generate the system clock signal and frequency reference signal. The 3D content processing module is used to receive 3D frame data and depth map of the content to be displayed, and extract depth information, motion vectors and viewpoint information from the 3D frame data and the depth map; The main control module is used to generate emission frequency encoding signals and emission brightness encoding signals for each pixel based on the depth information, the motion vector, and the viewpoint information. A global synchronization module is used to synchronize the operating timing according to the system clock signal and the frequency reference signal; A brightness correction module is used to perform Gamma correction and non-uniformity correction on the luminous brightness encoding signal to obtain a corrected luminous brightness encoding signal; The column-driven module is used to generate target emission frequency encoding signals and target emission brightness encoding signals for each pixel in the selected row based on all the emission frequency encoding signals and all the corrected emission brightness encoding signals, and output them to the column-level time-division multiplexing network. The GOA driver module is used to generate GOA information and output the GOA signal to the GOA driver array.

6. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1, characterized in that, The first frequency has a range of [50 Hz, 70 Hz], the second frequency has a range of [100 Hz, 140 Hz], and the ratio of the first frequency to the second frequency is 1:

2.

7. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1, characterized in that, The GOA driving array adopts a shift register cascade structure, and the GOA driving array is distributed on both sides of the pixel array.

8. The pixel-level frequency-coded naked-eye 3D display driving system according to claim 1, characterized in that, The display substrate is a glass substrate or a flexible substrate. When the display substrate is a glass substrate, the pixel array, the column-level time-division multiplexing network, and the GOA driving array are all fabricated on the glass substrate, and the driving integrated circuit is bonded to the glass substrate by COG process. When the display substrate is a flexible substrate, the pixel array, the column-level time-division multiplexing network, and the GOA driving array are all fabricated on the flexible substrate, and the driving integrated circuit is bonded to the flexible substrate by COF process.

9. A pixel-level frequency-encoded glasses-free 3D display method, characterized in that, The method includes: Based on the GOA signal output by the driver integrated circuit, the pixel array integrated on the display substrate is selected row by row through the GOA driver array to determine the selected row. The GOA driver array is integrated on the display substrate. When the driving integrated circuit receives 3D frame data and depth map of the content to be displayed, it generates a target emission frequency encoding signal and a target emission brightness encoding signal for each pixel in the selected passage based on the 3D frame data and the depth map; the target emission frequency encoding signal is an emission frequency encoding signal of a first frequency or an emission frequency encoding signal of a second frequency, wherein the first frequency is the frequency allocated to the left eye image pixel and the second frequency is the frequency allocated to the right eye image pixel. The target emission frequency encoding signal and the target emission brightness encoding signal are output to the column-level time-division multiplexing network. Based on the decoder and transmission gate in the single-channel unit of the column-level time-division multiplexing network, the target emission frequency encoding signal and the target emission brightness encoding signal are written into the latch in the single-channel unit. Within a single row cycle, the target emission frequency encoding signal and the target emission brightness encoding signal are output to the pixel driving unit of the corresponding pixel in the pixel array through the latch. The column-level time-division multiplexing network is composed of multiple single-channel units. The duration of the data stored in the latch is the row cycle. The column-level time-division multiplexing network is integrated on the display substrate. The pixel driving unit controls the emission frequency and emission brightness of the corresponding pixels according to the target emission frequency encoding signal and the target emission brightness encoding signal.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is loaded and executed by the processor, it implements the method of claim 9.

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