A driving circuit and a display panel

Abstract

The application belongs to the technical field of display, and particularly relates to a driving circuit and a display panel. The driving circuit comprises N cascaded driving modules. The nth driving module comprises: a gate driving unit configured to output a gate driving signal of a current stage under the action of a signal output by an nth-i driving module, a first clock signal and a second clock signal of the current stage, wherein the phase of the first clock signal is opposite to that of the second clock signal, and the gate driving signal is an effective frame signal in a sampling stage; a switching unit configured to output a switching control signal under the action of the signal output by the nth-i driving module and the gate driving signal of the current stage, wherein the switching control signal is an effective frame signal in a light emitting stage; and a light emitting control unit configured to output a light emitting control signal of the current stage under the action of the switching control signal and a light emitting waveform signal, so that the frame area of the display panel can be saved.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a driving circuit and a display panel. Background Technology

[0002] OLED (Organic Light-Emitting Diode) is a thin, high-brightness, high-contrast active-matrix display technology that generates the three primary colors of light by driving organic light-emitting materials with an electric current. Unlike LCD (Liquid Crystal Display), since the organic light-emitting materials are formed into light-emitting diodes through a vapor deposition process, their luminous intensity is related to the current. The luminous intensity of the light-emitting diode is controlled by a light-emitting control signal and a data voltage. In related technologies, the light-emitting control signal is generated using a separate GOA (Gate Driver On Array) circuit, which occupies space in the bezel of the display panel.

[0003] Therefore, how to save the bezel area of ​​the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a driving circuit and a display panel that solves the problem of how to save the bezel area of ​​the display panel.

[0005] In a first aspect, this application provides a driving circuit comprising N cascaded driving modules. The nth driving module includes: a gate driving unit connected to a first clock signal line and a second clock signal line of the current stage, configured to output a gate driving signal of the current stage under the action of the signal output by the nith driving module and the first and second clock signals of the current stage; wherein the first clock signal and the second clock signal are out of phase, and the gate driving signal is a valid frame signal during the sampling phase; a switching unit connected to the gate driving unit, configured to output a switching control signal under the action of the signal output by the nith driving module and the gate driving signal of the current stage; wherein the switching control signal is a valid frame signal during the light emission phase; and a light emission control unit connected to the output terminals of the switching unit and the light emission waveform signal, configured to output a light emission control signal of the current stage under the action of the switching control signal and the light emission waveform signal.

[0006] Optionally, the light emission control signal includes: a first light emission control sub-signal and a second light emission control sub-signal. The light emission control unit includes: an auxiliary control sub-unit connected to the output terminal of the light emission waveform signal and an auxiliary control node, configured to: generate a first auxiliary control signal at the auxiliary control node when the light emission waveform signal is at a high potential; and generate a second auxiliary control signal at the auxiliary control node when the light emission waveform signal is at a low potential; wherein the first auxiliary control signal and the second auxiliary control signal are generated alternately; a first control sub-unit connected to the auxiliary control node and the switching unit, configured to: output the first light emission control sub-signal during the light emission stage under the action of the switching control signal and the first auxiliary control signal; wherein the first light emission control sub-signal is a valid frame signal; and a second control sub-unit connected to the auxiliary control node, configured to: output the second light emission control sub-signal during the light emission stage under the action of the second auxiliary control signal; wherein the second light emission control sub-signal is a non-valid frame signal.

[0007] Optionally, the light emission control signal includes a third light emission control sub-signal, and the light emission control unit includes a third control sub-unit connected to the switch unit and configured to output the third light emission control sub-signal under the action of the switch control signal; wherein the third light emission control sub-signal is an invalid frame signal during the reset phase and the sampling phase.

[0008] Optionally, the gate driving unit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor, a second capacitor, and a seventh transistor; the control terminal of the first transistor is connected to the first clock signal line and the control terminal of the fourth transistor, respectively; the first terminal of the first transistor is connected to the output terminal of the ni-th gate driving unit, and the second terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the fifth transistor; the control terminal of the second transistor is connected to a low-potential terminal, and the second terminal of the second transistor is connected to the first terminal of the first capacitor and the control terminal of the third transistor; the first terminal of the third transistor is connected to the second clock signal line, and the second terminal of the third transistor is connected to the second terminal of the first capacitor and the switching unit, respectively; the first terminal of the fourth transistor is connected to a low-potential terminal, and the second terminal of the fourth transistor is connected to the first terminal of the sixth transistor, the first terminal of the second capacitor, and the control terminal of the seventh transistor, respectively; the control terminal of the fifth transistor is connected to the second clock signal line, and the second terminal of the fifth transistor is connected to the control terminal of the sixth transistor; the second terminal of the sixth transistor is connected to the second terminal of the second capacitor and the second terminal of the seventh transistor, respectively, and is connected to a high-potential terminal.

[0009] Optionally, the switching unit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; the control terminals of the eighth transistor and the tenth transistor are connected to the output terminal of the ni-th stage gate driving unit; the first terminal of the eighth transistor is connected to a low-potential terminal; the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor; the control terminal of the ninth transistor is connected to the output terminal of the current stage gate driving unit; the second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the first terminal of the eleventh transistor; the second terminal of the tenth transistor and the second terminal of the eleventh transistor are connected to a high-potential terminal.

[0010] Optionally, the auxiliary control subunit includes: a third capacitor; the first end of the third capacitor is connected to the output end of the light-emitting waveform signal, and the second end of the third capacitor is connected to the auxiliary control node.

[0011] Optionally, the first control subunit includes a twelfth transistor and a thirteenth transistor; the control terminal of the twelfth transistor is connected to the auxiliary control node, the first terminal of the twelfth transistor is connected to a low potential terminal, and the second terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor; the control terminal of the thirteenth transistor is connected to the switching unit, and the second terminal of the thirteenth transistor is the output terminal of the first light emission control sub-signal.

[0012] Optionally, the second control subunit includes: a fourteenth transistor and a fourth capacitor; the control terminal of the fourteenth transistor is connected to the auxiliary control node and the first terminal of the fourth capacitor, the first terminal of the fourteenth transistor and the second terminal of the fourth capacitor are connected to a high potential terminal, and the second terminal of the fourteenth transistor serves as the output terminal of the second light emission control sub-signal.

[0013] Optionally, the third control subunit includes: a fifteenth transistor; the control terminal of the fifteenth transistor is connected to the switching unit, the first terminal of the fifteenth transistor is connected to a high potential terminal, and the second terminal of the fifteenth transistor serves as the output terminal of the third light emission control sub-signal.

[0014] Secondly, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, multiple data lines, and multiple pixel circuits. The non-display area includes a driving circuit as described in any of the first aspects. The gate driving unit of the driving circuit is connected to at least one of the scan lines, and the light-emitting control unit of the driving circuit is connected to at least one pixel circuit. The pixel circuit is connected to at least one scan line and at least one data line.

[0015] The technical solution provided in this application has at least the following beneficial effects: This application sets up a gate driving unit to output the current stage's gate driving signal during the sampling phase to drive the pixel circuit. A switching unit is connected to the gate driving unit, and a light-emitting control unit is connected to the switching unit and the output terminal of the light-emitting waveform signal. The switching unit outputs a switching control signal based on the gate driving signal. Under the action of the switching control signal and the light-emitting waveform signal, the light-emitting control unit can output a light-emitting control signal to modulate the brightness of the light-emitting diodes in the pixel circuit during the light-emitting phase. Compared to related technologies that use a separate GOA circuit to generate the light-emitting control signal, this application sets up a switching unit to convert the current stage's gate driving signal and the nith stage's gate driving signal output by the gate driving unit to obtain a switching control signal. Under the action of the switching control signal and the light-emitting waveform signal, the current stage's light-emitting control signal is output, eliminating the need for a separate GOA circuit to generate the light-emitting control signal and saving bezel area on the display panel. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] Figure 1 A schematic diagram of a driving circuit provided in an embodiment of this application is shown.

[0018] Figure 2 The diagram shows the timing of a driving circuit during the reset phase according to an embodiment of this application.

[0019] Figure 3 A schematic diagram of the structure of a light-emitting control unit provided in an embodiment of this application is shown.

[0020] Figure 4 A circuit diagram of a driving module provided in an embodiment of this application is shown.

[0021] Figure 5 This paper illustrates the signal flow diagram of a driver module during the reset phase according to an embodiment of this application.

[0022] Figure 6 The diagram illustrates the signal flow chart of a driving module during the sampling phase, as provided in an embodiment of this application.

[0023] Figure 7 The diagram shows the timing of a driving circuit during the sampling phase according to an embodiment of this application.

[0024] Figure 8 This illustration shows a first signal flow diagram of a driving module during the sampling phase, as provided in an embodiment of this application.

[0025] Figure 9 The diagram shows the timing of the first sub-stage of a driving circuit in the sampling phase according to an embodiment of this application.

[0026] Figure 10 This illustration shows a second signal flow diagram of a driving module during the sampling phase, as provided in an embodiment of this application.

[0027] Figure 11 The diagram shows the timing of a driving circuit in the second sub-stage according to an embodiment of this application.

[0028] Figure 12 A circuit diagram of a pixel circuit provided in an embodiment of this application is shown.

[0029] Figure 13 The diagram shows the timing diagram of a pixel circuit provided in an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures: 100. Driving circuit; 110. Gate driving unit; 120. Switching unit; 130. Light-emitting control unit; 131. Auxiliary control subunit; 132. First control subunit; 133. Second control subunit; 134. Third control subunit; T1. First transistor; T2. Second transistor; T3. Third transistor; T4. Fourth transistor; T5. Fifth transistor; T6. Sixth transistor; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor; T11. Eleventh transistor; T12. Twelfth transistor; T13. Thirteenth transistor; T14. Fourteenth transistor; T15. Fifteenth transistor; T16. Sixteenth transistor; T17. Seventeenth transistor; T18. Eighteenth transistor Transistor; T19, nineteenth transistor; T20, twentieth transistor; T21, twenty-first transistor; T22, twenty-second transistor; C1, first capacitor; C2, second capacitor; C3, third capacitor; C4, fourth capacitor; C5, fifth capacitor; D, light-emitting diode; XCK, first clock signal line; CK, second clock signal line; Pscan, output of gate drive unit; Nscan, output of second gate drive signal; An, auxiliary control node; CK_PWM, output of light-emitting waveform signal; EM, output of light-emitting control signal; Data, data line; ELVDD, first power supply terminal; Vint, first reset terminal; VI_Anode, second reset terminal; VGL, low potential terminal; VGH, high potential terminal. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0034] Figure 1 A schematic diagram of a driving circuit provided in an embodiment of this application is shown below. Please refer to [link / reference]. Figure 1 As shown, the driving circuit includes N cascaded driving modules 100. The nth driving module 100 includes: a gate driving unit 110, a switching unit 120, and a light-emitting control unit 130. The gate driving unit 110 is connected to the first clock signal line XCK(n) and the second clock signal line CK(n) of the current stage. The switching unit 120 is connected to the gate driving unit 110. The light-emitting control unit 130 is connected to the switching unit 120 and the output terminal CK_PWM of the light-emitting waveform signal.

[0035] It should be noted that XCK(n-1) represents the first clock signal line of the (n-1)th stage, XCK(n) represents the first clock signal line of the nth stage, XCK(n+1) represents the first clock signal line of the (n+1)th stage, CK(n-1) represents the second clock signal line of the (n-1)th stage, CK(n) represents the second clock signal line of the nth stage, CK(n+1) represents the second clock signal line of the (n+1)th stage, Pscan(n-2) represents the output terminal of the gate driving unit of the (n-2)th stage, Pscan(n-1) represents the output terminal of the gate driving unit of the (n-1)th stage, Pscan(n) represents the output terminal of the gate driving unit of the nth stage, Pscan(n+1) represents the output terminal of the gate driving unit of the (n+1)th stage, EM(n-1) represents the output terminal of the light-emitting control unit of the (n-1)th stage, EM(n) represents the output terminal of the light-emitting control unit of the nth stage, and EM(n+1) represents the output terminal of the light-emitting control unit of the (n+1)th stage.

[0036] In some embodiments, the gate driving unit 110 is configured to output the gate driving signal of the current stage under the action of the signal output by the ni-th stage driving module 100, the first clock signal and the second clock signal of the current stage; wherein the first clock signal and the second clock signal are out of phase, and the gate driving signal is a valid frame signal during the sampling stage.

[0037] For example, the signal output by the ni-th stage drive output module can be the gate drive signal of the ni-th stage, where i can be 1. Figure 2 This paper presents a timing diagram of a driving circuit during the reset phase according to an embodiment of this application. Please refer to [link / reference]. Figure 2 As shown, the first clock signal and the second clock signal of the current stage are out of phase. When the first clock signal is high, the second clock signal is low; when the first clock signal is low, the second clock signal is high. When the gate driving unit 110 receives the gate driving signal of the ni-th stage, the clock signal of the current stage, and the second clock signal of the current stage, the gate driving unit 110 will output the gate driving signal of the current stage. Each gate driving module 100 is connected to the corresponding pixel circuit. The working period of the pixel circuit includes: reset stage, sampling stage, and light emission stage. The gate driving signal is only a valid frame signal in the sampling stage, that is, the gate driving signal is output in the light emission stage to control the pixel writing of the pixel circuit; the gate driving signal is an invalid frame signal in the reset stage and the light emission stage, that is, the pixel circuit is not driven in the reset stage and the light emission stage.

[0038] In some embodiments, the switching unit 120 is configured to output a switching control signal under the action of the signal output by the ni-th stage driving module 100 and the gate driving signal of the current stage; wherein the switching control signal is an effective frame signal during the light emission stage.

[0039] For example, the signal of the ni-th stage driving module 100 can be the gate driving signal of the ni-th stage. When the switching unit 120 receives the gate driving signal of the ni-th stage and the gate driving signal of the current stage, it will output a switching control signal to control the light-emitting control unit 130 to output a light-emitting control signal during the light-emitting stage, and adjust the brightness of the pixel circuit during the light-emitting stage.

[0040] In some embodiments, the light-emitting control unit 130 is configured to output the light-emitting control signal of the current stage under the action of the switch control signal and the light-emitting waveform signal.

[0041] For example, the light-emitting waveform signal can be a PWM signal (Pulse Width Modulation), which can modulate the brightness of the light-emitting diode D in the pixel circuit. Under the action of the switching control signal and the light-emitting waveform signal, a light-emitting control signal can be output to modulate the brightness of the light-emitting diode D in the pixel circuit during the light-emitting stage. Compared with the use of an independent GOA circuit to generate the light-emitting control signal in related technologies, this application sets the switching unit 120 to convert the current stage gate drive signal and the nith stage gate drive signal output by the gate drive unit 110 to obtain the switching control signal, so as to output the current stage light-emitting control signal under the action of the switching control signal and the light-emitting waveform signal. There is no need to set an independent GOA circuit to generate the light-emitting control signal, which can save the bezel area of ​​the display panel.

[0042] In some embodiments, the light emission control signal includes: a first light emission control sub-signal and a second light emission control sub-signal. Figure 3 A schematic diagram of a light-emitting control unit provided in an embodiment of this application is shown below. Please refer to [link / reference]. Figure 3 As shown, the light-emitting control unit 130 includes: an auxiliary control subunit 131, a first control subunit 132, and a second control subunit 133. The auxiliary control subunit 131 is connected to the output terminal of the light-emitting waveform signal and the auxiliary control node An. The first control subunit 132 is connected to the auxiliary control node An and the switching unit 120. The second control subunit 133 is connected to the auxiliary control node An.

[0043] In some embodiments, the auxiliary control subunit 131 is configured to: generate a first auxiliary control signal at the auxiliary control node An when the light emission waveform signal is at a high potential; and generate a second auxiliary control signal at the auxiliary control node An when the light emission waveform signal is at a low potential; wherein the first auxiliary control signal and the second auxiliary control signal are generated alternately.

[0044] For example, when the auxiliary control subunit 131 receives the light-emitting waveform signal, it generates a corresponding first auxiliary control signal and a second auxiliary control signal on the auxiliary control node An according to the potential change of the light-emitting waveform signal. Please refer to [link to relevant documentation]. Figure 2 As shown, the light-emitting waveform signal is a waveform signal that alternates between high and low potential output, thereby generating the first auxiliary control signal and the second auxiliary control signal alternately. By adjusting the duty cycle of the light-emitting waveform signal, the output first light-emitting control sub-signal and the second light-emitting control sub-signal can be adjusted, thereby adjusting the brightness of the light-emitting diode D of the pixel circuit.

[0045] In some embodiments, the first control subunit 132 is configured to output a first light emission control sub-signal during the light emission stage under the action of a switch control signal and a first auxiliary control signal; wherein the first light emission control sub-signal is an effective frame signal.

[0046] For example, when the first control subunit 132 receives the switch control signal and the first auxiliary control signal, it outputs the first light emission control sub-signal during the light emission stage to the pixel circuit, and the effective frame signal drives the pixel circuit.

[0047] In some embodiments, the second control subunit 133 is configured to output a second light emission control sub-signal during the light emission stage under the action of the second auxiliary control signal; wherein the second light emission control sub-signal is an invalid frame signal.

[0048] For example, when the second control subunit 133 receives the second auxiliary control signal, the second control subunit 133 will output the second light emission control signal. The second light emission control signal is an invalid frame signal and will not drive the pixel circuit.

[0049] By setting the auxiliary control subunit 131 to alternately output the first auxiliary control signal and the second auxiliary control signal, the first control subunit 132 and the second control subunit 133 will also alternately output the first light emission control sub-signal and the second light emission control sub-signal, and the potential polarities of the first light emission control sub-signal and the second light emission control sub-signal are opposite, thereby controlling the light emission brightness of the light emission diode D of the pixel circuit.

[0050] In some embodiments, please refer to Figure 2 and Figure 3 As shown, the light emission control signal includes a third light emission control sub-signal. The light emission control unit 130 includes a third control sub-unit 134, which is connected to the switch unit 120 and is configured to output the third light emission control sub-signal under the action of the switch control signal. The third light emission control sub-signal is a non-valid frame signal during the reset phase and the sampling phase.

[0051] For example, by setting the third control subunit 134 to be connected to the light-emitting unit, the third control subunit 134 will also receive the switch control signal, thereby outputting the third light-emitting control sub-signal to the pixel circuit during the reset and sampling phases. The third light-emitting control sub-signal is an invalid frame signal, that is, the pixel circuit will not be dimmed during the reset and sampling phases.

[0052] Figure 4 A circuit diagram of a driving module provided in an embodiment of this application is shown below. Please refer to [link / reference]. Figure 4 As shown, the gate driving unit 110 includes: a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a second capacitor C2, and a seventh transistor T7. The control terminal of the first transistor T1 is connected to the first clock signal line XCK(n) and the control terminal of the fourth transistor T4, respectively. The first terminal of the first transistor T1 is connected to the output terminal of the ni-th gate driving unit 110, and the second terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and the first terminal of the fifth transistor T5. The control terminal of the second transistor T2 is connected to the low potential terminal VGL, and the second terminal of the second transistor T2 is connected to the first terminal of the first capacitor C1 and the first terminal of the third transistor T7. The control terminal of transistor T3 is connected; the first terminal of the third transistor T3 is connected to the second clock signal line CK(n), and the second terminal of the third transistor T3 is connected to the second terminal of the first capacitor C1 and the switching unit 120 respectively; the first terminal of the fourth transistor T4 is connected to the low potential terminal VGL, and the second terminal of the fourth transistor T4 is connected to the first terminal of the sixth transistor T6, the first terminal of the second capacitor C2 and the control terminal of the seventh transistor T7 respectively; the control terminal of the fifth transistor T5 is connected to the second clock signal line CK(n), and the second terminal of the fifth transistor T5 is connected to the control terminal of the sixth transistor T6; the second terminal of the sixth transistor T6 is connected to the second terminal of the second capacitor C2 and the second terminal of the seventh transistor T7 and connected to the high potential terminal VGH.

[0053] For example, Figure 5 This paper illustrates a signal flow diagram of a driver module during the reset phase, as provided in an embodiment of this application. Please refer to [link / reference]. Figure 2 and Figure 5As shown, during the reset phase, the gate drive signal of the ni-th stage and the first clock signal of the current stage are valid frame signals, i.e., low-level signals. The first terminal of the first transistor T1 receives the gate drive signal of the ni-th stage. The control terminal of the first transistor T1 receives the first clock signal of the current stage and turns on, transmitting the gate drive signal of the ni-th stage to the second transistor T2. The control terminal of the second transistor T2 receives the low-level signal and turns on. The control terminal of the third transistor T3 receives the gate drive signal of the ni-th stage and turns on. The gate drive signal of the ni-th stage will charge the first capacitor C1 and promote the third transistor T3 to turn on. The first terminal of the third transistor T3 will output the gate drive signal of the current stage according to the received second clock signal, which is an invalid frame signal, i.e., a high-level signal. During the reset phase, the gate drive signal of the current stage is an invalid frame signal, meaning it will not drive the pixel circuit.

[0054] For example, Figure 6 This illustration shows a signal flow diagram of a driving module during the sampling phase, according to an embodiment of this application. Figure 7 The diagram illustrates the operating timing of a driving circuit during the sampling phase according to an embodiment of this application. During the sampling phase, the gate driving signal of the ni-th stage and the first clock signal of the current stage are invalid frame signals, i.e., high-level signals. The first transistor T1 will be turned off. Since the first capacitor C1 is pre-charged during the reset phase, the voltage of the first capacitor C1 will maintain the conduction of the third transistor T3. The first terminal of the third transistor T3 receives the second clock signal, which is an valid frame signal, i.e., a low-level signal. The second terminal of the third transistor T3 will output the gate driving signal of the current stage. During the sampling phase, the gate driving signal of the current stage is an valid frame signal, which will drive the pixel circuit to write the pixel voltage.

[0055] For example, Figure 8 This illustration shows a first signal flow diagram of a driving module during the sampling phase, according to an embodiment of this application. Figure 9 This document shows a timing diagram of the first sub-stage of a driving circuit during the sampling phase, according to an embodiment of this application. Please refer to [link / reference]. Figure 8 and Figure 9 As shown, the first clock signal is a valid frame signal, i.e., a high-level signal. The fourth transistor T4 is turned on, and the control terminal of the seventh transistor T7 is connected to the low-potential terminal VGL and charges the second capacitor C2. The voltage on the second capacitor C2 will promote the seventh transistor T7 to turn on. The second terminal of the seventh transistor T7 will be connected to the high-potential terminal VGH. The first terminal of the seventh transistor T7 outputs the gate drive signal of the current stage, i.e., a high-level signal. In the first sub-stage, the gate drive signal of the current stage is a non-valid frame signal and will not drive the pixel circuit.

[0056] For example, Figure 10 This illustration shows a second signal flow diagram of a driving module during the sampling phase, according to an embodiment of this application. Figure 11 The following is a timing diagram of the operation of a driving circuit in the second sub-stage according to an embodiment of this application. Please refer to [link / reference]. Figure 10 and Figure 11 As shown, the first clock signal is an invalid frame signal, i.e., a high-level signal. The fourth transistor T4 will be turned off, and the voltage on the second capacitor C2 will still store voltage. The voltage on the second capacitor C2 will control the seventh transistor T7 to turn on. The second terminal of the seventh transistor T7 will be connected to the high-potential terminal VGH. The first terminal of the seventh transistor T7 outputs the gate drive signal of the current stage. In the second sub-stage, the gate drive signal of the current stage is an invalid frame signal and will not drive the pixel circuit.

[0057] In some embodiments, please refer to Figure 4 As shown, the switching unit 120 includes: an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; the control terminals of the eighth transistor T8 and the tenth transistor T10 are connected to the output terminal Pscan(ni) of the ni-th stage gate drive unit 110; the first terminal of the eighth transistor T8 is connected to the low potential terminal VGL; the second terminal of the eighth transistor T8 is connected to the first terminal of the ninth transistor T9; the control terminal of the ninth transistor T9 is connected to the output terminal Pscan(ni) of the current stage gate drive unit 110; the second terminal of the ninth transistor T9 is connected to the first terminal of the tenth transistor T10 and the first terminal of the eleventh transistor T11, respectively; the second terminal of the tenth transistor T10 and the second terminal of the eleventh transistor T11 are connected to the high potential terminal VGH.

[0058] For example, please refer to Figure 2 and Figure 5 As shown, during the reset phase, the gate drive signal of the ni-th stage is a valid frame signal, i.e., a low-level signal, and the eighth transistor T8 is in the off state; the gate drive signal of the current stage is an invalid frame signal, i.e., a high-level signal, and the ninth transistor T9 and the eleventh transistor T11 are in the off state; the control terminal of the tenth transistor T10 receives the gate drive signal of the ni-th stage and is turned on; the first terminal of the tenth transistor T10 is connected to the high-potential terminal VGH; the second terminal of the tenth transistor T10 outputs a high-level signal, i.e., a switch control signal, which is an invalid frame signal during the reset phase.

[0059] For example, please refer to Figure 6 and Figure 7As shown, during the sampling phase, the gate drive signal of the ni-th stage is an invalid frame signal, i.e., a high-level signal. The control terminal of the eighth transistor T8 receives the gate drive signal of the ni-th stage and turns on, while the tenth transistor T10 is in the off state. The gate drive signal of the current stage is an valid frame signal, i.e., a low-level signal. The ninth transistor T9 is in the off state, and the control terminal of the eleventh transistor T11 receives the gate drive signal of the current stage and turns on. The first terminal of the eleventh transistor T11 is connected to the high-potential terminal VGH, and the second terminal of the eleventh transistor T11 outputs a high-level signal, i.e., a switch control signal. The switch control signal is an invalid frame signal during the sampling phase.

[0060] For example, please refer to Figures 8-10 As shown, the light-emitting stage includes a first sub-stage and a second sub-stage. In the light-emitting stage, the gate drive signal of the ni-th stage is an ineffective frame signal, i.e., a high-level signal. The control terminal of the eighth transistor T8 receives the gate drive signal of the ni-th stage and turns on, while the tenth transistor T10 is in the off state. The gate drive signal of the current stage is an ineffective frame signal, i.e., a high-level signal. The control terminal of the ninth transistor T9 receives the gate drive signal of the current stage and turns on, while the eleventh transistor T11 is in the off state. The first terminal of the eighth transistor T8 is connected to the low-potential terminal VGL, the eleventh transistor T11 is in the off state, and the second terminal of the ninth transistor T9 will output a low-level signal, i.e., a switch control signal. The switch control signal is an effective frame signal in the first and second sub-stages.

[0061] In some embodiments, please refer to Figure 4 As shown, the auxiliary control subunit 131 includes: a third capacitor C3; the first end of the third capacitor C3 is connected to the output terminal CK_PWM of the light emission waveform signal, and the second end of the third capacitor C3 is connected to the auxiliary control node An.

[0062] For example, the output terminal CK_PWM of the light-emitting waveform signal outputs a light-emitting waveform signal during the light-emitting phase. The light-emitting waveform signal is an alternating high and low level signal. When the light-emitting waveform signal is at a high level, when the first terminal of the third capacitor C3 receives the light-emitting waveform signal, a first auxiliary control signal will be generated at the auxiliary control node An. The first auxiliary control signal is a high level signal. When the light-emitting waveform signal is at a low level, when the first terminal of the third capacitor C3 receives the light-emitting waveform signal, a second auxiliary control signal will be generated at the auxiliary control node An. The second auxiliary control signal is a low level signal.

[0063] In some embodiments, please refer to Figure 4As shown, the first control subunit 132 includes: a twelfth transistor T12 and a thirteenth transistor T13; the control terminal of the twelfth transistor T12 is connected to the auxiliary control node An, the first terminal of the twelfth transistor T12 is connected to the low potential terminal VGL, and the second terminal of the twelfth transistor T12 is connected to the first terminal of the thirteenth transistor T13; the control terminal of the thirteenth transistor T13 is connected to the switching unit 120, and the second terminal of the thirteenth transistor T13 is the output terminal of the first light-emitting control sub-signal.

[0064] In some embodiments, please refer to Figure 4 As shown, the second control subunit 133 includes: a fourteenth transistor T14 and a fourth capacitor C4; the control terminal of the fourteenth transistor T14 is connected to the auxiliary control node An and the first terminal of the fourth capacitor C4, the first terminal of the fourteenth transistor T14 and the second terminal of the fourth capacitor C4 are connected to the high potential terminal VGH, and the second terminal of the fourteenth transistor T14 serves as the output terminal of the second light emission control sub-signal.

[0065] For example, please refer to Figures 8-10 As shown, during the light-emitting stage, the switch control signal is a valid frame signal, i.e., a low-level signal. When the control terminal of the twelfth transistor T12 receives the first auxiliary control signal, the twelfth transistor T12 is turned on, the thirteenth transistor T13 is turned on, and the fourteenth transistor T14 is turned off. The low-level signal received by the first terminal of the twelfth transistor T12 will be output through the second terminal of the thirteenth transistor T13. The second terminal of the twelfth transistor T12 outputs the first light-emitting sub-signal, which is a valid frame signal.

[0066] For example, Figures 8-10 As shown, during the light-emitting stage, the switch control signal is a valid frame signal, i.e., a low-level signal. When the control terminal of the twelfth transistor T12 receives the second auxiliary control signal, the second auxiliary control signal is a high-level signal, the twelfth transistor T12 is cut off, the thirteenth transistor T13 is turned on, and the control terminal of the fourteenth transistor T14 receives a high-level signal through the fourth capacitor C4 and is turned on. The high-level signal received by the first terminal of the fourteenth transistor T14 will be output through the second terminal of the fourteenth transistor T14. The second terminal of the fourteenth transistor T14 outputs the second light-emitting sub-signal, which is a non-valid frame signal.

[0067] As the first auxiliary control signal and the second auxiliary control signal are output alternately on the auxiliary control node An, the first light-emitting sub-signal and the second light-emitting sub-signal will also be output alternately during the light-emitting phase.

[0068] In some embodiments, the third control subunit 134 includes: a fifteenth transistor T15; the control terminal of the fifteenth transistor T15 is connected to the switching unit 120, the first terminal of the fifteenth transistor T15 is connected to the high potential terminal VGH, and the second terminal of the fifteenth transistor T15 serves as the output terminal of the third light emission control sub-signal.

[0069] For example, please refer to Figure 2 , Figures 5-7 As shown, during the reset and sampling phases, the switch control signal is an invalid frame signal, i.e., a high-level signal. The control terminal of the fifteenth transistor T15 receives the high-level signal and turns on. The first terminal of the fifteenth transistor T15 receives the high-level signal and outputs a high-level signal through the second terminal of the fifteenth transistor T15. That is, the second terminal of the fifteenth transistor T15 outputs a high electrical signal, i.e., the third light-emitting control sub-signal. The third light-emitting control sub-signal is an invalid frame signal during the reset and sampling phases.

[0070] For example, in the first and second sub-stages, the switch control signal is a valid frame signal, i.e., a low-level signal, and the fifteenth transistor T15 is in the off state, so the third light-emitting control sub-signal will not be output.

[0071] In some embodiments, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, multiple data lines (Data), and multiple pixel circuits. The non-display area includes the aforementioned driving circuit. The gate driving unit 110 of the driving circuit is connected to at least one scan line, and the light-emitting control unit 130 of the driving circuit is connected to at least one pixel circuit. The pixel circuit is connected to at least one scan line and at least one data line (Data).

[0072] It should be noted that the multiple scan lines include multiple first scan lines and multiple second scan lines. The gate driving unit 110 in the driving circuit is the first gate driving unit 110, which is connected to the first scan line Pscan(n) of the current stage, and the output gate driving signal is the first gate driving signal. Then, multiple independent second gate driving units are set up. The second gate driving unit of the nth stage is connected to the corresponding second scan line Nscan(n) to output the second gate driving signal to the second scan line Nscan(n); the polarity of the first gate driving signal and the second gate driving signal are opposite.

[0073] Figure 12 This paper shows a circuit diagram of a pixel circuit provided in an embodiment of the present application. Figure 13This illustration shows a timing diagram of a pixel circuit according to an embodiment of this application. The pixel circuit includes: a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a fifth capacitor C5, a twentieth transistor T20, a twenty-first transistor T21, a light-emitting diode D, and a twenty-second transistor T22. The control terminal of the sixteenth transistor T16 is connected to the first scan line Pscan(n) of the current stage, the first terminal of the sixteenth transistor T16 is connected to the corresponding data line Data, and the second terminal of the sixteenth transistor T16 is connected to the second terminal of the seventeenth transistor T17 and the first terminal of the eighteenth transistor T18. The control terminal of the seventeenth transistor T17 is connected to the control terminal of the twenty-first transistor T21 and the output terminal EM(n) of the light-emitting control unit 130 of the driving circuit, and the first terminal of the seventeenth transistor T17 is connected to the first power supply terminal ELVDD and the first terminal of the fifth capacitor C5. The eighteenth transistor T16... The control terminal of T18 is connected to the second terminal of the fifth capacitor C5, the second terminal of the nineteenth transistor T19, and the second terminal of the twentieth transistor T20. The second terminal of the eighteenth transistor T18 is connected to the first terminal of the twentieth transistor T20 and the first terminal of the twenty-first transistor T21. The control terminal of the nineteenth transistor T19 is connected to the second scan line Nscan(ni) of the ni-th stage, and the first terminal of the nineteenth transistor T19 is connected to the first reset terminal Vint. The control terminal of the twentieth transistor T20 is connected to the second scan line Nscan(n) of the current stage. The second terminal of the twenty-first transistor T21 is connected to the anode of the light-emitting diode D and the second terminal of the twenty-second transistor T22. The cathode of the light-emitting diode D is connected to the low potential terminal VGL. The control terminal of the twenty-second transistor T22 is connected to the first scan line Pscan(ni) of the ni-th stage, and the first terminal of the twenty-second transistor T22 is connected to the second reset terminal VI_Anode.

[0074] For example, Figure 13 A timing diagram of a pixel circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 12 and Figure 13 As shown, during the reset phase, the second gate drive signal of the ni-th stage is a valid frame signal, i.e., a high-level signal. The control terminal of the nineteenth transistor T19 receives the gate drive signal of the ni-th stage and will be turned on. The first reset signal output by the first reset terminal Vint is output through the nineteenth transistor T19 to the control terminal of the eighteenth transistor T18 to reset the eighteenth transistor T18. The control terminal of the twenty-second transistor T22 receives the gate drive signal of the ni-th stage and will be turned on. The second reset signal output by the second reset terminal VI_Anode is output through the twenty-second transistor T22 to the anode of the light-emitting diode D to reset the light-emitting diode D.

[0075] For example, please refer to Figure 12 and Figure 13 As shown, during the sampling phase, the first gate drive signal of the current stage is a valid frame signal, i.e., a low-level signal. The control terminal of the sixteenth transistor T16 receives the first gate drive signal of the current stage and turns on; the control terminal of the eighteenth transistor T18 receives the voltage of the fifth capacitor C5 and turns on; the second gate drive signal of the current stage is a valid frame signal, i.e., a high-level signal. The control terminal of the twentieth transistor T20 receives the second gate drive signal of the current stage and turns on. The pixel voltage on the data line Data is written to the fifth capacitor C5 through the sixteenth transistor T16 and the eighteenth transistor T18.

[0076] For example, Figure 12 and Figure 13 As shown, during the light-emitting stage, the control terminals of the seventeenth transistor T17 and the twentieth transistor T20 receive the light-emitting control signal of the current stage. The light-emitting control signal is a signal that alternately outputs high-level and low-level signals, thereby controlling the seventeenth transistor T17 to conduct alternately and the twentieth transistor T20 to conduct alternately, thereby adjusting the brightness of the light-emitting diode D.

[0077] It should be noted that in this application, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the twenty-first transistor T21, and the twenty-second transistor T22 can be P-type field-effect transistors, and the eighth transistor T8, the ninth transistor T9, the fourteenth transistor T14, the fifteenth transistor T15, the nineteenth transistor T19, and the twentieth transistor T20 can be N-type field-effect transistors. The specific type of transistor is set according to actual needs and is not limited here.

[0078] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0079] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0080] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A driving circuit, characterized in that, The driving circuit includes N cascaded driving modules, and the nth driving module includes: The gate driving unit, connected to the first clock signal line and the second clock signal line of the current stage, is configured to output the gate driving signal of the current stage under the action of the signal output by the nth stage driving module and the first clock signal and the second clock signal of the current stage; wherein the first clock signal and the second clock signal are out of phase, and the gate driving signal is a valid frame signal during the sampling phase; A switching unit, connected to the gate driving unit, is configured to output a switching control signal under the action of the signal output by the ni-th stage driving module and the gate driving signal of the current stage; wherein, the switching control signal is an effective frame signal during the light emission stage; The light-emitting control unit, connected to the output terminal of the switching unit and the light-emitting waveform signal, is configured to output the light-emitting control signal of the current stage under the action of the switching control signal and the light-emitting waveform signal.

2. The driving circuit according to claim 1, characterized in that, The light emission control signal includes: a first light emission control sub-signal and a second light emission control sub-signal; the light emission control unit includes: An auxiliary control subunit, connected to the output terminal of the light-emitting waveform signal and an auxiliary control node, is configured to: generate a first auxiliary control signal at the auxiliary control node when the light-emitting waveform signal is at a high potential; and generate a second auxiliary control signal at the auxiliary control node when the light-emitting waveform signal is at a low potential; wherein the first auxiliary control signal and the second auxiliary control signal are generated alternately. The first control subunit, connected to the auxiliary control node and the switch unit, is configured to: output the first light emission control sub-signal during the light emission stage under the action of the switch control signal and the first auxiliary control signal; wherein the first light emission control sub-signal is a valid frame signal; The second control subunit, connected to the auxiliary control node, is configured to output the second light emission control sub-signal during the light emission stage under the action of the second auxiliary control signal; wherein the second light emission control sub-signal is an invalid frame signal.

3. The driving circuit according to claim 1, characterized in that, The light emission control signal includes: a third light emission control sub-signal, and the light emission control unit includes: The third control subunit, connected to the switch unit, is configured to output the third light emission control sub-signal under the action of the switch control signal; wherein the third light emission control sub-signal is an invalid frame signal during the reset phase and the sampling phase.

4. The driving circuit according to claim 1, characterized in that, The gate driving unit includes: a first transistor, a second transistor, a third transistor, a first capacitor, a fourth transistor, a fifth transistor, a sixth transistor, a second capacitor, and a seventh transistor; The control terminal of the first transistor is connected to the first clock signal line and the control terminal of the fourth transistor, respectively. The first terminal of the first transistor is connected to the output terminal of the nith gate drive unit, and the second terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the fifth transistor. The control terminal of the second transistor is connected to the low potential terminal, and the second terminal of the second transistor is connected to the first terminal of the first capacitor and the control terminal of the third transistor. The first terminal of the third transistor is connected to the second clock signal line, and the second terminal of the third transistor is connected to the second terminal of the first capacitor and the switching unit, respectively. The first terminal of the fourth transistor is connected to the low potential terminal, and the second terminal of the fourth transistor is connected to the first terminal of the sixth transistor, the first terminal of the second capacitor, and the control terminal of the seventh transistor, respectively. The control terminal of the fifth transistor is connected to the second clock signal line, and the second terminal of the fifth transistor is connected to the control terminal of the sixth transistor. The second terminal of the sixth transistor is connected to the second terminal of the second capacitor and the second terminal of the seventh transistor to a high potential terminal.

5. The driving circuit according to claim 1, characterized in that, The switching unit includes: an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor; The control terminals of the eighth transistor and the tenth transistor are connected to the output terminal of the ni-th gate drive unit. The first terminal of the eighth transistor is connected to the low potential terminal, and the second terminal of the eighth transistor is connected to the first terminal of the ninth transistor. The control terminal of the ninth transistor is connected to the output terminal of the gate drive unit of the current stage, and the second terminal of the ninth transistor is connected to the first terminal of the tenth transistor and the first terminal of the eleventh transistor, respectively. The second terminal of the tenth transistor and the second terminal of the eleventh transistor are connected to a high potential terminal.

6. The driving circuit according to claim 2, characterized in that, The auxiliary control subunit includes: a third capacitor; The first terminal of the third capacitor is connected to the output terminal of the light-emitting waveform signal, and the second terminal of the third capacitor is connected to the auxiliary control node.

7. The driving circuit according to claim 2, characterized in that, The first control subunit includes: a twelfth transistor and a thirteenth transistor; The control terminal of the twelfth transistor is connected to the auxiliary control node, the first terminal of the twelfth transistor is connected to the low potential terminal, and the second terminal of the twelfth transistor is connected to the first terminal of the thirteenth transistor. The control terminal of the thirteenth transistor is connected to the switching unit, and the second terminal of the thirteenth transistor is the output terminal of the first light-emitting control sub-signal.

8. The driving circuit according to claim 2, characterized in that, The second control subunit includes: a fourteenth transistor and a fourth capacitor; The control terminal of the fourteenth transistor is connected to the auxiliary control node and the first terminal of the fourth capacitor. The first terminal of the fourteenth transistor and the second terminal of the fourth capacitor are connected to a high potential terminal. The second terminal of the fourteenth transistor serves as the output terminal of the second light-emitting control sub-signal.

9. The driving circuit according to claim 3, characterized in that, The third control subunit includes: a fifteenth transistor; The control terminal of the fifteenth transistor is connected to the switching unit, the first terminal of the fifteenth transistor is connected to the high potential terminal, and the second terminal of the fifteenth transistor serves as the output terminal of the third light-emitting control sub-signal.

10. A display panel, comprising a display area and a non-display area, wherein the display area includes multiple scan lines, multiple data lines, and multiple pixel circuits, characterized in that, The non-display area includes the driving circuit according to any one of claims 1-9, wherein the gate driving unit of the driving circuit is connected to at least one of the scan lines, and the light emission control unit of the driving circuit is connected to at least one pixel circuit; the pixel circuit is connected to at least one of the scan lines and at least one of the data lines.

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