Display panel

Abstract

Embodiments of the present specification disclose a display panel. The display panel includes a plurality of pixels arranged in a first direction and a second direction intersecting each other, a plurality of signal output terminals configured to provide data signals, and a plurality of data lines connected to the plurality of signal output terminals and configured to transmit the data signals to the pixels, wherein the plurality of pixels includes a first pixel configured to be connected to a first signal output terminal, a second pixel configured to be connected to a second signal output terminal, and a third pixel arranged between the first pixel and the second pixel in the first direction and configured to be alternately connected to the first signal output terminal and the second signal output terminal in the second direction.

Description

Technical Field

[0001] This specification relates to display panels, and more specifically, to display panels that can reduce the number of source driver integrated circuits (ICs). Background Technology

[0002] With the advancement of information technology, the market for display devices, which serve as a medium between users and information, has expanded. As a result, display devices such as organic light emitting displays (OLEDs), quantum dot displays (QDDs), liquid crystal displays (LCDs), and plasma display panels (PDPs) have been widely used.

[0003] For example, a liquid crystal display (LCD) or an organic light-emitting display includes a display panel having multiple sub-pixels, a driver configured to output drive signals for driving the display panel, and a power supply configured to generate power to be supplied to the display panel or the driver. Drivers include gate drivers, data drivers, etc.

[0004] The descriptions provided in the Related Art section should not be considered prior art simply because they are mentioned or associated with in that section. The Related Art section may include information describing one or more aspects of the subject matter art, and the descriptions in that section are not limited to this disclosure. Summary of the Invention

[0005] One objective of this specification is to reduce the number of source driver integrated circuits (ICs) configured to convert data signals into voltage signals and apply those voltage signals to a data driver.

[0006] Another objective of this specification is to minimize or reduce signal interference that may occur as the number of source driver ICs decreases.

[0007] The problems to be solved in this specification are not limited to those mentioned above. Those skilled in the art to which the technical ideas of this specification pertain will clearly understand other unmentioned problems from the following description.

[0008] A display panel according to an embodiment of this specification may include a plurality of pixels arranged in a first direction and a second direction intersecting each other; a plurality of signal output terminals configured to provide data signals; and a plurality of data lines connected to the signal output terminals and configured to transmit the data signals to the plurality of pixels, wherein the plurality of pixels may include a first pixel connected to a first signal output terminal, a second pixel connected to a second signal output terminal, and a third pixel arranged in the first direction between the first pixel and the second pixel and configured to be alternately connected to the first signal output terminal and the second signal output terminal in the second direction.

[0009] The display panel according to the embodiments of this specification can reduce the number of source driver ICs.

[0010] The display panel according to the embodiments of this specification can minimize or reduce signal interference between electrodes.

[0011] The effects of this specification are not limited to those described above. Those skilled in the art to which the technical concept of this specification pertains will clearly understand other effects not mentioned in the following description.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0013] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein: Figure 1 This is a plan view of the display panel according to the embodiments described in this specification; Figure 2 This is a circuit diagram of the sub-pixel circuit according to the implementation method; Figure 3 This is a schematic circuit diagram illustrating an embodiment according to this specification; Figure 4 This is a schematic circuit diagram illustrating an embodiment according to this specification; Figure 5 This is a schematic circuit diagram according to another embodiment of this specification; Figures 6A to 6D yes Figure 5 Example of modifications to region A; Figure 7 This illustrates the first embodiment. Figure 5 A plan view of a portion of area A; Figure 8It is shown Figure 5 A plan view of region B; Figure 9 It is along Figure 7 A sectional view taken by line I-I'; Figure 10 This illustrates the second embodiment. Figure 5 A plan view of a portion of area A; Figure 11 It is along Figure 10 A sectional view taken from line II-II'; and Figure 12 It is shown Figure 5 Plan view of region D.

[0014] [List of reference numerals in the attached diagram]

[0015] DS1: First signal output terminal

[0016] DS2: Second signal output terminal

[0017] DL1-1a, DL1-2a, DL1-3a: Data lines from first-1a to first-3a

[0018] DL1-1b, DL1-2b, DL1-3b: Data lines from first-1b to first-3b

[0019] SL1, SL2, SL3, SL4, SL5: First scan line to fifth scan line

[0020] T3-1: Extended Pattern

[0021] VL1-1: Drive voltage line

[0022] VL1-2, VL1-3: First driving voltage pattern, second driving voltage pattern

[0023] LL: Link pattern

[0024] 211B: Connection pattern Detailed Implementation

[0025] See below and appendix for reference. Figure 1 The advantages and features of this specification, as well as the methods for achieving these advantages and features, will become apparent from the detailed description of the embodiments described below. However, this specification is not limited to the embodiments disclosed below, but can be implemented in various different ways, and these embodiments are provided only to complete the disclosure of this specification and to enable those skilled in the art to fully understand the scope of this specification, which is limited only by the scope of the claims.

[0026] The shapes, sizes, proportions, angles, quantities, etc., disclosed in the accompanying drawings used to describe embodiments of this specification are exemplary, and therefore this specification is not limited to the matters shown in the drawings. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art may unnecessarily obscure the main points of this specification, its detailed description will be omitted.

[0027] When terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. When a component is referred to in the singular, the inclusion of a plural is included unless otherwise explicitly stated.

[0028] When explaining a component, the tolerance range is included, even if there is no separate explicit description.

[0029] When describing positional relationships, for example, when the positional relationship between two parts is described as "above", "on the upper part", "on the lower part", "on the side", etc., one or more other parts may be located between the two parts unless "directly" or "immediately" is used.

[0030] When an element or layer is referred to as being on another element or layer, it includes cases where the element or layer is directly on the other element or where the other layer or element is interposed between the two.

[0031] Furthermore, although terms such as "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, within the technical concept of this specification, the "first component" mentioned below can also be a "second component."

[0032] Throughout the specification, the same reference numerals denote the same parts.

[0033] For ease of description, the dimensions and thicknesses of the various components shown in the accompanying drawings are illustrated, and this specification is not necessarily limited to the dimensions and thicknesses of the components shown in the accompanying drawings.

[0034] Features of the various embodiments described herein may be combined or associated in part or in whole, and may be interlocked and driven differently in a technically distinct manner, and each embodiment may be implemented independently of each other or together in an associated relationship.

[0035] Any implementation described as an "example" in this article should not be interpreted as being better or more advantageous than other implementations.

[0036] When describing temporal relationships, if the temporal sequence is described as such as “after,” “following,” “next,” and “before,” non-continuous cases may be included unless more restrictive terms such as “just,” “immediately,” or “directly” are used.

[0037] Furthermore, when one element or layer is "connected," "joined," or "attached" to another element or layer, unless otherwise stated, it indicates that the element or layer can be directly connected or attached to the other element or layer, or indirectly connected or attached to the other element or layer through an intermediate element or layer "set" or "inserted" therebetween. It should be understood that this means the element can be set in direct contact or not in direct physical contact.

[0038] The statements regarding the first element, the second element, and / or the third element should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0039] The term “at least one” should be understood to include any and all combinations of one or more associated listed items. For example, “at least one of the first, second and third elements” means all combinations of the three listed elements, any two of the three elements, and each individual element, i.e., the first, second or third element.

[0040] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It will be further understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant technical context, and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit device, or any structure configured to perform the functions described herein (as would be understood by one of ordinary skill in the art).

[0041] In this specification, "equipment" may include display devices, such as liquid crystal modules (LCMs) and organic light emitting display modules (OLEDs), wherein the liquid crystal module includes a display panel and a driver for driving the display panel. Furthermore, equipment may include assemblies of electronic devices or assemblies of equipment (such as equipment including notebook computers, televisions, computer monitors, automotive devices or other forms of vehicles, which are complete products or end products including LCMs, OLED modules, etc.), and mobile electronic devices (such as smartphones or electronic boards).

[0042] Therefore, the display devices in this specification may include the display devices themselves, such as LCM and OLED modules, as well as complete sets of application products or devices including LCM and OLED modules as end consumers.

[0043] In some implementations, LCM and OLED modules, consisting of a display panel and a driver, can be referred to as a 'display device', and electronic devices comprising LCM and OLED modules as a complete product can be distinguished and referred to as a "kit". For example, a display device may include a liquid crystal (LCD) or organic light-emitting diode (OLED) display panel and a source PCB, which is a controller for driving the display panel. A kit may also include a kit PCB, which is a kit controller electrically connected to the source PCB and driving the entire kit.

[0044] The display panels used in the embodiments of this specification may include all types of display panels, such as liquid crystal display panels, organic light-emitting diode (OLED) display panels, and electroluminescent display panels. However, the display panels are not limited to these.

[0045] Features of the various embodiments described herein may be combined or associated in part or in whole, and may be interlocked and driven differently in a technically distinct manner, and each embodiment may be implemented independently of each other or together in an associated relationship.

[0046] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. The proportions of the components shown in the drawings are different from the actual proportions for ease of explanation, and therefore the invention is not limited to the proportions shown in the drawings.

[0047] Figure 1 This is a schematic plan view of the display panel according to an embodiment of the present specification.

[0048] refer to Figure 1Each of the horizontal (X) and vertical (Y) directions of the display panel 100 can be the length and width directions of the display panel 100. Alternatively, each of the horizontal (X) and vertical (Y) directions of the display panel 100 can also be represented as the row direction and the length direction. The thickness direction (Z) can represent the direction perpendicular to the plane having the horizontal (X) and vertical (Y) directions of the display panel 100. Additionally, the display panel 100 can also have a cross-section in the thickness direction (Z).

[0049] refer to Figure 1 The display panel 100 according to an embodiment of the present invention may include a display panel driving circuit for writing pixel data to pixels, and a power supply unit 140 for generating power required to drive the pixels and the display panel driving circuit.

[0050] The screen AA of the display panel 100 may include a pixel array for displaying input images. The pixel array may include multiple data lines DL, multiple gate lines GL intersecting the data lines DL, and pixels arranged in a matrix. The display panel 100 may include power lines commonly connected to the pixels. These power lines may be connected to constant voltage nodes in the pixel circuitry to provide the constant voltage required to drive the pixels (PXL). The power lines may be implemented as strip or mesh wiring and commonly connected to the pixels of the display panel 100.

[0051] Each pixel PXL can include multiple subpixels for color implementation. Each pixel PXL can include three, four, or more subpixels. Multiple subpixels can be arranged in various ways.

[0052] For example, when each pixel PXL includes first to third sub-pixels of different colors, each of the sub-pixels may emit blue, red, and green light, but is not limited to these. For example, when each of the pixels PXL includes first to fourth sub-pixels, in addition to the three sub-pixels mentioned above, the first to fourth sub-pixels may also include a white sub-pixel, but is not limited to these.

[0053] Each subpixel may include pixel circuitry configured to drive a light-emitting element. Each pixel circuitry may be connected to a data line DL, a gate line GL, and a power line. Each subpixel may be divided into a circuitry section and a light-emitting section.

[0054] The pixel array may include multiple pixel rows L1 to LN. Each of the pixel rows L1 to LN may include a row of pixels set along the X-axis direction X in the pixel array of the display panel 100. A horizontal period is the time obtained by dividing one frame period by the total number of pixel rows L1 to LN.

[0055] The power supply unit 140 outputs the voltage required to drive the pixels of the display panel 100 and the display panel driving circuit by using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc.

[0056] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels of the display panel 100. The display panel driving circuit may include a data driver 110 and a gate driver 120.

[0057] The display panel driving circuit can use a 2.5 RD (rate drive) structure to drive pixels. A display panel driven by a 2.5 RD structure can connect to 2.5 pixels per channel (or one signal output terminal), thereby reducing the number of channels in the data driver 110 and the number of source driver integrated circuits (ICs). This reduction in the number of channels and source driver ICs leads to a decrease in manufacturing costs.

[0058] The display panel driving circuit may also include a touch sensor driver configured to drive a touch sensor. Although from Figure 1 The touch sensor driver is omitted, but it can be integrated into a single source driver IC along with the data driver 110.

[0059] The data driver 110 can receive pixel data of the input image received as a digital signal from the timing controller 130, and output a data voltage. The data voltage can be output via the output buffer in the corresponding channel of the data driver 110.

[0060] The gate driver 120 may be located in the non-display area NA, may be located at least partially in the display area AA that reproduces the input image, or may be formed on the display panel 100 together with the wiring of the thin-film transistor (TFT) array and the pixel array.

[0061] The gate driver 120 can be disposed on either side or one side of the non-display area NA of the display panel 100, with the display area AA inserted in between, and can use a dual-feed or single-feed scheme to supply gate pulses.

[0062] Under the control of the timing controller 130, the gate driver 120 sequentially outputs pulses of the gate signal (hereinafter referred to as "gate pulses") to the gate line. The gate driver 120 can sequentially provide signals to the gate line GL by shifting the gate pulses using shift registers. The gate driver 120 may include one or more shift registers that output the gate signal pulses.

[0063] The timing controller 130 can receive digital video data of the input image and timing signals synchronized with the data from the host system 200. Based on the timing signals received from the host system 200, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120.

[0064] For example, the timing controller 130 can add white data to the RGB pixel data (primary colors) input from the host system, convert the data into RGBW sub-color data (four colors), and transmit them to the data driver 110. Known color conversion algorithms can be used as a method for converting the RGB pixel data into RGBW sub-color data (including white data).

[0065] Level shifter 150 can receive gate timing control signals from timing controller 130, generate a start pulse and a shift clock, and provide them to gate driver 120. The start pulse and shift clock output from level shifter 150 oscillate between gate high voltage and gate low voltage.

[0066] The host system 200 may include a motherboard. The host system may scale the image signal from the video source to match the resolution of the display panel 100 and transmit it along with a timing signal to the timing controller 130. Components such as the timing controller 130, level shifter 150, power supply unit 140, host system 200, etc., may be part of a display device including the display panel 100.

[0067] Figure 2 This is a circuit diagram of the sub-pixel circuit according to the implementation method.

[0068] refer to Figure 2 The circuitry of each sub-pixel PXL (hereinafter referred to as the sub-pixel circuitry) can be connected to the data line DL for applying the data voltage Vdata, the gate line GL for applying the gate pulse SCAN, the drive voltage line VDDL for applying the pixel drive voltage EVDD, the low potential voltage line VSSL for applying the low potential voltage EVSS, and the reference voltage line RL for applying the reference voltage Vref.

[0069] Each subpixel circuit may include a light-emitting element EL, multiple transistors DT, T1, and T2, and a capacitor C. However, the structure of the subpixel circuit in the display panel described in this specification is not limited to this.

[0070] The light-emitting element (EL) can be an organic light-emitting diode (OLED) or an inorganic light-emitting element, such as a micro-LED. The EL can include, but is not limited to, red, green, and blue light-emitting elements. The anode electrode of the EL can be electrically connected to the driving element (DT) and can be located within a corresponding light-emitting area in each pixel. When current is generated from the driving element (DT), the EL is driven to emit light, and this light is emitted to the outside of the display panel via the light-emitting area.

[0071] The driving element DT can generate current based on the gate-source voltage, thereby driving the light-emitting element EL. The driving element DT includes a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. A capacitor C is connected between the first node N1 and the third node N3. The second node N2 is connected to the driving voltage line VDDL. The third node N3 is connected to the anode electrode of the light-emitting element EL. The cathode electrode of the light-emitting element EL is connected to a low-potential voltage line VSSL to which a low-potential voltage EVSS is applied.

[0072] A first switching element T1 is connected between the data line DL and the first node N1. The first switching element T1 is turned on in response to the gate pulse SCAN. When the first switching element T1 is turned on, the data voltage Vdata of the pixel data is applied to the first node N1, thereby writing the pixel data to the sub-pixel. The first switching element T1 may include a gate electrode connected to the gate line GL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0073] A second switching element T2 is connected between the third node N3 and the reference voltage line RL. The second switching element T2 is turned on in response to the gate pulse SCAN. When the second switching element T2 is on, the third node N3 is connected to the reference voltage line RL. The second switching element T2 may include a gate electrode connected to the gate line GL, a first electrode connected to the third node N3, and a second electrode connected to the reference voltage line RL.

[0074] Although the driving element DT is required to have uniform electrical characteristics across all sub-pixels, variations in manufacturing processes and device characteristics can lead to differences between sub-pixels, and these differences may increase over time as the sub-pixels are driven. To compensate for these electrical characteristic variations in the driving element DT, an external compensation circuit can be applied to the display panel driving circuit.

[0075] In the following embodiments, the gate line GL, drive voltage line VL, reference voltage line RL, drive element DT, first switching element T1, and second switching element T2 may sometimes be referred to as follows: Gate line GL may be referred to as scan line SL. Drive voltage line VL may be referred to as drive voltage line VL1-1. Reference voltage line RL may be referred to as reference voltage line VL2. Drive element DT may be referred to as third transistor T3. First switching element T1 and second switching element T2 may be referred to as first transistor T1 and second transistor T2, respectively.

[0076] Figure 4 This is a schematic circuit diagram for three sub-pixels according to an embodiment. Figure 5 This is a schematic circuit diagram for four sub-pixels according to an embodiment. In this specification, in... Figure 3 The diagram shows display panels configured with three and four sub-pixels as implementations, but the number of sub-pixels is not limited to this. Figures 6A to 6D yes Figure 5 A modified example of region A.

[0077] Figure 4 and Figure 5 The same reference numerals in the figures do not necessarily refer to the same color or signal. That is to say, Figure 4 and Figure 5 The same reference numerals in the figures can represent sub-pixels emitting different colors or signal output terminals containing different color information. For example, Figure 4 The first-1a sub-pixel SP1-1a shown is SP1-1a and Figure 5 The first sub-pixel SP1-1a shown can emit different colors.

[0078] refer to Figures 3 to 5 According to embodiments of this specification, a display panel includes: a plurality of pixels PXL arranged in a first direction X and a second direction Y that intersect each other; a plurality of signal output terminals DS (including DS1 and DS2) configured to supply data signals; and a plurality of data lines DL connected to the plurality of signal output terminals DS and configured to transmit the data signals to the plurality of pixels PXL, wherein the plurality of pixels PXL may include a first pixel connected to the first signal output terminal DS1, a second pixel connected to the second signal output terminal DS2, and a third pixel arranged in the first direction X between the first pixel and the second pixel and configured to be alternately connected to the first signal output terminal DS1 and the second signal output terminal DS2 in the second direction Y.

[0079] Multiple pixels (PXL) can be formed at the intersection of scan lines and data lines. Multiple pixels (PXL) can be arranged in multiple rows and columns. For example, multiple pixels (PXL) can be arranged in a grid.

[0080] Multiple pixels PXL may include a first-a pixel PXL1a, a second-a pixel PXL2a, a third-a pixel PXL3a, a fourth-a pixel PXL4a, a fifth-a pixel PXL5a, a first-b pixel PXL1b, a second-b pixel PXL2b, a third-b pixel PXL3b, a fourth-b pixel PXL4b, and a fifth-b pixel PXL5b. According to embodiments of this specification, the first-a to fifth-a pixels PXL1a, PXL2a, PXL3a, PXL4a, and PXL5a, as well as the first-b to fifth-b pixels PXL1b, PXL2b, PXL3b, PXL4b, and PXL5b, may be repeatedly arranged as pixel units in the display area.

[0081] Pixels PXL1a, PXL2a, PXL3a, PXL4a, and PXL5a from the first-a to the fifth-a, and pixels PXL1b, PXL2b, PXL3b, PXL4b, and PXL5b from the first-b to the fifth-b, can be arranged in multiple rows and columns. For example, pixels PXL1a, PXL2a, PXL3a, PXL4a, and PXL5a from the first-a to the fifth-a can be arranged sequentially in the first row and the first to fifth columns. For example, pixels PXL1b, PXL2b, PXL3b, PXL4b, and PXL5b from the first-b to the fifth-b can be arranged sequentially in the second row and the first to fifth columns.

[0082] Each of the multiple pixels in PXL can include multiple sub-pixels. (See reference) Figure 4 The display panel according to the embodiment may include three sub-pixels from each of a plurality of pixels PXL. The three sub-pixels may be any one of red, green and blue, but are not limited thereto.

[0083] refer to Figure 3 and Figure 4 The first -a pixel PXL1a may include the first -1a sub-pixel SP1-1a, the first -2a sub-pixel SP1-2a, and the first -3a sub-pixel SP1-3a. The second -a pixel PXL2a may include the second -1a sub-pixel SP2-1a, the second -2a sub-pixel SP2-2a, and the second -3a sub-pixel SP2-3a.

[0084] The third-a pixel PXL3a may include the third-1a sub-pixel SP3-1a, the third-2a sub-pixel SP3-2a, and the third-3a sub-pixel SP3-3a. The fourth-a pixel PXL4a may include the fourth-1a sub-pixel SP4-1a, the fourth-2a sub-pixel SP4-2a, and the fourth-3a sub-pixel SP4-3a. The fifth-a pixel PXL5a may include the fifth-1a sub-pixel SP5-1a, the fifth-2a sub-pixel SP5-2a, and the fifth-3a sub-pixel SP5-3a.

[0085] The first -b pixel PXL1b may include a first -1b sub-pixel SP1-1b, a first -2b sub-pixel SP1-2b, and a first -3b sub-pixel SP1-3b. The second -b pixel PXL2b may include a second -1b sub-pixel SP2-1b, a second -2b sub-pixel SP2-2b, and a second -3b sub-pixel SP2-3b. The third -b pixel PXL3b may include a third -1b sub-pixel SP3-1b, a third -2b sub-pixel SP3-2b, and a third -3b sub-pixel SP3-3b.

[0086] The fourth-b pixel PXL4b may include the fourth-1b sub-pixel SP4-1b, the fourth-2b sub-pixel SP4-2b, and the fourth-3b sub-pixel SP4-3b. The fifth-b pixel Px15b may include the fifth-1b sub-pixel SP5-1b, the fifth-2b sub-pixel SP5-2b, and the fifth-3b sub-pixel SP5-3b.

[0087] refer to Figure 5 According to another embodiment, the display panel may include four sub-pixels SP in each of a plurality of pixels PXL. Each of the four sub-pixels may be any one of white, red, green, and blue, but is not limited thereto.

[0088] refer to Figure 3 and Figure 5 The first -a pixel PXL1a may include first -1a sub-pixels SP1-1a, first -2a sub-pixels SP1-2a, first -3a sub-pixels SP1-3a, and first -4a sub-pixels SP1-4a. The second -a pixel PXL2a may include second -1a sub-pixels SP2-1a, second -2a sub-pixels SP2-2a, second -3a sub-pixels SP2-3a, and second -4a sub-pixels SP2-4a. The third -a pixel PXL3a may include third -1a sub-pixels SP3-1a, third -2a sub-pixels SP3-2a, third -3a sub-pixels SP3-3a, and third -4a sub-pixels SP3-4a.

[0089] The fourth-a pixel PXL4a may include the fourth-1a sub-pixel SP4-1a, the fourth-2a sub-pixel SP4-2a, the fourth-3a sub-pixel SP4-3a, and the fourth-4a sub-pixel SP4-4a. The fifth-a pixel PX15a may include the fifth-1a sub-pixel SP5-1a, the fifth-2a sub-pixel SP5-2a, the fifth-3a sub-pixel SP5-3a, and the fifth-4a sub-pixel SP5-4a.

[0090] The first -b pixel PXL1b may include a first -1b sub-pixel SP1-1b, a first -2b sub-pixel SP1-2b, a first -3b sub-pixel SP1-3b, and a first -4b sub-pixel SP1-4b. The second -b pixel PXL2b may include a second -1b sub-pixel SP2-1b, a second -2b sub-pixel SP2-2b, a second -3b sub-pixel SP2-3b, and a second -4b sub-pixel SP2-4b. The third -b pixel PXL3b may include a third -1b sub-pixel SP3-1b, a third -2b sub-pixel SP3-2b, a third -3b sub-pixel SP3-3b, and a third -4b sub-pixel SP3-4b.

[0091] The fourth-b pixel PXL4b may include the fourth-1b sub-pixel SP4-1b, the fourth-2b sub-pixel SP4-2b, the fourth-3b sub-pixel SP4-3b, and the fourth-4b sub-pixel SP4-4b. The fifth-b pixel Px15b may include the fifth-1b sub-pixel SP5-1b, the fifth-2b sub-pixel SP5-2b, the fifth-3b sub-pixel SP5-3b, and the fifth-4b sub-pixel SP5-4b.

[0092] Each sub-pixel SP may include a light-emitting portion EA and a circuit portion CA. The circuit portion CA includes pixel circuitry configured to drive each sub-pixel SP and may include at least one transistor. The light-emitting portion EA may be a region that emits light from a light-emitting element electrically connected to the pixel circuitry.

[0093] The light-emitting portion EA and the circuit portion CA can also be arranged side by side in the column direction Y. Sub-pixels SP included in a pixel PXL can have the same arrangement direction of the corresponding light-emitting portion EA and circuit portion CA, but this specification is not limited to this.

[0094] The arrangement of the light-emitting portion EA and the circuit portion CA can vary depending on the number and arrangement of scan lines connecting multiple pixels PXL. According to an embodiment of this specification, in a 2.5 RD structure, at least five scan lines can be provided for every two rows and five columns of pixel units, and scan signals are supplied to said at least five scan lines. However, in this specification, the number of scan lines, the arrangement structure of multiple scan lines, and the pixels connected to the scan lines are not limited to those disclosed.

[0095] According to embodiments of this specification, a first scan line SL1, a second scan line SL2, a third scan line SL3, a fourth scan line SL4, and a fifth scan line SL5 may be provided per pixel unit. Five scan lines can be configured to minimize or reduce the reduction in the aperture ratio of each sub-pixel SP.

[0096] Each of the first to fifth scan lines SL1, SL2, SL3, SL4, and SL5 can be arranged in the row direction and can be spaced apart from each other in the column direction. The first scan line SL1 and the second scan line SL2 can be configured to supply signals to sub-pixels SP arranged in the first row. The fourth scan line SL4 and the fifth scan line SL5 can be configured to supply signals to sub-pixels SP arranged in the second row. The third scan line SL3 can be arranged between the pixels arranged in the first row and the pixels arranged in the second row to supply signals to at least one pixel among a plurality of pixels in each of the first and second rows.

[0097] Except for some pixels (e.g., some pixels connected to the third scan line SL3), the pixels arranged in the first row and the pixels arranged in the second row may have an overall flip structure with respect to the third scan line SL3. A flip structure may mean that the arrangement of the circuit portion CA and the light-emitting portion EA of the pixels arranged in the first row and the pixels arranged in the second row are reversed with respect to each other. Here, some pixels that are not flipped with respect to the third scan line SL3 may be pixels connected to the third scan line SL3. In this case, the pixels arranged in the second direction Y (including some pixels connected to the third scan line SL3) may not have a flip structure with respect to the third scan line SL3. In other words, in one embodiment, some pixels arranged in the first row and some pixels arranged in the second row may be symmetrically arranged with respect to the third scan line SL3.

[0098] Apart from the pixels connected to the third scan line SL3, the first-a through fifth-a pixels PXL1a, PXL2a, PXL3a, PXL4a, and PXL5a can have their circuit portions CA and light-emitting portions EA positioned in the same direction. For example, each of the first-a, second-a, fourth-a, and fifth-a pixels PXL1a, PXL2a, PXL4a, and PXL5a can be arranged such that the light-emitting portion EA is closer to the second row than the circuit portion CA, while the third-a pixel PXL3a can be arranged such that the circuit portion CA is closer to the second row than the light-emitting portion EA.

[0099] The first scan line SL1 and the second scan line SL2 can be disposed between the circuit portion CA and the light-emitting portion EA of each of at least four pixels of the five first-a to fifth-a pixels PXL1a, PXL2a, PXL3a, PXL4a, and PXL5a arranged in the first row. The first scan line SL1 and the second scan line SL2 can be configured to intersect the light-emitting portion EA of at least one pixel arranged in the first row. For example, when the third-a pixel PXL3a is connected to the third scan line SL3, the first scan line SL1 and the second scan line SL2 can be configured to intersect the light-emitting portion EA of the third-a pixel PXL3a.

[0100] Each of the first scan line SL1 and the second scan line SL2 can be connected to two pixels out of the four pixels arranged in the first row. For example, the first scan line SL1 can be connected to the first-a pixel PXL1a and the fifth-a pixel PXL5a, and the second scan line SL2 can be connected to the second-a pixel PXL2a and the fourth-a pixel PXL4a.

[0101] Connecting scan lines and pixels (or sub-pixels) can include transmitting signals from scan lines to pixels. Furthermore, connecting scan lines and pixels (or sub-pixels) can include forming transistors at the intersections of scan lines and data lines connected to pixels, such that when a signal is supplied to the scan line, the transistors are switched and the signal from the data lines is supplied to the corresponding pixel. The transistors formed at the intersections of scan lines and data lines connected to pixels can be configured to... Figure 7 and Figure 10 In the switch unit ND shown.

[0102] Figure 4 The sub-pixels and Figure 5 The subpixels disclosed herein can be connected to the first scan line SL1 and the second scan line SL2 in the same manner as the corresponding pixels. Furthermore, the connection relationships between the third to fifth scan lines SL3, SL4, and SL5 and the pixels described below can relate to... Figure 4 and Figure 5 The pixels corresponding to the sub-pixels disclosed in the document.

[0103] Apart from the pixels connected to the third scan line SL3, the first-b to fifth-b pixels PXL1b, PXL2b, PXL3b, PXL4b, and PXL5b can have their circuit portions CA and light-emitting portions EA arranged in the same direction. For example, the first-b to third-b and fifth-b pixels PXL1b, PXL2b, PXL3b, and PXL5b can be arranged such that the light-emitting portion EA is closer to the first row than the circuit portion CA, and the fourth-b pixel PXL4b can be arranged such that the circuit portion CA is closer to the first row than the light-emitting portion EA.

[0104] The fourth scan line SL4 and the fifth scan line SL5 can be positioned between the circuit portion CA and the light-emitting portion EA of each of at least four of the five first-b to fifth-b pixels PXL1b, PXL2b, PXL3b, PXL4b, and PXL5b arranged in the second row. Furthermore, the fourth scan line SL4 and the fifth scan line SL5 can be positioned to intersect the light-emitting portion EA of at least one pixel arranged in the second row. For example, when the fourth-b pixel PXL4b is connected to the third scan line SL3, the fourth scan line SL4 and the fifth scan line SL5 can be positioned to intersect the light-emitting portion EA of the fourth-b pixel PXL4b.

[0105] Therefore, each of the fourth scan line SL4 and the fifth scan line SL5 can be connected to two pixels out of the five pixels in the pixel unit arranged in the second row. For example, the fourth scan line SL4 can be connected to the first-b pixel PXL1b and the fifth-b pixel PXL5b, and the fifth scan line SL5 can be connected to the second-b pixel PXL2b and the third-b pixel PXL3b.

[0106] The third scan line SL3 can be positioned between pixels PXL1a, PXL2a, PXL3a, PXL4a and PXL5a arranged in the first row and pixels PXL1b, PXL2b, PXL3b, PXL4b and PXL5b arranged in the second row.

[0107] In pixels connected to the third scan line SL3, the circuit portion CA can be arranged closer to the third scan line SL3 than the light-emitting portion EA. Pixels connected to the third scan line SL3 can be arranged in reverse order compared to pixels arranged in the same row. That is, at least one pixel arranged in the same row can have a circuit portion CA and a light-emitting portion EA arranged in the opposite direction to the other pixels.

[0108] For example, compared to pixels arranged in the same row, pixels connected to the third scan line SL3 may have circuit portions CA and light-emitting portions EA arranged in reverse order. For example, the third scan line SL3 may be connected to the third-a pixel PXL3a and the fourth-b pixel PXL4b. However, according to embodiments of this specification, the pixels connected to the third scan line SL3 in each row are not limited to this.

[0109] Multiple signal output terminals can be obtained from the data driver ( Figure 1(110) Output data voltage. Multiple signal output terminals can supply data signals to multiple pixels PXL via multiple data lines respectively connected to multiple pixels PXL. Data lines receiving the same data signal from one signal output terminal can be connected to different scan lines to independently drive each pixel or each sub-pixel.

[0110] Multiple signal output terminals may include a first signal output terminal DS1 and a second signal output terminal DS2. The first signal output terminal DS1 and the second signal output terminal DS2 may contain information of the same color.

[0111] Multiple data lines can be connected to each of the multiple signal output terminals. According to one embodiment, three data lines can be connected to each of the multiple signal output terminals. According to another embodiment, three data lines can be connected to each of the first signal output terminal DS1 and the second signal output terminal DS2. The first signal output terminal DS1 can supply signals to pixels arranged in the first to third columns via multiple data lines respectively connected thereto. The second signal output terminal DS2 can supply signals to pixels arranged in the third to fifth columns via multiple data lines respectively connected thereto.

[0112] The pixels arranged in the third column can be alternately connected to the first signal output terminal DS1 and the second signal output terminal DS2. Therefore, each of the first signal output terminal DS1 and the second signal output terminal DS2 can be connected to pixels arranged in 2.5 columns. According to an embodiment, each of the first signal output terminal DS1 and the second signal output terminal DS2 can be connected to pixels evenly arranged in 2.5 columns.

[0113] The first -1a data line DL1-1a, the first -2a data line DL1-2a, and the first -3a data line DL1-3a can be connected to the first signal output terminal DS1. The first -1b data line DL1-1b, the first -2b data line DL1-2b, and the first -3b data line DL1-3b can be connected to the second signal output terminal DS2.

[0114] Data line DL1-1a (first-1a) can transmit signals to pixels PXL1a and PXL1b arranged in the first column. Data line DL1-2a (first-2a) can transmit signals to pixels PXL2a and PXL2b arranged in the second column.

[0115] The first-3a data line DL1-3a can transmit signals to either pixel PXL3a or PXL3b arranged in the third column. The first-1b data line DL1-1b can also transmit signals to either pixel PXL3a or PXL3b arranged in the third column. Therefore, signals from the first-3a data line DL1-3a and the first-1b data line DL1-1b can be supplied alternately to pixels PXL3a and PXL3b arranged in the third column.

[0116] Alternating or continuously transmitting signals to pixels can mean alternately transmitting signals from a first signal output terminal and a second signal output terminal to pixels arranged in the second direction Y, or it can mean transmitting signals from the first signal output terminal to some sub-pixels included in each pixel, while simultaneously transmitting signals from the second signal output terminal to the remaining sub-pixels. When signals from different signal output terminals are transmitted to at least one sub-pixel included in each pixel, it can be considered that signals are being transmitted alternately to pixels.

[0117] Furthermore, alternately or continuously transmitting signals to pixels can mean alternately connecting the first signal output terminal and the second signal output terminal to pixels arranged in the second direction Y. Alternatively, alternately or continuously transmitting signals to pixels can mean connecting the first signal output terminal to one, two, or more pixels arranged in the second direction Y, and connecting the second signal output terminal to one, two, or more pixels arranged in the second direction Y, such that the first and second signal output terminals are alternately connected as a whole to pixels arranged in the second direction Y.

[0118] The first-2b data line DL1-2b can transmit signals to pixels PXL4a and PXL4b arranged in the fourth column. The first-3b data line DL1-3b can transmit signals to pixels PXL5a and PXL5b arranged in the fifth column.

[0119] The first-a pixel PXL1a can be located at the intersection of the first-1a data line DL1-1a and the first scan line SL1, and a signal can be supplied from there. The first-b pixel PXL1b can be located at the intersection of the first-1a data line DL1-1a and the fourth scan line SL4, and a signal can be supplied from there.

[0120] The second-a pixel PXL2a can be located at the intersection of the first-2a data line DL1-2a and the second scan line SL2, and can be supplied with signals from there. The second-b pixel PXL2b can be located at the intersection of the first-2a data line DL1-2a and the fifth scan line SL5, and can be supplied with signals from there.

[0121] The third-a pixel PXL3a can be located at the intersection of the first-3a data line DL1-3a and the third scan line SL3, and signals can be supplied from there. Alternatively, the third-a pixel PXL3a can be located at the intersection of the first-1b data line DL1-1b and the third scan line SL3, and signals can be supplied from there. Furthermore, among the multiple sub-pixels included in the third-a pixel PXL3a, some sub-pixels can be supplied with signals from the first-3a data line DL1-3a and the third scan line SL3, while the remaining sub-pixels can be supplied with signals from the first-1b data line DL1-1b and the third scan line SL3.

[0122] Signals can be provided to the third-b pixel PXL3b from the data lines not connected to the third-a pixel PXL3a from the first-3a data line DL1-3a and the first-1b data line DL1-1b, as well as from the fifth scan line SL5. For example, when the third-a pixel PXL3a is connected to the first-3a data line DL1-3a, the third-b pixel PXL3b can be connected to the first-1b data line DL1-1b. For example, when the third-a pixel PXL3a is connected to the first-1b data line DL1-1b, the third-b pixel PXL3b can be connected to the first-3a data line DL1-3a.

[0123] For example, when some sub-pixels of the third-a pixel PXL3a are connected to the first-3a data line DL1-3a and the remaining sub-pixels are connected to the first-1b data line DL1-1b, the third-b pixel PXL3b can be configured such that the sub-pixels corresponding to some sub-pixels of the third-a pixel PXL3a are connected to the first-1b data line DL1-1b, and the sub-pixels corresponding to the remaining sub-pixels of the third-a pixel PXL3a are connected to the first-3a data line DL1-3a.

[0124] The fourth-a pixel PXL4a can be located at the intersection of the first-2b data line DL1-2b and the second scan line SL2, and can be supplied with signals from there. The fourth-b pixel PXL4b can be located at the intersection of the first-2b data line DL1-2b and the third scan line SL3, and can be supplied with signals from there.

[0125] The fifth-a pixel PXL5a can be located at the intersection of the first-3b data line DL1-3b and the first scan line SL1, and can be supplied with signals from there. The fifth-b pixel PXL5b can be located at the intersection of the first-3b data line DL1-3b and the fourth scan line SL4, and can be supplied with signals from there.

[0126] The number of the first signal output terminal DS1 and the second signal output terminal DS2 can vary depending on the number of sub-pixels SP included in each pixel PXL. (Reference) Figure 4 When each pixel comprises three sub-pixels, the first-1 signal output terminal DS1-1, the first-2 signal output terminal DS1-2, and the first-3 signal output terminal DS1-3, which contain information of different colors, can correspond to the first signal output terminal DS1. In this case, the second-1 signal output terminal DS2-1, the second-2 signal output terminal DS2-2, and the second-3 signal output terminal DS2-3, which contain information of different colors, can correspond to the second signal output terminal DS2.

[0127] Signal output terminals DS1-1 and DS2-1 can contain information of the same color. Signal output terminals DS1-2 and DS2-2 can contain information of the same color. Signal output terminals DS1-3 and DS2-3 can contain information of the same color.

[0128] First data lines 1a to 3a (DL1-1a, DL1-2a, and DL1-3a) can be connected to the first signal output terminal DS1-1 and supplied with the same data signal. Second data lines 1a to 3a (DL2-1a, DL2-2a, and DL2-3a) can be connected to the first signal output terminal DS1-2 and supplied with the same data signal. Third data lines 1a to 3a (DL3-1a, DL3-2a, and DL3-3a) can be connected to the first signal output terminal DS1-3 and supplied with the same data signal.

[0129] Data lines DL1-1b, DL1-2b, and DL1-3b from the first-1b to the first-3b can be connected to the second-1 signal output terminal DS2-1 and supplied with the same data signal. Data lines DL2-1b, DL2-2b, and DL2-3b from the second-1b to the second-3b can be connected to the second-2 signal output terminal DS2-2 and supplied with the same data signal. Data lines DL3-1b, DL3-2b, and DL3-3b from the third-1b to the third-3b can be connected to the second-3 signal output terminal DS2-3 and supplied with the same data signal.

[0130] The first-1a sub-pixels SP1-1a and SP1-1b sub-pixels SP1-1b arranged in the first-1 column can be connected to the first-1a data line DL1-1a. The first-2a sub-pixels SP1-2a and SP1-2b sub-pixels SP1-2b arranged in the first-2 column can be connected to the second-1a data line DL2-1a. The first-3a sub-pixels SP1-3a and SP1-3b sub-pixels SP1-3b arranged in the first-3 column can be connected to the third-1a data line DL3-1a.

[0131] The second-1a sub-pixel SP2-1a and the second-1b sub-pixel SP2-1b arranged in column 2-1 can be connected to the first-2a data line DL1-2a. The second-2a sub-pixel SP2-2a and the second-2b sub-pixel SP2-2b arranged in column 2-2 can be connected to the second-2a data line DL2-2a. The second-3a sub-pixel SP2-3a and the second-3b sub-pixel SP2-3b arranged in column 2-3 can be connected to the third-2a data line DL3-2a.

[0132] The third-1a sub-pixel SP3-1a and the third-1b sub-pixel SP3-1b, arranged in column 3-1, can be connected to the first-3a data line DL1-3a or the first-1b data line DL1-1b, respectively. The third-2a sub-pixel SP3-2a and the third-2b sub-pixel SP3-2b, arranged in column 3-2, can be connected to the second-3a data line DL2-3a or the second-1b data line DL2-1b, respectively. The third-3a sub-pixel SP3-3a and the third-3b sub-pixel SP3-3b, arranged in column 3-3, can be connected to the third-3a data line DL3-3a or the third-1b data line DL3-1b.

[0133] For example, according to an embodiment of this specification, in the pixels arranged in the third column, the first-3a, second-3a, and third-3a data lines DL1-3a, DL2-3a, and DL3-3a corresponding to the first signal output terminal can be connected to the third-1a to third-3a sub-pixels SP3-1a, SP3-2a, and SP3-3a arranged in the first row, respectively, and the first-1b, second-1b, and third-1b data lines DL1-1b, DL2-1b, and DL3-1b corresponding to the second signal output terminal can be connected to the third-1b to third-3b sub-pixels SP3-1b, SP3-2b, and SP3-3b arranged in the second row, respectively. However, the embodiment of this specification is not limited to this, and signals from data lines connected to different signal output terminals can be alternately provided to the sub-pixels arranged in each column.

[0134] The fourth-1a sub-pixel SP4-1a and the fourth-1b sub-pixel SP4-1b, arranged in column 4-1, can be connected to the first-2b data line DL1-2b. The fourth-2a sub-pixel SP4-2a and the fourth-2b sub-pixel SP4-2b, arranged in column 4-2, can be connected to the second-2b data line DL2-2b. The fourth-3a sub-pixel SP4-3a and the fourth-3b sub-pixel SP4-3b, arranged in column 4-3, can be connected to the third-2b data line DL3-2b.

[0135] The fifth-1a sub-pixel SP5-1a and the fifth-1b sub-pixel SP5-1b, located in column 5-1, can be connected to the first-3b data line DL1-3b. The fifth-2a sub-pixel SP5-2a and the fifth-2b sub-pixel SP5-2b, located in column 5-2, can be connected to the second-3b data line DL2-3b. The fifth-3a sub-pixel SP5-3a and the fifth-3b sub-pixel SP5-3b, located in column 5-3, can be connected to the third-3b data line DL3-3b.

[0136] refer to Figure 5 When each pixel comprises four sub-pixels, the first signal output terminal DS1 may include a first-1 signal output terminal DS1-1, a first-2 signal output terminal DS1-2, a first-3 signal output terminal DS1-3, and a first-4 signal output terminal DS1-4, each containing information about different colors. In this case, the second signal output terminal DS2 may include a second-1 signal output terminal DS2-1, a second-2 signal output terminal DS2-2, a second-3 signal output terminal DS2-3, and a second-4 signal output terminal DS2-4, each containing information about different colors.

[0137] The first -1 signal output terminal DS1-1 and the second -1 signal output terminal DS2-1 can contain information of the same color. The first -2 signal output terminal DS1-2 and the second -2 signal output terminal DS2-2 can contain information of the same color. The first -3 signal output terminal DS1-3 and the second -3 signal output terminal DS2-3 can contain information of the same color. The first -4 signal output terminal DS1-4 and the second -4 signal output terminal DS2-4 can contain information of the same color.

[0138] Therefore, for the sub-pixels arranged in the third column, which is region A, data lines containing information of the same color can be alternately connected to the sub-pixels arranged in the same column. That is, multiple data lines are concentrated in region A, and the sub-pixels arranged in the same column can be arranged to have the same color.

[0139] Data lines DL1-1a, DL1-2a, and DL1-3a from the first-1a to the first-3a can be connected to the first-1 signal output terminal DS1-1. Data lines DL2-1a, DL2-2a, and DL2-3a from the second-1a to the second-3a can be connected to the first-2 signal output terminal DS1-2. Data lines DL3-1a, DL3-2a, and DL3-3a from the third-1a to the third-3a can be connected to the first-3 signal output terminal DS1-3. Data lines DL4-1a, DL4-2a, and DL4-3a from the fourth-1a to the fourth-3a can be connected to the first-4 signal output terminal DS1-4.

[0140] Data lines DL1-1b, DL1-2b, and DL1-3b from the first -1b to the first -3b can be connected to the second -1 signal output terminal DS2-1. Data lines DL2-1b, DL2-2b, and DL2-3b from the second -1b to the second -3b can be connected to the second -2 signal output terminal DS2-2. Data lines DL3-1b, DL3-2b, and DL3-3b from the third -1b to the third -3b can be connected to the second -3 signal output terminal DS2-3. Data lines DL4-1b, DL4-2b, and DL4-3b from the fourth -1b to the fourth -3b can be connected to the second -4 signal output terminal DS2-4.

[0141] Compared to an implementation with three sub-pixels, an implementation with four sub-pixels may include one or more data lines for each signal output terminal. In addition to the connections between sub-pixels and data lines implemented in the three sub-pixels, each pixel may also include connections between sub-pixels and data lines. Therefore, a description of the same structure as the connections between sub-pixels and data lines implemented in the three sub-pixels described above will be omitted.

[0142] Compared to three subpixels, the implementation of four subpixels can also include a first-4th column, a second-4th column, a third-4th column, a fourth-4th column, and a fifth-4th column. The first-4a subpixels SP1-4a and SP1-4b subpixels SP1-4b arranged in the first-4th column can be connected to the fourth-1a data line DL4-1a. The second-4a subpixels SP2-4a and SP2-4b subpixels SP2-4b arranged in the second-4th column can be connected to the fourth-2a data line DL4-2a. The fourth-4a subpixels SP4-4a and SP4-4b subpixels SP4-4b arranged in the fourth-4th column can be connected to the fourth-2b data line DL4-2b. The fifth-4a subpixels SP5-4a and SP5-4b subpixels SP5-4b arranged in the fifth-4th column can be connected to the fourth-3b data line DL4-3b.

[0143] Signals from data lines corresponding to the first signal output terminal and data lines corresponding to the second signal output terminal can be alternately provided to the sub-pixels arranged in the third column. In an embodiment including four sub-pixels, reference will be made to... Figures 6A to 6D This describes the connection relationship between the sub-pixels arranged in the third column and the data lines. However, this specification is not limited to this, and signals from different signal output terminals can be selectively and alternately provided to the sub-pixels arranged in each column.

[0144] Each of the four sub-pixels arranged in each row can be selectively driven by a data line corresponding to either the first or second signal output terminal. Since region A is an area where data lines of different signals are concentrated, signal interference between the different data lines may occur. Signal interference may cause a decrease in pixel brightness. To prevent this, in this specification, the four sub-pixels included in one pixel can be connected to the data lines corresponding to the first or second signal output terminal, in units of two sub-pixels.

[0145] refer to Figures 6A to 6D The four sub-pixels can be driven by connecting to each of the first and second signal output terminals in units of two sub-pixels. For example, the sub-pixels can be connected to the first or second signal output terminals in units of third-1a sub-pixels SP3-1a and third-2a sub-pixels SP3-2a, third-3a sub-pixels SP3-3a and third-4a sub-pixels SP3-4a, third-1b sub-pixels SP3-1b and third-2b sub-pixels SP3-2b, and third-3b sub-pixels SP3-3b and third-4b sub-pixels SP3-4b.

[0146] For example, sub-pixels SP3-1a and SP3-1b arranged in column 3-1 and sub-pixels SP3-2a and SP3-2b arranged in column 3-2 may each include one of white and blue. For example, sub-pixels SP3-3a and SP3-3b arranged in column 3-3 and sub-pixels SP3-4a and SP3-4b arranged in column 3-4 may each include one of red and green, but this specification is not limited thereto.

[0147] The first signal output terminal driving area C1 can be a region driven by the first-3a, second-3a, third-3a and fourth-3a data lines DL1-3a, DL2-3a, DL3-3a and DL4-3a corresponding to the first signal output terminal, and the second signal output terminal driving area C2 can be a region driven by the first-1b, second-1b, third-1b and fourth-1b data lines DL1-1b, DL2-1b, DL3-1b and DL4-1b corresponding to the second signal output terminal.

[0148] refer to Figure 6A Sub-pixels SP3-1a, SP3-2a, SP3-3b, and SP3-4b, respectively, can belong to the first signal output terminal driving area C1. Sub-pixels SP3-3a, SP3-4a, SP3-1b, and SP3-2b, respectively, can belong to the second signal output terminal driving area C2. Therefore, the sub-pixels arranged in the third column can be alternately connected to different signal output terminals.

[0149] refer to Figure 6B Sub-pixels SP3-1a to SP3-4a (SP3-1a, SP3-2a, SP3-3a, and SP3-4a) can belong to the first signal output terminal driving area C1. Sub-pixels SP3-1b to SP3-4b (SP3-1b, SP3-2b, SP3-3b, and SP3-4b) can belong to the second signal output terminal driving area C2. Therefore, the sub-pixels arranged in the third column can be alternately connected to different signal output terminals.

[0150] refer to Figure 6C Sub-pixels SP3-1a to SP3-4a (SP3-1a, SP3-2a, SP3-3a, and SP3-4a) can belong to the second signal output terminal driving area C2. Sub-pixels SP3-1b to SP3-4b (SP3-1b, SP3-2b, SP3-3b, and SP3-4b) can belong to the first signal output terminal driving area C1. Therefore, the sub-pixels arranged in the third column can be alternately connected to different signal output terminals.

[0151] refer to Figure 6D Sub-pixels SP3-1a, SP3-2a, SP3-3b, and SP3-4b, respectively, can belong to the second signal output terminal driving area C2. Sub-pixels SP3-3a, SP3-4a, SP3-1b, and SP3-2b, respectively, can belong to the first signal output terminal driving area C1. Therefore, the sub-pixels arranged in the third column can be alternately connected to different signal output terminals.

[0152] refer to Figure 4 and Figure 5A reference voltage Vref can be supplied from the pad portion to the reference voltage line VL2. The reference voltage line VL2 can be positioned in the same direction as the data line. The reference voltage line VL2 can be positioned between multiple pixels PXL arranged repeatedly in the row direction. The reference voltage line VL2 can supply voltage to the sub-pixels adjacent to it on its left and right sides. For example, the reference voltage line VL2 can be connected to the second transistor T2 in the circuit portion CA of each sub-pixel.

[0153] The pixel driving voltage EVDD can be supplied from the pad portion to the driving voltage line VL1-1. According to an embodiment of this specification, the pixel driving voltage EVDD can be supplied via a first driving voltage pattern VL1-2 and a second driving voltage pattern VL1-3 formed in a direction intersecting with the driving voltage line VL1-1. The driving voltage line VL1-1 and the first driving voltage pattern VL1-2 or the driving voltage line VL1-1 and the second driving voltage pattern VL1-3 can be formed on different layers together with an insulating layer interposed therebetween, and can be connected to each other via contact holes, but this specification is not limited thereto.

[0154] The driving voltage line VL1-1 can be positioned in the same direction as the data lines. According to an embodiment of this specification, the driving voltage line VL1-1 can be positioned to correspond to the remaining pixels in five pixel units repeatedly arranged in the row direction, excluding those arranged in any column. According to the embodiment, the driving voltage line VL1-1 may not be positioned in the pixels arranged in the third column, which is region A where the data lines corresponding to the first signal output terminal and the data lines corresponding to the second signal output terminal are concentrated.

[0155] For example, in an embodiment including three sub-pixels, the driving voltage line VL1-1 can be disposed between the sub-pixels arranged in the first and second columns of each pixel, while excluding region A. For example, in an embodiment including four sub-pixels, the driving voltage line VL1-1 can be disposed between the sub-pixels arranged in the second and third columns of each pixel, while excluding region A.

[0156] The first driving voltage pattern VL1-2 can be disposed in the first direction X. According to an embodiment, the first driving voltage pattern VL1-2 can be disposed between circuit portions CA facing each other in the second direction Y. For example, the first driving voltage pattern VL1-2 can be disposed at the upper end (upper end in the Y-axis direction) of pixels arranged in the first row and the lower end (lower end in the Y-axis direction) of pixels arranged in the second row. For example, the first driving voltage pattern VL1-2 may not be disposed in the area where the third scan line SL3 is disposed between pixels arranged in the first row and pixels arranged in the second row.

[0157] The first driving voltage pattern VL1-2 can be connected to the circuit portion CA of each adjacent sub-pixel. The sub-pixels where the circuit portion CA is arranged closer to the first driving voltage pattern VL1-2 than the light-emitting portion EA, and the sub-pixels where the light-emitting portion EA is arranged closer to the first driving voltage pattern VL1-2 than the circuit portion CA, can have different structures for connecting to the first driving voltage pattern VL1-2. (Reference) Figure 7 and Figure 8 This will be described.

[0158] Figure 7 This illustrates the first embodiment. Figure 5 A plan view of a portion of area A. Figure 8 It is shown Figure 5 Plan view of region B.

[0159] refer to Figure 7 and Figure 8 According to the embodiments, the sub-pixel may include a first electrode 161, which includes a light-emitting portion EA and a circuit portion CA, as well as a plurality of transistors T1, T2 and T3 disposed in the circuit portion CA and a light-shielding pattern 111. For example, a first driving voltage pattern VL1-2 may be connected to the third transistor T3 of each adjacent sub-pixel, but this specification is not limited thereto.

[0160] refer to Figure 7 Because the drive voltage line VL1-1 is not set in the data line set corresponding to the first signal output terminal and the second signal output terminal. Figure 5 In region A, the light-emitting portion EA is therefore positioned closer to the first driving voltage pattern VL1-2 than the circuit portion CA. Figure 5 The sub-pixels in region A can be connected to the first driving voltage pattern VL1-2 via the extended pattern T3-1 of the third transistor T3.

[0161] The extended pattern T3-1 can be formed by extending the source or drain electrode of the third transistor T3. However, this specification is not limited thereto. For example, the extended pattern T3-1 can be formed on a different layer than the source and drain electrodes of the third transistor T3 and connected to the third transistor T3 via a contact hole.

[0162] The extended pattern T3-1 can be connected from the circuit portion CA to the light-emitting portion EA via the first driving voltage pattern VL1-2. The extended pattern T3-1 can be configured to minimize or reduce interference with the light-emitting portion EA. The extended pattern T3-1 can be configured to overlap with the first portion 161a and the second portion 161b of the first electrode 161, but not with the third portion 161c of the first electrode 161, in order to minimize or reduce overlap with the light-emitting portion EA.

[0163] refer to Figure 8 ,exist Figure 5 In the region outside region A, the driving voltage line VL1-1 is set for each pixel, so the light-emitting part EA is set closer to the sub-pixel of the first driving voltage pattern VL1-2 than the circuit part CA, and can be connected to the second driving voltage pattern VL1-3 which is set to intersect with the driving voltage line VL1-1. In other words, in Figure 5 In areas other than region A, subpixels of pixels connected to the third scan line SL3 can be connected to the second driving voltage pattern VL1-3. The second driving voltage pattern VL1-3 can be connected to the driving voltage line VL1-1 to provide driving voltage to the corresponding pixels.

[0164] The second driving voltage pattern VL1-3 can be formed across the circuit portions of multiple sub-pixels. The second driving voltage pattern VL1-3 can extend from the point where it intersects with the driving voltage line VL1-1 to both sides of the first direction X, so as to electrically connect to the source electrode or drain electrode of the third transistor T3 of the adjacent sub-pixel.

[0165] refer to Figure 7 and Figure 8 The first electrode 161 may have a minimum width in some regions to minimize or reduce interference between the first electrode 161 and scan lines SL1, SL2, SL4 and SL5.

[0166] The first electrode 161 may include a first portion 161a, a second portion 161b, and a third portion 161c. The first portion 161a and the second portion 161b may also be configured to be adjacent to each other with the third portion 161c inserted therebetween. The third portion 161c is disposed between the first portion 161a and the second portion 161b, and may overlap with the first scan line SL1 and the second scan line SL2 or the fourth scan line SL4 and the fifth scan line SL5.

[0167] The third portion 161c, overlapping with scan lines SL1, SL2, SL4, and SL5, may have a first-1 width W1-1 that is narrower than the first-2 width W1-2 of the first portion 161a or the second portion 161b, to minimize or reduce signal interference. The first portion 161a and the second portion 161b may have substantially the same first-2 width W1-2. The minimum width of the first-1 width W1-1 of the third portion 161c may be determined based on the etching characteristics of the first electrode 161. The first-1 width W1-1 may be formed to be 1 / 4 to 1 / 2 narrower than the first-2 width W1-2, but this specification is not limited thereto.

[0168] Figure 9 yes Figure 7 A sectional view taken along line I-I'.

[0169] refer to Figure 9 According to embodiments of this specification, the display panel may include a substrate 10, a first insulating layer 20, a second insulating layer 30, a third insulating layer 40, a fourth insulating layer 50, and a light-emitting element 160. The light-emitting element includes a first electrode 161, an intermediate layer 163, and a second electrode 165 disposed on the fourth insulating layer 50. A first scan line SL1 and a second scan line SL2 may be formed on the second insulating layer 30 and disposed between the second insulating layer 30 and the third insulating layer 40.

[0170] The first insulating layer 20 may cover the substrate 10. The first insulating layer 20 may be referred to as a buffer layer. For example, the first insulating layer 20 may be made of an inorganic insulating film and may be formed as a single layer or multiple layers.

[0171] The second insulating layer 30 may be disposed on the first insulating layer 20. The second insulating layer 30 may be referred to as an interlayer insulating film. For example, the second insulating layer 30 may be made of an inorganic insulating film and may be formed as a single layer or multiple layers.

[0172] The third insulating layer 40 may be disposed on the second insulating layer 30. The third insulating layer 40 may be referred to as a passivation layer. For example, the third insulating layer 40 may be made of an inorganic insulating film and may be formed as a single layer or multiple layers.

[0173] A fourth insulating layer 50 may be disposed on the third insulating layer 40 to planarize the surface steps of the third insulating layer 40. The fourth insulating layer 50 may be referred to as a planarization film or an outer coating. For example, the fourth insulating layer 50 may be made of an organic insulating film and may be formed as a single layer or multiple layers.

[0174] The first electrode 161 can be disposed in each sub-pixel. The first electrode 161 may include a light-emitting portion EA and a circuit portion CA. In the case of a top-emitting display panel in this specification, the first electrode 161 can be formed to have a higher reflectivity than the second electrode 165. However, this specification is not limited to this, and in the case of a bottom-emitting type, the second electrode 165 can be formed to have a higher reflectivity than the first electrode 161.

[0175] For example, the first electrode 161 can be formed in a multilayer structure including a transparent conductive film with high reflectivity and an opaque conductive film.

[0176] An intermediate layer 163 is disposed on the first electrode 161 and can be formed through the substrate 10. The intermediate layer 163 may refer to a single or multiple stacked organic layer composed of multiple layers including a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0177] The second electrode 165 is disposed on the intermediate layer 163 facing the first electrode 161. The second electrode 165 may be formed throughout the substrate 10.

[0178] When the display panel in this specification is a top-emitting type, the second electrode 165 may be made of a transparent conductive layer.

[0179] Figure 10 This illustrates the second embodiment. Figure 5 A plan view of a portion of area A. Figure 11 yes Figure 10 A sectional view taken along line II-II'. Figure 10 and Figure 11 An embodiment capable of preventing or reducing interference between the first electrode and the scan line is shown. Figure 10 and Figure 11 In this document, the description of the same structure as in the previous embodiment will be omitted.

[0180] refer to Figure 10 and Figure 11 The first electrode 261 may include a first portion 261a and a second portion 261b. According to the second embodiment, the first electrode 261 may not overlap with scan lines SL1 and SL2.

[0181] According to the embodiment, the first portion 261a and the second portion 261b can be arranged spaced apart from each other. That is, according to the second embodiment, the first portion 261a and the second portion 261b can be in a directly separated state. The second portion 261b of the first electrode 261 can be integrally formed on the circuit portion CA with the first electrode 261 and driven by the circuit portion CA of the corresponding sub-pixel. The first portion 261a of the first electrode 261, which is spaced apart from the second portion 261b, can be electrically connected to the light-shielding pattern 211 formed in the circuit portion CA.

[0182] The light-emitting portions EA1 and EA2 are defined on the first electrode 261, such that the light-emitting portion EA according to the second embodiment does not overlap with the area where scan lines SL1 and SL2 are disposed. The light-emitting portion EA according to the second embodiment can be divided into a first light-emitting portion EA1 and a second light-emitting portion EA2. The first portion 261a of the first electrode 261 may include the first light-emitting portion EA1. The second portion 261b of the first electrode 261 may include the second light-emitting portion EA2.

[0183] The light-shielding pattern 211 according to the second embodiment may include a light-shielding area 211a, a connecting pattern 211b, and a contact pattern 211c. The light-shielding area 211a, the connecting pattern 211b, and the contact pattern 211c of the light-shielding pattern 211 may be integrally formed, but this specification is not limited thereto.

[0184] The light-shielding area 211a of the light-shielding pattern 211 can be set in the circuit section CA.

[0185] The connecting pattern 211b of the light-shielding pattern 211 can extend from the circuit portion CA to the first portion 261a of the first electrode 261. The connecting pattern 211b of the light-shielding pattern 211 can be disposed in the second direction Y.

[0186] The connection pattern 211b can be formed with a minimum width to minimize or reduce signal interference with scan lines SL1 and SL2. The second-1 width W2-1, which is the minimum width of the connection pattern 211b, can be narrower than the width of the first electrode 261. The minimum width of the second-1 width W2-1 can be determined based on the etching characteristics of the light-shielding pattern 211. The second-1 width W2-1 can be formed to be 1 / 10 or less of the width of the first electrode 261 in the first direction X, but this specification is not limited thereto.

[0187] Furthermore, since the material of the connecting pattern 211b has better etching properties than the material of the first electrode 261, according to the first embodiment, the second-1 width W2-1 can be formed to be narrower than the first-1 width W1-1 of the first electrode 261.

[0188] A contact pattern 211c electrically connected to the first portion 261a of the first electrode 261 can be disposed on the end of the connection pattern 211b. For good contact, the second-2 width W2-2 of the contact pattern 211c in the first direction X can be at least wider than the second-1 width W2-1.

[0189] The first portion 261a of the first electrode 261 and the contact pattern 211c of the light-shielding pattern 211 can be electrically connected at the first contact portion CTA. (Reference) Figure 11The contact pattern 211c of the light-shielding pattern 211 and the first portion 261a of the first electrode 261 can be electrically connected via a contact hole in the first contact portion CTA. The first portion 261a of the first electrode 261 may include a first electrode contact portion 261a-1 disposed within the contact hole of the first contact portion CTA.

[0190] A connecting electrode 21 can be further formed to reduce the resistance between the first portion 261a of the first electrode 261 and the contact pattern 211c of the light-shielding pattern 211. The connecting electrode 21 can be disposed on the same layer as the scan lines SL1 and SL2. However, embodiments according to this specification are not limited thereto, and the first electrode 261 and the contact pattern 211c can be in direct contact without the connecting electrode 21.

[0191] According to the second embodiment, the first to fourth insulating layers 20, 30, 40 and 50 may include contact holes for contacting the first portion 261a of the first electrode 261 with the contact pattern 211c of the light-shielding pattern 211.

[0192] The dam 70 can be disposed between the first portion 261a and the second portion 261b of the first electrode 261. The dam 70 disposed between the first portion 261a and the second portion 261b can overlap with the scan lines SL1 and SL2.

[0193] The first portion 261a and the second portion 261b of the first electrode 261, which are spaced apart from each other, are not limited to the disclosed embodiments, and can be driven by forming electrode patterns on a different layer from the first electrode 261, thereby electrically connecting them to each other.

[0194] Figure 12 It is shown Figure 5 A plan view of area D. Descriptions using the same reference numerals will be omitted.

[0195] refer to Figure 12 Multiple data lines DL1-1a to DL1-3a, DL2-1a to DL2-3a, DL3-1a to DL3-3a, DL4-1a to DL4-3a, DL1-1b to DL1-3b, DL2-1b to DL2-3b, DL3-1b to DL3-3b, and DL4-1b to DL4-3b can be connected to the corresponding signal output terminals DS1-1 to DS1-4 and DS2-1 to DS2-4 via link pattern LL. The link pattern LL, positioned in the first direction X, can be positioned on a different layer than the signal output terminals and data lines positioned in the second direction Y. The link pattern LL can be connected via the second contact portion CTB to each of the data lines and signal output terminals positioned on different layers to electrically connect the data lines and signal output terminals.

[0196] For example, the link pattern LL can be set on the same layer as the scan lines, and the data lines and signal output terminals can be set on the same layer as the light-shielding pattern.

[0197] Multiple driving voltage lines VL1-1 can be connected to a driving voltage output section VL1. The driving voltage output section VL1 extends from the pad portion and is formed into a strip shape at the ends where the multiple driving voltage lines VL1-1 meet. The multiple driving voltage lines VL1-1 are connected to the strip-shaped ends of the driving voltage output section VL1, thereby enabling a uniform supply of the pixel driving voltage EVDD. The multiple driving voltage lines VL1-1 and the driving voltage output section VL1 can be electrically connected via contact portions. According to the embodiment, the shape of the driving voltage output section VL1 described herein is merely exemplary and is not limited thereto.

[0198] This specification discloses a display panel. The display panel includes a plurality of pixels arranged in a first direction and a second direction intersecting each other, a plurality of signal output terminals configured to supply data signals, and a plurality of data lines connected to the plurality of signal output terminals and configured to transmit data signals to the pixels. The plurality of pixels includes a first pixel connected to a first signal output terminal, a second pixel connected to a second signal output terminal, and a third pixel arranged in the first direction between the first and second pixels and configured to alternately connect to the first and second signal output terminals in the second direction.

[0199] According to the embodiment of the display panel in this specification, each of the third pixels includes a plurality of sub-pixels, at least one sub-pixel of any of the third pixels is connected to the first signal output terminal, and the remaining sub-pixels are connected to the second signal output terminal.

[0200] According to the embodiment of the display panel in this specification, each of the third pixels includes a first to a fourth sub-pixel, the first and second sub-pixels of any of the third pixels are connected to either the first signal output terminal or the second signal output terminal, and the third and fourth sub-pixels are connected to the other of the first and second signal output terminals.

[0201] According to the embodiment of the display panel in this specification, the plurality of data lines include: first-1 to first-3 data lines connected to a first signal output terminal; and second-1 to second-3 data lines connected to a second signal output terminal. A first pixel is connected to a first-2 data line, a second pixel is connected to a second-2 data line, and a third pixel is alternately connected to the first-3 data line and the second-1 data line in a second direction. The plurality of pixels also include: a fourth pixel connected to the first-1 data line; and a fifth pixel connected to the second-3 data line.

[0202] According to the embodiment of the display panel in this specification, each of the plurality of pixels includes a light-emitting portion and a circuit portion arranged side by side in one direction, and any one of the first to third pixels has a light-emitting portion and a circuit portion arranged in the opposite direction to the other pixels.

[0203] According to an embodiment of the display panel in this specification, the display panel includes first to third scan lines configured to supply scan signals to a plurality of pixels, wherein a light-emitting portion and a circuit portion are disposed in a direction opposite to the other pixels and any pixel is connected to the third scan line, and except for the pixels connected to the third scan line, the pixels arranged in the first row and the pixels arranged in the second row are arranged to be flipped about the third scan line.

[0204] According to an embodiment of the display panel described in this specification, the display panel includes a first electrode disposed in each of the plurality of pixels and including a light-emitting portion. The first scan line and the second scan line overlap with the light-emitting portion of the first electrode of the pixel connected to a third scan line. The first electrode of the pixel connected to the third scan line includes: a first portion overlapping the first scan line and the second scan line, and a second portion and the third portion adjacent to each other with the first portion inserted therebetween. The first portion has a first width in the first direction that is narrower than the second portion or the third portion in the first direction.

[0205] According to an embodiment of the display panel in this specification, the display panel includes a first electrode disposed in each of a plurality of pixels and a light-shielding pattern disposed in a circuit portion of each of the plurality of pixels. The first electrode of the pixel connected to the third scan line includes: a first portion; and a second portion spaced apart from the first portion and having a region overlapping with the light-shielding pattern. The first scan line and the second scan line are disposed in a gap region between the first portion and the second portion of the first electrode of the pixel connected to the third scan line. The first portion of the first electrode is electrically connected to a connecting pattern extending from the light-shielding pattern to the first portion. The first width of the connecting pattern in a first direction is narrower than the second width of the first portion or the second portion of the first electrode in a first direction.

[0206] According to an embodiment of the display panel described in this specification, the display panel includes: a driving voltage line configured to supply a pixel driving voltage; and a first driving voltage pattern electrically connected to the driving voltage line and disposed in a direction intersecting the driving voltage line, the third pixel including an extension pattern extending from the source electrode or drain electrode of a transistor disposed in a circuit portion, the driving voltage line being disposed in each of the first pixel and the second pixel but not in the third pixel, the first driving voltage pattern being disposed on one side of the light-emitting portion of the third pixel, and the extension pattern being electrically connected to the first driving voltage pattern.

[0207] According to an embodiment of the display panel described in this specification, the display panel includes: a driving voltage line configured to supply a pixel driving voltage; and a second driving voltage pattern electrically connected to the driving voltage line and disposed in a direction intersecting the driving voltage line, wherein each of the plurality of pixels includes a plurality of sub-pixels, the second driving voltage pattern is formed across the plurality of sub-pixels of a first pixel, and the source electrode or drain electrode of a transistor disposed in a circuit portion of each of the plurality of sub-pixels of the first pixel is electrically connected to the second driving voltage pattern.

[0208] Although embodiments of the invention have been described in more detail with reference to the accompanying drawings, the invention is not necessarily limited to these embodiments, and various modifications and implementations can be made without departing from the spirit of the invention.

[0209] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to represent the technical concept of the invention, the scope of which is not limited by these embodiments.

[0210] Therefore, the above embodiments should be understood in all respects as illustrative rather than restrictive.

[0211] The scope of protection of this disclosure shall be interpreted by the claims, and all technical ideas within the same scope shall be interpreted as being included within the scope of this disclosure.

[0212] Cross-references to related applications

[0213] This application claims priority and benefit to Korean Patent Application No. 10-2025-0050806, filed on April 18, 2025, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display panel, the display panel comprising: Multiple pixels, the multiple pixels being arranged in a first direction and a second direction that intersect each other; Multiple signal output terminals, the multiple signal output terminals being configured to supply data signals; as well as Multiple data lines are connected to the multiple signal output terminals and configured to transmit the data signals to the multiple pixels. The plurality of pixels includes: A first pixel, wherein the first pixel is connected to a first signal output terminal among the plurality of signal output terminals; The second pixel is connected to the second signal output terminal among the plurality of signal output terminals; and A third pixel is disposed between the first pixel and the second pixel in the first direction and is configured to be alternately connected to the first signal output terminal and the second signal output terminal in the second direction.

2. The display panel according to claim 1, wherein, Each of the third pixels comprises multiple sub-pixels, and Wherein, at least one sub-pixel of any of the third pixels is connected to the first signal output terminal, and the remaining sub-pixels of any of the third pixels are connected to the second signal output terminal.

3. The display panel according to claim 1, wherein, Each of the third pixels includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and The first sub-pixel and the second sub-pixel, which are included in either of the third pixels, are connected to either the first signal output terminal and the second signal output terminal, and the third sub-pixel and the fourth sub-pixel are connected to the other of the first signal output terminal and the second signal output terminal.

4. The display panel according to claim 1, wherein, The multiple data lines include: The first-1 data line, the first-2 data line, and the first-3 data line are connected to the first signal output terminal; and Data lines 2-1, 2-2, and 2-3 are connected to the second signal output terminal. The first pixel is connected to the first -2 data line. The second pixel is connected to the second-2 data line.

5. The display panel according to claim 4, wherein, The third pixel is alternately connected to the first -3 data line and the second -1 data line in the second direction.

6. The display panel according to claim 5, wherein, The plurality of pixels also includes: The fourth pixel, which is connected to the first -1 data line; and The fifth pixel is connected to the second-3 data line.

7. The display panel according to claim 1, wherein, Each of the plurality of pixels includes a light-emitting portion and a circuit portion arranged side by side in one direction, and Wherein, any one of the first pixel, the second pixel, and the third pixel has a light-emitting portion and a circuit portion disposed in a direction opposite to the direction of the light-emitting portion and the circuit portion of the remaining pixels among the first pixel, the second pixel, and the third pixel.

8. The display panel according to claim 7, further comprising: A first scan line, a second scan line, and a third scan line are configured to supply scan signals to the plurality of pixels. Wherein, the light-emitting portion and the circuit portion are disposed in any pixel that is connected to the third scan line in a direction opposite to the direction of the light-emitting portion and the circuit portion of the remaining pixels.

9. The display panel according to claim 8, wherein, The pixels arranged in the first row and the pixels arranged in the second row, except for the pixels in the first row and the second row that are connected to the third scan line, are arranged to be flipped about the third scan line.

10. The display panel according to claim 8, further comprising: A first electrode is disposed in each of the plurality of pixels and includes a light-emitting portion. The first scan line and the second scan line overlap with the light-emitting portion of the first electrode of the pixel connected to the third scan line.

11. The display panel according to claim 10, wherein, The first electrode of the pixel connected to the third scan line includes: The first portion that overlaps with the first scan line and the second scan line, and The second and third portions are adjacent to each other, with the first portion inserted between the second and third portions.

12. The display panel according to claim 11, wherein, The first width of the first portion in the first direction is narrower than the second width of the second portion or the third portion in the first direction.

13. The display panel according to claim 8, further comprising: A first electrode, wherein the first electrode is disposed in each of the plurality of pixels, and A light-shielding pattern is disposed in the circuit portion of each of the plurality of pixels.

14. The display panel according to claim 13, wherein, The first electrode of the pixel connected to the third scan line includes: Part One; and The second part is spaced apart from the first part and has an area that overlaps with the light-shielding pattern. The first scan line and the second scan line are disposed in the interval region between the first portion and the second portion of the first electrode of the pixel connected to the third scan line.

15. The display panel according to claim 14, wherein, The first portion of the first electrode is electrically connected to a connection pattern extending from the light-shielding pattern to the first portion, and Wherein, the first width of the connection pattern in the first direction is narrower than the second width of the first portion or the second portion of the first electrode in the first direction.

16. The display panel according to claim 1, further comprising: A driving voltage line, configured to supply pixel driving voltage, and The driving voltage line is provided in each of the first pixel and the second pixel.

17. The display panel according to claim 16, further comprising: A first driving voltage pattern is electrically connected to the driving voltage line and is positioned in the direction intersecting the driving voltage line. One of the third pixels includes an extension pattern in which the source or drain electrode of a transistor disposed in the circuit portion extends, and The extended pattern is electrically connected to the first driving voltage pattern.

18. The display panel according to claim 17, wherein, The first driving voltage pattern is disposed on one side of the light-emitting portion of the third pixel, including the extended pattern.

19. The display panel according to claim 1, further comprising: A driving voltage line, the driving voltage line being configured to supply pixel driving voltage; as well as A second driving voltage pattern, electrically connected to the driving voltage line and positioned in the direction intersecting the driving voltage line, Each of the plurality of pixels includes a plurality of sub-pixels, and The second driving voltage pattern extends across the plurality of sub-pixels of the first pixel.

20. The display panel according to claim 19, wherein, The source or drain electrode of a transistor disposed in the circuit portion of each of the plurality of sub-pixels of the first pixel is electrically connected to the second driving voltage pattern.

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