Electronic device

Abstract

An electronic device includes a processor configured to provide image data and a display luminance value, a display panel including a pixel circuit including a plurality of transistors and a plurality of capacitors, a light emitting element connected to the pixel circuit, and a signal line connected to the plurality of transistors, and a panel driver configured to drive the display panel, wherein, in a planar view, the signal line includes a first voltage line, a reference scan line below the first voltage line, a first emission signal line below the reference scan line, a first power line below the first emission signal line, a write scan line below the first power line, a second emission signal line below the write scan line, an initialization scan line below the second emission signal line, and a second voltage line below the initialization scan line.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0042530, filed on April 2, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to electronic devices including pixel circuits with improved reliability. Background Technology

[0003] A display panel included in an electronic device may include multiple pixels and driving circuitry (e.g., scan driver circuitry and data driver circuitry) capable of controlling the multiple pixels. Each of the multiple pixels may include a light-emitting element and pixel circuitry capable of controlling the light-emitting element. The pixel circuitry may include multiple transistors cooperating with each other and at least one capacitor. As the resolution of the pixels increases, optimizing the pixel circuitry structure can be beneficial. Summary of the Invention

[0004] An electronic device including pixel circuitry with improved reliability is provided.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description or may be learned by practice of the presented embodiments.

[0006] According to an aspect of this disclosure, an electronic device includes: a processor configured to provide image data and display brightness values; a display panel including pixel circuits comprising a plurality of transistors and a plurality of capacitors, light-emitting elements connected to the pixel circuits, and signal lines connected to the plurality of transistors; and a panel driver configured to receive image data and display brightness values ​​and drive the display panel based on the image data and display brightness values, wherein, on a plane, the signal lines include: a first voltage line; a reference scan line below the first voltage line; a first transmit signal line below the reference scan line; a first power line below the first transmit signal line; a write scan line below the first power line; a second transmit signal line below the write scan line; an initialization scan line below the second transmit signal line; and a second voltage line below the initialization scan line.

[0007] The plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor correspond to the first transistor type.

[0008] The fifth and sixth transistors correspond to a second transistor type that is different from the first transistor type.

[0009] The electronic device may further include a first node connected to a first transistor and a light-emitting element, wherein the first transistor is connected between the first node and a first power line, wherein a fifth transistor is connected between the first power line and the drain of the first transistor and is connected to a first transmit signal line, wherein a sixth transistor is connected between the first node and the light-emitting element and is connected to a second transmit signal line, wherein the fifth transistor is configured to receive a first transmit signal using the first transmit signal line, and wherein the sixth transistor is configured to receive a second transmit signal using the second transmit signal line.

[0010] On a plane, the first semiconductor pattern corresponding to the first transistor may be above the fifth semiconductor pattern corresponding to the fifth transistor and the sixth semiconductor pattern corresponding to the sixth transistor.

[0011] On a plane, the fifth semiconductor pattern can be between the first semiconductor pattern and the sixth semiconductor pattern.

[0012] The fifth and sixth semiconductor patterns may include polycrystalline silicon.

[0013] The electronic device may further include: a second node connected to a first transistor and a second transistor, wherein the second transistor is connected between the second node and a data line and is connected to a write scan line, wherein a third transistor is connected between the second node and a first voltage line and is connected to a reference scan line, wherein the first voltage line is configured to receive a reference voltage, wherein the second transistor is configured to receive a data signal using the data line, and wherein the third transistor is configured to receive a reference scan signal using the reference scan line.

[0014] On a plane, the second semiconductor pattern corresponding to the second transistor may be below the first semiconductor pattern corresponding to the first transistor, and the third semiconductor pattern corresponding to the third transistor may be above the first semiconductor pattern.

[0015] The first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern may include oxide semiconductors.

[0016] On a plane, the first semiconductor pattern corresponding to the first transistor can be located between the reference scan line and the first transmit signal line.

[0017] According to an aspect of this disclosure, an electronic device includes: a processor configured to provide image data and display brightness values; a display panel including pixel circuitry, light-emitting elements connected to the pixel circuitry, and signal lines connected to a plurality of transistors, wherein the pixel circuitry includes a plurality of transistors and a plurality of capacitors; and a panel driver configured to receive image data and display brightness values ​​and drive the display panel based on the image data and display brightness values, wherein, on a plane, the signal lines include: a second voltage line; an initialization scan line below the second voltage line; a second transmission signal line below the initialization scan line; a write scan line below the second transmission signal line; a reference scan line below the write scan line; a first transmission signal line below the reference scan line; a first voltage line below the first transmission signal line; and a first power line below the first voltage line.

[0018] The plurality of transistors may include a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, wherein the first transistor, the second transistor, the third transistor, and the fourth transistor correspond to the first transistor type.

[0019] The fifth and sixth transistors correspond to a second transistor type that is different from the first transistor type.

[0020] The electronic device may further include: a first node connected to a first transistor and a light-emitting element, wherein the first transistor is connected between the first node and a first power line, wherein a fifth transistor is connected between the first power line and the drain of the first transistor and is connected to a first transmit signal line, wherein a sixth transistor is connected between the first node and the light-emitting element and is connected to a second transmit signal line, wherein the fifth transistor is configured to receive a first transmit signal using the first transmit signal line, and wherein the sixth transistor is configured to receive a second transmit signal using the second transmit signal line.

[0021] On a plane, the fifth semiconductor pattern corresponding to the fifth transistor may be below the first semiconductor pattern corresponding to the first transistor, and the sixth semiconductor pattern corresponding to the sixth transistor may be above the first semiconductor pattern corresponding to the first transistor.

[0022] The fifth and sixth semiconductor patterns may include polycrystalline silicon.

[0023] The electronic device may further include: a second node connected to a first transistor and a second transistor, wherein the second transistor is connected between the second node and a data line and is connected to a write scan line, wherein a third transistor is connected between the second node and a first voltage line and is connected to a reference scan line.

[0024] The first voltage line is configured to receive a reference voltage, wherein the second transistor is configured to receive a data signal using a data line, and wherein the third transistor is configured to receive a reference scan signal using a reference scan line.

[0025] On a plane, the second semiconductor pattern corresponding to the second transistor may be above the first semiconductor pattern corresponding to the first transistor, and the third semiconductor pattern corresponding to the third transistor may be below the first semiconductor pattern corresponding to the first transistor.

[0026] The first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern may include oxide semiconductors.

[0027] On a plane, the first semiconductor pattern corresponding to the first transistor can be located between the write scan line and the reference scan line.

[0028] The light-emitting element may include a first electrode, a second electrode, and an emitting layer between the first electrode and the second electrode. Attached Figure Description

[0029] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which: Figure 1A This is a block diagram of an electronic device according to an embodiment; Figure 1B Schematic diagrams of electronic devices according to various embodiments are shown; Figure 1C This is a perspective view of an electronic device according to an embodiment; Figure 2 This illustrates an embodiment. Figure 1C A cross-sectional view of the electronic device shown; Figure 3 This illustrates an embodiment. Figure 2 A cross-sectional view of the display panel shown; Figure 4 This is a block diagram of an electronic device according to an embodiment; Figure 5 This is a circuit diagram of the pixels according to an embodiment; Figure 6 This is a cross-sectional view of the display panel according to an embodiment; Figure 7 This is a schematic plan view illustrating the pixel circuitry according to an embodiment; Figure 8A and Figure 8B This illustrates an embodiment. Figure 7 A schematic plan view of the pixel circuit shown; Figure 9This is a schematic plan view illustrating the pixel circuitry according to an embodiment; and Figure 10A and Figure 10B This illustrates an embodiment. Figure 9 A schematic plan view of the pixel circuit shown. Detailed Implementation

[0030] In this disclosure, when a first component (e.g., a region, layer, portion, etc.) is referred to as being "on" a second component, "connected to" a second component, or "coupled to" a second component, this may mean that the first component is directly on, directly connected to, or directly coupled to the second component, and may also mean that a third component may exist between the first and second components. According to embodiments, a first component described as being "connected to" a second component may also be referred to as being "connected to" a second component.

[0031] The same reference numerals may refer to the same or similar components. Furthermore, in the drawings, the thickness, scale, and dimensions of components are exaggerated for ease of description. As used herein, the term "and / or" can include all combinations of one or more combinations defined by the relevant components.

[0032] Terms such as “first” and “second” may be used to describe various components, but these components are not intended to be limited by these terms. These terms may be used only to distinguish one component from other components. For example, without departing from the scope of this disclosure, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless otherwise stated, singular terms may include plural forms.

[0033] Furthermore, terms such as "below," "under," "above," and "on top of" are used to describe the relationships between the components shown in the accompanying drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0034] It should be understood that when terms such as “comprising,” “including,” and “having” are used herein, it indicates the presence of the stated features, numbers (numbers), steps, operations, components, parts, or combinations thereof, but does not exclude the presence or addition of one or more other features, numbers (numbers), steps, operations, components, parts, or combinations thereof.

[0035] Unless otherwise specified, all terms used herein (including technical or scientific terms) may have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Unless expressly defined herein as having an ideal or overly formal meaning, terms such as those defined in a general dictionary shall be interpreted as having the same meaning as in the context of the relevant technical field and shall not be interpreted as having an ideal or overly formal meaning.

[0036] In the following description, embodiments of the present disclosure are illustrated with reference to the accompanying drawings.

[0037] Figure 1A This is a block diagram of an electronic device according to an embodiment. Figure 1B Schematic diagrams of electronic devices according to various embodiments are shown. Figure 1C This is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0038] Reference Figure 1A The electronic device ED according to the embodiment may include a display module 11, a processor 12, a memory 13 and a power module 14.

[0039] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In an embodiment, processor 12 may be configured to provide image data and display brightness values.

[0040] Data information for the operation of processor 12 or display module 11 can be stored in memory 13. When processor 12 executes the application stored in memory 13, image data signals and / or input control signals can be transmitted to display module 11, and display module 11 can process the provided signals and output image information using the display screen.

[0041] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module and generates the power required for the operation of the electronic device ED.

[0042] At least one of the components of the electronic device ED described above may be included in the display device according to the embodiment. Furthermore, some modules that are functionally included in a single module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include display module 11, and processor 12, memory 13, and power module 14 may be provided as other devices in the electronic device ED other than the display device.

[0043] Reference Figure 1BThe various electronic devices to which the display device according to the embodiment is applied may include electronic devices for displaying images, such as smartphones 10_1a, tablet PCs 10_1b, laptops 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e, and may also include wearable electronic devices including display modules, such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c, as well as vehicle electronic devices including display modules, such as central information displays and rearview mirror displays installed on the dashboard, central instrument panel, and dashboard of a vehicle.

[0044] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the display device described above, and may also include modules or devices with other additional functions besides the display device.

[0045] Reference Figure 1C According to an embodiment, the electronic device ED may have long sides (e.g., sides with a first length) extending parallel to each other in a first direction DR1 and short sides (e.g., sides with a second length shorter than the first length) extending parallel to each other in a second direction DR2 intersecting the first direction DR1. The angle connecting the long and short sides of the electronic device ED may have a curved shape. The curved angle of the electronic device ED may be referred to as a rounded corner. The shape of the electronic device ED may be referred to as a rounded rectangular shape.

[0046] In the following text, the direction substantially perpendicular to the plane defined by the first direction DR1 and the second direction DR2 may be referred to as the third direction DR3. Furthermore, as used herein, when an element is described as “viewed from above the plane” or “on the plane,” this means that the element is viewed in the third direction DR3.

[0047] The front surface of the electronic device ED can be referred to as the display surface DS, and may have or correspond to a plane defined by a first direction DR1 and a second direction DR2. The image IM generated by the electronic device ED can be provided to the user through the display surface DS.

[0048] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround or enclose the display area DA, and may define the boundaries of the electronic device ED printed in a specific color.

[0049] The display area DA can have a rounded rectangular shape depending on the shape of the electronic device ED. For example, the display area DA may include rectangular sides extending in a first direction DR1 and a second direction DR2, and rounded corners connecting these sides. Of the four sides, the side extending in the first direction DR1 may be referred to as the long side, and the side extending in the second direction DR2 may be referred to as the short side.

[0050] An electronic device (ED) can sense one or more inputs applied from outside the ED. For example, the ED can sense a first input via a stylus pen (PEN) and a second input via a touch TT. The stylus pen (PEN) can be referred to as an input device.

[0051] The stylus (PEN) can be an active pen that outputs signals. A second input via the touch TT can include various types of external inputs such as the user's body parts, light, heat, or pressure.

[0052] The electronic device (ED) and the stylus (PEN) can communicate bidirectionally with each other. The electronic device (ED) can provide uplink signals to the stylus (PEN). For example, the uplink signals may include information such as panel information and protocol version, but are not particularly limited to this.

[0053] The stylus pen (PEN) can provide downlink signals to the electronic device (ED). Downlink signals may include synchronization signals or status information of the stylus pen (PEN). For example, downlink signals may include coordinate information of the stylus pen (PEN), battery information of the stylus pen (PEN), tilt information of the stylus pen (PEN), and / or various information stored in the stylus pen (PEN), but are not particularly limited thereto.

[0054] Electronic devices (EDs) can be used in large electronic devices such as televisions, monitors, and billboards. Furthermore, electronic devices (EDs) can be used in small to medium-sized electronic devices such as personal computers, laptops, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, and cameras. However, these are merely examples, and electronic devices (EDs) can be used in other electronic devices without departing from the spirit and scope of this disclosure.

[0055] Figure 2 It is shown Figure 1C A cross-sectional view of the electronic device shown. According to an embodiment, Figure 2 An example of a cross-section of the electronic device ED as viewed in the second direction DR2 is shown.

[0056] Reference Figure 2The electronic device ED may include a display panel DP, an input sensing portion ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, a first adhesive layer AL1, and a second adhesive layer AL2. In an embodiment, the electronic device ED may further include a receiver for receiving signals from a processor 12 (see reference 12). Figure 1A The panel driver (not shown) provides image data and display brightness values, and the panel driver can drive the display panel DP based on the image data and display brightness values.

[0057] The display panel DP according to embodiments of this disclosure can be an emitting display panel. For example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The emitting layer of an inorganic light-emitting display panel can include quantum dots and quantum rods. Hereinafter, the display panel DP is described as an example of an organic light-emitting display panel, but the embodiments are not limited thereto.

[0058] The input sensing portion (ISP) can be disposed on the display panel (DP). The input sensing portion (ISP) may include multiple sensing portions (e.g., sensors such as capacitive sensors) for sensing external inputs of the capacitive type. When manufacturing the electronic device (ED), the input sensing portion (ISP) can be fabricated directly on the display panel (DP). However, embodiments are not limited thereto. For example, in some embodiments, the input sensing portion (ISP) can be fabricated as a panel, film, or layer separate from the display panel (DP) and can be attached to the display panel (DP) via an adhesive layer.

[0059] The anti-reflective layer RPL can be disposed on the input sensing portion ISP. When manufacturing the electronic device ED, the anti-reflective layer RPL can be fabricated directly on the input sensing portion ISP. However, embodiments are not limited thereto. For example, in some embodiments, the anti-reflective layer RPL can be fabricated as a separate panel, film, or layer, and can be attached to the input sensing portion ISP via an adhesive layer.

[0060] An anti-reflective layer (RPL) can be described as a film used to prevent the reflection of external light. The RPL reduces the reflectivity of external light incident on the display panel (DP) from above the electronic device (ED). Because of the RPL, external light is invisible to the user.

[0061] When external light traveling towards the display panel DP is reflected by the display panel DP and then returned to the user, the user can visually perceive the external light as if it were reflected in a mirror. To prevent this phenomenon, for example, an anti-reflective layer RPL may include pixels PX (refer to) the display panel DP. Figure 4 It displays multiple color filters of the same color.

[0062] A color filter can filter out external light of the same color as pixel PX. In this case, the external light is invisible to the user. However, embodiments are not limited to this. For example, in some embodiments, the anti-reflective layer RPL may include a phase retarder and / or a polarizer to reduce the reflectivity of external light.

[0063] The electronic device ED according to an embodiment may further include a camera module. The camera module may be disposed below the display panel DP, which includes a display area DA. Pixels PX (e.g., such as...) that overlap with the camera module are also included. Figure 4 The pixel circuit PXC (as shown) in the diagram (e.g., as shown) Figure 5 (as shown) and includes pixel PXs that do not overlap with the camera module (e.g., as shown) Figure 4 The pixel circuit PXC (as shown) in the diagram (e.g., as shown) Figure 5 The (shown) may have a stacked structure of conductive layers as described below, and is not limited to any of the examples described herein.

[0064] The WIN window can be installed on the anti-reflective layer RPL. The WIN window can protect the display panel DP, the input sensing part ISP, and the anti-reflective layer RPL from external scratches and impacts.

[0065] A panel protective film (PPF) can be applied beneath the display panel (DP). The PPF protects the bottom of the display panel (DP). The PPF can comprise flexible plastic materials such as polyethylene terephthalate (PET).

[0066] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 can be disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be bonded to each other through the second adhesive layer AL2.

[0067] Figure 3 It is shown Figure 2 The view shown is a cross-sectional view of the display panel.

[0068] According to an embodiment, Figure 3 An example of a cross-section of the display panel DP as viewed in the second direction DR2 is shown.

[0069] Reference Figure 3 The display panel DP may include a substrate layer SUB, a circuit element layer DP-CL disposed on the substrate layer SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0070] The substrate layer SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate layer SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed in the display area DA.

[0071] Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light-emitting element disposed in the display element layer DP-OLED and connected to the transistor.

[0072] A thin-film encapsulation layer (TFE) can be applied to the DP-CL circuit element layer to cover both the DP-OLED display element layer and the DP-CL circuit element layer. The TFE can protect the pixels from moisture, oxygen, and external foreign matter.

[0073] Figure 4 This is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0074] Reference Figure 4 The electronic device ED may include a display panel DP, a first gate driver circuit GDC1, a second gate driver circuit GDC2, a data driver circuit DDC, and a control circuit TC.

[0075] The control circuit TC controls the operation of the first gate driver circuit GDC1, the second gate driver circuit GDC2, and the data driver circuit DDC. The control circuit TC generates image data RGB by converting the data format of the input image signal according to the interface specification with the data driver circuit DDC. The control circuit TC outputs the image data RGB, as well as various types of control signals DCS, GCS1, and GCS2.

[0076] The first gate driver circuit GDC1 receives a first gate control signal GCS1 from the control circuit TC, and the second gate driver circuit GDC2 receives a second gate control signal GCS2 from the control circuit TC. The first gate control signal GCS1 may include a start signal for initiating the operation of the first gate driver circuit GDC1 and a clock signal for determining the output timing of the signals, and the second gate control signal GCS2 may include a start signal for initiating the operation of the second gate driver circuit GDC2 and a clock signal for determining the output timing of the signals. The first gate driver circuit GDC1 and the second gate driver circuit GDC2 output multiple scan signals to multiple scan lines GWL1, GWL2, GWL3, ... and GWLn, GRL1, GRL2, GRL3, ... and GRLn, and GIL1, GIL2, GIL3, ... and GILn, examples of which are described below. Among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the first group of scan lines GWL1 to GWLn may be referred to as write scan lines. Among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the second set of scan lines GRL1 to GRLn can be referred to as the reference scan lines. Among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the third set of scan lines GIL1 to GILn can be referred to as the initialization scan lines. In this paper, n is a positive integer greater than 1.

[0077] Furthermore, at least one of the first gate driver circuit GDC1 and the second gate driver circuit GDC2 generates a plurality of transmit control signals and outputs the plurality of transmit control signals to a plurality of first transmit signal lines EL1, EL2, EL3, ... and ELn and a plurality of second transmit signal lines ELB (see [link to relevant documentation]). Figure 7 ).

[0078] In the embodiment, multiple second transmit signal lines ELB (see...) Figure 7 Each line in ) can be set to be related to Figure 4 The multiple first transmit signal lines EL1 to ELn shown are substantially parallel, and for the sake of simplicity, in Figure 4 The second transmit signal line ELB is omitted.

[0079] The data driver circuit DDC receives the data control signal DCS and the image data RGB from the control circuit TC. The data driver circuit DDC converts the image data RGB into a data signal and outputs the data signal to multiple data lines DL1, DL2, ..., DLm, examples of which are described below. The data signal is an analog voltage corresponding to the grayscale value of the image data RGB. In this document, m is a positive integer greater than 1.

[0080] The display panel DP includes: multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn; multiple first transmit signal lines EL1 to ELn; multiple data lines DL1 to DLm; and multiple pixels PX. The multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn extend along a first direction DR1 and are arranged along a second direction DR2 perpendicular to the first direction DR1. Each of the multiple first transmit signal lines EL1 to ELn can be arranged parallel to a corresponding scan line among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn. To insulate themselves from the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn, the multiple data lines DL1 to DLm intersect the multiple scan lines GWL1 to GWLn, GRL1 to GRLn, and GIL1 to GILn.

[0081] Each of the multiple pixels PX is connected to the corresponding scan line among the multiple scan lines GWL1 to GWLn, GRL1 to GRLn and GIL1 to GILn, the corresponding transmission signal line among the multiple transmission signal lines EL1 to ELn, and the corresponding data line among the multiple data lines DL1 to DLm.

[0082] The display panel DP receives a first power supply voltage ELVDD and a second power supply voltage ELVSS. The first power supply voltage ELVDD can be supplied to multiple pixels PX via a first power line PL1. The second power supply voltage ELVSS can be supplied via a second power line PL2 formed in the display panel DP (e.g., as shown in the image). Figure 5 (As shown in the image) is provided to multiple pixels PX.

[0083] The display panel (DP) additionally receives an initialization voltage Vint and a reference voltage Vref. The initialization voltage Vint and the reference voltage Vref can be supplied to multiple pixels (PX) via voltage lines VL.

[0084] Figure 5 This is a circuit diagram of a pixel according to an embodiment of the present disclosure. According to the embodiment, Figure 5 yes Figure 4 An example of a circuit diagram for pixel PXij among pixels PX shown.

[0085] exist Figure 5 In the example, multiple write scan lines GWL1 to GWLn are connected (e.g., as shown in the image). Figure 4 The i-th write scan line GWLi (as shown) is used to receive the i-th write scan signal GWi and is connected to multiple data lines DL1 to DLm (e.g., as shown). Figure 4In the diagram, pixel PXij is connected to the j-th data line DLj to receive the j-th data signal Dj. Pixel PXij is connected to reference scan lines GRL1 to GRLn (e.g., as shown in the diagram). Figure 4 The i-th reference scan line GRLi (as shown in the diagram) is used to receive the i-th reference scan signal GRi, and is connected to the initialization scan lines GIL1 to GILn (e.g., as shown in the diagram). Figure 4 The i-th initial scan line GILi (shown in the diagram) is used to receive the i-th initial scan signal GIi. In this text, i is a positive integer greater than or equal to 1 and less than or equal to n, and j is a positive integer greater than or equal to 1 and less than or equal to m.

[0086] Pixel PXij may include pixel circuitry (e.g., pixel driving circuitry) PXC and a light-emitting element (OLED) electrically connected to pixel circuitry PXC. In an embodiment, pixel circuitry PXC may include six transistors (e.g., first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6) and two capacitors (e.g., first capacitor C1 and second capacitor C2). In an embodiment, first transistors T1 to fourth transistors T4 may have a first transistor type (e.g., they may be N-type transistors). Fifth transistor T5 and sixth transistor T6 may have a second transistor type (e.g., they may be P-type transistors). In embodiments of this disclosure, at least one of first transistors T1 to fourth transistors T4 may be omitted from pixel PXij, or at least one additional transistor may be included in pixel PXij.

[0087] According to an embodiment, each of the first transistor T1 and the second transistor T2 may include two gates (e.g., an upper gate and a lower gate). In some embodiments, at least one of the first transistor T1 and the second transistor T2 may include only one gate.

[0088] In this embodiment, the first transistor T1 can be referred to as the driving transistor, and the second transistor T2 can be referred to as the switching transistor. The node to which the first transistor T1 and the light-emitting element OLED are connected can be referred to as the first node ND1, and the node to which the first transistor T1 and the second transistor T2 are connected can be referred to as the second node ND2.

[0089] An OLED light-emitting element includes a first electrode electrically connected to a first node ND1, a second electrode connected to a second power line PL2 receiving a second power supply voltage ELVSS, and an emitting layer disposed between the first and second electrodes. An example of an OLED light-emitting element is described in more detail below.

[0090] A first transistor T1 is electrically connected between a first power line PL1 receiving a first power supply voltage ELVDD and a first node ND1. The first transistor T1 may include a source S1 (which may be referred to as the first source S1), a drain D1 (which may be referred to as the first drain D1), a semiconductor region, and a gate G1 (which may be referred to as the first gate G1) electrically connected to a second node ND2. According to an embodiment, the first transistor T1 may further include a lower gate connected to the gate G1. In this disclosure, phrases such as "source, drain, and semiconductor region" included in a transistor can be obtained by dividing "a semiconductor pattern" based on the region.

[0091] The second transistor T2 is electrically connected between the j-th data line DLj and the second node ND2. The second transistor T2 may include a source S2 (which may be referred to as the second source S2) connected to the second node ND2, a drain D2 (which may be referred to as the second drain D2) connected to the j-th data line DLj, a semiconductor region, and a gate G2 (which may be referred to as the second gate G2) connected to the i-th write scan line GWLi. According to an embodiment, the second transistor T2 may further include a lower gate electrically connected to the gate G2.

[0092] The third transistor T3 is electrically connected between the second node ND2 and the first voltage line VL1 that receives the reference voltage Vref. The third transistor T3 may include a drain D3 (which may be referred to as the third drain D3) connected to the second node ND2, a source S3 (which may be referred to as the third source S3) connected to the first voltage line VL1, a semiconductor region, and a gate G3 (which may be referred to as the third gate G3) connected to the i-th reference scan line GRLi. According to an embodiment, the third transistor T3 may further include a lower gate electrically connected to the gate G3.

[0093] The fourth transistor T4 is electrically connected between the second voltage line VL2, which receives the initialization voltage Vint, and the light-emitting element OLED. The fourth transistor T4 may include a drain D4 (which may be referred to as the fourth drain D4) connected to the first node ND1, a source S4 (which may be referred to as the fourth source S4) connected to the second voltage line VL2, a semiconductor region, and a gate G4 (which may be referred to as the fourth gate G4) connected to the i-th initialization scan line GILi. According to an embodiment, the fourth transistor T4 may further include a lower gate electrically connected to the gate G4.

[0094] The fifth transistor T5 is electrically connected between the first power line PL1 and the drain D1 of the first transistor T1. In an embodiment, the fifth transistor T5 may include a drain D5 connected to the first power line PL1 (which may be referred to as the fifth drain D5), a source S5 connected to the drain D1 of the first transistor T1 (which may be referred to as the fifth source S5), a semiconductor region, and a gate G5 (which may be referred to as the fifth gate G5) connected to the i-th first transmit signal line ELi and receiving the i-th first transmit signal EMi. The fifth transistor T5 may also include a lower gate electrically connected to the gate G5.

[0095] The sixth transistor T6 is electrically connected between the first node ND1 and the light-emitting element OLED. In an embodiment, the sixth transistor T6 may include a drain D6 (which may be referred to as the sixth drain D6) connected to the first node ND1, a source S6 (which may be referred to as the sixth source S6) connected to the first electrode of the light-emitting element OLED, a semiconductor region, and a gate G6 (which may be referred to as the sixth gate G6) connected to the i-th second emission signal line ELBi and receiving the i-th second emission signal EMBi. The sixth transistor T6 may also include a lower gate electrically connected to the gate G6.

[0096] The first capacitor C1 is electrically connected between the first node ND1 and the second node ND2. The first capacitor C1 includes a first-first capacitor pattern E1-1 connected to the first node ND1 and a first-second capacitor pattern E1-2 connected to the second node ND2.

[0097] The second capacitor C2 is electrically connected between the first power line PL1 and the first node ND1. The second capacitor C2 may include a second-first capacitor pattern E2-1 connected to the first node ND1 and a second-second capacitor pattern E2-2 connected to the first power line PL1.

[0098] The third capacitor C3 is electrically connected between the first electrode and the second electrode of the OLED. The third capacitor C3 includes a third-first capacitor pattern E3-1 connected to the first electrode of the OLED and a third-second capacitor pattern E3-2 connected to the second electrode of the OLED.

[0099] According to the embodiment, one of the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be omitted.

[0100] Figure 6 This is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0101] Reference Figure 6The display panel DP may include a substrate layer SUB and a circuit element layer DP-CL, a display element layer DP-OLED, and a thin-film encapsulation layer TFE disposed on the substrate layer SUB. According to an embodiment, the display panel DP may further include functional layers such as an anti-reflective layer or a refractive index control layer disposed on the thin-film encapsulation layer TFE.

[0102] The substrate layer SUB may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. For example, the synthetic resin layer may be a polyimide resin layer or may include a polyimide resin, but the embodiments are not limited thereto. For example, the synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. Furthermore, the substrate layer may be a glass substrate layer, a metal substrate layer, or an organic / inorganic composite substrate layer, or may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate. The substrate layer may include a first polyimide layer, a second polyimide layer, and an inorganic layer disposed between the first polyimide layer and the second polyimide layer.

[0103] A buffer layer BFL, comprising at least one inorganic layer, is disposed on the upper surface of the substrate layer SUB. The buffer layer BFL may comprise at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The buffer layer BFL prevents foreign matter from flowing in from the outside. The buffer layer BFL improves the coupling between the substrate layer SUB and the semiconductor pattern and / or conductive pattern disposed on the buffer layer BFL.

[0104] A silicon semiconductor layer is disposed on the buffer layer BFL. The silicon semiconductor layer may include multiple semiconductor patterns. In an embodiment, the semiconductor pattern may be a silicon semiconductor pattern SP5. The silicon semiconductor pattern SP5 (which may be referred to as the fifth semiconductor pattern SP5 or the fifth semiconductor pattern A5) may be a semiconductor pattern corresponding to the fifth transistor T5.

[0105] The silicon semiconductor pattern SP5 may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the silicon semiconductor pattern SP5 may include polycrystalline silicon that crystallizes at low temperatures (which may be referred to as crystalline polycrystalline silicon / crystalline polycrystalline silicon).

[0106] Silicon semiconductor pattern SP5 can have different electrical properties depending on whether it is doped. (See reference...) Figure 5 The fifth source S5, the fifth drain D5, and the channel region (semiconductor region) described can be formed by a silicon semiconductor pattern SP5. Figure 5The fifth source S5, the fifth drain D5, and the channel region can correspond to the fifth source S5, the fifth drain D5, and the fifth channel region. The fifth source S5 and the fifth drain D5 can extend from the fifth channel region in opposite directions.

[0107] In this embodiment, the fifth source S5 may be referred to as the fifth input region, and the fifth drain D5 may be referred to as the fifth output region. Although an example of a P-type transistor T5 has been described, the embodiments are not limited thereto. For example, in some embodiments, the fifth transistor T5 may be an N-type transistor, and the fifth source S5 and the fifth drain D5 may be referred to in reverse order. For example, when the fifth transistor T5 is an N-type transistor, the fifth drain D5 may be referred to as the fifth input region, and the fifth source S5 may be referred to as the fifth output region.

[0108] With reference Figure 5 The semiconductor pattern corresponding to the sixth transistor T6 described herein can also be disposed on the same layer as the silicon semiconductor pattern SP5. The semiconductor pattern corresponding to the sixth transistor T6 can be formed using the same process as the silicon semiconductor pattern SP5 and can include the same semiconductor. The silicon semiconductor pattern SP5 is disposed on different insulating layers than the first semiconductor pattern SP1 and the second semiconductor pattern SP2, examples of which are described below. The expression "disposed on different insulating layers" as used herein means that they are in contact with the upper surface of different insulating layers disposed on the substrate layer SUB.

[0109] exist Figure 5 and Figure 6 In this design, the fifth transistor T5 and the sixth transistor T6 can include crystalline polycrystalline silicon semiconductor patterns, which improves the response speed of the fifth transistor T5 and the sixth transistor T6. This is because crystalline polycrystalline silicon semiconductor patterns have a faster mobility than other semiconductors.

[0110] A first insulating layer 10 is disposed on the buffer layer BFL to cover the fifth semiconductor pattern SP5. In an embodiment, the first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. In an embodiment, the first insulating layer 10 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0111] A conductive layer (which may be referred to as a first conductive layer) is disposed on the first insulating layer 10. The first conductive layer may include multiple conductive patterns (which may be referred to as first conductive patterns). Figure 6 In the diagram, the fifth gate G5 and the second voltage line VL2 are shown as an example of the first conductive pattern. The fifth gate G5 can be connected with... Figure 5 It corresponds to the fifth gate G5 and can have essentially the same area as the fifth channel region.

[0112] Figure 6 An example is shown where the second voltage line VL2 is divided into two parts. However, the embodiments are not limited to this, and in some embodiments, the second voltage line VL2 may have a single shape (e.g., it may not be divided into two parts). Furthermore, the conductive pattern receiving the first power supply voltage ELVDD may be disposed on the first insulating layer 10, and the second voltage line VL2 may not necessarily be disposed on the first insulating layer 10.

[0113] A second insulating layer 20 is disposed on the first insulating layer 10 to cover the first conductive layer. In embodiments, the second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In embodiments, the second insulating layer 20 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0114] A conductive layer (which may be referred to as a second conductive layer) is disposed on the second insulating layer 20. The second conductive layer may include multiple conductive patterns (which may be referred to as second conductive patterns). Figure 6 In the illustration, a conductive pattern CP is shown as an example of a second conductive pattern, but the embodiment is not limited thereto. The conductive pattern CP can be related to a reference... Figure 5 The second capacitor C2 described corresponds to the second capacitor pattern E2-2. The conductive pattern CP, together with the second voltage line VL2 disposed below the conductive pattern CP, can be included in the reference... Figure 5 The second capacitor C2 is described.

[0115] A third insulating layer 30 is disposed on the second insulating layer 20 to cover the second conductive layer. In embodiments, the third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In embodiments, the third insulating layer 30 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0116] A metal oxide semiconductor layer is disposed on the third insulating layer 30. The metal oxide semiconductor layer may include multiple semiconductor patterns. In an embodiment, a first semiconductor pattern SP1 and a second semiconductor pattern SP2, comprising different metal oxide semiconductors, may be disposed on the third insulating layer 30. The first semiconductor pattern SP1 may be... Figure 5 The semiconductor pattern corresponding to the first transistor T1, and the second semiconductor pattern SP2 can be the same as... Figure 5 The semiconductor pattern corresponding to the second transistor T2.

[0117] In some embodiments, with reference Figure 5 The semiconductor patterns corresponding to the third transistor T3 and the fourth transistor T4 described can also be formed using the same process as the second semiconductor pattern SP2, and can include the same semiconductor.

[0118] In the embodiment, the first semiconductor pattern SP1 (also referred to herein as the first semiconductor pattern A1), the second semiconductor pattern SP2 (also referred to herein as the second semiconductor pattern A2), and the third semiconductor pattern (also referred to herein as the third semiconductor pattern A3 (see reference)) are... Figure 8B The transistor may include oxide semiconductors. For example, the first semiconductor pattern SP1 may include a crystalline oxide semiconductor, and the second semiconductor pattern SP2 may include an amorphous oxide semiconductor. The first semiconductor pattern SP1 may include a crystalline indium gallium oxide (IGO) semiconductor, and the second semiconductor pattern SP2 may include one of an amorphous indium gallium zinc oxide (IGZO) semiconductor and an amorphous indium tin gallium zinc oxide (ITGZO) semiconductor. Transistors including oxide semiconductors have lower leakage current than transistors including silicon semiconductors.

[0119] Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include multiple regions distinguished from each other based on whether the metal oxide is reduced. Regions where the metal oxide is reduced (which may be referred to as reduced regions) have higher conductivity than regions where the metal oxide is not reduced (which may be referred to as non-reduced regions). Reduced regions essentially serve as the source or drain of a transistor, or a signal transmission region. Non-reduced regions essentially correspond to the channel region of a transistor (e.g., a semiconductor region or a non-reduced region). For example, a portion of the semiconductor pattern may be the channel region of a transistor, another portion may be the source or drain of a transistor, and the remainder may be a signal transmission region.

[0120] Reference Figure 5 The first source S1, the first drain D1, and the channel region described can be formed by the first semiconductor pattern SP1. Figure 5 The first source S1, the first drain D1, and the channel region can correspond to the first source S1, the first drain D1, and the first channel region. The first source S1 and the first drain D1 can extend from the first channel region in opposite directions. In embodiments, the first drain D1 can be referred to as the first input region, and the first source S1 can be referred to as the first output region. Although an example of the first transistor T1 being an N-type transistor has been described, the embodiments are not limited thereto. For example, in some embodiments, the first transistor T1 can be a P-type transistor, and the first source S1 and the first drain D1 can be referred to in opposite ways. For example, when the first transistor T1 is a P-type transistor, the first drain D1 can be referred to as the first output region, and the first source S1 can be referred to as the first input region.

[0121] Reference Figure 5 The second source S2, the second drain D2, and the channel region described can be formed by the second semiconductor pattern SP2. Figure 5The second source S2, the second drain D2, and the channel region can correspond to the second source S2, the second drain D2, and the second channel region. The second source S2 and the second drain D2 can extend from the second channel region in opposite directions. In embodiments, the second drain D2 can be referred to as the second input region, and the second source S2 can be referred to as the second output region. Although an example of the second transistor T2 being an N-type transistor has been described, the embodiments are not limited thereto. For example, in some embodiments, the second transistor T2 can be a P-type transistor, and the second source S2 and the second drain D2 can be referred to in opposite ways. For example, when the second transistor T2 is a P-type transistor, the second drain D2 can be referred to as the second output region, and the second source S2 can be referred to as the second input region.

[0122] A fourth insulating layer 40 is disposed on the first semiconductor pattern SP1 and the second semiconductor pattern SP2. In an embodiment, the fourth insulating layer 40 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0123] In this embodiment, the fourth insulating layer 40 is not formed on the entire surface of the third insulating layer 30, but rather overlaps only with the channel region of the transistor. The fourth insulating layer 40 may include multiple insulating patterns. Figure 6 In the illustration, the first insulating pattern 40-1 and the second insulating pattern 40-2 are shown as examples, but the embodiments are not limited thereto. In embodiments of this disclosure, the fourth insulating layer 40 may overlap the entire surface of the third insulating layer 30 without being patterned.

[0124] A conductive layer (which may be referred to as the third conductive layer) is disposed on the fourth insulating layer 40. A first gate G1 is disposed on the first insulating pattern 40-1, and a second gate G2 is disposed on the second insulating pattern 40-2. Figure 6 The first gate G1 and Figure 5 The first gate G1 corresponds to, and Figure 6 The second gate G2 and Figure 5 The second gate G2 corresponds to.

[0125] Because the insulating layer is etched using the first gate G1 and the second gate G2 as masks after the first gate G1 and the second gate G2 are formed, the shape of the first insulating pattern 40-1 can be substantially the same as or similar to the shape of the first gate G1. Similarly, the shape of the second insulating pattern 40-2 can be substantially the same as or similar to the shape of the second gate G2. The edges of the overlapping gates and the edges of the insulating patterns can be aligned with each other.

[0126] A fifth insulating layer 50 is disposed on the third insulating layer 30. The fifth insulating layer 50 may cover the first gate G1 and the second gate G2. In embodiments, the fifth insulating layer 50 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. In embodiments, the fifth insulating layer 50 may include silicon oxide, silicon nitride, or silicon oxynitride.

[0127] A conductive layer (which may be referred to as the fourth conductive layer) is disposed on the fifth insulating layer 50. The fourth conductive layer may include multiple conductive patterns (which may be referred to as the fourth conductive pattern). Figure 6 In the example, three types of connecting electrodes CNE1, CNE2 and CNE3 are shown as examples of the fourth conductive pattern, but the embodiments are not limited thereto.

[0128] A first connection electrode CNE1, connected to at least one of the first source electrode S1 and the first drain electrode D1, may be disposed on the fifth insulating layer 50. Figure 6 In the example shown, the two first connection electrodes CNE1 are connected to the first source S1 and the first drain D1, respectively, but the embodiment is not limited to this. The first connection electrodes CNE1 are connected to the corresponding regions of the first source S1 and the first drain D1 through contact holes CH1 penetrating the fifth insulating layer 50.

[0129] A first connection electrode CNE1 can electrically connect the first source S1 and the conductive pattern CP. This first connection electrode CNE1 can be connected to the conductive pattern CP through a contact hole CH2 that penetrates the third insulating layer 30 and the fifth insulating layer 50.

[0130] A second connection electrode CNE2, connected to at least one of the second source electrode S2 and the second drain electrode D2, may be disposed on the fifth insulating layer 50. Figure 6 In the example shown, the two second connection electrodes CNE2 are connected to the second source S2 and the second drain D2, respectively, but the embodiment is not limited to this. The second connection electrodes CNE2 are connected to the corresponding regions of the second source S2 and the second drain D2 through the contact hole CH1 penetrating the fifth insulating layer 50.

[0131] A third connection electrode CNE3, connected to at least one of the fifth source electrode S5 and the fifth drain electrode D5, may be disposed on the fifth insulating layer 50. Figure 6 In the example shown, the two third connection electrodes CNE3 are connected to the fifth source S5 and the fifth drain D5, respectively, but the embodiment is not limited to this. The third connection electrodes CNE3 are connected to the corresponding regions of the fifth source S5 and the fifth drain D5 through contact holes CH3 that penetrate the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, and the fifth insulating layer 50. Figure 6 The example shown is different; a connection electrode can connect the first drain D1 and the fifth drain D5.

[0132] A sixth insulating layer 60 is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may cover the connecting electrodes CNE1, CNE2, and CNE3. In an embodiment, the sixth insulating layer 60 may be an organic layer and may have a monolayer structure. However, the embodiment is not limited thereto.

[0133] A conductive layer (which may be referred to as the fifth conductive layer) is disposed on the sixth insulating layer 60. The fifth conductive layer may include multiple conductive patterns. The fifth conductive layer includes a fourth connection electrode CNE4. The fourth connection electrode CNE4 is connected to the first connection electrode CNE1 through a contact hole CH4 penetrating the sixth insulating layer 60.

[0134] The fifth conductive layer may further include a data line DLj and a first voltage line VL1. The data line DLj can be connected to the second connection electrode CNE2 through a contact hole CH4 penetrating the sixth insulating layer 60. The portion of the first voltage line VL1 overlapping with the first electrode AE ​​of the light-emitting element OLED described below defines the... Figure 6 The third capacitor C3 shown is a third-second capacitor pattern E3-2. A portion of the first electrode AE ​​of the light-emitting element OLED defines the... Figure 5 The third capacitor C3 shown is the third-first capacitor pattern E3-1.

[0135] A seventh insulating layer 70 is disposed on the sixth insulating layer 60 to cover the fifth conductive layer. In an embodiment, the seventh insulating layer 70 may be an organic layer and may have a single-layer structure. However, the embodiments are not limited thereto.

[0136] The first electrode AE ​​of the OLED light-emitting element is disposed on the seventh insulating layer 70. The first electrode AE ​​can be an anode. The first electrode AE ​​is connected to the fourth connecting electrode CNE4 through a contact hole CH5 penetrating the seventh insulating layer 70. The pixel defining layer PDL is disposed on the seventh insulating layer 70.

[0137] An opening OP in the pixel-defining layer PDL exposes at least a portion of the first electrode AE. The opening OP in the pixel-defining layer PDL can define an emission region LA. For example, in a plane, multiple pixels PX (e.g., as...) Figure 4 As shown in the diagram, the pixels (PX) can be arranged in the display panel (DP) according to predetermined rules or patterns. The area containing multiple pixels (PX) can be referred to as the display area, and the display area can include multiple emitting areas (LA) and non-emitting areas (NLA) adjacent to the emitting areas (LA). The non-emitting areas (NLA) can be around or surrounding the emitting areas (LA).

[0138] A hole control layer (HCL) can be commonly disposed in the emission region (LA) and the non-emission region (NLA). Common layers such as the hole control layer (HCL) can be commonly formed in multiple pixels (PX). The hole control layer (HCL) may include a hole transport layer and a hole injection layer.

[0139] The emitter layer EML is set on the hole control layer HCL. The emitter layer EML can be set only in the region corresponding to the aperture OP. The emitter layer EML can be formed individually in each of multiple pixels PX.

[0140] Although the patterned emission layer EML is shown as an example in the embodiments, the emission layer EML can be commonly disposed in multiple pixels PX. The commonly disposed emission layer EML can generate white light or blue light. Furthermore, the emission layer EML can have a multi-layer structure.

[0141] An electronic control layer (ECL) is disposed on the emitter layer (EML). The ECL may include an electron transport layer and an electron injection layer. A second electrode (CE) is disposed on the ECL. The ECL and the second electrode (CE) are commonly disposed in multiple pixels (PX).

[0142] A thin-film encapsulation layer (TFE) is disposed on the second electrode (CE). The TFE is commonly disposed in multiple pixels (PX). In one embodiment, the TFE directly covers the second electrode (CE). In embodiments of this disclosure, a capping layer may also be disposed directly covering the second electrode (CE). In embodiments of this disclosure, the stacked structure of the OLED light-emitting element can have a structure that can be inverted... Figure 6 The structure is obtained by the structure shown in the figure.

[0143] The thin-film encapsulation layer (TFE) comprises at least an inorganic layer or an organic layer. In embodiments of this disclosure, the TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. In embodiments of this disclosure, the TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked on top of each other.

[0144] Figure 7 This is a schematic plan view illustrating a pixel circuit according to an embodiment of the present disclosure. Figure 8A and Figure 8B It is shown Figure 7 A schematic plan view of the pixel circuit shown. Figure 7 , Figure 8A and Figure 8B It shows Figure 5 An example of the arrangement of transistors and signal lines shown in a circuit diagram. (Refer to...) Figure 7 , Figure 8A and Figure 8B The described signal lines can be compared with the reference. Figure 5The described signal lines correspond, and some components have been omitted.

[0145] Reference Figure 7 According to the embodiment, the pixel circuit PXC1 may include, on a plane, a first voltage line VL1, a reference scan line GRL disposed below the first voltage line VL1, a first transmit signal line EL disposed below the reference scan line GRL, a first power line PL1 disposed below the first transmit signal line EL, a write scan line GWL disposed below the first power line PL1, a second transmit signal line ELB disposed below the write scan line GWL, an initialization scan line GIL disposed below the second transmit signal line ELB, and a second voltage line VL2 disposed below the initialization scan line GIL.

[0146] For example, the pixel circuit PXC1 may include a first voltage line VL1, a reference scan line GRL, a first transmit signal line EL, a first power line PL1, a write scan line GWL, a second transmit signal line ELB, an initialization scan line GIL, and a second voltage line VL2, arranged sequentially from the top of the pixel circuit PXC1 in the second direction DR2.

[0147] The third transistor T3 can overlap with and be connected to the reference scan line GRL. The first transistor T1 can be disposed between the reference scan line GRL and the first transmit signal line EL. The fifth transistor T5 can overlap with and be connected to the first transmit signal line EL. The second transistor T2 can overlap with and be connected to the write scan line GWL. The sixth transistor T6 can overlap with and be connected to the second transmit signal line ELB. The fourth transistor T4 can overlap with and be connected to the initialization scan line GIL.

[0148] exist Figure 8A The image shows a first semiconductor pattern A1 included in a first transistor T1, a fifth semiconductor pattern A5 included in a fifth transistor T5, and a sixth semiconductor pattern A6 included in a sixth transistor T6.

[0149] exist Figure 8B The image shows a first semiconductor pattern A1 included in a first transistor T1, a second semiconductor pattern A2 included in a second transistor T2, and a third semiconductor pattern A3 included in a third transistor T3.

[0150] According to an embodiment, on the plane of the pixel circuit PXC1, a first semiconductor pattern A1 may be disposed above a fifth semiconductor pattern A5 and a sixth semiconductor pattern A6. The fifth semiconductor pattern A5 may be disposed between the first semiconductor pattern A1 and the sixth semiconductor pattern A6. The fifth semiconductor pattern A5 and the sixth semiconductor pattern A6 may comprise polysilicon.

[0151] The second semiconductor pattern A2 can be disposed below the first semiconductor pattern A1. The third semiconductor pattern A3 can be disposed above the first semiconductor pattern A1.

[0152] According to an embodiment, through optimized design of the pixel circuit PXC1, compared with the reference... Figure 5 The coupling capacitance between adjacent signal lines described, including those in the second node ND2 (e.g., the line connecting the gate G1 of the first transistor T1, the source S2 of the second transistor T2, the drain D3 of the third transistor T3, and the first capacitor C1 in the first-second capacitor pattern E1-2), can be minimized.

[0153] Furthermore, according to an embodiment, by placing the first power line PL1, to which a constant voltage is applied, below the line included in the second node ND2, the coupling capacitance between the signal lines adjacent to the line included in the second node ND2 can be minimized.

[0154] Figure 9 This is a schematic plan view illustrating a pixel circuit according to an embodiment of the present disclosure. Figure 10A and Figure 10B It is shown Figure 9 A schematic plan view of the pixel circuit shown. Figure 9 , Figure 10A and Figure 10B It shows Figure 5 An example of the arrangement of transistors and signal lines shown in a circuit diagram. (Refer to...) Figure 9 , Figure 10A and Figure 10B The described signal lines can be compared with the reference. Figure 5 The described signal lines correspond, and some components have been omitted.

[0155] Reference Figure 9According to the embodiment, the pixel circuit PXC2 may include, on a plane, a second voltage line VL2, an initialization scan line GIL disposed below the second voltage line VL2, a second transmit signal line ELB disposed below the initialization scan line GIL, a write scan line GWL disposed below the second transmit signal line ELB, a reference scan line GRL disposed below the write scan line GWL, a first transmit signal line EL disposed below the reference scan line GRL, a first voltage line VL1 disposed below the first transmit signal line EL, and a first power line PL1 disposed below the first voltage line VL1.

[0156] In other words, the pixel circuit PXC2 may include a second voltage line VL2, an initialization scan line GIL, a second transmit signal line ELB, a write scan line GWL, a reference scan line GRL, a first transmit signal line EL, a first voltage line VL1, and a first power line PL1, arranged sequentially from the top of the pixel circuit PXC2 on the second direction DR2.

[0157] The fourth transistor T4 can overlap with and be connected to the initialization scan line GIL. The sixth transistor T6 can overlap with and be connected to the second transmit signal line ELB. The second transistor T2 can overlap with and be connected to the write scan line GWL. The first transistor T1 can be positioned between the write scan line GWL and the reference scan line GRL. The third transistor T3 can overlap with and be connected to the reference scan line GRL. The fifth transistor T5 can overlap with and be connected to the first transmit signal line EL.

[0158] exist Figure 10A The example shown includes a first semiconductor pattern A1 contained in a first transistor T1, a fifth semiconductor pattern A5 contained in a fifth transistor T5, and a sixth semiconductor pattern A6 contained in a sixth transistor T6.

[0159] exist Figure 10B The example shown includes a first semiconductor pattern A1 contained in a first transistor T1, a second semiconductor pattern A2 contained in a second transistor T2, and a third semiconductor pattern A3 contained in a third transistor T3.

[0160] According to an embodiment, on the plane of the pixel circuit PXC2, a fifth semiconductor pattern A5 may be disposed below a first semiconductor pattern A1. A sixth semiconductor pattern A6 may be disposed above a first semiconductor pattern A1. The first semiconductor pattern A1 may be disposed between the fifth semiconductor pattern A5 and the sixth semiconductor pattern A6. The fifth semiconductor pattern A5 and the sixth semiconductor pattern A6 may comprise polysilicon.

[0161] The third semiconductor pattern A3 can be disposed below the first semiconductor pattern A1. The second semiconductor pattern A2 can be disposed above the first semiconductor pattern A1.

[0162] According to an embodiment, through optimized design of the pixel circuit PXC2, compared with the reference... Figure 5 The coupling capacitance between adjacent signal lines described, including those in the second node ND2 (e.g., the line connecting the gate G1 of the first transistor T1, the source S2 of the second transistor T2, the drain D3 of the third transistor T3, and the first capacitor C1 in the first-second capacitor pattern E1-2), can be minimized.

[0163] According to embodiments of this disclosure, through optimized design of the pixel circuitry, coupling capacitance occurring between signal lines adjacent to lines included in the nodes of connecting transistors can be minimized. Therefore, electronic devices with improved reliability can be provided.

[0164] Although some specific embodiments of the present disclosure have been described above, it will be apparent to those skilled in the art that various changes and modifications may be made to the present disclosure without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. An electronic device, wherein, The electronic device includes: The processor is configured to provide image data and display brightness values; A display panel includes a pixel circuit comprising multiple transistors and multiple capacitors, light-emitting elements connected to the pixel circuit, and signal lines connected to the multiple transistors; and A panel driver is configured to receive the image data and the display brightness value, and to drive the display panel based on the image data and the display brightness value. Wherein, on the plane, the signal line includes: First voltage line; Reference scan line, below the first voltage line; The first transmit signal line is located below the reference scan line; The first power line is located below the first transmitted signal line; Write the scan line below the first power line; The second transmit signal line is located below the write scan line; Initialize the scan line below the second transmit signal line; and The second voltage line is located below the initialization scan line.

2. The electronic device according to claim 1, wherein, The plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and Wherein, the first transistor, the second transistor, the third transistor, and the fourth transistor correspond to the first transistor type, and The fifth transistor and the sixth transistor correspond to a second transistor type that is different from the first transistor type.

3. The electronic device according to claim 2, wherein, The electronic device also includes: The first node is connected to the first transistor and the light-emitting element. The first transistor is connected between the first node and the first power line. The fifth transistor is connected between the first power line and the drain of the first transistor, and the fifth transistor is also connected to the first transmit signal line. The sixth transistor is connected between the first node and the light-emitting element, and the sixth transistor is also connected to the second transmission signal line. The fifth transistor is configured to receive the first transmitted signal using the first transmitted signal line, and The sixth transistor is configured to receive the second transmitted signal using the second transmitted signal line.

4. The electronic device according to claim 3, wherein, On the plane, the first semiconductor pattern corresponding to the first transistor is above the fifth semiconductor pattern corresponding to the fifth transistor and the sixth semiconductor pattern corresponding to the sixth transistor.

5. The electronic device according to claim 4, wherein, On the plane, the fifth semiconductor pattern lies between the first semiconductor pattern and the sixth semiconductor pattern.

6. The electronic device according to claim 4, wherein, The fifth semiconductor pattern and the sixth semiconductor pattern comprise polycrystalline silicon.

7. The electronic device according to claim 2, wherein, The electronic device also includes: The second node is connected to both the first transistor and the second transistor. The second transistor is connected between the second node and the data line, and the second transistor is also connected to the write scan line. The third transistor is connected between the second node and the first voltage line, and the third transistor is also connected to the reference scan line. The first voltage line is configured to receive a reference voltage. The second transistor is configured to receive a data signal using the data line, and The third transistor is configured to receive a reference scan signal using the reference scan line.

8. The electronic device according to claim 7, wherein, On the plane, the second semiconductor pattern corresponding to the second transistor is below the first semiconductor pattern corresponding to the first transistor, and The third semiconductor pattern corresponding to the third transistor is located above the first semiconductor pattern.

9. The electronic device according to claim 8, wherein, The first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern comprise oxide semiconductors.

10. The electronic device according to claim 2, wherein, On the plane, a first semiconductor pattern corresponding to the first transistor is located between the reference scan line and the first transmit signal line.

11. An electronic device, wherein, The electronic device includes: The processor is configured to provide image data and display brightness values; A display panel includes a pixel circuit, light-emitting elements connected to the pixel circuit, and signal lines connected to a plurality of transistors, wherein the pixel circuit includes the plurality of transistors and a plurality of capacitors; and A panel driver is configured to receive the image data and the display brightness value, and to drive the display panel based on the image data and the display brightness value. Wherein, on the plane, the signal line includes: Second voltage line; Initialize the scan line below the second voltage line; The second transmit signal line is located below the initialization scan line; Write the scan line below the second transmit signal line; Reference scan line, below the write scan line; The first transmit signal line is located below the reference scan line; The first voltage line is located below the first transmitted signal line; and The first electric field line is located below the first voltage line.

12. The electronic device according to claim 11, wherein, The plurality of transistors includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, and Wherein, the first transistor, the second transistor, the third transistor, and the fourth transistor correspond to the first transistor type, and The fifth transistor and the sixth transistor correspond to a second transistor type that is different from the first transistor type.

13. The electronic device according to claim 12, wherein, The electronic device also includes: The first node is connected to the first transistor and the light-emitting element. The first transistor is connected between the first node and the first power line. The fifth transistor is connected between the first power line and the drain of the first transistor, and the fifth transistor is also connected to the first transmit signal line. The sixth transistor is connected between the first node and the light-emitting element, and the sixth transistor is also connected to the second transmission signal line. The fifth transistor is configured to receive the first transmitted signal using the first transmitted signal line, and The sixth transistor is configured to receive the second transmitted signal using the second transmitted signal line.

14. The electronic device according to claim 13, wherein, On the plane, the fifth semiconductor pattern corresponding to the fifth transistor is below the first semiconductor pattern corresponding to the first transistor, and The sixth semiconductor pattern corresponding to the sixth transistor is located above the first semiconductor pattern corresponding to the first transistor.

15. The electronic device according to claim 14, wherein, The fifth semiconductor pattern and the sixth semiconductor pattern comprise polycrystalline silicon.

16. The electronic device according to claim 12, wherein, The electronic device also includes: The second node is connected to both the first transistor and the second transistor. The second transistor is connected to the second node and the data line, and the second transistor is also connected to the write scan line. The third transistor is connected between the second node and the first voltage line, and the third transistor is also connected to the reference scan line. The first voltage line is configured to receive a reference voltage. The second transistor is configured to receive a data signal using the data line, and The third transistor is configured to receive a reference scan signal using the reference scan line.

17. The electronic device according to claim 16, wherein, On the plane, the second semiconductor pattern corresponding to the second transistor is above the first semiconductor pattern corresponding to the first transistor, and The third semiconductor pattern corresponding to the third transistor is located below the first semiconductor pattern corresponding to the first transistor.

18. The electronic device according to claim 17, wherein, The first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern comprise oxide semiconductors.

19. The electronic device according to claim 12, wherein, On the plane, a first semiconductor pattern corresponding to the first transistor is located between the write scan line and the reference scan line.

20. The electronic device according to claim 11, wherein, The light-emitting element includes a first electrode, a second electrode, and an emitting layer between the first electrode and the second electrode.

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