Gate driving circuit, display panel and display device

Abstract

Embodiments of the present application disclose a gate driving circuit, a display panel and a display device, and belong to the technical field of display. The gate driving circuit is applied to the display panel, and comprises at least one shift register. The shift register comprises a plurality of adjustable driving units connected in cascade. Each adjustable driving unit comprises a group of flip-flops and a multiplexer. The data input end of the flip-flop is used as the input end of the adjustable driving unit, and the output end of the multiplexer is used as the output end of the adjustable driving unit. The multiplexer is configured to provide the input signal or the output signal of the flip-flop to the input end of the next adjustable driving unit in response to a control signal, so as to adjust the number of pixel rows scanned in one clock cycle. According to the embodiments of the present application, the multiplexer is additionally arranged in the shift register of the gate driving circuit, so that the number of pixel rows scanned in one clock cycle is flexibly adjustable, and thus the display panel comprising the circuit can support the gaze point rendering function.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to gate driving circuits, display panels, and display devices. Background Technology

[0002] Foveative rendering is a technique based on eye-tracking technology that provides high-resolution rendering in the area the user is looking at, while gradually reducing resolution and rendering accuracy in the peripheral visual areas, thereby significantly reducing computing power and energy consumption. Currently, the gate drive circuit of a display panel consists of multiple shift registers and corresponding combinational logic gates working together to generate timing gate drive signals for the entire panel. Pixels in each row share the same set of gate drive signals. However, to achieve foveative rendering, it is necessary to design corresponding gate drive circuits for different display areas of the display panel. Summary of the Invention

[0003] The main objective of this application is to provide a gate driving circuit, a display panel, and a display device, aiming to solve the technical problem of how to enable the display panel to support foveated rendering function.

[0004] To achieve the above objectives, this application provides a gate driving circuit for use in a display panel. The gate driving circuit includes at least one shift register, which includes multiple cascaded adjustable driving units. Each adjustable driving unit includes a set of flip-flops and multiplexers. The data input terminal of the flip-flops serves as the input terminal of the adjustable driving unit, and the output terminal of the multiplexer serves as the output terminal of the adjustable driving unit. The multiplexer is configured to, in response to a control signal, provide the input or output signal of the trigger to the input of the next-level adjustable drive unit to adjust the number of pixel rows scanned in one clock cycle.

[0005] In one embodiment, the clock input terminal of the trigger is connected to a clock signal, the data input terminal of the trigger is electrically connected to the first input terminal of the multiplexer, the data output terminal of the trigger is electrically connected to the second input terminal of the multiplexer, the output terminal of the multiplexer is electrically connected to the input terminal of the next-stage adjustable drive unit, and the controlled terminal of the multiplexer is connected to the control signal.

[0006] In one embodiment, when the control signal is at a first active level, the first input and output of the multiplexer are connected, and the second input and output of the multiplexer are disconnected. When the control signal is at the second active level, the first input and output of the multiplexer are turned off, and the second input and output of the multiplexer are turned on.

[0007] In one embodiment, when the control signals received by the consecutive nth to n+ith multiplexers are all at the first valid level, the number of pixel rows scanned in one clock cycle is i+2 rows, where n is a positive integer and i is greater than or equal to 0.

[0008] In one embodiment, when the control signals received by two adjacent multiplexers are both at the second active level, the number of pixel rows scanned in one clock cycle is one row.

[0009] In one embodiment, when the pixel row corresponding to the m-th adjustable drive unit belongs to the foveation rendering area of ​​the display panel, the control signals received by the (m-1)-th adjustable drive unit and the multiplexer in the m-th adjustable drive unit are both the second active level.

[0010] In one embodiment, the display panel includes a first type of pixel row, a second type of pixel row, and a third type of pixel row, wherein the first type of pixel row belongs to the foveation point rendering region, the second type of pixel row is located on one side of the foveation point rendering region, and the third type of pixel row is located on the side of the second type of pixel row away from the foveation point rendering region; The plurality of adjustable driving units include: a first adjustable driving unit corresponding to the first type of pixel row, a second adjustable driving unit corresponding to the second type of pixel row, and a third adjustable driving unit corresponding to the third type of pixel row. Within one clock cycle, the number of the third adjustable driving units providing the scan signal is greater than the number of the second adjustable driving units providing the scan signal, and the number of the second adjustable driving units providing the scan signal is greater than the number of the first adjustable driving units providing the scan signal.

[0011] In one embodiment, the shift register further includes a scan order switching switch, the first terminal of which is connected to a start signal, the second terminal of which is electrically connected to the input terminal of the first-stage adjustable drive unit, and the third terminal of which is electrically connected to the input terminal of the last-stage adjustable drive unit. The scan order switching switch is configured to, in response to a switch signal, determine the pixel scan order as either scanning pixels from the first row to the last row, or scanning pixels from the last row to the first row.

[0012] In addition, to achieve the above objectives, embodiments of this application also provide a display panel, which includes a plurality of gate driving circuits as described above.

[0013] In addition, to achieve the above objectives, this application also provides a display device, which includes the display panel described above.

[0014] This application provides a gate driving circuit, a display panel, and a display device. By adding a multiplexer equal to the number of flip-flops to the shift register of the gate driving circuit of the display panel, the connection method between the originally cascaded flip-flops can be changed, thereby making the number of pixel rows scanned in one clock cycle flexibly adjustable. Differentiated rendering can be performed on different display areas with high resolution and low resolution, thereby enabling the display panel to support flexibly adjustable foveated rendering function, which is beneficial to flexibly adjust the resolution between different areas of the display panel according to the position of the foveated area. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This application provides a schematic diagram of the structure of a shift register involved in a gate driving circuit. Figure 2 A schematic diagram of the internal electrical connections of an adjustable drive unit involved in a gate drive circuit provided in an embodiment of this application; Figure 3 A schematic diagram of the pixel row layout of a display panel related to a gate driving circuit provided in an embodiment of this application; Figure 4 This application provides a schematic diagram of the layout of a display panel's gaze point rendering area, which is related to a gate driving circuit in an embodiment of the present application. Figure 5 A schematic diagram of the layout of another display panel gaze point rendering area related to a gate driving circuit provided in an embodiment of this application; Figure 6 A schematic diagram of the layout of another display panel gaze point rendering area related to a gate driving circuit provided in an embodiment of this application; Figure 7 A schematic diagram of an extended structure of a shift register involved in a gate driving circuit provided in an embodiment of this application; Figure 8 A schematic diagram illustrating the connection relationship between adjacent adjustable units in a gate driving circuit provided in an embodiment of this application; Figure 9A schematic diagram illustrating an application scenario where a gate driving circuit, as provided in this application embodiment, involves scanning pixels from the first row to the last row. Figure 10 In order to be in Figure 9 A schematic diagram illustrating an application scenario where four rows of pixels are scanned in one clock cycle; Figure 11 In order to be in Figure 9 A schematic diagram illustrating an application scenario where three rows of pixels are scanned in one clock cycle; Figure 12 In order to be in Figure 9 A schematic diagram illustrating an application scenario where two rows of pixels are scanned in one clock cycle. Figure 13 In order to be in Figure 9 A schematic diagram illustrating an application scenario where one row of pixels is scanned in one clock cycle. Figure 14 This application provides an embodiment of a gate driving circuit that involves a pixel scanning sequence from the last row to the first row, illustrating an application scenario. Figure 15 In order to be in Figure 14 A schematic diagram illustrating an application scenario where four rows of pixels are scanned in one clock cycle. Figure 16 In order to be in Figure 14 A schematic diagram illustrating an application scenario where three rows of pixels are scanned in one clock cycle; Figure 17 In order to be in Figure 14 A schematic diagram illustrating an application scenario where two rows of pixels are scanned in one clock cycle. Figure 18 In order to be in Figure 14 A schematic diagram illustrating an application scenario where one row of pixels is scanned in one clock cycle. Figure 19 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application; Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this application.

[0017] Explanation of icon numbers: 10. Adjustable drive unit; 11. Flip-flop; 12. Multiplexer; D. Data input terminal of the flip-flop; CLK. Clock input terminal of the flip-flop; Q. Data output terminal of the flip-flop; QB. Inverted data output terminal of the flip-flop; 1. First input terminal of the multiplexer; 0. Second input terminal of the multiplexer; CKV. Clock signal; Sel. Control signal; GOA. Gate drive circuit; Panel; 20. Scan sequence switching switch; S1. Forward scan switch; S2. Reverse scan switch; 1000. Display device; 100. Display panel. Detailed Implementation

[0018] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that the embodiments of this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the embodiments of this application with unnecessary detail.

[0019] The gate drive circuit of a display panel typically consists of multiple shift registers and corresponding combinational logic gates working together to generate sequential gate drive signals for the entire panel, with pixels in each row sharing the same set of gate drive signals. The advantage of this method is that the pulse width of each row's gate drive signal is generated by the delay between clock signals (CKV). This avoids large deviations in pulse width. Due to the large panel size, if the pulse width were generated at a single location and then routed to each row, the distortion could be very significant.

[0020] Taking a display panel with 3840 rows of pixels and 6 shift registers as an example, the pixel circuit of each row of pixels is driven and controlled by three driving signals WS / DS / AZ generated by the gate driving circuit. In the 6 shift registers, each shift register includes 3840 flip-flops, and the number of combinational logic gates is also 3840. The output signals Q and QB of the corresponding flip-flops in the 6 shift registers are input to the corresponding combinational logic gates to generate the WS / DS / AZ driving signals for the corresponding row.

[0021] To save bandwidth during video data transmission, the display panel can be divided into multiple display areas with different resolutions, such as the foveation region using 1... 1. High-resolution display, with 2. 1 / 1 2. Low-resolution displays. To achieve foveated rendering, a new type of gate drive circuit is urgently needed to enable dynamically adjustable display resolution.

[0022] Based on this, embodiments of this application provide a gate driving circuit, a display panel, and a display device. By adding a multiplexer equal to the number of flip-flops to the shift register of the gate driving circuit of the display panel, the connection method between the originally cascaded flip-flops can be changed, thereby making the number of pixel rows scanned in one clock cycle flexibly adjustable. Differentiated rendering can be performed on different display areas with high resolution and low resolution, thereby enabling the display panel to support flexibly adjustable foveated rendering function, which is beneficial to realize the flexible adjustment of the resolution between different areas of the display panel according to the position of the foveated area.

[0023] The gate driving circuit, display panel, and display device provided in this application are specifically described through the following embodiments. First, the gate driving circuit in the embodiments of this application is described.

[0024] This application provides a gate driving circuit, referring to... Figure 1 , Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present application. The gate driving circuit is applied to a display panel and includes at least one shift register. The shift register includes a plurality of cascaded adjustable driving units 10. Each adjustable driving unit 10 includes a set of flip-flops 11 and multiplexers 12. The data input terminal of the flip-flops 11 serves as the input terminal of the adjustable driving unit 10, and the output terminal of the multiplexers 12 serves as the output terminal of the adjustable driving unit 10. The multiplexer 12 is configured to, in response to a control signal, provide the input or output signal of the trigger 11 to the input of the next-stage adjustable drive unit 10 to adjust the number of pixel rows scanned in one clock cycle.

[0025] In this embodiment, multiple adjustable driving units 10 are connected sequentially. The output terminal of the previous adjustable driving unit 10 is electrically connected to the input terminal of the next adjustable driving unit 10, so that the scanning signal can be transmitted step by step along the signal link formed by the multiple adjustable driving units 10. As an example, the number of adjustable driving units 10 can be the same as the number of pixel rows in the display panel, that is, each adjustable driving unit 10 corresponds to one pixel row in the display panel. The output signal of the trigger 11 in the adjustable driving unit 10 can be converted into a gate driving signal by the corresponding combinational logic gate circuit in the gate driving circuit and provided to the pixel circuit of the corresponding pixel row. The adjustable driving unit 10 can adjust the transmission timing of the scanning signal by receiving external control signals, thereby changing the number of pixel rows scanned in one clock cycle.

[0026] The flip-flop 11 is a sequential logic device with data latching function. It can latch the level state of its own data input terminal at the trigger edge of the clock signal and output it stably from the data output terminal to realize the synchronous delay of the electrical signal. As an example, the flip-flop 11 in this embodiment can be a D-type flip-flop or a latching structure composed of thin film transistors (TFTs) to adapt to the integrated manufacturing process of the display panel. The specific selection is not limited in this embodiment.

[0027] The multiplexer 12 is a controllable switching device that can select the output based on the level of the control signal received at its control terminal. The control signal it receives can be generated by the area address signal received by the display driver integrated circuit (DDIC) of the display panel through the corresponding decoder.

[0028] It should be noted that, in this embodiment, the input signal of the trigger 11 refers to the signal connected to the data input terminal of the trigger 11. If the trigger 11 is in the first-level adjustable drive unit 10, the signal can be an STV (StartVertical) pulse signal; otherwise, the signal is the signal output by the multiplexer 12 in the previous-level adjustable drive unit 10. The output signal of the trigger 11 refers to the signal output from the data output terminal of the trigger 11 in the next clock cycle after being latched by the clock. The number of pixel rows scanned in one clock cycle refers to the number of pixel rows that can simultaneously receive a valid gate drive signal within a single cycle of the clock signal. The more rows there are, the faster the scanning speed and the coarser the scanning granularity; the fewer rows there are, the higher the scanning accuracy and the richer the image details. If the input terminal of the next-level adjustable driving unit 10 receives the input signal of the flip-flop 11 in the current-level adjustable driving unit 10, then the current-level and next-level adjustable driving units 10 can output gate driving signals to their respective pixel rows through their respective combinational logic gates within one clock cycle, thus simultaneously scanning two rows of pixels within one clock cycle. If the input terminal of the next-level adjustable driving unit 10 receives the output signal of the flip-flop 11 in the current-level adjustable driving unit 10, then the current-level adjustable driving unit 10 outputs gate driving signals to the corresponding pixel rows through its corresponding combinational logic gates in the current clock cycle, and the next-level adjustable driving unit 10 outputs gate driving signals to the corresponding pixel rows through its corresponding combinational logic gates in the next clock cycle. That is, the current-level and next-level adjustable driving units 10 do not simultaneously scan two rows of pixels within one clock cycle. This embodiment achieves delayed latching and direct bypass transmission of the scanning signal based on the cooperation of the flip-flop 11 and the multiplexer 12, thereby realizing dynamic adjustment of the number of pixel rows scanned within one clock cycle.

[0029] Reference Figure 2 In some feasible embodiments, the clock input terminal CLK of the trigger is connected to the clock signal CKV, the data input terminal D of the trigger is electrically connected to the first input terminal 1 of the multiplexer, the data output terminal Q of the trigger is electrically connected to the second input terminal 0 of the multiplexer, the output terminal of the multiplexer is electrically connected to the input terminal of the next stage adjustable drive unit, and the controlled terminal of the multiplexer is connected to the control signal Sel.

[0030] As an example, this embodiment illustrates the internal electrical connections of an adjustable drive unit. The access of the clock signal CKV can provide a synchronization timing reference for the flip-flop. The data input terminal D of the flip-flop can be electrically connected to the first input terminal 1 of the multiplexer while simultaneously receiving the input signal, thus enabling the input signal of the flip-flop to simultaneously access the first path of the multiplexer. The data output terminal Q of the flip-flop is electrically connected to the second input terminal O of the multiplexer, enabling the latched output signal of the flip-flop to access the second path of the multiplexer. The output terminal of the multiplexer is electrically connected to the input terminal of the next-level adjustable drive unit, enabling signal transmission between adjacent adjustable drive units. The access of the control signal Sel can control the selection state of the first and second paths of the multiplexer, thereby determining whether the input terminal of the next-level adjustable drive unit accesses the input signal of the data input terminal D of the flip-flop through the first path of the multiplexer or the output signal of the data output terminal Q of the flip-flop through the second path of the multiplexer.

[0031] It is understandable that the scan signals output from the data output terminal Q and the data inversion output terminal QB of the flip-flop need to be provided to the corresponding combinational logic gate circuit to generate the gate drive signal before being provided to the pixel circuit of the corresponding pixel row to realize the gate drive.

[0032] In some feasible embodiments, when the control signal is at a first valid level, the first input and output of the multiplexer are connected, and the second input and output of the multiplexer are disconnected; when the control signal is at a second valid level, the first input and output of the multiplexer are disconnected, and the second input and output of the multiplexer are connected.

[0033] In this embodiment, the first effective level is either a high level or a low level, and the second effective level is either a high level or a low level.

[0034] When the control signal is at the first valid level, the adjustable drive unit can be considered to be in bypass mode. In this mode, the first path of the multiplexer is on and the second path is off. Therefore, the input signal of this stage's flip-flop does not need to undergo the flip-flop's latch delay and can be directly transmitted to the output of this stage through the first path of the multiplexer. This allows the flip-flops in the next stage of the adjustable drive unit to receive the same input signal as this stage's flip-flop, thereby enabling simultaneous scanning of two rows of pixels within one clock cycle. In bypass mode, the scan signal is equivalent to bypassing this stage's flip-flop and is transmitted to the next stage without delay.

[0035] When the control signal is at the second active level, the adjustable drive unit can be considered to be in latching mode. In this mode, the first path of the multiplexer is off, and the second path is on. Therefore, the input signal of this stage's flip-flop cannot be directly output through the first path of the multiplexer; it must first enter this stage's flip-flop, wait for the next clock trigger edge, be latched by this stage's flip-flop, and then output from the data output terminal. It is then transmitted to the output terminal of this stage via the second path of the multiplexer. In latching mode, the scan signal experiences a one-clock-cycle delay each time it passes through an adjustable drive unit, consistent with the operating mode of a traditional shift register.

[0036] In some feasible embodiments, when the control signals received by the consecutive nth to n+ith stage multiplexers are all at the first active level, the number of pixel rows scanned in one clock cycle is i+2 rows, where n is a positive integer and i is greater than or equal to 0.

[0037] In this embodiment, after the scan signal is transmitted from the output of the (n-1)th stage adjustable drive unit to the input of the nth stage adjustable drive unit, since the nth stage adjustable drive unit is in bypass mode under the control of the first effective level, the scan signal can be directly output to the output of the nth stage adjustable drive unit and simultaneously transmitted to the input of the (n+1)th stage adjustable drive unit. Since the (n+1)th to (n+1)th stage adjustable drive units are all in bypass mode, the scan signal can pass through each stage multiplexer sequentially without delay. The first path directly reaches the output of the (n+i)th adjustable drive unit and is then transmitted to the input of the (n+i+1)th adjustable drive unit. Therefore, within the same clock cycle, the flip-flops of the (n)th to (n+i+1)th adjustable drive units all receive the same scan signal and output multiple identical signals to the (n)th to (n+i+1)th combinational logic gates to generate multiple identical gate drive signals, which are then provided to the (n)th to (n+i+1)th pixel rows, thereby achieving parallel scanning of the (i+2)th pixel row.

[0038] As an example, when i=0, only the nth adjustable drive unit is in bypass mode, and in this case, the nth and (n+1)th rows of pixels are scanned simultaneously in one clock cycle; when i=1, the nth and (n+1)th adjustable drive units are in bypass mode, and in this case, the nth to (n+2)th rows of pixels are scanned simultaneously in one clock cycle; when i=2, the nth, (n+1)th, and (n+2)th adjustable drive units are in bypass mode, and in this case, the nth to (n+3)th rows of pixels are scanned simultaneously in one clock cycle.

[0039] In some feasible embodiments, when the control signals received by two adjacent multiplexers are both at the second active level, the number of pixel rows scanned in one clock cycle is one row.

[0040] In this embodiment, when the scan signal passes through each adjustable drive unit, it must be latched and delayed for one clock cycle by the flip-flop in the adjustable drive unit before it can be passed to the next adjustable drive unit. Therefore, after each clock cycle, the scan signal is only passed to the next level, corresponding to only one row of pixels for outputting a valid scan signal. When all control signals of the adjustable drive units in the shift register are set to the second valid level, the gate drive circuit operates in the standard progressive scan mode, with the highest scanning accuracy, scanning only one row of pixels per clock cycle.

[0041] The gate driving circuit provided in this embodiment enables the display panel to have a gaze point rendering function, and can configure the scanning accuracy according to the differences in the human eye's gaze position, thereby improving driving efficiency while ensuring the subjective visual experience.

[0042] In some feasible embodiments, when the pixel row corresponding to the m-th adjustable drive unit belongs to the foveation rendering area of ​​the display panel, the control signals received by the multiplexers in the (m-1)-th and m-th adjustable drive units are both the second effective level.

[0043] In this embodiment, when the scanning signal passes through the (m-1)th adjustable driving unit and the mth adjustable driving unit, it needs to be clock-latched by the trigger. Each stage of the scanning signal transmission consumes one clock cycle. Therefore, the pixel rows in the foveation rendering area are scanned line by line, and only one row of pixels is scanned in each clock cycle, ensuring that the foveation rendering area has the highest scanning accuracy and display resolution, matching the high-definition requirements of human eye center vision.

[0044] Reference Figure 3In some feasible embodiments, the display panel includes a first type of pixel row, a second type of pixel row and a third type of pixel row, wherein the first type of pixel row belongs to the foveation point rendering area, the second type of pixel row is located on one side of the foveation point rendering area, and the third type of pixel row is located on the side of the second type of pixel row away from the foveation point rendering area. The multiple adjustable driving units include: a first adjustable driving unit corresponding to a first type of pixel row, a second adjustable driving unit corresponding to a second type of pixel row, and a third adjustable driving unit corresponding to a third type of pixel row. Within one clock cycle, the number of third adjustable driving units providing scan signals is greater than the number of second adjustable driving units providing scan signals, and the number of second adjustable driving units providing scan signals is greater than the number of first adjustable driving units providing scan signals.

[0045] In this embodiment, the first type of pixel rows corresponds to the central vision of the human eye, requiring the highest level of display clarity; the second type of pixel rows belong to the transition area from central to peripheral vision, requiring the next highest level of display clarity; the third type of pixel rows corresponds to the peripheral vision of the human eye, where the human eye has the lowest sensitivity to details, requiring the lowest level of display clarity. Therefore, the peripheral area containing the third type of pixel rows has the highest number of pixel rows scanned per clock cycle, resulting in the fastest scanning speed and coarsest granularity; the transition area containing the second type of pixel rows has the next highest number of pixel rows scanned per clock cycle; and the central area of ​​the fixation point containing the first type of pixel rows has the lowest number of pixel rows scanned per clock cycle, resulting in the highest scanning accuracy. This embodiment, through differentiated scanning configuration, can significantly reduce the number of scanning clock cycles per frame without compromising the subjective visual experience of the human eye, thereby improving the display refresh rate or reducing drive power consumption.

[0046] Reference Figure 4 Taking a display panel with 4 / 2 / 1x scan areas as an example, let's assume the definition of the foveation point rendering area is as follows: The end line number of the first "4 lines per clock cycle": Line_end4_1st; The end line number of the first "2 lines per clock cycle": Line_end2_1st; The end line number for "1 line per clock cycle": Line_end1; The end line number of the second "2 lines per clock cycle": Line_end2_2nd; The end line number of the second "4 lines per clock cycle" is: Line_end4_2nd.

[0047] The decoding logic for the control signal Selx is as follows, where x represents the row number of the pixel, and Sel[x+3:x] represents the control signal from row x+3 to row x: If x ≤ Line_end4_1st, then Sel[x+3:x] = 1110, repeating once every 4 lines; If Line_end4_1st < x ≤ Line_end2_1st, then Sel[x+1:x] = 10, repeating once every 2 lines; If Line_end2_1st < x ≤ Line_end1, then Sel[x] = 0000 for all rows in this region; If Line_end1 < x ≤ Line_end2_2nd, then Sel[x+1:x] = 10, repeating once every 2 lines; If Line_end2_2nd < x ≤ Line_end4_2nd, then Sel[x+3:x] = 1110, repeating once every 4 lines.

[0048] It is important to note that Line_end4_1st must be a multiple of 4, and the result of subtracting Line_end4_1st from Line_end2_1st must be a multiple of 2. The same rule applies to the second "2 lines per clock cycle" area and the "4 lines per clock cycle" area. When the row number of the pixel row is a multiple of 4 (such as 2288), the control logic can be designed in groups of 4 rows to reduce design complexity.

[0049] Taking a display panel containing 20 rows of pixels as an example, assuming the scanning direction is from row 1 to row 20, and the scanning starts from the 4-row / clock-cycle area, the end row number of the first "4-row / clock-cycle" area (Line_end4_1st) = 4, the end row number of the first "2-row / clock-cycle" area (Line_end2_1st) = 8, the end row number of the "1-row / clock-cycle" area (Line_end1) = 12, the end row number of the second "2-row / clock-cycle" area (Line_end2_2nd) = 16, and the end row number of the second "4-row / clock-cycle" area (Line_end4_2nd) = 20, then the values ​​of the control signal Sel are: Sel[1:4] = 1110; Sel[5:8] = 1010; Sel[9:12] = 0000; Sel[13:16] = 1010; Sel[17:20] = 1110.

[0050] The positional change in the foveation point rendering area is as follows: Figure 5As shown, taking a 20-row panel as an example, the scanning direction is from row 1 to row 20. The scan starts from the 2-row / clock-cycle area. The end row number of the first "4-row / clock-cycle" area (Line_end4_1st) = 0, the end row number of the first "2-row / clock-cycle" area (Line_end2_1st) = 4, the end row number of the "1-row / clock-cycle" area (Line_end1) = 8, and the end row number of the second "2-row / clock-cycle" area (Line_end2_1st) = 8... nd2_2nd)=12, the end line number of the second “4 lines / clock cycle” region (Line_end4_2nd)=20, then the value of the control signal Sel is: Sel[1:4]=1010; Sel[5:8]=0000; Sel[9:12]=1010; Sel[13:20]=1110, 1110 (meaning that the control signal Sel of the two “4 lines / clock cycle” regions for lines 13 to 16 and lines 17 to 20 is 1110).

[0051] The positional change in the foveation point rendering area is as follows: Figure 6 As shown, taking a 20-row panel as an example, the scanning direction is from row 1 to row 20. The scan starts from the 1-row / clock-cycle area. The first "4-row / clock-cycle" area ends with line number (Line_end4_1st) = 0, the first "2-row / clock-cycle" area ends with line number (Line_end2_1st) = 0, the "1-row / clock-cycle" area ends with line number (Line_end1) = 4, and the second "2-row / clock-cycle" area ends with line number (Line_end2_1st) = 4. _end2_2nd)=8, the end line number of the second “4 lines / clock cycle” region (Line_end4_2nd)=20, then the value of the control signal Sel is: Sel[1:4]=0000; Sel[5:8]=1010; Sel[9:20]=1110, 1110, 1110 (meaning that the control signal Sel of the three groups of “4 lines / clock cycle” regions are all 1110 for lines 9 to 12, lines 13 to 16, and lines 17 to 20).

[0052] Reference Figure 7 In some feasible embodiments, the shift register further includes a scan sequence switching switch 20, the first end of which is connected to a start signal, the second end of which is electrically connected to the input of the first stage adjustable drive unit 10, and the third end of which is electrically connected to the input of the last stage adjustable drive unit 10. The scan order switching switch 20 is set to determine the pixel scan order as either scanning pixels from the first row to the last row, or scanning pixels from the last row to the first row, in response to a switch signal.

[0053] In this embodiment, the start signal can be an STV pulse signal; the switch signal can include SCAN_UP and SCAN_DOWN, where one is 1 and the other is 0; furthermore, to ensure that the signal transmission order between the adjustable drive units is consistent with the pixel scanning order, refer to... Figure 8 For every two adjacent adjustable drive units, a forward scan switch S1 is provided between the output terminal of the previous adjustable drive unit and the input terminal of the subsequent adjustable drive unit, and a reverse scan switch S2 is provided between the input terminal of the previous adjustable drive unit and the output terminal of the subsequent adjustable drive unit. When the pixel scanning order is from the first row to the last row, the forward scan switch S1 is closed and the reverse scan switch S2 is open. When the pixel scanning order is from the last row to the first row, the forward scan switch S1 is open and the reverse scan switch S2 is closed.

[0054] As an example, with SCAN_UP=0 and SCAN_DOWN=1, refer to Figure 9 The first and second terminals of the scan sequence switching switch 20 are turned on, and the first and third terminals are turned off. The pixel scanning sequence is from the first row (corresponding to the highest number) to the last row (corresponding to the lowest number). The start signal is input from the first-stage adjustable drive unit and transmitted sequentially along the forward cascaded link to the last-stage adjustable drive unit, that is, scanning pixel rows from high to low. Further, refer to... Figures 10 to 13 , Figures 10 to 13 While demonstrating a scanning order from the first row to the last row, it also shows that the value of the control signal Sel determines whether the multiplexer selects the first or second path, thus determining whether the input of the next-level adjustable drive unit is connected to the data input or output of the flip-flop in this level of adjustable drive unit. The following are four specific cases: 1. Programming 4 lines within one clock cycle: In this region, Sel[x+3:x] (representing the 4 signals from Selx+3 to Selx) is 1110, and repeats every 4 bits. In this example, for a 4x region (4 rows of pixels outputting the same WS / DS / AZ drive signals), for example, the 3840 to 3837th rows of pixels, in the corresponding... Figure 10In the shift register shown, the 3840th flip-flop receives the input signal STV. Since the control signal Sel[3840:3837] = 1110 corresponding to the 3840 / 3839 / 3838 / 3837 multiplexers, the input signal of the 3839 / 3838 / 3837 flip-flops is also the STV signal. Within one clock cycle, the Q and QB signals output by the 3840 / 3839 / 3838 / 3837 flip-flops are identical, meaning that four rows of pixels are scanned simultaneously and the drive signals WS / DS / AZ received by the four rows of pixels are also identical. 2. Programming three lines within one clock cycle: In this region, Sel[x+2:x] (representing the three signals from Selx+2 to Selx) takes the value 110 and repeats every three bits. In this example, for a three-fold region, such as the three rows of pixels from 3339 to 3337, the corresponding... Figure 11 In the shift register shown, the control signal Sel[3339:3337] corresponding to the 3839 / 3838 / 3837 multiplexers is 110. Therefore, the input signals of the 3339 / 3338 / 3337 flip-flops are the same, which are all the output signals of the 3340 multiplexer. Since the control signal of the 3339 / 3338 / 3337 multiplexers is 110, the Q and QB signals output by the 3839 / 3838 / 3837 flip-flops are the same, that is, the simultaneous scanning of three rows of pixels is achieved. 3. Programming two lines in one clock cycle: In this area, Sel[x+1:x] (representing the two signals from Selx+1 to Selx) takes the value of 10 and repeats every 2 bits. In this example, for a double area, such as the four rows of pixels from 2840 to 2837, the corresponding... Figure 12 In the shift register shown, the control signal Sel[2840:2837]=1010 for multiplexers 2840 / 2839 / 2838 / 2837. The 2840 / 2839 flip-flops receive the same input signal. Since the control signal for multiplexers 2840 and 2839 is 10, the 2840 and 2839 flip-flops output the same Q and QB signals respectively. The 2839 multiplexer uses the Q2839 signal output by the 2839 flip-flop as its input signal to the 2838 flip-flop. Therefore, the 2838 flip-flop will only output Q2838 in the next CLK. Similarly, the 2837 flip-flop outputs the same Q and QB signals as the 2838 flip-flop. 4. Programming one line within one clock cycle: In this region, the Selx value of all bits is 0, such as... Figure 13 As shown.

[0055] As an example, with SCAN_UP=1 and SCAN_DOWN=0, refer to Figure 14 When the first and second terminals of the scan sequence switching switch 20 are off, and the first and third terminals are on, the pixel scanning sequence is from the last row (corresponding to the lowest number) to the first row (corresponding to the highest number). The start signal is input from the last stage adjustable drive unit and transmitted sequentially to the first stage adjustable drive unit along the reverse cascaded link, that is, scanning pixel rows from low to high. Further, refer to... Figures 15 to 18 , Figures 15 to 18 While demonstrating a scanning order from the last row to the first row, it also shows that the value of the control signal Sel determines whether the multiplexer selects the first or second path, thus determining whether the input of the next-level adjustable drive unit is connected to the data input or output of the flip-flop in this level of adjustable drive unit. The following are four specific cases: 1. Programming four lines within one clock cycle: In this area, Sel[x:x+3] (representing the four signals from the lowest number Selx to the highest number Selx+3) has a value of 1110, and repeats every four bits. Figure 15 As shown; 2. Programming 3 lines within one clock cycle: In this area, Sel[x:x+2] (representing the 3 signals from the low number Selx to the high number Selx+2) takes the value 110, and repeats every 3 bits, as shown. Figure 16 As shown; 3. Programming two lines within one clock cycle: In this region, Sel[x:x+1] (representing the two signals from the lower number Selx to the higher number Selx+1) takes the value 10, and repeats every 2 bits, as shown. Figure 17 As shown; 4. Programming one line within one clock cycle: In this region, the Selx value of all bits is 0, such as... Figure 18 As shown. The specific working principle involved in this example is the same as described above. Figure 6 The specific implementation methods corresponding to the examples are similar, only the scanning order is reversed, which will not be elaborated here.

[0056] In addition, refer to Figure 19 This application also provides a display panel, which includes the gate driving circuit in the above embodiments. The gate driving circuit can be disposed on both sides of the display area of ​​the display panel.

[0057] As an example, the display panel in this embodiment may be a silicon-based OLED (Organic Light-Emitting Diode) display panel or a silicon-based Micro-LED display panel; this embodiment does not limit it in this way.

[0058] Since the display panel proposed in this embodiment adopts all the technical solutions of all the above embodiments and belongs to the same technical concept, this embodiment has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0059] In addition, refer to Figure 20 This application also provides a display device, which 1000 includes the display panel 100 in the above embodiments.

[0060] As an example, the display device can be a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, VR (Virtual Reality) device, AR (Augmented Reality) device, MR (Mixed Reality) device, etc., or any other product or component with display function. This embodiment does not limit this.

[0061] Since the display device proposed in this embodiment adopts all the technical solutions of all the above embodiments and belongs to the same technical concept, this embodiment has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0062] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0063] Furthermore, in the embodiments of this application, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B.

[0064] In the embodiments of this application, unless otherwise expressly specified and limited, the terms "connection" and "fixed" should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0065] It should also be understood that references to "one embodiment" or "some embodiments" in the specification of embodiments of this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0066] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the embodiments of this application.

[0067] The above are merely optional embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, Applied to a display panel, the gate driving circuit includes at least one shift register, the shift register includes multiple cascaded adjustable driving units, each stage of the adjustable driving unit includes a set of flip-flops and multiplexers, the data input terminal of the flip-flops serves as the input terminal of the adjustable driving unit, and the output terminal of the multiplexer serves as the output terminal of the adjustable driving unit; The multiplexer is configured to, in response to a control signal, provide the input or output signal of the trigger to the input of the next-level adjustable drive unit to adjust the number of pixel rows scanned in one clock cycle.

2. The gate driving circuit as described in claim 1, characterized in that, The clock input terminal of the trigger is connected to a clock signal, the data input terminal of the trigger is electrically connected to the first input terminal of the multiplexer, the data output terminal of the trigger is electrically connected to the second input terminal of the multiplexer, the output terminal of the multiplexer is electrically connected to the input terminal of the next-level adjustable drive unit, and the controlled terminal of the multiplexer is connected to the control signal.

3. The gate driving circuit as described in claim 2, characterized in that, When the control signal is at the first active level, the first input and output of the multiplexer are connected, and the second input and output of the multiplexer are disconnected. When the control signal is at the second active level, the first input and output of the multiplexer are turned off, and the second input and output of the multiplexer are turned on.

4. The gate driving circuit as described in claim 3, characterized in that, When the control signals received by the consecutive multiplexers from the nth to the (n+i)th stage are all at the first valid level, the number of pixel rows scanned in one clock cycle is i+2 rows, where n is a positive integer and i is greater than or equal to 0.

5. The gate driving circuit as described in claim 3, characterized in that, When the control signals received by the two adjacent multiplexers are both at the second active level, the number of pixel rows scanned in one clock cycle is one row.

6. The gate driving circuit as described in claim 3, characterized in that, When the pixel row corresponding to the m-th adjustable drive unit belongs to the foveation rendering area of ​​the display panel, the control signals received by the (m-1)-th adjustable drive unit and the multiplexer in the m-th adjustable drive unit are both the second active level.

7. The gate driving circuit as described in claim 1, characterized in that, The display panel includes a first type of pixel row, a second type of pixel row and a third type of pixel row. The first type of pixel row belongs to the foveation point rendering area, the second type of pixel row is located on one side of the foveation point rendering area, and the third type of pixel row is located on the side of the second type of pixel row away from the foveation point rendering area. The plurality of adjustable driving units include: a first adjustable driving unit corresponding to the first type of pixel row, a second adjustable driving unit corresponding to the second type of pixel row, and a third adjustable driving unit corresponding to the third type of pixel row. Within one clock cycle, the number of the third adjustable driving units providing the scan signal is greater than the number of the second adjustable driving units providing the scan signal, and the number of the second adjustable driving units providing the scan signal is greater than the number of the first adjustable driving units providing the scan signal.

8. The gate driving circuit as described in claim 1, characterized in that, The shift register also includes a scan order switching switch. The first terminal of the scan order switching switch is connected to a start signal, the second terminal of the scan order switching switch is electrically connected to the input terminal of the first-stage adjustable drive unit, and the third terminal of the scan order switching switch is electrically connected to the input terminal of the last-stage adjustable drive unit. The scan order switching switch is configured to, in response to a switch signal, determine the pixel scan order as either scanning pixels from the first row to the last row, or scanning pixels from the last row to the first row.

9. A display panel, characterized in that, The display panel includes a gate driving circuit as described in any one of claims 1 to 8.

10. A display device, characterized in that, The display device includes the display panel as described in claim 9.

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