Solid-state memory, information processing apparatus, and data processing method

Abstract

The present invention relates to a solid-state memory, an information processing apparatus, and a data processing method, and reliably reads data written regardless of the time elapsed from the time of writing. A storage unit respectively has a plurality of storage cells, and the storage cells respectively hold a voltage corresponding to a value as an element of data. A controller sets a reference voltage that demarcates the voltage corresponding to the value, based on the elapsed time from the time of writing data to the storage unit, when reading data from the storage unit, and determines the value indicated by the voltage held in the storage cell using the reference voltage.

Description

Technical Field

[0001] This invention relates to solid-state storage, information processing apparatus, and data processing methods, for example, to reading data stored in solid-state storage. Background Technology

[0002] Solid-state storage (SSD) is a storage device that uses flash memory as its storage element. SSDs can read and write data much faster than the previously prevalent hard disk drives (HDDs). Data reading and writing are performed electrically, without mechanical movement, resulting in excellent quiet operation. Flash memory has multiple memory cells, each equipped with a floating-gate MOSFET (metal-oxide-semiconductor field-effect transistor).

[0003] A floating-gate MOSFET has a double-gate structure, consisting of an insulating tunnel oxide film sandwiched between the source and drain electrodes on the substrate. This double-gate structure is formed by sandwiching an insulating gate oxide film between the floating gate and the control gate. Data writing is achieved by applying a voltage to the drain, thus accumulating charge in the floating gate. Data erasure is achieved by releasing charge from the floating gate. In other words, the value constituting the data is stored by the voltage generated at the floating gate of the memory cell.

[0004] NAND flash memory storage methods include SLC (Single-Level Cell), MLC (Multi-Level Cell), TLC (Triple-Level Cell), and QLC (Quadrature-Level Cell). SLC, MLC, TLC, and QLC utilize threshold voltages of 2, 4, 8, and 16 levels, respectively. th Each cell records a value of 1, 2, 3, or 4 bits. When reading data, reference voltages V1, V3, V7, and V15 levels are used in SLC, MLC, TLC, and QLC, respectively. ref To determine the value corresponding to the held voltage. Each reference voltage V ref The threshold voltage V is set in the adjacent level 2. th In the middle. Reference voltage V refSometimes referred to as programming voltage. That is, the more voltage levels per unit, the more high-density data can be recorded; conversely, the voltage width representing a single level becomes narrower, thus requiring a precise threshold voltage V. th The settings.

[0005] On the other hand, in NAND flash memory, frequent repeated data reads and writes generate stress-induced leakage current (SILC). Therefore, the voltage generated in the data cells cannot be maintained and sometimes gradually decreases. Leakage current is mainly caused by the leakage of electrons from the floating gate and the electrons retained in the oxide film. Leakage current is exacerbated by the passage of time, degradation of the data cells themselves, and high-temperature environments. This voltage drop can be a major cause of read errors. Additionally, sometimes the voltage generated in the data cells due to the leakage of charge injected into the oxide film becomes the threshold voltage V. th The following phenomena occur. In particular, the more threshold voltage levels V are set... th The more complex the multi-level cell NAND flash memory, the more significant the read errors.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-141219

[0007] Therefore, in existing SSDs, changing the reference voltage V ref Read Retry data reading maintains the integrity of the stored data and ensures reliability. More specifically, in the write process, data is stored with error detection codes pre-included. In the read process, the following process is repeated until the read is successful. (1) Set a predetermined reference voltage V ref (2) By using the set reference voltage V ref To determine the voltage generated in each data unit, thereby decoding the data, (3) determine whether the reading is successful or not based on the error detection code. (4) when the reading fails, change the reference voltage V. ref And return to (2). However, the more significant the voltage drop generated in the data unit, the more repetitions are required until the read is successful. Therefore, the read time becomes longer. Summary of the Invention

[0008] This application was made to solve the aforementioned problems. One aspect of this application relates to a solid-state memory comprising: a plurality of storage units; and a controller that controls the writing and reading of data according to each of the storage units. Each of the storage units comprises a plurality of storage cells, and each of the storage cells maintains a voltage corresponding to a value that is an element of the data. When the controller reads data from the storage cell, it sets a reference voltage based on the elapsed time from the time when the data is written to the storage cell. The reference voltage is used to define the voltage corresponding to the value, and the reference voltage is used to determine the value represented by the voltage maintained in the storage cell.

[0009] In the aforementioned solid-state memory, the controller may be configured to set the reference voltage in such a way that the longer the elapsed time, the lower the reference voltage becomes.

[0010] In the aforementioned solid-state memory, the controller may also record the moment when writing data to the storage unit as the write moment.

[0011] In the aforementioned solid-state memory, the controller may be configured to determine the reference voltage corresponding to the elapsed time by referring to a pre-set reference table, wherein the reference table represents the reference voltage reference value according to each elapsed time from the writing moment.

[0012] In the aforementioned solid-state memory, the controller may also be configured such that when it detects an error based on the data read from the storage unit, it reduces the reference voltage and uses the reduced reference voltage to determine the value represented by the voltage held in the storage unit.

[0013] The information processing apparatus involved in the second aspect of this application may also be configured to include a host system and the aforementioned solid-state memory, wherein the controller determines the writing time based on the time notified by the host system when writing the aforementioned data.

[0014] The third aspect of the present invention relates to a data processing method for a solid-state memory. The solid-state memory has multiple storage units and a controller. The controller controls the writing and reading of data according to each storage unit. Each storage unit has multiple storage cells. Each storage cell holds a voltage representing a value that is an element of the data. When the controller reads data from the storage cell, it sets a reference voltage based on the elapsed time since the time when the data was written to the storage cell. The reference voltage is used to define the voltage corresponding to the value. The reference voltage is used to determine the value represented by the voltage held in the storage cell.

[0015] According to the embodiments of this application, the performance of the read processing is improved by reliably reading the written data regardless of the elapsed time since the writing moment. That is, the reference voltage V... ref The value is set to correspond to the elapsed time since the write time. The read process begins using the set value, thereby increasing the probability of successful data read and enabling faster read processing. Attached Figure Description

[0016] Figure 1 This is a schematic block diagram illustrating the hardware structure of the information processing device involved in this embodiment.

[0017] Figure 2 This is a schematic block diagram illustrating an example of the functional structure of the SSD involved in this embodiment.

[0018] Figure 3 This is a diagram illustrating an example configuration of the memory chip involved in this embodiment.

[0019] Figure 4 This is a diagram illustrating an example of a data structure for the header information involved in this embodiment.

[0020] Figure 5 This is a diagram illustrating an example of a data structure for block information involved in this embodiment.

[0021] Figure 6 This is a circuit diagram illustrating a structural example of the memory chip involved in this embodiment.

[0022] Figure 7 This is an explanatory diagram illustrating an example of setting the reference voltage according to this embodiment.

[0023] Figure 8 This is a diagram illustrating a record example of the write time involved in this embodiment.

[0024] Figure 9 This is a diagram illustrating an example of setting the reference voltage according to this embodiment.

[0025] Figure 10 This is a diagram illustrating the reference table involved in this embodiment.

[0026] Figure 11 This is a flowchart illustrating the write process involved in this embodiment.

[0027] Figure 12 This is a flowchart illustrating the reading process involved in this embodiment.

[0028] Explanation of reference numerals in the attached figures

[0029] 1…Information processing device; 10…Host system; 11…CPU; 12…Main memory; 21…Chipset; 22…BIOS memory; 23…USB connector; 24…SSD; 242…SSD controller; 244 (244-1 to 244-N)…Storage chip; 25…Video subsystem; 25d…Display; 26…Audio system; 27…Network card; 31…EC; 32…Input device; 33…Power supply circuit. Detailed Implementation

[0030] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. First, an example of the structure of the information processing apparatus 1 according to the embodiments of the present application will be described. Figure 1 This is a schematic block diagram illustrating the hardware structure of the information processing device 1 according to this embodiment. In the following description, the information processing device 1 is primarily described as a notebook personal computer (PC), but it is not limited thereto. The information processing device 1 can also be implemented using any of the following methods: desktop PC, tablet terminal device, multi-function mobile phone (smartphone).

[0031] The information processing device 1 includes: a host system 10, a BIOS (Basic Input Output System) memory 22, a USB (Universal Serial Bus) connector 23, an SSD (Solid State Drive) 24, a video subsystem 25, a display 25d, an audio system 26, a network card 27, an EC (Embedded Controller) 31, an input device 32, and a power supply circuit 33.

[0032] The host system 10 includes a CPU (Central Processing Unit) 11, main memory 12, and chipset 21.

[0033] CPU 11 is a processor that executes programs stored in main memory 12, performs various arithmetic operations, cooperates with hardware, primarily main memory 12, to implement and control the operations of various parts of information processing device 1. In this application, "executing a program" or "program execution" refers to executing processing instructed by commands described in the program.

[0034] Main memory 12 functions as the working area for the processing executed by CPU 11. It temporarily or permanently stores programs executed by CPU 11, data (including parameters) used by the processing of CPU 11, and data generated by the processing of CPU 11. The data stored in main memory 12 may also include intermediate data generated by a process and usable by subsequent processes. Programs executed by CPU 11 may include, for example, an OS (Operating System), various drivers for operating peripheral devices and other hardware, various services / utilities, applications, etc. Main memory 12 has one or more DRAMs (Dynamic Random Access Memory).

[0035] Chipset 21 includes a bus controller for connecting various devices via wired connections. Chipset 21 connects to other devices, for example, using a PCIe bus. Using the PCIe bus, chipset 21 can connect to at least EC31 and SSD24. In addition to PCIe, chipset 21 can also connect to other devices using one or more of the following methods: USB, Serial ATA (AT Attachment), SPI (Serial Peripheral Interface), PCI (Peripheral Component Interconnect), and LPC (Low Pin Count). The bus controller controls the input and output of data to the devices connected via each method.

[0036] The BIOS memory 22 is configured as a non-volatile memory containing system firmware. As a non-volatile memory, EEPROM (Electrically Erasable Programmable Read Only Memory), flash ROM, etc., are used. System firmware is a program related to the overall operation of the computer system, used to provide an interface between the hardware and various programs executing in the host device. For example, the system firmware includes the BIOS (Basic Input / Output System). In this application, the aforementioned system firmware is sometimes collectively referred to as "BIOS".

[0037] The USB connector 23 is an interface for detachably connecting peripheral devices using USB. The USB connector 23 is fixed to the frame of the information processing device 1.

[0038] The SSD24 features rewritable non-volatile memory and serves as an auxiliary storage device for storing various types of data. The SSD24 can execute commands from the host system 10 to write new data, read existing data, or erase previously stored data. Sometimes, the SSD24 contains programs executed by the host system 10, such as the operating system, drivers, services / utilities, and applications.

[0039] The video subsystem 25 performs image display (drawing) related processing based on control from the CPU 11. The video subsystem 25 is a processor with video memory and image display related functions based on control from the CPU 11. The video subsystem 25 processes drawing commands output from the CPU 11 and writes the obtained drawing information into the video memory. The video subsystem 25 reads the newly written drawing information from the video memory and outputs the read drawing information as drawing data (display data) to the display 25d.

[0040] The display 25d displays the image based on the drawing data (display data) input from the video subsystem 25. The display 25d is, for example, a liquid crystal display (LCD).

[0041] The audio system 26 is a device capable of performing input, output, recording, and playback of sound data.

[0042] Network interface card 27 connects to a network and can perform data communication via wired or wireless means. Network interface card 27 can also connect to other devices directly via a wireless LAN (Local Area Network) or further via other networks.

[0043] EC31 is a microcomputer that monitors and controls the status of various devices (peripheral devices, sensors, etc.) regardless of the operating state (operating mode) of information processing device 1. EC31 is configured, for example, as a one-chip microcomputer (not shown) with a CPU, ROM, RAM, multiple channels of A / D (Analog to Digital) input terminals, D / A (Digital to Analog) output terminals, a timer, and digital input / output terminals. Input devices 32 and power supply circuits 33 are connected to the digital input / output terminals, for example. SSD 24 is connected to EC31, for example, according to the I3C (registered trademark) standard.

[0044] EC31 executes firmware different from the system firmware to perform its functions. EC31 has temperature management and power management functions. The temperature management function is the function of acquiring temperature data from SSD24 and controlling the operation of the heat dissipation mechanism (e.g., cooling fan (not shown)) of information processing device 1 based on the acquired temperature data. The power management function is the function of controlling the power supply circuit 33 to supply power to the various parts of information processing device 1. EC31, for example, controls the power supply to CPU11 and other devices.

[0045] Input device 32 accepts user operations and outputs corresponding operation signals to EC31. These operation signals indicate various information or instructions. Input device 32 can be, for example, any type of keyboard, touchpad, or pointing device.

[0046] The power supply circuit 33 converts the voltage of the DC power supplied from the AC / DC (Alternate Current / Direct Current) adapter or battery cell into an operating voltage for operating each device of the information processing device 1. The power supply circuit 33 supplies power with this operating voltage to each device. The power supply circuit 33 includes, for example, a DC / DC converter and a charging / discharging unit, in addition to the AC / DC adapter and battery cell. The power supply circuit 33 operates based on control from the EC31.

[0047] In addition, when performing its functions, the host system 10 performs actions such as writing data to the SSD 24, reading data stored in the SSD 24, or erasing data stored in the SSD 24.

[0048] When writing data to SSD24, host system 10 issues a write command that includes the data to be written and outputs the issued write command to SSD24.

[0049] When the host system 10 reads data from the SSD 24, it issues a read command indicating the data to be read and outputs the issued read command to the SSD 24. The host system 10 retrieves the data to be read as indicated by the read command from the SSD 24 as a response to the read command.

[0050] When the host system 10 erases the data stored in the SSD 24, it outputs an erasure command indicating the data to be erased to the SSD 24.

[0051] Next, the functional structure example of the SSD24 involved in this embodiment will be described. Figure 2 This is a schematic block diagram illustrating an example of the functional structure of the SSD24 involved in this embodiment.

[0052] SSD24 is connected to host system 10 and EC31 respectively.

[0053] The SSD24 features an SSD controller 242 and N (N is an integer greater than 2, typically 4 to 128) storage chips 244. Figure 2 In this design, each memory chip 244 is distinguished by a sub-number such as 244-1-1. Each memory chip 244 is also referred to as a die. The SSD controller 242 and the N memory chips 244 are configured to not overlap on the surface of a common substrate.

[0054] Each memory chip 244 has multiple memory cells. These memory cells can be based on any method, such as floating gate or charge trap. Each memory cell can store one or more bits of information. The memory cells can also be any of SLC, MLC, TLC, QLC, etc.

[0055] The SSD 24 is formed by N storage chips 244. Each storage chip 244 has multiple data blocks (sometimes referred to simply as "blocks" in this application). Figure 3 In this example, each memory chip 244 has multiple planes, and each plane has multiple blocks. Each plane is identified by a die-plane number. Each block is identified by a block number (BLK No.). Data writing or reading is performed on a page-by-page basis. Data erasure within each page is performed on a block-by-block basis. In other words, each block is equivalent to a storage unit used to store data.

[0056] The SSD controller 242 manages the presence or absence of data stored in each block, and the write timing of each page of data within a block containing data. It can use memory addresses to identify individual pages. A block header information is stored in the SSD24's storage area. This block header information describes the overall specifications of the SSD24's storage area, as well as the specifications shared by all blocks. Figure 4 The illustrated block header information (BLK INFO HEAD structure) describes the version, channel (ch), number of dies per channel (die_per_ch), number of planes per die (pl_per_die), and maximum overwrite lifetime (sslc_max_pe, xlc_max_pe). Overwrite lifetime tends to be shorter with storage methods that have more bits per unit.

[0057] Store one block of information for each block. Figure 5The illustrated block information (BLK INFO) describes the usage status and data recording status of each block. The usage status describes the rewrite lifetime (pe), storage mode (blk_mode), data type, temperature during write (temp), and access status (state). The data recording status describes the data retention time (duration), time to the next disk check (time_to_check), data quality (data_quality), valid data ratio (valid_data_ratio), and read count after a write. The SSD controller 242 updates the block information each time the block is accessed, based on the access content indicated by instructions received from the host system 10.

[0058] Next, an example of the structure of the memory chip 244 involved in this embodiment will be described. Figure 6 This is a circuit diagram illustrating a structural example of the memory chip 244 involved in this embodiment. Figure 6 The illustrated memory chip 244 is configured as NAND flash memory. The example uses SLC (Single LC) storage for each memory cell.

[0059] The memory chip 244 has multiple memory cells arranged in a two-dimensional pattern on a substrate, each block. Each block has bit lines in each column. Each row of a block is called a word line and corresponds to a page. Each column of a block corresponds to a bit. The bit lines are formed by connecting multiple memory cells in series. One end of the bit line is connected to a power supply via a bit line select transistor, and one end of a capacitor is connected to the other end of the bit line select transistor and one end of the memory cell in the first row. One end of each capacitor is connected to an I / O page buffer via an inverting circuit. The I / O page buffer is provided in the SSD controller 242 and temporarily stores write-object data or read-object data. The other end of the bit line is connected to a reference potential point via a ground select transistor. A power supply voltage VDD is applied to the control gate of the ground select transistor.

[0060] Next, use Figure 6 The data writing method is explained. Within the storage unit of the object page, the SSD controller 242 applies a threshold voltage V corresponding to each value constituting the data to be written to the object. th An application is made to the storage cell configured in the column where the value should be recorded. Since the storage cell uses SLC (Single-Low Voltage) storage, a threshold voltage V of level 1 is applied. th and reference voltage V ref Reference voltage V ref This is the voltage used to determine whether the written value is "1" or "0" based on the voltage V generated in the memory cell (hereinafter, sometimes called "holding voltage V"). The reference voltage V... refSet the threshold voltage V corresponding to the ratio and value "1". th Low value.

[0061] More specifically, the SSD controller 242 operates as follows during data writing: (1) It sets a reference voltage V for the control gate of the memory cell in each column of the target page. ref (2) For each column corresponding to the bit with the write value "1", the power supply voltage VDD is set to the control gate of the bit line select transistor. This connects one end of the capacitor to the power supply, thus charging one end of the capacitor. (3) For each column, the power supply voltage VDD is set to the control gate of the memory cell in each row other than the target page, and the drain current flows from the capacitor toward the memory cell of the target page, thus charging it. (4) The voltage generated at one end of the capacitor in each column is detected. The SSD controller 242 continues to charge the memory cell until the voltage detected from each column exceeds the set reference voltage VDD. ref Threshold voltage V th until.

[0062] When the SSD controller 242 finishes writing data, it stores the write time of the object page to which the data was written in the block information.

[0063] On the other hand, when reading data, the SSD controller 242 detects the holding voltage V of each column within the page being read. The SSD controller 242 then compares the detected holding voltage V with the reference voltage V. ref The value corresponding to the holding voltage V is determined by comparison. That is, the reference voltage V. ref This is equivalent to the threshold used to define the value represented by the holding voltage V.

[0064] When the storage method of the memory cell is SLC, the reference voltage V of level 1 is used to determine the value. ref While maintaining a voltage V lower than a reference voltage V ref In this case, the SSD controller 242 will maintain the value represented by the voltage V as "0".

[0065] Furthermore, for storage units such as MLC that can record multi-bit values, the SSD controller 242 can also perform data reading and writing through the same process described above. This involves setting a threshold voltage V corresponding to each value n. th,n and reference voltage V ref,n (Reference Figure 9 The threshold voltage V involved in the value n. th,n The reference voltage V is set to be the value n. ref,n The reference voltage V involved with the value n+1 one level higher ref,n+1The intermediate value. During data writing, the SSD controller 242 only needs to apply a threshold voltage V corresponding to the value n that constitutes the data being written. th,n That's all.

[0066] Additionally, during data reading, the SSD controller 242 detects the holding voltage V for each storage cell within the object page, and compares the detected holding voltage V with the reference voltage V for each stage. ref,n A comparison is made. The reference voltage V is used when the voltage V is held at a certain level of value n. ref,n The reference voltage V involved in the value above and less than the next larger value n+1 ref,n+1 In this case, the SSD controller 242 can determine the value represented by the holding voltage V as n.

[0067] The holding voltage V has a threshold voltage V at the initial time of data writing. th The voltage is equal, but tends to gradually decrease over time. If the holding voltage V is equal to the reference voltage V corresponding to the written value n. ref,n If the voltage decreases, the value determined based on the holding voltage V detected at that time point becomes a value n-1 smaller than the written value n, thus the SSD controller 242 generates a read error. Generally, due to individual differences in storage cells and usage frequency, the holding voltage of storage cells to which a threshold voltage corresponding to a specific value is applied may vary. Therefore, the holding voltage V varies for each value. Figure 7 The upper part illustrates the distribution of the number of memory cells based on the holding voltage V for each of the values ​​001, 010, 011, and 100. This is because the holding voltage V in a portion of the memory cells is lower than the respective reference voltage V for values ​​001, 010, 011, and 100. ref,1 V ref,2 V ref,3 V ref,4 Therefore, reading the written value failed.

[0068] Therefore, the SSD controller 242 in this embodiment records the time of writing data for each page as the write time. Figure 8 In the example, for each page 1, 2, and 3, the write time is recorded as TIME 1, TIME 2, and TIME 3. The write time can also be recorded as part of the block information of the block to which each page belongs, or it can be recorded separately from the block information.

[0069] When reading data, the SSD controller 242 determines the elapsed time from the write time recorded on the page being read to that point in time, and adjusts the reference voltage V in a decreasing manner based on the elapsed time. ref,n .exist Figure 7In the example below, for each of the values ​​001, 010, 011, and 100, the setting is adjusted to be greater than the initial reference voltage V written to. ref,1 V ref,2 V ref,3 V ref,4 Low reference voltage V ref,1 '、 V ref,2 '、 V ref,3 '、 V ref,4 '. Reference voltage V ref,1 '、 V ref,2 '、 V ref,3 '、V ref,4 The holding voltage V of the memory cells associated with values ​​001, 010, 011, and 100 are respectively lower than the distributions of these values. Therefore, there is no value lower than the reference voltage V of each of the values ​​001, 010, 011, and 100. ref,1 '、 V ref,2 '、 V ref,3 '、 V ref,4 The storage unit is used to eliminate false detections.

[0070] Alternatively, the reference voltage V can be preset in the SSD controller 242 according to each elapsed time. ref,n The reference table for the baseline value is based on the reference voltage V corresponding to the storage method of the memory cell after the passage of time. ref,n This value is determined as a reference value and used to determine the value from the holding voltage V. Figure 10 The illustrated reference table, for each elapsed time T0, T1, T2, uses the reference voltage as a baseline value, described as V. ref,n (T0), V ref,n (T1), V ref,n (T2). The reference voltage is set according to V. ref,n (T0), V ref,n (T1), V ref,n The order of (T2) decreases, V ref,n (T0) is the highest. Figure 10 The example shown represents the reference voltage V for the value n. ref,n The reference table can be set in the SSD controller 242 for each value.

[0071] For each of the following cases: when the elapsed time at that point is less than T0, more than T0 but less than T1, or more than T1 but less than T2, the SSD controller 242 can determine the reference voltage as V. ref,n (T0), V ref,n (T1), V ref,n(T2). In the SSD controller 242, a function that inputs elapsed time and outputs a reference voltage can be preset instead of a reference table. The SSD controller 242 uses the preset function to calculate the reference voltage corresponding to the elapsed time.

[0072] The SSD controller 242 can also use the time recorded by its own device or EC31 as the write or read time, or it can obtain a timestamp indicating the time recorded by the host system 10 and refer to the obtained timestamp. The SSD controller 242 can also use a timestamp appended to a write command or read command. In this case, the host system 10 appends a timestamp indicating the time of issuance to the write command and the read command respectively, and outputs it to the SSD 24.

[0073] Next, an example of the write processing involved in this embodiment will be described. Figure 11 This is a flowchart illustrating the write process involved in this embodiment.

[0074] (Step S102) The SSD controller 242 waits for a write command from the host system 10. When a write command is input from the host system 10, the SSD controller 242 determines the write object data and write object address specified by the input write command, and reads the timestamp attached to the write command.

[0075] (Step S104) The SSD controller 242 writes write object data to the write object page indicated by the determined write object address. Here, the SSD controller 242 sets the threshold voltage V corresponding to each value constituting the data. th The storage unit within the write object page to which the value is written is applied.

[0076] (Step S106) The SSD controller 242 records the time indicated by the read timestamp as the write time for the page to be written. Then, the process ends. Figure 11 The processing.

[0077] Next, an example of the read processing involved in this embodiment will be described. Figure 12 This is a flowchart illustrating the reading process involved in this embodiment.

[0078] (Step S202) The SSD controller 242 waits for a read command from the host system 10. When a read command is input from the host system 10, the SSD controller 242 determines the read target data and read target address specified by the input read command, and reads the timestamp attached to the read command.

[0079] (Step S204) The SSD controller 242 reads the write time of the read object page indicated by the determined read object address, and determines the time indicated by the timestamp as the read time. The SSD controller 242 calculates the elapsed time from the write time to the read time.

[0080] (Step S206) The SSD controller 242 determines the reference voltage V corresponding to the calculated elapsed time by referring to a pre-set reference table. ref .

[0081] (Step S208) The SSD controller 242 detects the holding voltage V for each storage cell within the target page and compares it with the determined reference voltage V. ref The comparison determines the value corresponding to the detected holding voltage V, and converts it into data representing the value determined for each memory cell. The SSD controller 242 outputs the converted data as read target data to the host system 10 as a response to a read command. Then, the process ends. Figure 12 The processing.

[0082] exist Figure 11 In the process, the SSD controller 242 may also include error detection codes generated using a predetermined error detection method to store write object data in write object pages.

[0083] In this case, Figure 12 During processing, the SSD controller 242 can also use the error detection method to determine whether there are errors in the data obtained based on the holding voltage V of each storage cell within the read target page. If no errors are detected, the read is considered successful, and the process ends. Figure 12 The processing. If an error is detected, the SSD controller 242 may also determine that the read operation has failed and repeat the following processes (i) and (ii) until an error is detected, or until the number of repetitions reaches a predetermined limit. If the error is not cleared even after the number of repetitions reaches the limit, the SSD controller 242 determines that the data is unreadable and notifies the host system 10 of this situation. (i) Set the reference voltage V ref (ii) Reduce the predetermined adjustment amount. (ii) For the reference voltage V after adjusting the holding voltage V of each memory cell within the read target page. ref The data obtained through conversion is then checked for errors. Even in this case, according to this embodiment, the initial reference voltage V can be adjusted based on the elapsed time since the writing time. ref Therefore, the number of repetitions or the risk of read failure until successful is reduced.

[0084] also, Figure 11 , Figure 12 This processing assumes the use of SLC as the storage unit, but is not limited to it. It can also be applied to storage methods capable of recording multi-bit values. This storage method can also be applied to MLC, TLC, QLC, and other methods capable of recording multi-bit values. In this case, when reading data, the SSD controller 242 can adjust the reference voltage V at each stage based on the elapsed time since the write operation. ref,n Using the adjusted reference voltage V ref,n The value represented by the holding voltage V detected from the storage cell can then be determined.

[0085] Furthermore, in the above example, the case where the SSD24 is built into the information processing device 1 is taken as an example, but it is not limited to this. As long as the SSD24 can be connected to the information processing device 1 in a way that can send and receive various types of data, it can also be configured as a storage device separate from the information processing device 1.

[0086] As described above, the solid-state memory (e.g., SSD 24) according to this embodiment includes: a plurality of storage units (e.g., pages); and a controller (e.g., SSD controller 242) that controls the writing and reading of data for each storage unit. Each storage unit includes a plurality of storage cells, and each storage cell maintains a voltage corresponding to a value that is an element of data. When reading data from a storage cell, the controller sets a reference voltage corresponding to the value based on the elapsed time since the time of writing data to the storage cell, and uses the set reference voltage to determine the value represented by the voltage maintained in the storage cell (e.g., holding voltage).

[0087] The controller can also set the reference voltage in such a way that it decreases as time goes on.

[0088] According to this structure, a reference voltage is determined based on the elapsed time from the write time to the read time. Taking into account the voltage variation characteristics of the storage cell over time, this voltage is converted into a value constituting the data. Therefore, data written to the solid-state memory can be reliably read regardless of the elapsed time since the write time. Furthermore, read time can be reduced by avoiding or suppressing rereads that involve adjustments to the reference voltage.

[0089] In addition, the controller can also record the moment when writing data to the storage unit as the write time.

[0090] Alternatively, the controller can refer to a pre-set reference table that represents the reference voltage based on each elapsed time from the write time to the memory cell in the read target page to determine the reference voltage.

[0091] Additionally, when an error is detected based on data read from a storage unit, the controller can lower the reference voltage and use the lowered reference voltage to determine the value represented by the voltage of the storage cell held within the page being read.

[0092] Alternatively, the information processing apparatus 1 described in this embodiment may also include a host system 10 and the aforementioned SSD 24, and the controller determines the write time based on the time notified by the host system 10 when writing write object data.

[0093] Alternatively, this embodiment can also be a data processing method for a solid-state memory, which includes: a plurality of storage units; and a controller that controls the writing and reading of data for each storage unit. Each storage unit has a plurality of storage cells, and each storage cell holds a voltage representing a value that is an element of data. The controller sets a reference voltage corresponding to the value based on the elapsed time since the time from the moment data is written to the storage unit, and uses the set reference voltage to determine the value represented by the voltage held in the storage cell (e.g., a holding voltage).

[0094] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the specific structure is not limited to the embodiments described above, and also includes designs that do not depart from the spirit of the present invention. The structures described in the above embodiments can be combined arbitrarily.

Claims

1. A solid-state memory, comprising: Multiple storage units; and The controller controls the writing and reading of data according to each of the aforementioned storage units. The aforementioned storage units each have multiple storage cells. The aforementioned storage units each maintain a voltage corresponding to the value of the element that constitutes the aforementioned data. When the controller reads data from the storage unit, The reference voltage is set based on the elapsed time since the moment the data was written to the storage unit, wherein, The reference voltage mentioned above is used to define the voltage corresponding to the above value. The reference voltage is used to determine the value represented by the voltage held in the memory cell.

2. The solid-state memory according to claim 1, wherein, The controller sets the reference voltage in such a way that the longer the time elapsed, the lower the voltage becomes.

3. The solid-state memory according to claim 1, wherein, When the controller writes data to the storage unit, it records the moment when the data is written as the write time.

4. The solid-state memory according to claim 1, wherein, The controller determines the reference voltage corresponding to the elapsed time by referring to a pre-set reference table, wherein the reference table represents the reference voltage reference value according to each elapsed time from the writing time.

5. The solid-state memory according to claim 1, wherein, When the controller detects an error based on the data read from the storage unit, it lowers the reference voltage and uses the lowered reference voltage to determine the value represented by the voltage held in the storage unit.

6. An information processing device, comprising: Host system; and The solid-state memory according to claim 1, When writing the data, the controller determines the writing time based on the time of notification from the host system.

7. A data processing method, specifically a data processing method for solid-state storage, wherein, The aforementioned solid-state memory includes multiple storage units and a controller. The controller controls the writing and reading of data for each storage unit. Each storage unit includes multiple storage cells, and each storage cell holds a voltage representing a value that is an element of the data. When the controller reads data from the storage unit, it sets a reference voltage based on the elapsed time since the time it wrote the data to the storage unit. This reference voltage is used to define the voltage corresponding to the specified value. The reference voltage is used to determine the value represented by the voltage held in the memory cell.

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