Non-volatile memory device including sub-planes

Abstract

A memory device includes first and second sub-planes, first and second page buffers, data input / output circuitry, and first and second page buffer drivers. The first sub-plane includes memory cells connected to first bit lines. The second sub-plane includes memory cells connected to second bit lines. The first page buffer driver provides data from the first page buffer to the data input / output circuitry. The second page buffer driver provides data from the second page buffer to the data input / output circuitry. A subset of the first bit lines are connected to a subset of the first page buffer, the remaining first bit lines are connected to a subset of the second page buffer, a subset of the second bit lines are connected to the remaining first page buffer, and the remaining second bit lines are connected to the remaining second page buffer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0050422, filed on April 17, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a non-volatile memory device, and more specifically, to a non-volatile memory device comprising a plurality of sub-planes. Background Technology

[0004] In response to the demand for high-capacity and small-sized non-volatile memory devices, a three-dimensional non-volatile memory device in which the memory cell array and peripheral circuitry are arranged vertically has been developed. As the computational load in electronic devices, including those with embedded non-volatile memory devices, increases, the need to reduce the power consumption of non-volatile memory devices is growing. Furthermore, as the computational speed of electronic devices increases, the need to enhance the data input / output speed of non-volatile memory devices is also increasing. Summary of the Invention

[0005] One or more embodiments provide a memory device capable of maintaining input / output performance regardless of the size of the data read.

[0006] In addition, one or more embodiments provide a memory device capable of performing low-power read operations based on the size of the data being read.

[0007] In one or more embodiments of this disclosure, a memory device may include: a first subplane including a plurality of memory cells connected to a plurality of first bit lines; a second subplane including a plurality of memory cells connected to a plurality of second bit lines; a first page buffer and a second page buffer, each configured to sense data from the memory cells via a corresponding bit line; a data input / output circuit configured to transmit data via a plurality of data pins; a first page buffer driver configured to provide data from the first page buffer to the data input / output circuit; and a second page buffer driver configured to provide data from the second page buffer to the data input / output circuit, wherein a first subset of the plurality of first bit lines may be connected to a first subset of the first page buffer, a second subset of the plurality of first bit lines may be connected to a first subset of the second page buffer, a first subset of the plurality of second bit lines may be connected to a second subset of the first page buffer, and a second subset of the plurality of second bit lines may be connected to a second subset of the second page buffer.

[0008] In one or more embodiments of this disclosure, a memory device may include: a first subplane including a plurality of memory cells; a second subplane including a plurality of memory cells; a first bit line group including a plurality of first bit lines, which can be connected to the first subplane, extend in a first horizontal direction, and can be arranged in a second horizontal direction perpendicular to the first horizontal direction; and a second bit line group including a plurality of second bit lines, which can be connected to the second subplane, extend in the first horizontal direction, and can be arranged in the second horizontal direction, the second bit line group being connected to a bit line cut region. The region is separated from the first bit line group in a first horizontal direction; the first extension line group includes a plurality of first extension lines that can be connected to a first subset of a plurality of second bit lines and extends from a region that vertically overlaps with the first subset of the plurality of second bit lines across the bit line cut region to a region that vertically overlaps with the first subset of the plurality of first bit lines; the second extension line group includes a plurality of second extension lines that can be connected to a second subset of the plurality of first bit lines and extends from a region that vertically overlaps with the second subset of the plurality of first bit lines across the bit line cut region to a region that vertically overlaps with the second subset of the plurality of second bit lines; and a page buffer circuit including a page buffer connected to the first bit line group and the second bit line group via the first extension line group and the second extension line group.

[0009] In one or more embodiments of this disclosure, a memory device may include: a plurality of subplanes connected to a plurality of bit line groups including a first bit line group and a second bit line group, each of the first bit line group and the second bit line group including a plurality of bit lines; a plurality of page buffer groups including a first page buffer group and a second page buffer group, each of the first page buffer group and the second page buffer group including a plurality of page buffers respectively configured to sense data via a corresponding bit line; data input / output circuitry configured to transmit data via a plurality of data pins; and a plurality of page buffer drivers each configured to provide data sensed by the plurality of page buffer groups to the data input / output circuitry, wherein a first number of first bit lines included in the first bit line group may be connected to a first number of first page buffers included in the first page buffer group, a second number of first bit lines included in the first bit line group may be connected to a second number of second page buffers included in the second page buffer group, a third number of second bit lines included in the second bit line group may be connected to a third number of first page buffers included in the first page buffer group, and a fourth number of second bit lines included in the second bit line group may be connected to a fourth number of second page buffers included in the second page buffer group.

[0010] According to one aspect of the present invention, a memory device is provided, comprising a first subplane, a second subplane, a first page buffer, a second page buffer, data input / output circuitry, a first page buffer driver, and a second page buffer driver. The first subplane includes a plurality of memory cells connected to a plurality of first bit lines. The second subplane includes a plurality of memory cells connected to a plurality of second bit lines. The first page buffer and the second page buffer are each configured to sense data from the memory cells via corresponding bit lines. The data input / output circuitry is configured to transmit data via a plurality of data pins. The first page buffer driver is configured to provide data from the first page buffer to the data input / output circuitry. The second page buffer driver is configured to provide data from the second page buffer to the data input / output circuitry. A subset of the plurality of first bit lines is connected to a subset of the first page buffer, the remainder of the plurality of first bit lines is connected to a subset of the second page buffer, a subset of the plurality of second bit lines is connected to the remainder of the first page buffer, and the remainder of the plurality of second bit lines is connected to the remainder of the second page buffer.

[0011] According to another aspect of the present invention, a memory device is provided, including a first subplane, a second subplane, a first bit line group, a second bit line group, a first extension line group, a second extension line group, and a page buffer circuit. The first subplane includes a plurality of memory cells. The second subplane includes a plurality of memory cells. The first bit line group includes a plurality of first bit lines connected to the first subplane, extending in a first horizontal direction and arranged in a second horizontal direction perpendicular to the first horizontal direction. The second bit line group includes a plurality of second bit lines connected to the second subplane, extending in the first horizontal direction and arranged in the second horizontal direction, the second bit line group being separated from the first bit line group in the first horizontal direction by a bit line cut-off region. The first extension line group includes a plurality of first extension lines connected to a subset of the plurality of second bit lines and extending from a region perpendicularly overlapping the subset of the plurality of second bit lines across the bit line cut-off region to a region perpendicularly overlapping the subset of the plurality of first bit lines. The second extension line group includes a plurality of second extension lines connected to the remainder of the plurality of first bit lines and extending from a region perpendicularly overlapping the remainder of the plurality of first bit lines across the bit line cut-off region to a region perpendicularly overlapping the remainder of the plurality of second bit lines. The page buffer circuit includes a page buffer connected to the first bit line group and the second bit line group via a first extension line group and a second extension line group.

[0012] According to another aspect of the present invention, a memory device is provided, comprising a plurality of subplanes, a plurality of page buffer groups, data input / output circuitry, and a plurality of page buffer drivers. The plurality of subplanes are connected to a plurality of bit line groups, each comprising a plurality of bit lines. Each of the plurality of page buffer groups includes a plurality of page buffers, each page buffer being configured to sense data via a corresponding bit line. The data input / output circuitry is configured to transmit data via a plurality of data pins. Each of the plurality of page buffer drivers is configured to provide data sensed by the plurality of page buffer groups to the data input / output circuitry. A first number of first lines in a first bit line group are connected to a first number of first page buffers in a first page buffer group; a second number of first lines in a first bit line group are connected to a second number of second page buffers in a second page buffer group; a third number of second bit lines in a second bit line group are connected to a third number of first page buffers in a first page buffer group; and a fourth number of second bit lines in a second bit line group are connected to a fourth number of second page buffers in a second page buffer group.

[0013] Additionally, a third number of second bit lines are connected to a second line that extends in the second wiring layer from an area that vertically overlaps with the second page buffer to an area that vertically overlaps with the third number of first page buffers. Attached Figure Description

[0014] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 This is an example block diagram illustrating a memory device according to an embodiment;

[0016] Figure 2 This is an example block diagram illustrating a memory device according to a comparison example;

[0017] Figure 3 This is a circuit diagram showing a memory block according to an embodiment;

[0018] Figure 4 This is a view schematically illustrating the structure of a memory device according to an embodiment;

[0019] Figure 5 This is a view schematically illustrating the structure of a memory device according to an embodiment;

[0020] Figure 6 This is a view schematically illustrating the structure of a memory device according to an embodiment;

[0021] Figure 7This is an example view illustrating the connection between the first subplane and the page buffer circuit according to an embodiment;

[0022] Figure 8 This is a view illustrating the page buffer according to an embodiment;

[0023] Figure 9 This is a circuit diagram showing a cache unit according to an embodiment;

[0024] Figure 10 This is a block diagram illustrating the page buffer circuit and data input / output circuit according to an embodiment;

[0025] Figure 11 This is a plan view showing a memory device according to an embodiment;

[0026] Figures 12A to 12D This is a cross-sectional view of a memory device according to an embodiment;

[0027] Figures 13A to 13D This is a cross-sectional view of a memory device according to an embodiment;

[0028] Figure 14A and Figure 14B This is a layout illustrating the arrangement of bit lines and extension lines according to an embodiment;

[0029] Figures 15A to 15C This is a layout illustrating the arrangement of bit lines and extension lines according to an embodiment;

[0030] Figure 16A and Figure 16B This is a layout illustrating the arrangement of bit lines and extension lines according to an embodiment;

[0031] Figure 17 This is a plan view showing a memory device according to an embodiment;

[0032] Figure 18A and Figure 18B This is a cross-sectional view showing a memory device according to an embodiment;

[0033] Figure 19 This is a view illustrating a memory device according to an embodiment; and

[0034] Figure 20 This is a view illustrating a solid-state drive (SSD) including a memory device according to an embodiment. Detailed Implementation

[0035] The exemplary embodiments are described in more detail below with reference to the accompanying drawings.

[0036] In the following description, the same reference numerals are used for the same elements, even in different figures. Matters defined in the description, such as detailed constructions and elements, are provided to aid in a comprehensive understanding of the exemplary embodiments. However, it will be apparent that the exemplary embodiments can be practiced without those specifically defined matters. Furthermore, well-known functions or structures are not described in detail, as they would be obscured by unnecessary detail.

[0037] In this specification, the X-axis direction may be referred to as the first horizontal direction, the Y-axis direction as the second horizontal direction, and the Z-axis direction as the vertical direction. However, the inventive concept is not limited to these; for example, the Y-axis direction may also be referred to as the first horizontal direction and the X-axis direction may also be referred to as the second horizontal direction.

[0038] The term "embodiment" is intended to cover one or more embodiments, rather than being limited to a single example. Furthermore, the features described in the embodiments may be combined and implemented together.

[0039] Figure 1 This is an example block diagram illustrating a memory device 10 according to an embodiment. Figure 2 This is an example block diagram illustrating a memory device 10' according to a comparison example.

[0040] Reference Figure 1 The memory device 10 may include a memory cell array 100 and peripheral circuitry 200. The peripheral circuitry 200 may include a page buffer circuit 210, control logic circuitry 220, a voltage generator 230, a row decoder 240, and data input / output circuitry 250. The memory device 10 may also include a column decoder, a pre-decoder, a temperature sensor, a command decoder, and an address decoder. The memory device 10 may refer to a "non-volatile memory device".

[0041] The memory cell array 100 may include multiple subplanes, including a first subplane 110 and a second subplane 120. According to embodiments, the memory cell array 100 may include at least one plane or memory plane, and each plane may include multiple subplanes. In this specification, the memory cell array 100 is described as including two subplanes, but the inventive concept is not limited thereto. For example, the memory cell array 100 may include three or more subplanes. A plane may refer to a larger logical or physical partition within the memory cell array and may, for example, support 16KB page read operations. A subplane may represent a smaller partition of the plane, each partition capable of independently supporting a smaller page size, for example, 8KB per subplane. Therefore, a single 16KB page in a plane may consist of two 8KB pages from two subplanes. However, the inventive concept is not limited thereto.

[0042] The first subplane 110 and the second subplane 120 can be in the second horizontal direction (e.g., Figure 5 They are adjacent to each other along the Y-axis. The first subplane 110 and the second subplane 120 may each include multiple memory blocks, and each memory block may include multiple memory cells. See below for reference. Figure 3 This is described below. The first subplane 110 can be connected to the page buffer circuit 210 via bit lines BL11, BL12, BL13, and BL14, and can be connected to the line decoder 240 via the serial select line SSL_1, the word line WL_1, and the ground select line GSL_1. The bit lines BL11, BL12, BL13, and BL14 connected to the first subplane 110 can be referred to as the first bit line group. The second subplane 120 can be connected to the page buffer circuit 210 via bit lines BL21, BL22, BL23, and BL24, and can be connected to the line decoder 240 via the serial select line SSL_2, the word line WL_2, and the ground select line GSL_2. The bit lines BL21, BL22, BL23, and BL24 connected to the second subplane 120 can be referred to as the second bit line group. The first subplane 110 and the second subplane 120 can be controlled independently of each other. For example, programming, reading, and erasing operations on the first subplane 110 can be controlled independently of programming, reading, and erasing operations on the second subplane 120. The memory cells included in the memory cell array 100 can be flash memory cells. Hereinafter, embodiments will be described by way of example where the memory cells are NAND flash memory cells. However, the inventive concept is not limited thereto, and in some embodiments, the memory cells can be resistive memory cells, such as resistive random access memory (ReRAM) cells, phase-change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0043] In an embodiment, the memory cell array 100 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each of the NAND strings may include memory cells respectively connected to word lines vertically stacked on a substrate. (See below for further details.) Figure 3 This will be described.

[0044] Page buffer circuit 210 may include multiple page buffers PB11 to PB14 and PB21 to PB24, and page buffers PB11 to PB14 and PB21 to PB24 may each be connected to a memory cell via bit lines BL11 to BL14 and BL21 to BL24. Page buffers PB11 to PB14 may be referred to as the first page buffer group, and page buffers PB21 to PB24 as the second page buffer group. Although page buffer circuit 210 is shown as including eight page buffers, with four page buffers included in the first page buffer group and four page buffers included in the second page buffer group, the inventive concept is not limited thereto.

[0045] Page buffer circuit 210 can select at least one of bit lines BL11 to BL14 and BL21 to BL24 in response to column address Y-ADDR. Page buffer circuit 210 can operate as a write driver or a sense amplifier depending on the operating mode. For example, during a programming operation, page buffer circuit 210 can apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer circuit 210 can detect the current or voltage of the selected bit line to sense the data stored in the memory cell.

[0046] Page buffer circuit 210 may include page buffer drivers PBDRV1 and PBDRV2. Page buffer drivers PBDRV1 and PBDRV2 can operate as sense amplifiers during read or verification operations. Furthermore, page buffer drivers PBDRV1 and PBDRV2 can operate as write drivers during programming operations. (See below for reference.) Figure 10 Example structures of page buffer drivers PBDRV1 and PBDRV2 are described, but the structures of page buffer drivers PBDRV1 and PBDRV2 are not limited thereto. Page buffer driver PBDRV1 can provide data DATA received from data input / output circuit 250 to a first page buffer group, or provide data DATA received from the first page buffer group to data input / output circuit 250. Page buffer driver PBDRV2 can provide data DATA received from data input / output circuit 250 to a second page buffer group, or provide data DATA received from the second page buffer group to data input / output circuit 250. Although two page buffer drivers are shown, the inventive concept is not limited thereto.

[0047] The control logic circuit 220 can globally control various operations within the memory device 10. Based on the command CMD, address ADDR, and control signal CTRL, the control logic circuit 220 can output various control signals, such as row address X_ADDR, column address Y_ADDR, and voltage control signal CTRL_vol, to program data into the memory cell array 100, read data from the memory cell array 100, or erase data stored in the memory cell array 100. The row address X_ADDR can be provided to the row decoder 240, the column address Y_ADDR can be provided to the page buffer circuit 210, and the voltage control signal CTRL_vol can be provided to the voltage generator 230.

[0048] Voltage generator 230 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 230 can generate programming voltage, reading voltage, programming verification voltage, or erasing voltage as word line voltage VWL. Voltage generator 230 can provide word line voltage VWL to line decoder 240.

[0049] The row decoder 240 can select at least one memory block included in the first subplane 110 and the second subplane 120 in response to the row address X-ADDR. The row decoder 240 can select one of a plurality of word lines WL in the selected at least one memory block, and can select at least one of a plurality of string selection lines SSL_1 and SSL_2. For example, during a programming operation, the row decoder 240 can apply a programming voltage and a programming verification voltage to the selected word line, and during a read operation, the row decoder 240 can apply a read voltage to the selected word line.

[0050] Data input / output circuit 250 can receive data DATA from page buffer drivers PBDRV1 and PBDRV2, or can supply data DATA to page buffer drivers PBDRV1 and PBDRV2. Data input / output circuit 250 can send data to or receive data from external devices (e.g., memory controllers) via the DQ pin.

[0051] Reference Figure 1Some (or subsets) of the bit lines included in the first line group (such as bit lines BL11 and BL12) can be connected to some (or subsets) of the page buffers included in the first page buffer group (such as page buffers PB11 and PB13), and the remaining bit lines included in the first line group (such as bit lines BL13 and BL14) can be connected to some (or subsets) of the page buffers included in the second page buffer group (such as page buffers PB21 and PB23). That is, a first number of bit lines included in the first line group (such as bit lines BL11 and BL12) can be connected to a first number of page buffers included in the first page buffer group (such as page buffers PB11 and PB13), and a second number of bit lines included in the first line group (such as bit lines BL13 and BL14) can be connected to a second number of page buffers included in the second page buffer group (such as page buffers PB21 and PB23).

[0052] Some (or subsets) of the bit lines included in the second bit line group (such as bit lines BL21 and BL22) can be connected to the remaining page buffers included in the first page buffer group (such as page buffers PB12 and PB14), and the remaining bit lines included in the second bit line group (such as bit lines BL23 and BL24) can be connected to the remaining page buffers included in the second page buffer group (such as page buffers PB22 and PB24). That is, a third number of bit lines included in the second bit line group (such as bit lines BL21 and BL22) can be connected to a third number of page buffers included in the first page buffer group (such as page buffers PB12 and PB14), and a fourth number of bit lines included in the second bit line group (such as bit lines BL23 and BL24) can be connected to a fourth number of page buffers included in the second page buffer group (such as page buffers PB22 and PB24).

[0053] In some embodiments, during a 16-KB read operation, both the first subplane 110 and the second subplane 120 can be sensed. For example, some page buffers, such as page buffers PB11 and PB13 included in the first page buffer group and some page buffers, such as page buffers PB21 and PB23 included in the second page buffer group, can sense 8KB of data from the first subplane 110 via bit lines BL11 to BL14 of the first bit line group. Furthermore, the remaining page buffers, such as page buffers PB12 and PB14 included in the first page buffer group and the remaining page buffers, such as page buffers PB22 and PB24 included in the second page buffer group, can sense 8KB of data from the second subplane 120 via bit lines BL21 to BL24 of the second bit line group. The page buffer driver PBDRV1 can receive the data sensed by the page buffers PB11 to PB14 of the first page buffer group and can provide the received data to the data input / output circuitry 250. For example, page buffer driver PBDRV1 can receive 4KB of data from the first subplane 110 via some page buffers such as page buffers PB11 and PB13, and from the second subplane 120 via the remaining page buffers such as page buffers PB12 and PB14. Page buffer driver PBDRV2 can receive data sensed by page buffers PB21 to PB24 of the second page buffer group, and can provide the received data to the data input / output circuitry 250. For example, page buffer driver PBDRV2 can receive 4KB of data from the first subplane 110 via some page buffers such as page buffers PB21 and PB23, and from the second subplane 120 via the remaining page buffers such as page buffers PB22 and PB24. That is, both page buffer drivers PBDRV1 and PBDRV2 can be used during a 16-KB read operation.

[0054] In some embodiments, during an 8-KB read operation, only one of the first subplane 110 and the second subplane 120 may be sensed. For example, only the first subplane 110 may be sensed. For example, some page buffers, such as page buffers PB11 and PB13 included in the first page buffer group and some page buffers, such as page buffers PB21 and PB23 included in the second page buffer group, may sense 8KB of data from the first subplane 110 via bit lines BL11 to BL14 of the first bit line group. Page buffer driver PBDRV1 may receive data sensed by some page buffers (such as page buffers PB11 and PB13) included in the first page buffer group and may provide the received data to the data input / output circuitry 250. For example, page buffer driver PBDRV1 may receive 4KB of data from the first subplane 110 from some page buffers, such as page buffers PB11 and PB13. Page buffer driver PBDRV2 may receive data sensed by some page buffers (such as page buffers PB21 and PB23) included in the second page buffer group and may provide the received data to the data input / output circuitry 250. For example, page buffer driver PBDRV2 can receive 4KB of data from the first subplane 110 from some page buffers such as page buffers PB21 and PB23. That is, both page buffer drivers PBDRV1 and PBDRV2 can be used during an 8-KB read operation.

[0055] In some embodiments, during a 4-KB read operation, only one of the first subplane 110 and the second subplane 120 may be sensed. For example, only the first subplane 110 may be sensed. For example, page buffer PB11 of the first page buffer group and page buffer PB21 of the second page buffer group may sense 4KB of data from the first subplane 110 via bit lines BL11 and BL13 of the first bit line group. Page buffer driver PBDRV1 may receive the data sensed by page buffer PB11 of the first page buffer group and may provide the received data to the data input / output circuitry 250. For example, page buffer driver PBDRV1 may receive 2KB of data from the first subplane 110 from page buffer PB11. Page buffer driver PBDRV2 may receive the data sensed by page buffer PB21 of the second page buffer group and may provide the received data to the data input / output circuitry 250. For example, page buffer driver PBDRV2 may receive 2KB of data from the first subplane 110 from page buffer PB21. That is, both page buffer drivers PBDRV1 and PBDRV2 may be used during a 4-KB read operation.

[0056] According to the embodiment, since both page buffer drivers PBDRV1 and PBDRV2 are used regardless of the size of the data being read, the input / output (IO) performance of the page buffer circuit 210 can be maintained when sending data to the data input / output circuit 250.

[0057] According to an embodiment, during a read operation for small-sized data (e.g., 8KB, 4KB, etc.), only one of the first subplane 110 and the second subplane 120 can be read. Therefore, only the word lines of the subplane to be read can be driven, and thus, power consumption can be reduced during the read operation.

[0058] Reference Figure 2 In the memory device 10' according to the comparative example, a first bit line group is connected to a first page buffer group, and a second bit line group is connected to a second page buffer group. For example, bit lines BL11 to BL14 are connected to page buffers PB11 to PB14, respectively, and bit lines BL21 to BL24 are connected to page buffers PB21 to PB24, respectively. During a 16-KB read operation on the first subplane 110 and the second subplane 120, the first page buffer group can sense 8KB of data from the first subplane 110, and the second page buffer group can sense 8KB of data from the second subplane 120. Page buffer driver PBDRV1 can receive 8KB of data from the first page buffer group and provide 8KB of data to the data input / output circuit 250. Page buffer driver PBDRV2 can receive 8KB of data from the second page buffer group and provide 8KB of data to the data input / output circuit 250. That is, both page buffer drivers PBDRV1 and PBDRV2 can be used during a 16KB read operation. However, during an 8-KB read operation on the first subplane 110, only the first page buffer group performs sensing, and 8KB of data is provided to the data input / output circuitry 250 via the page buffer driver PBDRV1. Therefore, the IO performance in an 8-KB read operation may be lower than that in a 16-KB read operation.

[0059] Figure 3 This is a circuit diagram showing the memory block BLK according to an embodiment.

[0060] Reference Figure 3 The memory block BLK can correspond to the memory block included in the memory block BLK. Figure 1One of the memory blocks in the first subplane 110 and the second subplane 120 shown. The memory block BLK includes NAND strings NS11 to NS33, and each of the NAND strings NS11 to NS33 (e.g., NAND string NS11) may include a string select transistor SST, a plurality of memory cells MC connected in series with each other, and a ground select transistor GST. The string select transistor, memory cell MC, and ground select transistor GST included in each of the NAND strings NS11 to NS33 may be formed in a structure stacked vertically on a substrate.

[0061] The first line BL1 to the third line BL3 can be in the second horizontal direction (e.g., Figure 5 The word lines WL1 to WL8 extend along the Y-axis direction, and can extend in the first horizontal direction (e.g., Figure 5 The NAND strings NS11, NS21, and NS31 can be provided between the first bit line BL1 and the common source line CSL. NAND strings NS12, NS22, and NS32 can be provided between the second bit line BL2 and the common source line CSL. NAND strings NS13, NS23, and NS33 can be provided between the third bit line BL3 and the common source line CSL. For example, the first bit line BL1 to the third bit line BL3 can correspond to... Figure 1 The bit lines BL11 to BL14 shown may correspond to Figure 1 Bit lines BL21 to BL24 are shown.

[0062] The string select transistor SST can be connected to the corresponding string select lines SSL1 to SSL3. Each memory cell MC can be connected to the corresponding word line among word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1 to GSL3. The string select transistor SST can be connected to the corresponding bit line, and the ground select transistor GST can be connected to the common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines can vary according to the embodiment.

[0063] Figure 4 This is a schematic view illustrating the structure of the memory device 40 according to an embodiment.

[0064] Reference Figure 4 The memory device 40 may include a memory cell region 41 and a peripheral circuit region 42, and may correspond to Figure 1The illustrated memory device 10 is an example of an implementation. Memory cell region 41 may be formed on a first die and is therefore referred to as a memory chip or a first semiconductor chip. Peripheral circuitry region 42 may be formed on a second die and is therefore referred to as a peripheral circuitry chip or a second semiconductor chip. In an embodiment, memory cell region 41 and peripheral circuitry region 42 may be bonded together in a vertical direction (e.g., the Z-axis direction). Therefore, memory device 40 may be referred to as a bonded vertical NAND (B-VNAND) memory device, or a memory device having a chip-to-chip (C2C) bonding structure.

[0065] In an embodiment, the memory cell region 41 may include a first memory cell array MCA1 to a fourth memory cell array MCA4. For example, one of the first memory cell array MCA1 to the fourth memory cell array MCA4 may correspond to... Figure 1 The memory cell array 100 is shown. In this case, each of the first memory cell arrays MCA1 to the fourth memory cell arrays MCA4 can be referred to as a memory plane or memory array tile (MAT), and therefore, the memory cell region 41 can have a 4-MAT structure. The peripheral circuit region 42 can include first peripheral circuits PECT1 to fourth peripheral circuits PECT4 respectively corresponding to the first memory cell arrays MCA1 to the fourth memory cell arrays MCA4. For example, one of the first peripheral circuits PECT1 to the fourth peripheral circuits PECT4 can correspond to... Figure 1 The peripheral circuit 200 is shown. Additionally, the peripheral circuit region 42 may also include an external pad bonding region PA in which multiple pads PD are arranged.

[0066] Each of the first memory cell arrays MCA1 to the fourth memory cell arrays MCA4 may include multiple subplanes arranged in a first horizontal direction (X-axis direction) and / or a second horizontal direction (Y-axis direction).

[0067] Figure 5 This is a schematic view illustrating the structure of the memory device 50 according to an embodiment.

[0068] Reference Figure 5 The memory device 50 may include a memory cell region 51 and a peripheral circuit region 52, and may correspond to Figure 1 An implementation example of the memory device 10 shown. For example, Figure 1 The memory cell array 100 shown can be disposed in the memory cell region 51, and Figure 1 The peripheral circuit 200 shown can be set in the peripheral circuit area 52.

[0069] Memory cell region 51 may include a first sub-plane region 110a and a second sub-plane region 120a. The first sub-plane may be disposed in the first sub-plane region 110a, and the second sub-plane may be disposed in the second sub-plane region 120a. The first sub-plane may be connected to bit line BL1 and word line WL1, and the second sub-plane may be connected to bit line BL2 and word line WL2. Each of bit lines BL1 and BL2 may extend in a second horizontal direction. Bit lines BL1 and BL2 may be arranged separately from each other in the second horizontal direction. Each of word lines WL1 and WL2 may extend in a first horizontal direction. Memory device 50 is described as including a memory cell array comprising two sub-planes, but the number of memory cell arrays and the number of sub-planes included in memory device 50 are not limited thereto.

[0070] The peripheral circuit area 52 may include line decoder areas 241, 242, 243 and 244 and circuit areas 261 and 262. Figure 1 The line decoder 240 shown can be distributed in line decoder regions 241 and 244. For example, the line decoder portions connected to the first subplane can be arranged in line decoder regions 241 and 242, and the line decoder portions connected to the second subplane can be arranged in line decoder regions 243 and 244. Line decoder regions 241 and 242 can vertically overlap with the first subplane region 110a, and line decoder regions 243 and 244 can vertically overlap with the second subplane region 120a. Although the two line decoder regions are shown arranged for each subplane, the inventive concept is not limited thereto.

[0071] In addition to line decoder 240 Figure 1 The components of the peripheral circuit 200 shown can be arranged in circuit regions 261 and 262. For example, Figure 1 The page buffers PB11 to PB14 and the page buffer driver PBDRV1 included in the first page buffer group shown can be arranged in circuit region 261, and Figure 1 The page buffers PB21 to PB24 and the page buffer driver PBDRV2 included in the second page buffer group shown can be arranged in circuit region 262. Circuit region 261 can be perpendicularly overlapped with the first sub-plane region 110a, and circuit region 262 can be perpendicularly overlapped with the second sub-plane region 120a.

[0072] Figure 6 This is a schematic view illustrating the structure of a memory device 60 according to an embodiment.

[0073] Reference Figure 6The memory device 60 may include a memory cell region 61 and a peripheral circuit region 62, and may correspond to Figure 1 An example implementation of the memory device 10 shown.

[0074] Reference Figure 6 NAND strings NS11 and NS12 can be arranged in the first sub-plane region 110a, and NAND strings NS21 and NS22 can be arranged in the second sub-plane region 120a. NAND string NS11 can be connected to bit line BL11, NAND string NS12 can be connected to bit line BL12, NAND string NS21 can be connected to bit line BL21, and NAND string NS22 can be connected to bit line BL22. Figure 6 The bit lines BL11 and BL12 can correspond to Figure 1 The bit lines BL11 and BL13, and Figure 6 The bit lines BL21 and BL22 can correspond to Figure 1 The bit lines BL21 and BL23 are used, but the embodiments are not limited to these.

[0075] Page buffers PB11 and PB12 of the first page buffer group and the first page buffer driver PBDRV1 can be arranged in circuit area 261, and page buffers PB21 and PB22 of the second page buffer group and the second page buffer driver PBDRV2 can be arranged in circuit area 262.

[0076] Bit lines BL11, BL12, BL21, and BL22 can be formed in the first wiring layer M1. Bit lines BL11 and BL12, included in the first bit line group, can extend in the second horizontal direction and can be separated from each other in the first horizontal direction. Bit lines BL21 and BL22, included in the second bit line group, can extend in the second horizontal direction and can be separated from each other in the first horizontal direction. The first bit line group and the second bit line group can be arranged separately from each other in the second horizontal direction.

[0077] Bit line BL11 can be connected to page buffer PB11 disposed in circuit region 261. For example, bit line BL11 can be connected to page buffer PB11 via vertical extension structure 63. Bit line BL12 can be connected to page buffer PB21 disposed in circuit region 262. For example, bit line BL12 can be connected to page buffer PB21 via first extension line L1 and vertical extension structure 64, the first extension line L1 extending in the second horizontal direction in the second wiring layer M2. The first extension line L1 can extend to a position overlapping with the second sub-plane region 120a. Bit line BL21 can be connected to page buffer PB12 disposed in circuit region 261. For example, bit line BL21 can be connected to page buffer PB12 via second extension line L2 and vertical extension structure 65, the second extension line L2 extending in the second horizontal direction in the second wiring layer M2. The second extension line L2 can extend to a position overlapping with the first sub-plane region 110a. Bit line BL22 can be connected to page buffer PB22 disposed in circuit region 262. For example, bit line BL22 can be connected to page buffer PB22 via vertical extension structure 66.

[0078] The memory cell region 61 can be flipped and then attached to the peripheral circuit region 62. That is, when the memory cell region 61 is manufactured in a non-flipped state, the first wiring layer M1 can be formed below the second wiring layer M2, and after the manufacture of the memory cell region 61 is completed, the memory cell region 61 can be flipped and attached to the peripheral circuit region 62. That is, although... Figure 6 The first wiring layer M1 is shown relative to the second wiring layer M2 in the +Z axis direction, but the second wiring layer M2 may be formed above the first wiring layer M1 during the formation of the memory cell region 61. Based on the non-flipped state of the memory cell region 61, the upper side may indicate the +Z axis direction, and the lower side may indicate the -Z axis direction.

[0079] During a read operation, the first page buffer driver PBDRV1 can receive data stored in NAND strings NS11 and NS21 via page buffers PB11 and PB12. That is, the first page buffer driver PBDRV1 can receive data stored in both sub-planes. The second page buffer driver PBDRV2 can receive data stored in NAND strings NS12 and NS22 via page buffers PB21 and PB22. That is, the second page buffer driver PBDRV2 can receive data stored in both sub-planes.

[0080] Figure 7 This is an example view showing the connection between the first subplane 110 and the page buffer circuit 210 according to an embodiment.

[0081] Reference Figure 7 The first subplane 110 may include a first NAND string NS11 to an Nth NAND string NS1n. Each of the first NAND string NS11 to the Nth NAND string NS1n may include a ground select transistor GST connected to a ground select line GSL, a plurality of memory cells MC connected to a plurality of word lines WL0 to WLm respectively, and a string select transistor SST connected to a string select line SSL. The ground select transistor GST, the memory cells MC and the string select transistor SST may be connected in series with each other. Here, m refers to a positive integer. The description of the first subplane 110 can also be applied to the second subplane 120 (see Figure 1 ).

[0082] Page buffer circuit 210 may include first page buffer unit PBU11 to nth page buffer unit PBU1n. First page buffer unit PBU11 can be connected to first NAND string NS11 via first bit line BL11, and nth page buffer unit PBU1n can be connected to nth NAND string NS1n via nth bit line BL1n. Here, n is a positive integer. For example, first page buffer unit PBU11 to nth page buffer unit PBU1n may be arranged in a row along a second horizontal direction extending from first bit line BL11 to nth bit line BL1n. First page buffer unit PBU11 to nth page buffer unit PBU1n may be included in a first page buffer group. Therefore, first page buffer unit PBU11 to nth page buffer unit PBU1n may be arranged in circuit region 261 (see...). Figure 6 ).

[0083] Page buffer circuit 210 may further include first cache latches CL11 to nth cache latches CL1n corresponding to the first page buffer unit PBU11 to the nth page buffer unit PBU1n, respectively. The first cache latches CL11 to nth cache latches CL1n may be arranged as a single line in the extension direction of the first bit line BL11 to the nth bit line BL1n. The first cache latches CL11 to nth cache latches CL1n may be included in the first page buffer group. Therefore, the first cache latches CL11 to nth cache latches CL1n may be arranged in circuit region 261 (see...). Figure 6 ).

[0084] The sensing nodes of the first page buffer unit PBU11 to the nth page buffer unit PBU1n can be jointly connected to the binding sensing node SOC. Furthermore, the first cache latch CL11 to the nth cache latch CL1n can also be jointly connected to the binding sensing node SOC. Therefore, the first page buffer unit PBU11 to the nth page buffer unit PBU1n can be connected to the first cache latch CL11 to the nth cache latch CL1n via the binding sensing node SOC.

[0085] Figure 8 This is a view showing the page buffer PB according to an embodiment.

[0086] Reference Figure 8 Page buffer PB can correspond to Figure 1 An example of one of the page buffers PB11 to PB14 and PB21 to PB24 is shown. The page buffer PB may include a page buffer unit PBU and a cache unit CU. Because the cache unit CU includes a cache latch (C-LATCH) CL connected to the data input / output lines, the cache unit CU can be adjacent to the data input / output lines. Therefore, the page buffer unit PBU and the cache unit CU can be arranged separately from each other, and the page buffer PB can have a structure in which the page buffer unit PBU and the cache unit CU are separated from each other.

[0087] Page buffer unit (PBU) may include master unit (MU). Master unit (MU) may include master transistors in page buffer (PB). Page buffer unit (PBU) may also include bit line select transistor (TR_hv) connected to bit line (BL) and driven by bit line select signal (BLSLT). Bit line select transistor (TR_hv) may be implemented as a high-voltage transistor and therefore may be located in a different well region than master unit (MU), i.e., in high-voltage unit (HVU).

[0088] The master unit MU may include a sense latch (S-LATCH) SL, a force latch (F-LATCH) FL, a higher significant bit latch (M-LATCH) ML, and a lower significant bit latch (L-LATCH) LL. In some embodiments, the S-latch SL, F-latch FL, M-latch ML, or L-latch LL may be referred to as the "master latch". The master unit MU may also include a precharge circuit PC capable of controlling precharge operations for the bit line BL or sense node SO based on the bit line clamping control signal BLCLAMP. Furthermore, the master unit MU may also include a transistor PM' driven by the bit line setup signal BLSETUP.

[0089] During read or program verification operations, the S-latch SL can store the result of sensing data stored in the memory cell or the result of sensing the threshold voltage of the memory cell. Additionally, during programming operations, the S-latch SL can be used to apply a programming bit line voltage or a programming disable voltage to the bit line BL. The F-latch FL can be used to improve the threshold voltage distribution during programming operations. For example, the F-latch FL can store force data. The force data can be initially set to "1", and then, when the threshold voltage of the memory cell enters a force region smaller than the target region, the force data can be inverted to "0". During programming execution operations, the force data can be used to control the bit line voltage and narrow the programming threshold voltage distribution.

[0090] M latches ML, L latches LL, and C latches CL can be used to store data input from external sources during programming operations and can be referred to as data latches. When programming 3 bits of data into a memory cell, the 3 bits of data can be stored in M ​​latches ML, L latches LL, and C latches CL respectively. M latches ML, L latches LL, and C latches CL can retain the stored data until the programming of the memory cell is complete. Additionally, during read operations, C latches CL can receive data read from the memory cell and sent from S latches SL, and can output the received data to the outside of the page buffer PB via the data input / output lines, for example, output to... Figure 10 The page buffer decoders shown are PBDEC11, PBDEC12, PBDEC21, or PBDEC22.

[0091] Furthermore, the main unit MU may also include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected between the sensing node SO and the S latch SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the sensing node SO and the F latch FL, and may be driven by the force monitoring signal MON_F. The third transistor NM3 may be connected between the sensing node SO and the M latch ML, and may be driven by the higher significant bit monitoring signal MON_M. The fourth transistor NM4 may be connected between the sensing node SO and the L latch LL, and may be driven by the lower significant bit monitoring signal MON_L.

[0092] Furthermore, the main unit MU may also include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor TR_hv and the sensing node SO. The fifth transistor NM5 may be driven by the bit line shutdown signal BLSHF, and the sixth transistor NM6 may be driven by the bit line connection control signal CLBLK. Additionally, the main unit MU may include a precharge transistor PM. The precharge transistor PM is connected to the sensing node SO, driven by the load signal LOAD, and precharges the sensing node SO to a precharge level during the precharge period.

[0093] In the current embodiment, the main unit MU may further include a pair of pass transistors connected to the sensing node SO, namely, a first pass transistor TR and a second pass transistor TR' connected to the sensing node SO. The first pass transistor TR can be driven based on a first pass control signal SO_PASS, and the second pass transistor TR' can be driven based on a second pass control signal SO_PASS'. For example, the first pass transistor TR can be connected between the first terminal SOC_U and the sensing node SO, and the second pass transistor TR' can be connected between the sensing node SO and the second terminal SOC_D.

[0094] For example, when the page buffer unit (PBU) corresponds to Figure 7 In the second page buffer unit PBU12 shown, the first terminal SOC_U can be connected to one end of the transfer transistor included in the first page buffer unit PBU11, and the second terminal SOC_D can be connected to one end of the transfer transistor included in the third page buffer unit PBU13. In this way, the sensing node SO can be electrically connected to the bonding sensing node SOC via the transfer transistor included in each of the second page buffer units PBU12 to the nth page buffer unit PBU1n.

[0095] During programming operations, the page buffer PB can verify whether programming has been completed in a memory cell selected from memory cells included in the NAND string connected to the bit line BL. For example, during programming verification, the page buffer PB stores data sensed via the bit line BL in the S latch SL. The M latch ML and L latch LL, where the target data is stored, can be set based on the sensed data stored in the S latch SL. For example, when the sensed data indicates that programming is complete, the M latch ML and L latch LL can be switched to a programming-disabled setting for the memory cell selected in subsequent programming cycles. The C latch CL can temporarily store input data provided from an external source. During programming operations, the target data stored in the C latch CL can be stored in the M latch ML and L latch LL.

[0096] Reference Figure 6 and Figure 8 , Figure 6 The structures 63 to 66 shown can be connected to the bit line selection transistor TR_hv included in page buffers PB11, PB12, PB21 and PB22.

[0097] Figure 9 This is a circuit diagram showing a cache unit CU according to an embodiment.

[0098] Reference Figure 8 and Figure 9 The cache unit CU may include a monitoring transistor NM7 and a C latch CL. The C latch CL may include a first inverter INV1 and a second inverter INV2, a dump transistor 132, and transistors 131, 133, 134, and 135. The monitoring transistor NM7 may be driven based on the cache monitoring signal MON_C and may control the connection between the bonding sensing node SOC and the C latch CL.

[0099] A first inverter INV1 can be connected between the first node ND1 and the second node ND2, and a second inverter INV2 can be connected between the second node ND2 and the first node ND1. The first inverter INV1 and the second inverter INV2 can form a latch. Transistor 131 may include a gate connected to the bonding sense node SOC. Dump transistor 132 can be driven by a dump signal Dump_C and can send data stored in C latch CL to a master latch, for example, to S latch SL in the page buffer unit PBU. Transistor 133 can be driven by a data signal DI, transistor 134 can be driven by a data inversion signal nDI, and transistor 135 can be driven by a write control signal DIO_W. When the write control signal DIO_W is activated, the voltage levels of the first node ND1 and the second node ND2 can be determined based on the data signal DI and the data inversion signal nDI.

[0100] The cache unit CU can be connected to the input / output terminal RDi via transistors 136 and 137. Transistor 136 may include a gate connected to the second node ND2 and can be turned on or off based on the voltage level of the second node ND2. Transistor 137 can be driven by the read control signal DIO_R. When the read control signal DIO_R is activated and transistor 137 is turned on, the voltage level of the input / output terminal RDi can be determined to be "1" or "0" based on the state of latch CL.

[0101] Figure 10 This is a block diagram illustrating the page buffer circuit 210 and the data input / output circuit 250 according to an embodiment.

[0102] Reference Figure 10 The page buffer circuit 210 may include page buffers PB11 to PB14 and PB21 to PB24, page buffer decoders PBDEC11, PBDEC12, PBDEC21 and PBDEC22, and page buffer drivers PBDRV1 and PBDRV2. Page buffers PB11 to PB14, page buffer decoders PBDEC11 and PBDEC12, and page buffer driver PBDRV1 may be arranged in... Figure 6 In the circuit region 261 shown, page buffers PB21 to PB24, page buffer decoders PBDEC21 and PBDEC22, and page buffer driver PBDRV2 can be arranged in... Figure 6 The circuit region 262 shown. The number of page buffers, page buffer decoders, and page buffer drivers included in the page buffer circuit 210 are not limited to this.

[0103] Page buffers PB11 to PB14 and PB21 to PB24 can be connected to page buffer decoders PBDEC11 to PBDEC22 via cache latches. During a read operation, data sensed from a memory cell can be stored in the cache latches, and the data stored in the cache latches can be provided to the data input / output circuitry 250 via page buffer decoders PBDEC11, PBDEC12, PBDEC21, and PBDEC22 and page buffer drivers PBDRV1 and PBDRV2.

[0104] Each of page buffer decoders PBDEC11 and PBDEC12 can select a page buffer based on the column address Y_ADDR and connect the selected page buffer to page buffer driver PBDRV1. Each of page buffer decoders PBDEC21 and PBDEC22 can select a page buffer based on the column address Y_ADDR and connect the selected page buffer to page buffer driver PBDRV2.

[0105] The page buffer driver PBDRV1 may include transistors 201a, 202a, and 203a, and an inverter 204a. The first terminal of transistor 201a can be connected to page buffer decoders PBDEC11 and PBDEC12, and the second terminal of transistor 201a can be connected to the first terminal of transistor 202a. Transistor 201a can receive control signal ctrl11 through its gate terminal. The second terminal of transistor 202a can be connected to a ground node, and it can also receive control signal ctrl12 through its gate terminal. The first terminal of transistor 203a can be connected to a power supply voltage node, and the second terminal of transistor 203a can be connected to the second terminal of transistor 201a. The gate terminal of transistor 203a can be connected to the output node of inverter 204a. The input terminal of inverter 204a can be connected to the second terminal of transistor 203a, and the output terminal of inverter 204a can be connected to data input / output circuitry 250. Page buffer driver PBDRV1 can receive data through page buffer decoders PBDEC11 and PBDEC12, amplify the data through transistor 203a and inverter 204a, and provide the amplified data to data input / output circuit 250.

[0106] Page buffer driver PBDRV2 may include transistors 201b, 202b and 203b and inverter 204b, and the description of page buffer driver PBDRV1 can be applied to page buffer driver PBDRV2.

[0107] Reference Figure 1 and Figure 10 Page buffers PB11 and PB13 can be connected to bit lines BL11 and BL12 included in the first bit line group, and page buffers PB12 and PB14 can be connected to bit lines BL21 and BL22 included in the second bit line group. That is, page buffer driver PBDRV1 can be connected to both the first subplane 110 and the second subplane 120. Furthermore, page buffers PB21 and PB23 are connected to bit lines BL13 and BL14 included in the first bit line group, and page buffers PB22 and PB24 can be connected to bit lines BL23 and BL24 included in the second bit line group. That is, page buffer driver PBDRV2 can also be connected to both the first subplane 110 and the second subplane 120. Therefore, even during read operations on only one of the first subplane 110 and the second subplane 120, both page buffer drivers PBDRV1 and PBDRV2 can be used, thereby improving I / O performance.

[0108] The data input / output circuit 250 can output data received from page buffer drivers PBDRV1 and PBDRV2 to external components via data pins D1 to Dn. Data pins D1 to Dn can also be referred to as DQ pins.

[0109] In one or more embodiments, the memory device may include: a first half-cell array (e.g., a first subplane 110) connecting a plurality of first bit lines (e.g., BL11-BL14), a second half-cell array (second subplane 120) connecting a plurality of second bit lines (e.g., BL21-BL24), and a first input / output sense amplifier (IOSA) (e.g., page buffer circuit 210) electrically connected to a plurality of first bit lines (e.g., BL11, BL12) and a plurality of second bit lines (e.g., BL21, BL22). The second input / output sense amplifier (IOSA) (e.g., PBDRV1 in the page buffer circuit 210) electrically connected to a plurality of first bit lines (e.g., BL13, BL14) and a plurality of second bit lines (e.g., BL23, BL24), and additional metal lines (e.g., extension lines L1-L4) disposed above or below a metal layer (e.g., wiring layer M1) in which the bit lines (e.g., BL11-BL14 and BL21-BL24) are formed (e.g., wiring layer M1) (e.g., wiring layer M2 or wiring layer within peripheral circuit region 92). The bit lines of the first half-cell array may be alternately electrically connected to the first IOSA and the second IOSA, the bit lines of the second half-cell array may be alternately electrically connected to the first IOSA and the second IOSA, the bit lines of the second half-cell array may be connected to the first IOSA via additional metal lines; and the bit lines of the first half-cell array may be electrically connected to the second IOSA via additional metal lines. During a read operation on the first half-cell array, the first IOSA and the second IOSA can be driven such that the I / O speed of the read operation is substantially equal to the I / O speed of the read operation on the first half-cell array and the second half-cell array together.

[0110] Figure 11 This is a plan view showing a memory device 80 according to an embodiment. Figures 12A to 12D This is a cross-sectional view showing a memory device 80 according to an embodiment. For example, Figure 12A It is along Figure 11 A cross-sectional view taken from line Y1-Y1'. Figure 12B It is along Figure 11 A cross-sectional view taken from line Y2-Y2'. Figure 12C It is along Figure 11 The cross-sectional view taken by line Y3-Y3', and Figure 12D It is along Figure 11 The cross-sectional view taken from line Y4-Y4'.

[0111] Reference Figure 11 and Figures 12A to 12D The memory device 80 may include bit lines BL11 to BL14, bit lines BL21 to BL24, and first extension lines L1 to fourth extension lines L4 arranged in the memory cell region 81. The memory device 80 may include a first subplane 181 disposed in the first subplane region 281 and a second subplane 182 disposed in the second subplane region 282.

[0112] The memory device 80 may include main units MU11 to MU14 and MU21 to MU24, high-voltage units HVU11 to HVU14 and HVU21 to HVU24, cache units CU11 to CU14 and CU21 to CU24, page buffer decoders PBDEC11, PBDEC12, PBDEC21 and PBDEC22, and page buffer drivers PBDRV1 and PBDRV2, which are arranged in the peripheral circuit area 82. Main unit MU11, high-voltage unit HVU11, and cache unit CU11 may be included in page buffer PB11; main unit MU12, high-voltage unit HVU12, and cache unit CU12 may be included in page buffer PB12; main unit MU13, high-voltage unit HVU13, and cache unit CU13 may be included in page buffer PB13; and main unit MU14, high-voltage unit HVU14, and cache unit CU14 may be included in page buffer PB14. The main unit MU21, the high-voltage unit HVU21, and the cache unit CU21 may be included in the page buffer PB21; the main unit MU22, the high-voltage unit HVU22, and the cache unit CU22 may be included in the page buffer PB22; the main unit MU23, the high-voltage unit HVU23, and the cache unit CU23 may be included in the page buffer PB23; and the main unit MU24, the high-voltage unit HVU24, and the cache unit CU24 may be included in the page buffer PB24.

[0113] Page buffers PB11 to PB14, page buffer decoders PBDEC11 and PBDEC12, and page buffer driver PBDRV1 can be arranged in circuit area 291, and page buffers PB21 to PB24, page buffer decoders PBDEC21 and PBDEC22, and page buffer driver PBDRV2 can be arranged in circuit area 292.

[0114] Each of bit lines BL11 to BL14 and BL21 to BL24 may extend in the first wiring layer M1 in the second horizontal direction. Bit lines BL11 to BL14 included in the first bit line group may be separated from bit lines BL21 to BL24 included in the second bit line group in the second horizontal direction.

[0115] Reference Figure 11 , Figure 12B and Figure 12D Bit lines BL12 and BL14 can be connected to the first extension line L1 and the fourth extension line L4, respectively, via vias formed in the first via layer V1. The first extension line L1 and the fourth extension line L4 can extend in a second horizontal direction. The first extension line L1 and the fourth extension line L4 can also extend at least to portions perpendicular to and overlapping with the high-voltage portions HVU22 and HVU21 arranged in circuit region 292. The first extension line L1 and the fourth extension line L4 can be connected to the high-voltage transistors formed in the high-voltage units HVU22 and HVU21, respectively, via vias formed in the second via layer V2.

[0116] Reference Figure 11 , Figure 12A and Figure 12C Bit lines BL21 and BL23 can be connected to the second extension line L2 and the third extension line L3, respectively, through vias formed in the first via layer V1. The second extension line L2 and the third extension line L3 can extend in a second horizontal direction. The second and third extension lines can extend at least to portions perpendicular to and overlapping with the high-voltage units HVU14 and HVU13 arranged in circuit region 291. The second extension line L2 and the third extension line L3 can be connected to the high-voltage transistors formed in the high-voltage units HVU14 and HVU13, respectively, through vias formed in the second via layer V2.

[0117] Reference Figure 11 , Figure 12A and Figure 12C Bit lines BL11 and BL13 can be constructed through a structure perpendicularly formed through the first via layer V1, the second wiring layer M2, and the second via layer V2 (see, for example, see...). Figure 6 The structure 63 shown is connected to the high-voltage transistors of the high-voltage units HVU11 and HVU12, respectively.

[0118] Reference Figure 11 , Figure 12B as well as Figure 12D Bit lines BL22 and BL24 can be constructed through a structure perpendicularly formed passing through the first via layer V1, the second wiring layer M2, and the second via layer V2 (see, for example, see...). Figure 6The structure 66 shown is connected to the high-voltage transistors of the high-voltage units HVU23 and HVU24, respectively.

[0119] Reference Figure 12A The memory cell region 81 may include a first wiring layer M1, a first via layer V1, a second wiring layer M2, and a second via layer V2. Furthermore, the memory cell region 81 may include a metal line 381 formed above the second via layer V2 and a first bonding metal 382. The number of metal wiring layers formed in the memory cell region 81 is not limited thereto. The first bonding metal 382 may be electrically connected to a second bonding metal 383 of the peripheral circuit region 82 by a bonding method. The peripheral circuit region 82 may include sequentially stacked metal lines 384, 385, and 386. High-voltage cells and bit lines may be interconnected through metal lines 384, 385, and 386. The number of metal wiring layers is not limited thereto.

[0120] Reference Figure 11 and Figures 12A to 12D Because bit lines BL11 to BL14 and BL21 to BL24 are connected to page buffers PB11 to PB14 and PB21 to PB24 via first extension lines L1 to fourth extension lines L4 formed in the second wiring layer M2, the memory device 80 can use both page buffer drivers PBDRV1 and PBDRV2 during a read operation, regardless of the size of the data being read.

[0121] Figures 13A to 13D This is a cross-sectional view showing a memory device 90 according to an embodiment.

[0122] The memory device 90 may include a memory cell region 91 and a peripheral circuit region 92. When describing the memory cell region 91 and the peripheral circuit region 92, descriptions identical to those given above may be omitted.

[0123] Reference Figure 13A and Figure 12A In contrast, the second extension line L2' can extend from circuit region 292 to circuit region 291 within the peripheral circuit region 92. Bit line BL21 can be connected to the high-voltage transistor of the high-voltage unit HVU14 via the second extension line L2'.

[0124] Reference Figure 13B and Figure 12B In contrast, the first extension line L1' can extend from circuit region 291 to circuit region 292 within the peripheral circuit region 92. Bit line BL12 can be connected to the high-voltage transistor of high-voltage unit HVU22 via the first extension line L1'.

[0125] Reference Figure 13C and Figure 12CIn contrast, the third extension line L3' can extend from circuit region 292 to circuit region 291 within peripheral circuit region 92. Bit line BL23 can be connected to the high-voltage transistor of high-voltage unit HVU13 via the third extension line L3'.

[0126] Reference Figure 13D and Figure 12D In contrast, the fourth extension line L4' can extend from circuit region 291 to circuit region 292 within the peripheral circuit region 92. Bit line BL14 can be connected to the high-voltage transistor of the high-voltage unit HVU21 via the fourth extension line L4'.

[0127] Although the first extension line L1' to the fourth extension line L4' are shown as being formed in the wiring layer of the metal line 384, the embodiment is not limited thereto. The first extension line L1' to the fourth extension line L4' can be formed in any wiring layer within the peripheral circuit region 92.

[0128] Figure 14A and Figure 14B An example layout according to an embodiment is shown, illustrating the arrangement of bit line BL and extension line EW. Figure 14A and Figure 14B The bit line BL and extension line EW shown can be arranged in the memory cell region (e.g., see...). Figure 12A The memory cell region 81 shown is illustrated. Figures 14A to 16B In this context, it is assumed that the memory cell region is vertically flipped. Therefore, the term "above" can refer to the -Z axis direction.

[0129] Reference Figure 14A Multiple bit lines BL extending in the second horizontal direction can be spaced apart from each other in the first horizontal direction. The bit lines BL are divided by a bit line cutting region BLC1, thus forming two separate bit line groups: a first bit line group BLG1 and a second bit line group BLG2. The bit lines BL of the first bit line group BLG1 can be connected to a first subplane, and the bit lines BL of the second bit line group BLG2 can be connected to a second subplane. The first bit line group BLG1 and the second bit line group BLG2 can be spaced apart by a first spacing distance d1. In other words, all bit lines BL can be cut along a cutting line CR extending in the first horizontal direction to form the first bit line group BLG1 and the second bit line group BLG2. Bit lines BL included in the first bit line group BLG1 can have the same length, and bit lines BL included in the second bit line group BLG2 can also have the same length.

[0130] Reference Figure 14BEach extension line EW extending in the second horizontal direction can be spaced apart from each other in the first horizontal direction. The extension lines EW can be aligned with the bit lines BL of the first bit line group BLG1 and the second bit line group BLG2. The extension lines EW can overlap with the bit line cutting region BLC formed along the cutting row CR.

[0131] In the region perpendicularly overlapping with a subset of bit lines BL included in the second bit line group BLG2, extension lines EW11 to EW18 included in the first extension line group EWG1 can be connected to the subset of bit lines BL through vias in the first via layer V1. Extension lines EW11 to EW18 can extend across the bit line cutting region BLC1 to the region perpendicularly overlapping with the subset of bit lines BL included in the first line group BLG1. In the region perpendicularly overlapping with a subset of bit lines BL included in the first line group BLG1, extension lines EW11 to EW18 can be connected to different page buffers included in the first page buffer group through vias in the second via layer V2.

[0132] In the region perpendicularly overlapping with the remainder of the bit line BL included in the first bit line group BLG1, extension lines EW21 to EW28 included in the second extension line group EWG2 can be connected to the remainder of the bit line BL included in the first bit line group BLG1 via vias in the first via layer V1. Extension lines EW21 to EW28 can extend across the bit line cutting region BLC1 to the region perpendicularly overlapping with the remainder of the bit line BL included in the second bit line group BLG2. In the region perpendicularly overlapping with the remainder of the bit line BL included in the second bit line group BLG2, extension lines EW21 to EW28 can be connected to different page buffers included in the second page buffer group via vias in the second via layer V2.

[0133] Bit lines BL can be spaced apart from each other in a first horizontal direction by a first distance p1, and extension lines EW can be spaced apart from each other in the first horizontal direction by a second distance p2. When the width of the extension line EW is equal to the width of the bit line BL, the first distance p1 and the second distance p2 can be the same. However, when the width of the extension line EW is greater than the width of the bit line BL, the second distance p2 can be less than the first distance p1. Therefore, adjacent extension lines EW in the first horizontal direction may interfere with each other, potentially violating design rules.

[0134] Figures 15A to 15C This is a layout showing the arrangement of bit line BL and extension line EW according to an embodiment.

[0135] Reference Figure 15AMultiple bit lines BL extending in the second horizontal direction can be spaced apart from each other in the first horizontal direction. The bit lines BL can be separated by a bit line cutting region BLC2, thus forming a first bit line group BLG1 and a second bit line group BLG2. The bit lines BL of the first bit line group BLG1 can be connected to a first sub-plane, and the bit lines BL of the second bit line group BLG2 can be connected to a second sub-plane. The first bit line group BLG1 and the second bit line group BLG2 can be separated from each other by a first spacing distance d1.

[0136] One of every two adjacent bit lines BL in the first horizontal direction can be cut along a first cut line CR1 extending in the first horizontal direction, and the remaining bit lines BL not cut along the first cut line CR1 can be cut along a second cut line CR2 extending in the first horizontal direction. In this way, a first bit line group BLG1 and a second bit line group BLG2 can be formed. The bit lines BL included in the first bit line group BLG1 are arranged such that bit lines BL having a first length H1 and bit lines BL having a second length H2 can be arranged alternately in the first horizontal direction.

[0137] Reference Figure 15B The extension lines EW11 to EW18, which are included in the first extension line group EWG1, can be arranged at a position that overlaps with the bit line cutting area BLC2 formed along the first cutting row CR1.

[0138] In the region perpendicularly overlapping with a subset of bit lines BL included in the second bit line group BLG2, extension lines EW11 to EW18 included in the first extension line group EWG1 can be connected to the subset of bit lines BL included in the second bit line group BLG2 via vias in the first via layer V1. Extension lines EW11 to EW18 can extend across the bit line cutting region BLC2 to the region perpendicularly overlapping with the subset of bit lines BL included in the first line group BLG1. In the region perpendicularly overlapping with a subset of bit lines BL included in the first line group BLG1, extension lines EW11 to EW18 can be connected to different page buffers included in the first page buffer group via vias in the second via layer V2.

[0139] In the region perpendicularly overlapping with the remainder of the bit line BL included in the first bit line group BLG1, extension lines EW21 to EW28 included in the second extension line group EWG2 can be connected to the remainder of the bit line BL included in the first bit line group BLG1 via vias in the first via layer V1. Extension lines EW21 to EW28 can extend across the bit line cutting region BLC2 to the region perpendicularly overlapping with the remainder of the bit line BL included in the second bit line group BLG2. In the region perpendicularly overlapping with the remainder of the bit line BL included in the second bit line group BLG2, extension lines EW21 to EW28 can be connected to different page buffers included in the second page buffer group via vias in the second via layer V2.

[0140] In other words, the bit line BL is cut along two cut lines (i.e., a first cut line CR1 and a second cut line CR2 that extend in a first horizontal direction and are spaced apart from each other in a second horizontal direction) in such a way that one of every two adjacent bit lines BL in the first horizontal direction can be cut along the first cut line CR1, and the other can be cut along the second cut line CR2. Thus, a first bit line group BLG1 and a second bit line group BLG2 can be formed.

[0141] The first extension line group EWG1 and the second extension line group EWG2 can be separated from each other in the second horizontal direction. Therefore, extension lines that are adjacent to each other in the first horizontal direction can be spaced apart from each other by a third distance p3 in the first horizontal direction. The third distance p3 can be greater than the second distance p2 (see...). Figure 14B Therefore, interference between extension lines can be reduced, and the arrangement of extension lines can meet design rules.

[0142] However, because the size of the bit line cut region BLC2 is smaller than the size of the bit line cut region BLC1 (see...) Figure 14A Therefore, machinability may be degraded. For example, because the length of each bitline cutting region BLC2 in the first horizontal direction is less than the length of bitline cutting region BLC1 in the first horizontal direction, machinability may be degraded.

[0143] Reference Figure 15C Each of the extension lines can be L-shaped. The bottom of the L-shape can be connected to the page buffer through a via in the second via layer V2.

[0144] Figure 16A and Figure 16B This illustrates the arrangement of bit lines and extension lines according to an embodiment.

[0145] Reference Figure 16AMultiple bit lines BL extending in the second horizontal direction can be spaced apart from each other in the first horizontal direction. The bit lines BL are divided by a bit line cutting region BLC3, thus forming a first bit line group BLG1 and a second bit line group BLG2. The bit lines BL of the first bit line group BLG1 can be connected to a first sub-plane, and the bit lines BL of the second bit line group BLG2 can be connected to a second sub-plane. The first bit line group BLG1 and the second bit line group BLG2 can be separated from each other by a first spacing distance d1.

[0146] Two consecutive bit lines BL in every four consecutive bit lines BL arranged in the first horizontal direction can be cut along a first cutting line CR1 extending in the first horizontal direction, and the remaining two bit lines BL in the same four consecutive bit lines BL that are not cut along the first cutting line CR1 can be cut along a second cutting line CR2 extending in the first horizontal direction. In this way, a first bit line group BLG1 and a second bit line group BLG2 can be formed. The bit lines BL included in the first bit line group BLG1 are arranged such that two bit lines with a first length H1 and two bit lines with a second length H2 can be alternately repeated in the first horizontal direction.

[0147] Reference Figure 16B The extension lines EW11 to EW18, included in the first extension line group EWG1, can be connected to the bit line BL, included in the second bit line group BLG2, via vias in the first via layer V1. The extension lines EW11 to EW18 can be connected to different page buffers, included in the first page buffer group, via vias in the second via layer V2.

[0148] Extension lines EW21 to EW28, included in the second extension line group EWG2, can be connected to bit lines BL, included in the first line group BLG1, via vias in the first via layer V1. Extension lines EW21 to EW28 can be connected to different page buffers, included in the second page buffer group, via vias in the second via layer V2.

[0149] Adjacent extensions in the first horizontal direction can be spaced apart from each other by a third distance p3 in the first horizontal direction. The third distance p3 can be greater than the second distance p2 (see...). Figure 14B This increased spacing reduces interference between extension lines and ensures that the layout of the extension lines conforms to design rules. Furthermore, because the size of the bit line cut region BLC3 is larger than the size of the bit line cut region BLC2 (see...), Figure 15B and Figure 15C This improves manufacturability. For example, because the length of each bitline cutting region BL3 in the first horizontal direction is greater than the length of each bitline cutting region BL2 in the first horizontal direction, the overall process efficiency can be improved.

[0150] Figure 17 This is a plan view showing a memory device 70 according to an embodiment. Figure 18A and Figure 18B This is a cross-sectional view showing a memory device 70 according to an embodiment. For example, Figure 18A It is along Figure 17 The cross-sectional view taken by line Y5-Y5', and Figure 18B It is along Figure 17 The cross-sectional view taken along line Y6-Y6'. The description given above with reference to the attached figure can also be applied to... Figures 17 to 18B .

[0151] Bit lines BL11 to BL14 and BL21 to BL24 may extend in the first wiring layer M1 in the second horizontal direction. Bit lines BL11 to BL14 included in the first bit line group and bit lines BL21 to BL24 included in the second bit line group may be arranged separately from each other in the second horizontal direction.

[0152] Bit lines BL21 and BL23 may extend in the second horizontal direction to the portion overlapping with the first sub-plane region 281. Bit lines BL21 and BL23 may extend in the second horizontal direction to the portion overlapping with the circuit region 291. See also... Figure 15A Bit lines BL21 and BL23 can be separated from bit lines BL11 and BL13 by a first interval distance d1 in the second horizontal direction.

[0153] Bit lines BL12 and BL14 may extend in the second horizontal direction to the portion overlapping with the second sub-plane region 282. Bit lines BL12 and BL14 may extend in the second horizontal direction to the portion overlapping with the circuit region 292. See also... Figure 15A Bit lines BL12 and BL14 can be separated from bit lines BL22 and BL24 by a first interval distance d1 in the second horizontal direction.

[0154] although Figures 17 to 18B Not shown in the image, but refer to... Figure 16A and Figure 16B In the bit lines BL included in the first bit line group BLG1, the bit line BL adjacent to the bit line cutting region BLC3 formed along the second cutting row CR2 can extend in the second horizontal direction to the portion overlapping with the second sub-plane region 282 or the circuit region 292. In the bit lines BL included in the second bit line group BLG2, the bit line BL adjacent to the bit line cutting region BLC3 formed along the first cutting row CR1 can extend in the second horizontal direction to the portion overlapping with the first sub-plane region 281 or the circuit region 291.

[0155] Figure 19 This is a view showing a memory device 500 according to some embodiments.

[0156] Reference Figure 19 The memory device 500 may have a chip-to-chip (C2C) structure. At least one upper chip (including a cell region) and one lower chip (including a peripheral circuitry region PERI) may be manufactured separately. At least one upper chip and one lower chip may be connected to each other by a bonding process to form a C2C structure. For example, the bonding process may involve electrically or physically connecting a bonding metal pattern formed on the uppermost metal layer of the upper chip to a bonding metal pattern formed on the uppermost metal layer of the lower chip. For example, if the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0157] The memory device 500 may include at least one on-chip, which includes cell regions. For example, such as Figure 19 As shown, the memory device 500 may include two upper chips. However, the number of upper chips is not limited to this. In the case where the memory device 500 includes two upper chips, a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PERI can be manufactured separately. The first upper chip, the second upper chip, and the lower chip can then be connected to each other by a bonding method to manufacture the memory device 500. The first upper chip can be flipped and then connected to the lower chip by a bonding method, and the second upper chip can also be flipped and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower portions of each of the first and second upper chips will be defined based on the condition that each of the first and second upper chips is flipped. In other words, the upper portion of the lower chip may refer to the upper portion defined based on the +Z axis direction, and the upper portion of each of the first and second upper chips may refer to the upper portion defined based on the +Z axis direction. Figure 19 The upper part is defined by the -Z axis direction. However, the embodiments are not limited to this. In some embodiments, one of the first and second upper chips can be flipped and then connected to the corresponding chip by a bonding method.

[0158] Each of the peripheral circuit region PERI and the first cell region CELL1 and the second cell region CELL2 of the memory device 500 may include an external pad bonding region PA, a word line bonding region WLBA and a bit line bonding region BLBA.

[0159] The peripheral circuit region (PERI) may include a first substrate 610 and a plurality of circuit elements 620a, 620b, and 620c formed on the first substrate 610. An interlayer insulating layer 615, including one or more insulating layers, may be disposed on the plurality of circuit elements 620a, 620b, and 620c, and a plurality of metal wires electrically connected to the plurality of circuit elements 620a, 620b, and 620c may be disposed in the interlayer insulating layer 615. For example, the plurality of metal wires may include first metal wires 630a, 630b, and 630c connected to the plurality of circuit elements 620a, 620b, and 620c, and second metal wires 640a, 640b, and 640c formed on the first metal wires 630a, 630b, and 630c. The plurality of metal wires may be formed of at least one of a variety of conductive materials. For example, the first metal lines 630a, 630b and 630c can be formed of tungsten, which has a relatively high resistivity, and the second metal lines 640a, 640b and 640c can be formed of copper, which has a relatively low resistivity.

[0160] This embodiment shows and describes first metal lines 630a, 630b, and 630c and second metal lines 640a, 640b, and 640c. However, the embodiment is not limited thereto. In some embodiments, at least one or more additional metal lines may be formed on the second metal lines 640a, 640b, and 640c. In this case, the second metal lines 640a, 640b, and 640c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 640a, 640b, and 640c may be formed of copper, which has a resistivity lower than that of aluminum in the second metal lines 640a, 640b, and 640c.

[0161] An interlayer insulating layer 615 may be disposed on a first substrate 610 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0162] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 710 and a common source line 720. A plurality of word lines 730 (731 to 738) may be stacked on the second substrate 710 in a direction perpendicular to the top surface of the second substrate 710 (i.e., the Z-axis direction). A string select line and a ground select line may be disposed above and below the word lines 730, and the plurality of word lines 730 may be disposed between the string select line and the ground select line. Similarly, the second cell region CELL2 may include a third substrate 810 and a common source line 820, and a plurality of word lines 830 (831 to 838) may be stacked on the third substrate 810 in a direction perpendicular to the top surface of the third substrate 810 (i.e., the Z-axis direction). Each of the second substrate 710 and the third substrate 810 may be formed of at least one of a variety of materials, and may be, for example, a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single-crystal epitaxial layer grown on a single-crystal silicon substrate. Multiple channel structures CH can be formed in each of the first unit region CELL1 and the second unit region CELL2.

[0163] In some embodiments, as shown in region "A1", a channel structure CH may be disposed in a bit line bonding region BLBA and may extend in a direction perpendicular to the top surface of the second substrate 710 to penetrate word line 730, string select line, and ground select line. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to a first metal line 750c and a second metal line 760c in the bit line bonding region BLBA. For example, the second metal line 760c may be a bit line and may be connected to the channel structure CH via the first metal line 750c. The bit line 760c may extend in a second direction (e.g., the Y-axis direction) parallel to the top surface of the second substrate 710.

[0164] In some embodiments, as shown in region "A2", the channel structure CH may include a lower channel LCH and an upper channel UCH interconnected with each other. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and a process for forming the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the top surface of the second substrate 710 to penetrate the common source line 720 and the lower word lines 731 and 732. The lower channel LCH may include a data storage layer, a channel layer, and a fill insulating layer and may be connected to the upper channel UCH. The upper channel UCH may penetrate the upper word lines 733 to 738. The upper channel UCH may include a data storage layer, a channel layer, and a fill insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 750c and the second metal line 760c. As the length of the channel increases, it may be difficult to form a channel with a substantially uniform width due to the characteristics of the manufacturing process. The memory device 500 according to this embodiment may include a channel with improved width uniformity due to the lower channel LCH and upper channel UCH formed by sequentially executed processes.

[0165] In cases where the channel structure CH includes a lower channel LCH and an upper channel UCH as shown in region "A2", the word lines located near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, word lines 732 and 733 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines can be less than the number of pages corresponding to the memory cells connected to the general word lines. The voltage level applied to the dummy word lines can be different from the voltage level applied to the general word lines, and therefore it is possible to reduce the impact of the non-uniform channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device 500.

[0166] Meanwhile, in region 'A2', the number of lower word lines 731 and 732 penetrated by the lower channel LCH is less than the number of upper word lines 733 to 738 penetrated by the upper channel UCH. However, the embodiments are not limited to this. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. Furthermore, the structural features and connection relationships of the channel structure CH disposed in the second unit region CELL2 may be substantially the same as those of the channel structure CH disposed in the first unit region CELL1.

[0167] In the bit line bonding region BLBA, a first through-electrode THV1 can be disposed in the first cell region CELL1, and a second through-electrode THV2 can be disposed in the second cell region CELL2. For example... Figure 19 As shown, the first through-electrode THV1 can penetrate the common source line 720 and multiple word lines 730. In some embodiments, the first through-electrode THV1 can further penetrate the second substrate 710. The first through-electrode THV1 may include a conductive material. Alternatively, the first through-electrode THV1 may include a conductive material surrounded by an insulating material. The second through-electrode THV2 may have the same shape and structure as the first through-electrode THV1.

[0168] In some embodiments, the first through electrode THV1 and the second through electrode THV2 can be electrically connected to each other via a first through metal pattern 772d and a second through metal pattern 872d. The first through metal pattern 772d can be formed at the bottom of a first upper chip including a first cell region CELL1, and the second through metal pattern 872d can be formed at the top of a second upper chip including a second cell region CELL2. The first through electrode THV1 can be electrically connected to a first metal line 750c and a second metal line 760c. A lower via 771d can be formed between the first through electrode THV1 and the first through metal pattern 772d, and an upper via 871d can be formed between the second through electrode THV2 and the second through metal pattern 872d. The first through metal pattern 772d and the second through metal pattern 872d can be connected to each other by a bonding method.

[0169] Furthermore, in the bit line bonding area BLBA, an upper metal pattern 652 can be formed in the uppermost metal layer of the peripheral circuit region PERI, and an upper metal pattern 792 having the same shape as the upper metal pattern 652 can be formed in the uppermost metal layer of the first cell region CELL1. The upper metal pattern 792 of the first cell region CELL1 and the upper metal pattern 652 of the peripheral circuit region PERI can be electrically connected to each other by a bonding method. In the bit line bonding area BLBA, bit lines 760c can be electrically connected to page buffers included in the peripheral circuit region PERI. For example, some of the circuit elements 620c in the peripheral circuit region PERI can constitute page buffers, and bit lines 760c can be electrically connected to the circuit elements 620c constituting page buffers through the upper bonding metal pattern 770c of the first cell region CELL1 and the upper bonding metal pattern 670c of the peripheral circuit region PERI.

[0170] Continue to refer to Figure 19In the word line bonding area (WLBA), the word line 730 of the first cell region CELL1 can extend in a first direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 710 and can be connected to a plurality of cell contact plugs 740 (741 to 747). A first metal line 750b and a second metal line 760b can be sequentially connected to the cell contact plugs 740 connected to the word line 730. In the word line bonding area (WLBA), the cell contact plugs 740 can be connected to the peripheral circuit region PERI via an upper bonding metal pattern 770b of the first cell region CELL1 and an upper bonding metal pattern 670b of the peripheral circuit region PERI.

[0171] Cell contact plug 740 can be electrically connected to a line decoder included in the peripheral circuitry area (PERI). For example, some of the circuit elements 620b in the PERI can constitute a line decoder, and cell contact plug 740 can be electrically connected to the circuit elements 620b constituting the line decoder via the upper bonding metal pattern 770b of the first cell region (CELL1) and the upper bonding metal pattern 670b of the PERI. In some embodiments, the operating voltage of the circuit elements 620b constituting the line decoder can be different from the operating voltage of the circuit elements 620c constituting the page buffer. For example, the operating voltage of the circuit elements 620c constituting the page buffer can be greater than the operating voltage of the circuit elements 620b constituting the line decoder.

[0172] Similarly, in the word line bonding area WLBA, the word line 830 of the second cell region CELL2 can extend in a first direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 810, and can be connected to a plurality of cell contact plugs 840 (841 to 847). The cell contact plugs 840 can be connected to the peripheral circuit region PERI via the upper metal pattern of the second cell region CELL2, the lower and upper metal patterns of the first cell region CELL1, and the cell contact plug 748.

[0173] In the word line bonding area WLBA, an upper bonding metal pattern 770b can be formed in the first cell area CELL1, and an upper bonding metal pattern 670b can be formed in the peripheral circuit area PERI. The upper bonding metal pattern 770b in the first cell area CELL1 and the upper bonding metal pattern 670b in the peripheral circuit area PERI can be electrically connected to each other by a bonding method. The upper bonding metal pattern 770b and the upper bonding metal pattern 670b can be formed of aluminum, copper, or tungsten.

[0174] In the external pad bonding area PA, a lower metal pattern 771e can be formed in the lower part of the first cell region CELL1, and an upper metal pattern 872a can be formed in the upper part of the second cell region CELL2. The lower metal pattern 771e of the first cell region CELL1 and the upper metal pattern 872a of the second cell region CELL2 can be connected to each other by a bonding method in the external pad bonding area PA. Similarly, the upper metal pattern 772a can be formed in the upper part of the first cell region CELL1, and the upper metal pattern 672a can be formed in the upper part of the peripheral circuit region PERI. The upper metal pattern 772a of the first cell region CELL1 and the upper metal pattern 672a of the peripheral circuit region PERI can be connected to each other by a bonding method.

[0175] Common source line contact plugs 780 and 880 can be disposed in the external pad bonding area PA. Common source line contact plugs 780 and 880 can be formed of conductive materials such as metals, metal compounds, and / or doped polysilicon. Common source line contact plug 780 of the first cell region CELL1 can be electrically connected to common source line 720, and common source line contact plug 880 of the second cell region CELL2 can be electrically connected to common source line 820. First metal line 750a and second metal line 760a can be sequentially stacked on common source line contact plug 780 of the first cell region CELL1, and first metal line 850a and second metal line 860a can be sequentially stacked on common source line contact plug 880 of the second cell region CELL2.

[0176] Input / output pads 605, 805, and 806 can be set within the external pad bonding area PA. (See reference...) Figure 19 The lower insulating layer 601 may cover the bottom surface of the first substrate 610, and the first input / output pad 605 may be formed on the lower insulating layer 601. The first input / output pad 605 may be connected to at least one of a plurality of circuit elements 620a disposed in the peripheral circuit region PERI via the first input / output contact plug 603, and may be separated from the first substrate 610 via the lower insulating layer 601. Furthermore, a side insulating layer may be disposed between the first input / output contact plug 603 and the first substrate 610 to electrically isolate the first input / output contact plug 603 from the first substrate 610.

[0177] An upper insulating layer 801 covering the top surface of the third substrate 810 may be formed on the third substrate 810. A second input / output pad 805 and / or a third input / output pad 806 may be disposed on the upper insulating layer 801. The second input / output pad 805 may be connected to at least one of a plurality of circuit elements 620a disposed in the peripheral circuit region PERI via second input / output contact plugs 803 and 703, and the third input / output pad 806 may be connected to at least one of a plurality of circuit elements 620a disposed in the peripheral circuit region PERI via third input / output contact plugs 804 and 704.

[0178] In some embodiments, the third substrate 810 may not be disposed in the region where the input / output contact plug is disposed. For example, as shown in region "B", the third input / output contact plug 804 may be separated from the third substrate 810 in a direction parallel to the top surface of the third substrate 810 and may penetrate the interlayer insulating layer 815 of the second cell region CELL2 to connect to the third input / output pad 806. In this case, the third input / output contact plug 804 may be formed by at least one of various processes.

[0179] In some embodiments, as shown in region "B1", the third input / output contact plug 804 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 804 may gradually increase toward the upper insulating layer 801. In other words, the diameter of the channel structure CH described in region "A1" may gradually decrease toward the upper insulating layer 801, but the diameter of the third input / output contact plug 804 may gradually increase toward the upper insulating layer 801. For example, the third input / output contact plug 804 may be formed after the second cell region CELL2 and the first cell region CELL1 are joined together by a bonding method.

[0180] In some embodiments, as shown in region "B2", the third input / output contact plug 804 may extend in a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 804 may gradually decrease towards the upper insulating layer 801. In other words, like the channel structure CH, the diameter of the third input / output contact plug 804 may gradually decrease towards the upper insulating layer 801. For example, the third input / output contact plug 804 may be formed together with the cell contact plug 840 before the second cell region CELL2 and the first cell region CELL1 are engaged with each other.

[0181] In some embodiments, the input / output contact plugs may overlap with the third substrate 810. For example, as shown in region "C", the second input / output contact plug 803 may penetrate the interlayer insulating layer 815 of the second cell region CELL2 in a third direction (e.g., the Z-axis direction) and may be electrically connected to the second input / output pad 805 via the third substrate 810. In this case, the connection structure between the second input / output contact plug 803 and the second input / output pad 805 can be implemented by various methods.

[0182] In some embodiments, as shown in region "C1", an opening 808 may be formed to penetrate the third substrate 810, and the second input / output contact plug 803 may be directly connected to the second input / output pad 805 through the opening 808 formed in the third substrate 810. In this case, as shown in region "C1", the diameter of the second input / output contact plug 803 may gradually increase toward the second input / output pad 805. However, the embodiments are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 803 may gradually decrease toward the second input / output pad 805.

[0183] In some embodiments, as shown in region 'C2', an opening 808 penetrating the third substrate 810 may be formed, and a contact 807 may be formed in the opening 808. One end of the contact 807 may be connected to the second input / output pad 805, and the other end of the contact 807 may be connected to the second input / output contact plug 803. Therefore, the second input / output contact plug 803 can be electrically connected to the second input / output pad 805 through the contact 807 in the opening 808. In this case, as shown in region 'C2', the diameter of the contact 807 may gradually increase toward the second input / output pad 805, and the diameter of the second input / output contact plug 803 may gradually decrease toward the second input / output pad 805. For example, the second input / output contact plug 803 may be formed together with the cell contact plug 840 before the second cell region CELL2 and the first cell region CELL1 engage with each other, and the contact 807 may be formed after the second cell region CELL2 and the first cell region CELL1 engage with each other.

[0184] In some embodiments, as shown in region "C3", a stopper 809 may be further formed on the bottom end of the opening 808 of the third substrate 810, compared to the embodiment in region "C2". The stopper 809 may be a metal line formed in the same layer as the common source line 820. Alternatively, the stopper 809 may be a metal line formed in the same layer as at least one of the word lines 830. The second input / output contact plug 803 may be electrically connected to the second input / output pad 805 via the contact 807 and the stopper 809.

[0185] Similar to the second input / output contact plugs 803 and 804 of the second cell region CELL2, the diameter of each of the second input / output contact plugs 703 and 704 of the first cell region CELL1 can gradually decrease or gradually increase towards the lower metal pattern 771e.

[0186] In some embodiments, a slit 811 may be formed in the third substrate 810. For example, the slit 811 may be formed at a location within the outer pad bonding region PA. For instance, as shown in region "D", when viewed in a plan view, the slit 811 may be located between the second input / output pad 805 and the cell contact plug 840. Alternatively, when viewed in a plan view, the second input / output pad 805 may be located between the slit 811 and the cell contact plug 840.

[0187] In some embodiments, as shown in region “D1”, slit 811 may be formed to penetrate the third substrate 810. For example, slit 811 may be used to prevent the third substrate 810 from slightly cracking when the opening 808 is formed. However, embodiments are not limited thereto, and in some embodiments, slit 811 may be formed to have a depth ranging from about 60% to about 70% of the thickness of the third substrate 810.

[0188] In some embodiments, as shown in region "D2", conductive material 812 may be formed in slit 811. For example, conductive material 812 may be used to discharge leakage current occurring during the driving of circuit elements in the external pad bonding region PA to the outside. In this case, conductive material 812 may be connected to an external ground wire.

[0189] In some embodiments, as shown in region "D3", an insulating material 813 may be formed in the slit 811. For example, the insulating material 813 may be used to electrically isolate the second input / output pads 805 and the second input / output contact plugs 803 disposed in the external pad bonding region PA from the word line bonding region WLBA. Because the insulating material 813 is formed in the slit 811, the voltage supplied through the second input / output pads 805 can be prevented from affecting the metal layer disposed on the third substrate 810 in the word line bonding region WLBA.

[0190] Meanwhile, in some embodiments, the first input / output pads to the third input / output pads 605, 805, and 806 can be selectively formed. For example, the memory device 500 can be implemented to include only the first input / output pad 605 disposed on the first substrate 610, only the second input / output pad 805 disposed on the third substrate 810, or only the third input / output pad 806 disposed on the upper insulating layer 801.

[0191] In some embodiments, at least one of the second substrate 710 of the first cell region CELL1 or the third substrate 810 of the second cell region CELL2 can be used as a sacrificial substrate and can be completely or partially removed before or after the bonding process. Additional layers can be stacked after substrate removal. For example, the second substrate 710 of the first cell region CELL1 can be removed before or after the bonding process of the peripheral circuit region PERI and the first cell region CELL1, and then an insulating layer or a conductive layer for connection can be formed covering the top surface of the common source line 720. Similarly, the third substrate 810 of the second cell region CELL2 can be removed before or after the bonding process of the first cell region CELL1 and the second cell region CELL2, and then an upper insulating layer 801 or a conductive layer for connection can be formed covering the top surface of the common source line 820.

[0192] Figure 1 The memory cell array 100 can be disposed on the first cell region CELL1 and / or the second cell region CELL2. Figure 1 The peripheral circuit 200 can be set on the peripheral circuit area PERI.

[0193] The first extension line L1, the second extension line L2, the third extension line L3, and the fourth extension line L4 can be formed in the metal layer between the second metal line 760c and the upper bonding metal pattern 770c in the first cell region CELL1. Furthermore, the first extension line L1', the second extension line L2', the third extension line L3', and the fourth extension line L4' can be formed in the metal layer of the first metal line 630c and the second metal line 640c in the peripheral circuit region PERI.

[0194] Some of the circuit elements 620c in the PERI peripheral circuit area can form page buffer decoders and page buffer drivers.

[0195] Figure 20 This is a view showing a solid-state drive (SSD) 1200 including memory devices 1230, 1240 and 1250 according to an embodiment.

[0196] Reference Figure 20 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 exchanges signals (SIG) with the host 1100 via a signal connector and receives power (PWR) via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. Each of the memory devices 1230, 1240, and 1250 may be a vertically stacked NAND flash memory device. In this case, the SSD 1200 can use the referenced above. Figures 1 to 19 The described embodiments are implemented.

[0197] In one or more embodiments of this disclosure, a memory device may include: a first subplane including a plurality of memory cells connected to a plurality of first bit lines; a second subplane including a plurality of memory cells connected to a plurality of second bit lines; a first page buffer and a second page buffer, each configured to sense data from the memory cells via a corresponding bit line; a data input / output circuit configured to transmit data via a plurality of data pins; a first page buffer driver configured to provide data from the first page buffer to the data input / output circuit; and a second page buffer driver configured to provide data from the second page buffer to the data input / output circuit, wherein a first subset of the plurality of first bit lines may be connected to a first subset of the first page buffer, a second subset of the plurality of first bit lines may be connected to a first subset of the second page buffer, a first subset of the plurality of second bit lines may be connected to a second subset of the first page buffer, and a second subset of the plurality of second bit lines may be connected to a second subset of the second page buffer.

[0198] During a read operation performed on a plurality of memory cells included in a first subplane, a first page buffer driver may be configured to provide data sensed by a first subset of the first page buffer to a data input / output circuit via a first subset of a plurality of first bit lines, and a second page buffer driver may be configured to provide data sensed by a first subset of the second page buffer to a data input / output circuit via a second subset of a plurality of first bit lines.

[0199] During a read operation performed on a plurality of memory cells included in the second subplane, the first page buffer driver can be configured to provide data sensed by a second subset of the first page buffer to the data input / output circuit via a first subset of a plurality of second bit lines, and the second page buffer driver can be configured to provide data sensed by a second subset of the second page buffer to the data input / output circuit via a second subset of a plurality of second bit lines.

[0200] The first subplane and the second subplane can be in the first region, the first page buffer and the second page buffer can be in the second region, the second region can be vertically aligned with the first region and located above or below the first region, the first subplane and the first page buffer overlap vertically with each other, and the second subplane and the second page buffer overlap vertically with each other.

[0201] Multiple first bit lines may be separated from multiple second bit lines in a first horizontal direction and extend in a first wiring layer in the first horizontal direction, and a second subset of the multiple first bit lines may be connected to a first line that extends in a second wiring layer within a first region from a region that vertically overlaps with a first page buffer to a region that vertically overlaps with a first subset of a second page buffer.

[0202] A first subset of multiple second bit lines can be connected to a second line that extends in the second wiring layer from an area that vertically overlaps with the second page buffer to an area that vertically overlaps with the second subset of the first page buffer.

[0203] A second subset of multiple first-bit lines can be connected to a third line, which extends in a third wiring layer within the second region from a region perpendicularly overlapping with the first page buffer to a region perpendicularly overlapping with the first subset of the second page buffer.

[0204] A first subset of multiple second bit lines can be connected to a fourth line, which extends in the third wiring layer from an area perpendicularly overlapping the second page buffer to an area perpendicularly overlapping the second subset of the first page buffer.

[0205] In one or more embodiments of this disclosure, a memory device may include: a first subplane including a plurality of memory cells; a second subplane including a plurality of memory cells; a first bit line group including a plurality of first bit lines, which can be connected to the first subplane, extend in a first horizontal direction, and be arranged in a second horizontal direction perpendicular to the first horizontal direction; a second bit line group including a plurality of second bit lines, which can be connected to the second subplane, extend in the first horizontal direction, and be arranged in the second horizontal direction, the second bit line group being separated from the first bit line group in the first horizontal direction by a bit line cutting region; and a first extension line group. It includes a plurality of first extension lines that can be connected to a first subset of a plurality of second bit lines and extend from a region perpendicularly overlapping the first subset of the plurality of second bit lines across a bit line cut region to a region perpendicularly overlapping the first subset of the plurality of first bit lines; a second extension line group that includes a plurality of second extension lines that can be connected to a second subset of the plurality of first bit lines and extend from a region perpendicularly overlapping the second subset of the plurality of first bit lines across a bit line cut region to a region perpendicularly overlapping the second subset of the plurality of second bit lines; and a page buffer circuit that includes a page buffer connected to the first bit line group and the second bit line group via the first extension line group and the second extension line group.

[0206] Multiple first-order lines can be of equal length, and multiple second-order lines can be of equal length.

[0207] Among the multiple first-order lines, N first-order lines of a first length and N first-order lines of a second length can be alternately arranged in the second horizontal direction, where N represents a natural number.

[0208] The page buffer circuit may include a first page buffer and a second page buffer, each page buffer being configured to sense data from a memory cell via a corresponding bit line; wherein the memory device may further include: a data input / output circuit configured to transmit data via a plurality of data pins; a first page buffer driver configured to provide data from the first page buffer to the data input / output circuit; and a second page buffer driver configured to provide data from the second page buffer to the data input / output circuit, wherein a first subset of the plurality of first bit lines may be connected to a first subset of the first page buffer, a second subset of the plurality of first bit lines may be connected to a first subset of the second page buffer, a first subset of the plurality of second bit lines may be connected to a second subset of the first page buffer, and a second subset of the plurality of second bit lines may be connected to a second subset of the second page buffer.

[0209] The first subplane and the second subplane can be in the first region, the first page buffer and the second page buffer can be in the second region, the second region can be vertically aligned with the first region and located above or below the first region, the first subplane and the first page buffer overlap vertically with each other, and the second subplane and the second page buffer overlap vertically with each other.

[0210] Multiple first bit lines may be separated from multiple second bit lines in a first horizontal direction and extend in a first wiring layer in the first horizontal direction, and a second subset of the multiple first bit lines may be connected to a first line that extends in a second wiring layer within a first region from a region that vertically overlaps with a first page buffer to a region that vertically overlaps with a first subset of a second page buffer.

[0211] A first subset of multiple second bit lines can be connected to a second line that extends in the second wiring layer from an area that vertically overlaps with the second page buffer to an area that vertically overlaps with the second subset of the first page buffer.

[0212] In one or more embodiments of this disclosure, a memory device may include: a plurality of subplanes connected to a plurality of bit line groups including a first bit line group and a second bit line group, each of the first bit line group and the second bit line group including a plurality of bit lines; a plurality of page buffer groups including a first page buffer group and a second page buffer group, each of the first page buffer group and the second page buffer group including a plurality of page buffers respectively configured to sense data via a corresponding bit line; data input / output circuitry configured to transmit data via a plurality of data pins; and a plurality of page buffer drivers each configured to provide data sensed by the plurality of page buffer groups to the data input / output circuitry, wherein a first number of first bit lines included in the first bit line group may be connected to a first number of first page buffers included in the first page buffer group, a second number of first bit lines included in the first bit line group may be connected to a second number of second page buffers included in the second page buffer group, a third number of second bit lines included in the second bit line group may be connected to a third number of first page buffers included in the first page buffer group, and a fourth number of second bit lines included in the second bit line group may be connected to a fourth number of second page buffers included in the second page buffer group.

[0213] During a read operation performed on a memory cell in a first subplane comprising multiple subplanes, a first page buffer driver among multiple page buffer drivers may be configured to provide data sensed by a first number of first page buffers to a data input / output circuit via a first number of first bit lines, and a second page buffer driver among multiple page buffer drivers may be configured to provide data sensed by a second number of second page buffers to a data input / output circuit via a second number of first bit lines.

[0214] During a read operation performed on a memory cell in a second subplane comprising multiple subplanes, the first page buffer driver can be configured to provide data sensed by the third number of first page buffers to the data input / output circuit via a third number of second bit lines, and the second page buffer driver can be configured to provide data sensed by the fourth number of second page buffers to the data input / output circuit via a fourth number of second bit lines.

[0215] Multiple subplanes can be in the first region, and multiple page buffer groups, data input / output circuits, and multiple page buffer drivers can be in the second region, which can be vertically arranged on the first region.

[0216] The first bit line and the second bit line may be separated from each other in a first horizontal direction and extend in a first wiring layer in the first horizontal direction, and a second number of first bit lines may be connected to the first line, which extends in a second wiring layer within a first region from a region that vertically overlaps with the first page buffer to a region that vertically overlaps with the second number of second page buffers.

[0217] The foregoing exemplary embodiments are merely illustrative and should not be construed as limiting. This teaching can be readily applied to other types of devices. Furthermore, the description of the exemplary embodiments is intended to be illustrative and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A memory device, comprising: The first subplane includes multiple memory cells connected to multiple first bit lines; The second subplane includes multiple memory cells connected to multiple second bit lines; The first page buffer and the second page buffer are each configured to sense data from the memory cell via the corresponding bit line; The data input / output circuitry is configured to send data via multiple data pins. The first page buffer driver is configured to provide data from the first page buffer to the data input / output circuitry. and The second page buffer driver is configured to provide data from the second page buffer to the data input / output circuitry. Wherein, a first subset of the plurality of first bit lines is connected to a first subset of the first page buffer, a second subset of the plurality of first bit lines is connected to a first subset of the second page buffer, a first subset of the plurality of second bit lines is connected to a second subset of the first page buffer, and a second subset of the plurality of second bit lines is connected to a second subset of the second page buffer.

2. The memory device according to claim 1, wherein, During a read operation performed on the plurality of memory cells included in the first subplane: The first page buffer driver is configured to provide data sensed by the first subset of the first page buffer to the data input / output circuitry via the first subset of the plurality of first bit lines, and The second page buffer driver is configured to provide the data input / output circuitry with data sensed by the first subset of the second page buffer via the second subset of the plurality of first bit lines.

3. The memory device according to claim 1, wherein, During read operations performed on the plurality of memory cells included in the second subplane: The first page buffer driver is configured to provide data sensed by the second subset of the first page buffer to the data input / output circuitry via the first subset of the plurality of second bit lines, and The second page buffer driver is configured to provide the data sensed by the second subset of the second page buffer to the data input / output circuit via the second subset of the plurality of second bit lines.

4. The memory device according to claim 1, wherein, The first subplane and the second subplane in the first region, The first page buffer and the second page buffer are located in a second region, which is vertically aligned with and below the first region. The first subplane and the first page buffer overlap vertically with each other, and The second subplane and the second page buffer overlap each other perpendicularly.

5. The memory device according to claim 4, wherein, The plurality of first bit lines are separated from the plurality of second bit lines in a first horizontal direction and extend in a first wiring layer in the first horizontal direction, and A second subset of the plurality of first bit lines is connected to a first line, the first line extending in a second wiring layer within the first region from a region perpendicularly overlapping with the first page buffer to a region perpendicularly overlapping with the first subset of the second page buffer.

6. The memory device according to claim 5, wherein, The first subset of the plurality of second bit lines is connected to a second line, which extends in the second wiring layer from a region perpendicularly overlapping with the second page buffer to a region perpendicularly overlapping with the second subset of the first page buffer.

7. The memory device according to claim 4, wherein, The second subset of the plurality of first bit lines is connected to a third line, which extends in a third wiring layer within the second region from a region perpendicularly overlapping with the first page buffer to a region perpendicularly overlapping with the first subset of the second page buffer.

8. The memory device according to claim 7, wherein, The first subset of the plurality of second bit lines is connected to a fourth line, which extends in the third wiring layer from a region perpendicularly overlapping with the second page buffer to a region perpendicularly overlapping with the second subset of the first page buffer.

9. A memory device, comprising: The first subplane includes multiple memory cells; The second subplane includes multiple memory cells; The first line group includes a plurality of first lines, which are connected to the first subplane, extend in a first horizontal direction, and are arranged in a second horizontal direction perpendicular to the first horizontal direction; The second bit line group includes a plurality of second bit lines, the plurality of second bit lines being connected to the second subplane, extending in the first horizontal direction, and being arranged in the second horizontal direction, the second bit line group being separated from the first bit line group in the first horizontal direction by a bit line cutting region; A first extension line group includes a plurality of first extension lines, the plurality of first extension lines being connected to a first subset of the plurality of second bit lines and extending from a region that vertically overlaps with the first subset of the plurality of second bit lines across the bit line cutting region to a region that vertically overlaps with the first subset of the plurality of first bit lines; The second extension line group includes a plurality of second extension lines, the plurality of second extension lines being connected to a second subset of the plurality of first bit lines and extending from a region that vertically overlaps with the second subset of the plurality of first bit lines across the bit line cutting region to a region that vertically overlaps with the second subset of the plurality of second bit lines; and Page buffer circuitry includes a page buffer connected to the first bit line group and the second bit line group via the first extension line group and the second extension line group.

10. The memory device according to claim 9, wherein, The lengths of the plurality of first lines are equal to each other, and The lengths of the plurality of second bit lines are equal to each other.

11. The memory device according to claim 9, wherein, Among the plurality of first-position lines, N first-position lines of a first length and N first-position lines of a second length are arranged alternately in the second horizontal direction, where N represents a natural number.

12. The memory device according to claim 9, wherein, The page buffer circuit includes a first page buffer and a second page buffer, each of which is configured to sense data from a memory cell via a corresponding bit line. The memory device further includes: The data input / output circuitry is configured to send data via multiple data pins. A first page buffer driver is configured to provide data from the first page buffer to the data input / output circuitry; and The second page buffer driver is configured to provide data from the second page buffer to the data input / output circuitry. Wherein, the first subset of the plurality of first bit lines is connected to the first subset of the first page buffer, the second subset of the plurality of first bit lines is connected to the first subset of the second page buffer, the first subset of the plurality of second bit lines is connected to the second subset of the first page buffer, and the second subset of the plurality of second bit lines is connected to the second subset of the second page buffer.

13. The memory device according to claim 9, wherein, The first subplane and the second subplane in the first region, The first page buffer and the second page buffer are in a second region, which is vertically aligned with and below the first region. The first subplane and the first page buffer overlap vertically with each other, and The second subplane and the second page buffer overlap each other perpendicularly.

14. The memory device according to claim 13, wherein, The plurality of first bit lines are separated from the plurality of second bit lines in the first horizontal direction and extend in the first wiring layer in the first horizontal direction, and A second subset of the plurality of first bit lines is connected to a first line, which extends in a second wiring layer within the first region from a region perpendicularly overlapping with the first page buffer to a region perpendicularly overlapping with a first subset of the second page buffer.

15. The memory device according to claim 14, wherein, The first subset of the plurality of second bit lines is connected to a second line, which extends in the second wiring layer from a region that vertically overlaps with the second page buffer to a region that vertically overlaps with the second subset of the first page buffer.

16. A memory device, comprising: Multiple subplanes are connected to multiple bit line groups, including a first bit line group and a second bit line group, each of the first bit line group and the second bit line group including multiple bit lines; Multiple page buffer groups, including a first page buffer group and a second page buffer group, each of the first page buffer group and the second page buffer group including multiple page buffers respectively configured to sense data via corresponding bit lines; The data input / output circuitry is configured to send data via multiple data pins. and Multiple page buffer drivers, each configured to provide data sensed by the multiple page buffer groups to the data input / output circuitry. Specifically, a first number of first bit lines in the first bit line group are connected to a first number of first page buffers in the first page buffer group; a second number of first bit lines in the first bit line group are connected to a second number of second page buffers in the second page buffer group; a third number of second bit lines in the second bit line group are connected to a third number of first page buffers in the first page buffer group; and a fourth number of second bit lines in the second bit line group are connected to a fourth number of second page buffers in the second page buffer group.

17. The memory device according to claim 16, wherein, During a read operation performed on a memory cell in the first subplane, which includes the plurality of subplanes: The first page buffer driver of the plurality of page buffer drivers is configured to provide the data sensed by the first number of first page buffers to the data input / output circuit via the first number of first bit lines, and The second page buffer driver of the plurality of page buffer drivers is configured to provide the data sensed by the second number of second page buffers to the data input / output circuit via the second number of first bit lines.

18. The memory device according to claim 17, wherein, During a read operation performed on a memory cell in a second subplane included in the plurality of subplanes: The first page buffer driver is configured to provide the data sensed by the third number of first page buffers to the data input / output circuit via the third number of second bit lines, and The second page buffer driver is configured to provide the data sensed by the fourth number of second page buffers to the data input / output circuit via the fourth number of second bit lines.

19. The memory device according to claim 18, wherein, The plurality of sub-planes in the first region, and The plurality of page buffer groups, the data input / output circuit, and the plurality of page buffer drivers are located in a second region, which is vertically disposed on the first region.

20. The memory device according to claim 19, wherein, The first bit line and the second bit line are separated from each other in a first horizontal direction and extend in a first wiring layer in the first horizontal direction. The second number of first lines are connected to the first line, which extends in the second wiring layer within the first region from a region that vertically overlaps with the first page buffer to a region that vertically overlaps with the second number of second page buffers.

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