Storage device configured to input and output data

Abstract

The present disclosure relates to a storage device configured to input and output data. A semiconductor chip includes a frequency division circuit configured to generate a latch clock signal based on a command clock signal and an inverted command clock signal generated in synchronization with a clock signal, and a command address input circuit configured to generate a first group of transmission command addresses having a second valid data window by latching an input rising command address and a falling command address having a first valid data window in synchronization with a first group of the latch clock signals among the latch clock signals, and configured to generate a second group of transmission command addresses having the second valid data window by latching the input rising command address and the falling command address having the first valid data window in synchronization with a second group of the latch clock signals among the latch clock signals.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0049809, filed with the Korean Intellectual Property Office on April 16, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to a storage device, and more specifically to a storage device configured to input and output data by providing an effective data window to one or more core chips by increasing the effective data window of the command address in the base chip. Background Technology

[0004] With the development of semiconductor device manufacturing technology, packaging technology for multiple core chips has also evolved. This advancement in packaging technology has enabled semiconductor devices to be highly integrated and manufactured at a higher level. In packaging technologies used to realize semiconductor devices, in addition to two-dimensional (2D) structures where multiple core chips are placed flat on a printed circuit board (PCB), various three-dimensional (3D) structures involving the vertical stacking of multiple core chips have been developed. Semiconductor devices with 3D structures can be implemented by stacking multiple core chips via through-silicon vias (TSVs), such as high-bandwidth memory (HBM), or by stacking multiple core chips via wire bonding.

[0005] Typically, access to the core chip can be achieved through the base chip. For example, after a read operation on the core chip begins, the base chip can transmit commands and addresses to the core chip via input / output lines included in the interface area. The core chip can receive the commands and addresses and transfer the data stored in the core chip to the base chip. The input / output lines included in the interface area are implemented using wires, resulting in a relatively long loading time; therefore, commands and addresses can be transmitted to the core chip via a separate repeater.

[0006] Furthermore, commands and addresses, input at the rising and falling edges of the clock signal and with short effective data windows, are transmitted to the core chip synchronously with the frequency-divided clock signal through multiple latching circuits. When the frequency-divided clock signal is generated continuously, the margin of the multiple latching circuits used to latch the commands and addresses may be insufficient. Summary of the Invention

[0007] In one embodiment, a semiconductor chip may include: a frequency divider circuit configured to generate a plurality of latch clock signals based on a command clock signal generated synchronously with a clock signal and an inverted command clock signal; and a command address input circuit configured to generate a first set of transmission command addresses with a second valid data window by latching an input rising command address and a falling command address having a first valid data window synchronously with a first set of latch clock signals among the plurality of latch clock signals, and configured to generate a second set of transmission command addresses with a second valid data window by latching an input rising command address and a falling command address having a first valid data window synchronously with a second set of latch clock signals among the plurality of latch clock signals.

[0008] In one embodiment, a storage device may include: a base chip configured to: generate a rising command address and a falling command address having a first valid data window by latching an external command address in an interface region in synchronization with a clock signal generated from an external clock signal and an inverted clock signal; configured to generate a plurality of transmission command addresses having a second valid data window by latching the rising command address and the falling command address in synchronization with a plurality of latching clock signals generated based on pulses of an inverted clock signal; and configured to output the plurality of transmission command addresses to a core chip through a via region. The core chip outputs data to the base chip by receiving the plurality of transmission command addresses. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating the construction of a storage system according to an embodiment of the present disclosure.

[0010] Figure 2 This is a block diagram illustrating the construction of a base chip according to an embodiment of the present disclosure.

[0011] Figure 3 This is a block diagram illustrating the construction of an address buffer circuit according to an embodiment of the present disclosure.

[0012] Figure 4 This is a timing diagram used to describe the operation of the clock buffer circuit and the address buffer circuit according to embodiments of the present disclosure.

[0013] Figure 5 This is a block diagram illustrating the construction of a frequency divider circuit according to an embodiment of the present disclosure.

[0014] Figure 6 This is a diagram illustrating the construction of a command clock signal generation circuit according to an embodiment of the present disclosure.

[0015] Figure 7 This is a diagram illustrating the construction of a frequency-divided clock signal generation circuit according to an embodiment of the present disclosure.

[0016] Figure 8 This is a block diagram illustrating the construction of a latch clock signal generation circuit according to an embodiment of the present disclosure.

[0017] Figure 9 This is a diagram illustrating the construction of an odd / even sensing circuit according to an embodiment of the present disclosure.

[0018] Figure 10 This is a circuit diagram illustrating the construction of a masking circuit according to an embodiment of the present disclosure.

[0019] Figure 11 and Figure 12 This is a timing diagram used to describe the operation of a base chip generating a transmission command address based on an inverted clock signal according to an embodiment of the present disclosure.

[0020] Figure 13 and Figure 14 It is a timing diagram used to describe the operation of a base chip generating a transmission command address based on a clock signal according to an embodiment of the present disclosure.

[0021] Figure 15 This is a diagram illustrating the arrangement of interface regions and via regions included in a base chip according to embodiments of the present disclosure. Detailed Implementation

[0022] In the following description of embodiments, terms such as "first" and "second" are used to distinguish between multiple components and are not limited to any particular component. For example, a first component may be referred to as a second component, and vice versa.

[0023] When a component is described as "coupled" or "connected" to another component, it should be understood that these components can be directly coupled or connected to each other, or can be coupled or connected to each other through another component in between. Conversely, when a component is described as "directly coupled" or "directly connected" to another component, it should be understood that these components are directly coupled or connected to each other without the intervention of another component.

[0024] "Logic high" and "logic low" are used to describe the logic level of a signal. A signal with a "logic high" level is distinct from a signal with a "logic low" level. For example, when a signal with a first voltage corresponds to a signal with a "logic high" level, a signal with a second voltage can correspond to a signal with a "logic low" level. According to an embodiment, a "logic high" level can be set to a voltage higher than a "logic low" level. According to one embodiment, the logic levels of a signal can be set to different logic levels or opposite logic levels. For example, a signal with a logic high level can be set to a logic low level in some embodiments, while a signal with a logic low level can be set to a logic high level in some embodiments.

[0025] The present disclosure will be described in more detail below through embodiments. These embodiments are for illustrative purposes only, and the scope of the present disclosure is not limited to these embodiments.

[0026] Figure 1 This is a block diagram illustrating the construction of a storage system 1 according to an embodiment of the present disclosure. Figure 1 As shown, the storage system 1 may include a printed circuit board (PCB) 11, a substrate 13, an interposer 15, a storage device 17, and a processor 19.

[0027] PCB 11 connects multiple electronic components to form an electronic circuit (not shown). A copper layer, a solder mask, and a silkscreen can be formed on PCB 11. Circuit paths for transmitting signals or power can be formed in the copper layer. In one embodiment, the solder mask prevents or mitigates damage to the circuit and protects specific areas where components can be soldered. Furthermore, the silkscreen indicates the location or information of the electronic components in the form of words or symbols printed on the surface of PCB 11.

[0028] The substrate 13 is formed on the PCB 11 via bump pads (e.g., 111) and can mechanically support the interposer 15, storage device 17, and processor 19. The substrate 13 is generally used as an insulator, forming the physical basis of the PCB 11. Materials for the substrate 13 include: flame retardant grade 4 (FR4), i.e., an insulator made of glass fiber and epoxy resin; ceramics, which are heat-resistant due to their thermal conductivity and are often used in high-frequency circuits or high-temperature environments; and polyimide, which is used as a base material for flexible PCBs due to its flexibility.

[0029] Interchange layer 15 is formed on substrate 13 via bump pads and may include wires connecting electronic components (e.g., storage device 17 and processor 19) with mismatched size specifications or pin arrangements. Interchange layer 15 can convert signals from different interfaces.

[0030] Storage device 17 can be formed on interposer layer 15 via microbump pads (e.g., 113). Storage device 17 can store data applied by processor 19 under the control of processor 19, or output data stored in storage device 17 to processor 19. Storage device 17 may include base chip 120 and multiple core chips 121-1 to 121-L. Multiple core chips 121-1 to 121-L can be stacked on or on base chip 120 via microbump pads. Base chip 120 and multiple core chips 121-1 to 121-L can be vertically connected via TSV. Base chip 120 can receive external clock signals (…). Figure 2 ECLK in the middle generates a clock signal ( Figure 2CLK) and inverted clock signal ( Figure 2 CLKB in the middle). The base chip 120 can be connected to a clock signal ( Figure 2 CLK) and inverted clock signal ( Figure 2 The CLKB in the middle synchronously latches the external command address ( Figure 2 The ECA in the middle is used to generate the rising command address that has the first valid data window. Figure 2 CAR in the middle) and descent command address ( Figure 2 CAF in the middle). Ascending command address ( Figure 2 CAR in the middle) and descent command address ( Figure 2 The first valid data window of each of the CAFs in the clock signal can be set to the clock signal. Figure 2 The base chip 120 can be based on the inverted clock signal (CLK) and the first cycle of the inverted clock signal CLKB. Figure 2 The pulse generation latch clock signal of CLKB in the middle ( Figure 2 The base chip 120 can be connected to a latched clock signal (LC-EV, LC-OD, LCB-EV, and LCB-OD). Figure 2 The LC-EV, LC-OD, LCB-EV, and LCB-OD in the middle synchronously latch the address of the rising command ( Figure 2 CAR in the middle) and descent command address ( Figure 2 The CAF (Content Filtering Function) is used to generate a transfer command address with a second valid data window. Figure 2 TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8. Transmission command address ( Figure 2 The second valid data window of TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8 can be set as the clock signal ( Figure 2 The fourth cycle of the inverted clock signal CLKB (CLK in the middle). The base chip 120 can be used in the interface area with long load ( Figure 15 Both the 1st PHY and 2nd PHY have the address of the rising command of the first valid data window (in the latch). Figure 2 CAR in the middle) and descent command address ( Figure 2 The CAF (Content Filtering Function) is used to generate a transfer command address with a second valid data window. Figure 2 The base chip 120 can transmit command addresses (TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8) through vias. Figure 2 The TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8 outputs to multiple core chips 121-1 to 121-L. The base chip 120 can output through vias (...). Figure 15 The 1st TSV and 2nd TSV will transmit the command address ( Figure 2 The base chip 120 outputs data from the core chips 121-1 to 121-L via vias (TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8). The base chip 120 receives data from the core chips 121-1 to 121-L via vias. The core chips 121-1 to 121-L can receive data via the transmission command address (…). Figure 2 The interfaces (TD1, TD2, TD3, TD4, TD5, TD6, TD7, and TD8) are used to output data to the base chip 120 through vias. Interface area ( Figure 15 The loading of the 1st PHY and 2nd PHY in the via region can be set to be greater than that of the via region. Figure 15 The loading time for the 1st TSV and 2nd TSV is longer. External clock signal ( Figure 2 The ECLK signal can be set to be periodically switched and received from processor 19. External command address ( Figure 2 The ECA (Electronic Control Address) in the processor 19 can be configured to include signals for controlling the operation of multiple core chips 121-1 to 121-L, and for receiving commands and addresses from the processor 19. The base chip 120 can be implemented using components such as a controller, a base chip, a semiconductor chip, or a semiconductor device to control the operation of the core chips 121-1 to 121-L. The core chips 121-1 to 121-L can be implemented using components such as a storage device, a core chip, a semiconductor chip, or a semiconductor device that stores data and outputs data stored in the core chip.

[0031] Each of the multiple core chips 121-1 to 121-L may include multiple channel regions, which store data and output the data stored in each channel region. Each of the multiple channel regions may be assigned an independently operating channel and may receive or transmit data. Each of the multiple channel regions may include a core region and may receive or transmit data. The number L of core chips 121-1 to 121-L may be 4, 8, 12, or 16. For example, when each of the core chips 121-1 to 121-12 has 8 channels, core chips 121-1 to 121-4, core chips 121-5 to 121-8, and core chips 121-9 to 121-12 each include 32 channel regions and may transmit and receive data from processor 19 in units of storage rank comprising 32 channels. The number L of core chips 121-1 to 121-L may be greater than 16.

[0032] Processor 19 can output an external clock signal to base chip 120 through wires formed within interposer layer 15. Figure 2 ECLK in the middle) and external command address ( Figure 2 (ECA in the middle). Processor 19 can receive data from base chip 120 through wires formed within interposer layer 15. Processor 19 can control the operation of base chip 120 and multiple core chips 121-1 to 121-L.

[0033] Figure 2 This is a block diagram illustrating the construction of a base chip 120 according to an embodiment of the present disclosure. Figure 2 As shown, the base chip 120 may include a clock buffer circuit (CLK BUF) 210, an address buffer circuit (ADD BUF) 230, a frequency divider circuit (FREQDIV CT) 250, a command address input circuit (CAINPUT CT) 270, and a through-hole area (TSV AREA) 290.

[0034] Clock buffer circuit 210 can generate clock signal CLK and inverted clock signal CLKB based on external clock signal ECLK. Clock buffer circuit 210 can generate periodically shifted clock signal CLK and inverted clock signal CLKB by buffering periodically shifted external clock signal ECLK. Clock buffer circuit 210 can generate clock signal CLK with the same phase as external clock signal ECLK. Clock buffer circuit 210 can generate inverted clock signal CLKB with a phase opposite to that of external clock signal ECLK. The operation of clock buffer circuit 210 generating clock signal CLK and inverted clock signal CLKB based on external clock signal ECLK will be described in a later reference. Figure 4 Describe it.

[0035] Address buffer circuit 230 can generate a rising command address CAR and a falling command address CAF based on the external command address ECA, synchronized with clock signal CLK and inverted clock signal CLKB. Address buffer circuit 230 can generate a rising command address CAR with a first valid data window based on the external command address ECA, synchronized with clock signal CLK. Address buffer circuit 230 can generate a falling command address CAF with a first valid data window based on the external command address ECA, synchronized with inverted clock signal CLKB. The operation of address buffer circuit 230 generating the rising command address CAR and falling command address CAF based on the external command address ECA in synchronization with clock signal CLK and inverted clock signal CLKB will be referred to later. Figure 4 Describe it.

[0036] Frequency divider circuit 250 can generate first to fourth latch clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD by dividing the frequency of the inverted clock signal CLKB. These latch clock signals are based on a command clock signal generated synchronously with the inverted clock signal CLKB. Figure 5 The pulse of MCLK and the inverted command clock signal (in the middle) Figure 5 It is generated by the pulse of MCLKB in the command clock signal (MCLKB). Figure 5 When the pulse of MCLK is received, the frequency divider circuit 250 can prevent the generation of either the first latch clock signal LC-EV or the second latch clock signal LC-OD. When the inverted command clock signal ( Figure 5 When the pulse of MCLKB is generated, the frequency divider circuit 250 can prevent the generation of one of the third latch clock signal LCB-EV and the fourth latch clock signal LCB-OD. The first latch clock signal LC-EV and the third latch clock signal LCB-EV can be set as the first group of latch clock signals. The second latch clock signal LC-OD and the fourth latch clock signal LCB-OD can be set as the second group of latch clock signals.

[0037] Frequency divider circuit 250 generates first to fourth latched clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD by dividing the frequency of the inverted clock signal CLKB. However, according to one embodiment, frequency divider circuit 250 can generate first to fourth latched clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD by dividing the frequency of the clock signal CLK.

[0038] Frequency divider circuit 250 can generate first to fourth frequency-divided clock signals ICLK, QCLK, IBCLK, and QBCLK by dividing the frequency of the inverted clock signal CLKB. Frequency divider circuit 250 can generate the first to fourth frequency-divided clock signals ICLK, QCLK, IBCLK, and QBCLK sequentially in sync with the inverted clock signal CLKB. The first to fourth frequency-divided clock signals ICLK, QCLK, IBCLK, and QBCLK can all be generated with a 90° phase difference. Frequency divider circuit 250 can output the first to fourth frequency-divided clock signals ICLK, QCLK, IBCLK, and QBCLK to via region 290. The first to fourth frequency-divided clock signals ICLK, QCLK, IBCLK, and QBCLK can be configured to latch the signals of the first to eighth transmission command addresses TD1 to TD8 within multiple core chips 121-1 to 121-L.

[0039] Frequency divider circuit 250 generates first to fourth frequency divided clock signals ICLK, QCLK, IBCLK, and QBCLK by dividing the frequency of the inverted clock signal CLKB. However, according to one embodiment, frequency divider circuit 250 can generate first to fourth frequency divided clock signals ICLK, QCLK, IBCLK, and QBCLK by dividing the frequency of the clock signal CLK.

[0040] The address input circuit 270 includes multiple latch circuits and can generate first to eighth transfer command addresses TD1 to TD8 with second valid data windows by latching the rising command address CAR and falling command address CAF input via the multiple latch circuits, which have first valid data windows. The command address input circuit 270 can generate first to eighth transfer command addresses TD1 to TD8 with second valid data windows by latching the rising command address CAR and falling command address CAF input with first valid data windows synchronously with the first to fourth latch clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD. The command address input circuit 270 can generate first transfer command address TD1 and second transfer command address TD2 with second valid data windows by latching the rising command address CAR and falling command address CAF input with first valid data windows synchronously with the first latch clock signal LC-EV. Command address input circuit 270 can generate third transfer command addresses TD3 and fourth transfer command addresses TD4 with second valid data windows by latching the rising command address CAR and falling command address CAF with first valid data windows synchronously with the third latch clock signal LCB-EV. Command address input circuit 270 can generate fifth transfer command addresses TD5 and sixth transfer command addresses TD6 with second valid data windows by latching the rising command address CAR and falling command address CAF with first valid data windows synchronously with the second latch clock signal LC-OD. Command address input circuit 270 can generate seventh transfer command addresses TD7 and eighth transfer command addresses TD8 with second valid data windows by latching the rising command address CAR and falling command address CAF with first valid data windows synchronously with the fourth latch clock signal LCB-OD. Command address input circuit 270 can output the first to eighth transfer command addresses TD1 to TD8 to the via region 290 through command input / output line MIO. The first to eighth transmission command addresses TD1 to TD8 can all be configured to contain signals that control the operation of multiple core chips 121-1 to 121-L, including commands and addresses. The command input / output line MIO can be implemented using a single wire with a long load, or multiple wires. In one embodiment, the wire with a long load can be referred to as a heavy-load wire or a long-load wire. The first to fourth transmission command addresses TD1 to TD4 can be configured as a first group of transmission command addresses. The fifth to eighth transmission command addresses TD5 to TD8 can be configured as a second group of transmission command addresses.

[0041] The via region 290 can be implemented by including multiple vias. The via region 290 can output the first to eighth transmission command addresses TD1 to TD8 to multiple core chips 121-1 to 121-L through multiple vias. The via region 290 can also output the first to fourth frequency-divided clock signals ICLK, QCLK, IBCLK, and QBCLK to multiple core chips 121-1 to 121-L through multiple vias. The via region 290 can output data to or receive data from multiple core chips 121-1 to 121-L through multiple vias.

[0042] Figure 2 The clock buffer circuit 210, address buffer circuit 230, frequency divider circuit 250, and command address input circuit 270 shown can be included in the interface area. Figure 15 The 1st PHY and 2nd PHY are included in the via region. The via region 290 can be included in the via region (…). Figure 15 In the 1st TSV and 2nd TSV.

[0043] Figure 3 This is a block diagram illustrating the construction of an address buffer circuit 230 according to an embodiment of the present disclosure. Figure 3 As shown, the address buffer circuit 230 may include flip-flops (F / F) 231 and 233.

[0044] Flip-flop 231 can generate a rising command address CAR based on the external command address ECA in sync with the clock signal CLK. When the level of the clock signal CLK pulse changes from logic low to logic high, flip-flop 231 can latch the external command address ECA. Flip-flop 231 can output the external command address ECA latched when the level of the clock signal CLK pulse changes from logic high to logic low as the rising command address CAR.

[0045] Flip-flop 233 can generate a falling command address (CAF) based on the external command address (ECA) synchronously with the inverted clock signal CLKB. When the pulse level of the inverted clock signal CLKB transitions from logic low to logic high, flip-flop 233 can latch the external command address (ECA). Flip-flop 233 can output the external command address (ECA) latched when the pulse level of the inverted clock signal CLKB transitions from logic low to logic high as the falling command address (CAF).

[0046] Figure 4 This is a timing diagram used to describe the operation of the clock buffer circuit 210 and the address buffer circuit 230 according to embodiments of the present disclosure.

[0047] The operation reference for generating clock signal CLK and inverted clock signal CLKB based on external clock signal ECLK by clock buffer circuit 210 Figure 4 The description is as follows.

[0048] At timing T1, the clock buffer circuit 210 can generate a clock signal CLK with the same phase as the external clock signal ECLK by buffering the periodically changing external clock signal ECLK.

[0049] At timing T1, the clock buffer circuit 210 can generate an inverted clock signal CLKB with a phase opposite to that of the external clock signal ECLK by buffering the periodically changing external clock signal ECLK.

[0050] The address buffer circuit 230 synchronously generates the rising command address CAR and falling command address CAF based on the external command address ECA, using the clock signal CLK and the inverted clock signal CLKB as operating references. Figure 4 The description is as follows.

[0051] In one embodiment, the external command address ECA can be input to include the first through sixteenth bits sequentially input into the address buffer circuit 230. The effective data window of the external command address ECA can be set to have a period of half the period of the clock signal CLK and the inverted clock signal CLKB.

[0052] At timing T1, when the pulse level of the clock signal CLK changes from logic low to logic high, the flip-flop 231 of the address buffer circuit 230 can latch the first bit ECA of the external command address ECA. <1> .

[0053] At timing T2, the flip-flop 231 of the address buffer circuit 230 can output the first bit of the external command address ECA, which is latched when the level of the clock signal CLK pulse changes from logic high to logic low. <1> As the ascending command address CAR.

[0054] At timing T2, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the flip-flop 233 of the address buffer circuit 230 can latch the second bit ECA of the external command address. <2> The flip-flop 233 of the address buffer circuit 230 can latch the second bit ECA of the external command address when the pulse level of the inverted clock signal CLKB changes from logic low to logic high. <2> As the descent command address, the CAF output.

[0055] At timing T3, when the pulse level of the clock signal CLK changes from logic low to logic high, the flip-flop 231 of the address buffer circuit 230 can latch the third bit ECA of the external command address ECA. <3> .

[0056] At timing T4, flip-flop 231 of address buffer circuit 230 can latch the third bit ECA of external command address when the pulse level of clock signal CLK changes from logic high to logic low. <4> The output is given as the address CAR for the ascending command.

[0057] At timing T4, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the flip-flop 233 of the address buffer circuit 230 can latch the fourth bit ECA of the external command address. <4> The flip-flop 233 of the address buffer circuit 230 can latch the fourth bit ECA of the external command address when the pulse level of the inverted clock signal CLKB changes from logic low to logic high. <4> The output is given as the descent command address (CAF).

[0058] The first valid data window of the rising command address CAR can be set to the first cycle of the clock signal CLK and the inverted clock signal CLKB. The first valid data window of the falling command address CAF can be set to the first cycle of the clock signal CLK and the inverted clock signal CLKB.

[0059] In this case, the operation of generating the rising command address CAR and the falling command address CAF from the fifth to sixteenth bits of the external command address ECA<5:16> is the same as the operation of generating the rising command address CAR and the falling command address CAF from the first to fourth bits of the external command address ECA<1:4>, so its detailed description is omitted.

[0060] Figure 5 This is a block diagram illustrating the construction of a frequency divider circuit 250 according to an embodiment of the present disclosure. Figure 5 As shown, the frequency divider circuit 250 may include a command clock signal generation circuit (MCLK GEN) 251, a frequency divider clock signal generation circuit (ICLK GEN) 253, and a latch clock signal generation circuit (LC GEN) 255.

[0061] The command clock signal generation circuit 251 can generate a command clock signal MCLK and an inverted command clock signal MCLKB that are generated synchronously with the inverted clock signal CLKB. The command clock signal generation circuit 251 can generate the command clock signal MCLK and the inverted command clock signal MCLKB initialized after the power-down operation begins. The command clock signal generation circuit 251 can generate the command clock signal MCLK and the inverted command clock signal MCLKB by dividing the frequency of the inverted clock signal CLKB after the power-down operation. The command clock signal generation circuit 251 can generate the command clock signal MCLK, the level of which changes when the pulse level of the inverted clock signal CLKB changes from logic low to logic high. The command clock signal generation circuit 251 can also generate the inverted command clock signal MCLKB, the level of which changes when the pulse level of the inverted clock signal CLKB changes from logic low to logic high. The command clock signal generation circuit 251 can generate a command clock signal MCLK and an inverted command clock signal MCLKB with opposite phases when the pulse level of the inverted clock signal CLKB transitions from logic low to logic high. The power-down operation can be configured to prevent operation from being performed due to a power outage to the storage device 17.

[0062] The frequency divider clock signal generation circuit 253 can divide the frequencies of the command clock signal MCLK and the inverted command clock signal MCLKB to generate first to fourth frequency divider clock signals ICLK, QCLK, IBCLK, and QBCLK. The frequency divider clock signal generation circuit 253 can generate the first to fourth frequency divider clock signals ICLK, QCLK, IBCLK, and QBCLK sequentially and synchronously with the command clock signal MCLK and the inverted command clock signal MCLKB. The first to fourth frequency divider clock signals ICLK, QCLK, IBCLK, and QBCLK can all be generated with a 90° phase difference. The frequency divider clock signal generation circuit 253 can output the first to fourth frequency divider clock signals ICLK, QCLK, IBCLK, and QBCLK to the via region 290.

[0063] The latch clock signal generation circuit 255 can generate first to fourth latch clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD based on pulses of the command clock signal MCLK and the inverted command clock signal MCLKB. The latch clock signal generation circuit 255 can generate one of the first latch clock signal LC-EV and the second latch clock signal LC-OD when a pulse of the command clock signal MCLK with a logic high level is generated. The latch clock signal generation circuit 255 can prevent the generation of one of the first latch clock signal LC-EV and the second latch clock signal LC-OD when a pulse of the command clock signal MCLK with a logic high level is generated. The latch clock signal generation circuit 255 can generate one of the third latch clock signal LCB-EV and the fourth latch clock signal LCB-OD when a pulse of the inverted command clock signal MCLKB with a logic high level is generated. The latch clock signal generation circuit 255 can prevent the generation of one of the third latch clock signal LCB-EV and the fourth latch clock signal LCB-OD when the pulse of the inverted command clock signal MCLKB with a logic high level is generated.

[0064] Figure 6 This is a diagram illustrating the construction of a command clock signal generation circuit 251 according to an embodiment of the present disclosure. Figure 6 As shown, the command clock signal generation circuit 251 may include a first command clock signal generation circuit 251-1 and a second command clock signal generation circuit 251-3.

[0065] The first command clock signal generation circuit 251-1 may include a first initialization circuit 251-11, an inverter 251-12, and a flip-flop (F / F) 251-13. The first initialization circuit 251-11 can generate a command clock signal MCLK initialized to a first logic level (logic low level) when the power-down signal PD is enabled to a logic high level. The first initialization circuit 251-11 can also initialize the command clock signal MCLK to a logic low level (first logic level) by driving the command clock signal MCLK with the ground voltage VSS when the power-down signal PD is enabled to a logic high level. The inverter 251-12 can invert and output the command clock signal MCLK. The flip-flop 251-13 can generate the command clock signal MCLK by latching the output signal of the inverter 251-12 when the pulse level of the inverted clock signal CLKB transitions from a logic low level to a logic high level. The first command clock signal generation circuit 251-1 can generate a command clock signal MCLK that is initialized to a logic low level (first logic level) by the power-down signal PD. The first command clock signal generation circuit 251-1 can also generate the command clock signal MCLK when the pulse level of the inverted clock signal CLKB transitions from a logic low level to a logic high level. Thus, the first command clock signal generation circuit 251-1 generates a command clock signal MCLK that transitions synchronously with the inverted clock signal CLKB. The power-down signal PD can be set to be enabled to a logic high level after the power-down operation begins.

[0066] The second command clock signal generation circuit 251-3 may include a second initialization circuit 251-31, an inverter 251-32, and a flip-flop (F / F) 251-33. The second initialization circuit 251-31 can generate an inverted command clock signal MCLKB initialized to a logic high level (second logic level) when the power-down signal PD is enabled to a logic high level. The second initialization circuit 251-31 can initialize the inverted command clock signal MCLKB to a logic high level (second logic level) by driving the inverted command clock signal MCLKB with the power supply voltage VDD when the power-down signal PD is enabled to a logic high level. The inverter 251-32 can invert and output the inverted command clock signal MCLKB. The flip-flop 251-33 can generate the inverted command clock signal MCLKB by latching the output signal of the inverter 251-32 when the pulse level of the inverted clock signal CLKB changes from a logic low level to a logic high level. The second command clock signal generation circuit 251-3 can generate an inverted command clock signal MCLKB that is initialized to a logic high level (second logic level) by the power-down signal PD. The second command clock signal generation circuit 251-3 can also generate an inverted command clock signal MCLKB whose level changes when the pulse level of the inverted clock signal CLKB changes from logic low to logic high. Thus, the second command clock signal generation circuit 251-3 generates an inverted command clock signal MCLKB that changes synchronously with the inverted clock signal CLKB.

[0067] Figure 7 This is a diagram illustrating the construction of a frequency-divided clock signal generation circuit 253 according to an embodiment of the present disclosure. The frequency-divided clock signal generation circuit 253 may include a first frequency-divided clock signal generation circuit 253-1, a second frequency-divided clock signal generation circuit 253-2, a third frequency-divided clock signal generation circuit 253-3, and a fourth frequency-divided clock signal generation circuit 253-4.

[0068] The first frequency divider clock generation circuit 253-1 may include an inverter 253-11 and a flip-flop (F / F) 253-12. The inverter 253-11 inverts and outputs the first frequency divider clock signal ICLK. The flip-flop 253-12 latches the output signal of the inverter 253-11 when the command clock signal MCLK transitions from logic low to logic high. The flip-flop 253-12 outputs the output signal of the inverter 253-11 latched when the command clock signal MCLK transitions from logic low to logic high, serving as the first frequency divider clock signal ICLK. The first frequency divider clock generation circuit 253-1 generates the first frequency divider clock signal ICLK, the level of which changes whenever the command clock signal MCLK transitions from logic low to logic high.

[0069] The second clock divider generation circuit 253-2 may include a flip-flop (F / F) 253-21. Flip-flop 253-21 latches the first divided clock signal ICLK when the level of the inverted command clock signal MCLKB transitions from logic low to logic high. Flip-flop 253-21 can output the latched first divided clock signal ICLK when the level of the inverted command clock signal MCLKB transitions from logic low to logic high, as the second divided clock signal QCLK. The second clock divider generation circuit 253-2 can generate the second divided clock signal QCLK, the level of which changes whenever the level of the inverted command clock signal MCLKB transitions from logic low to logic high.

[0070] The third clock divider generation circuit 253-3 may include a flip-flop (F / F) 253-31. Flip-flop 253-31 latches the second clock divider signal QCLK when the command clock signal MCLK transitions from logic low to logic high. Flip-flop 253-31 outputs the second clock divider signal QCLK latched when the command clock signal MCLK transitions from logic low to logic high, as the third clock divider signal IBCLK. The third clock divider generation circuit 253-3 generates the third clock divider signal IBCLK, the level of which changes whenever the command clock signal MCLK transitions from logic low to logic high.

[0071] The fourth divider clock generation circuit 253-4 may include a flip-flop (F / F) 253-41. Flip-flop 253-41 latches the third divider clock signal IBCLK when the level of the inverted command clock signal MCLKB transitions from logic low to logic high. Flip-flop 253-41 outputs the latched third divider clock signal IBCLK when the level of the inverted command clock signal MCLKB transitions from logic low to logic high, as the fourth divider clock signal QBCLK. The fourth divider clock generation circuit 253-4 generates the fourth divider clock signal QBCLK, the level of which changes whenever the level of the inverted command clock signal MCLKB transitions from logic low to logic high.

[0072] Figure 8 This is a block diagram illustrating the construction of a latch clock signal generation circuit 255 according to an embodiment of the present disclosure. The latch clock signal generation circuit 255 may include an even / odd number sensing circuit (EV / OD DET CT) 255-1 and a masking circuit (MAKCT) 255-2.

[0073] The even-odd number sensing circuit 255-1 can generate the first even number flag signal EV-FL1 and the second even number flag signal EV-FL2, as well as the first odd number flag signal OD-FL1 and the second odd number flag signal OD-FL2, by detecting the input timing of the pulse of the command clock signal MCLK and the pulse of the inverted command clock signal MCLKB.

[0074] The even / odd number sensing circuit 255-1 can generate a first even number flag signal EV-FL1 and a first odd number flag signal OD-FL1 based on the pulse of the command clock signal MCLK. The even / odd number sensing circuit 255-1 can generate the first even number flag signal EV-FL1, the level of which changes when the level of the pulse of the command clock signal MCLK changes from logic high to logic low. The even / odd number sensing circuit 255-1 can generate the first odd number flag signal OD-FL1, the level of which changes when the level of the pulse of the command clock signal MCLK changes from logic high to logic low.

[0075] The even / odd number sensing circuit 255-1 can generate a second even number flag signal EV-FL2 ​​and a second odd number flag signal OD-FL2 based on the pulse of the inverted command clock signal MCLKB. The even / odd number sensing circuit 255-1 can generate the second even number flag signal EV-FL2, the level of which changes when the level of the pulse of the inverted command clock signal MCLKB transitions from logic high to logic low. The even / odd number sensing circuit 255-1 can generate the second odd number flag signal OD-FL2, the level of which changes when the level of the pulse of the inverted command clock signal MCLKB transitions from logic high to logic low.

[0076] When the pulses of the command clock signal MCLK and the inverted command clock signal MCLKB are generated, the masking circuit 255-2 can generate the first to fourth latch clock signals LC-EV, LC-OD, LCB-EV and LCB-OD based on the logic levels of the first even flag signal EV-FL1 and the second even flag signal EV-FL2, as well as the logic levels of the first odd flag signal OD-FL1 and the second odd flag signal OD-FL2.

[0077] When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic high level is generated, the masking circuit 255-2 can generate a first latch clock signal LC-EV with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the masking circuit 255-2 can generate a first latch clock signal LC-EV with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the masking circuit 255-2 can prevent the generation of the first latch clock signal LC-EV.

[0078] When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic high level is generated, the masking circuit 255-2 can generate a second latch clock signal LC-OD with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the masking circuit 255-2 can generate a second latch clock signal LC-OD with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the masking circuit 255-2 can prevent the generation of the second latch clock signal LC-OD.

[0079] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic high level is generated, the masking circuit 255-2 can generate a third latch clock signal LCB-EV with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the masking circuit 255-2 can generate a third latch clock signal LCB-EV with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the masking circuit 255-2 can prevent the generation of the third latch clock signal LCB-EV.

[0080] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic high level is generated, the masking circuit 255-2 can generate a fourth latch clock signal LCB-OD with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the masking circuit 255-2 can generate a fourth latch clock signal LCB-OD with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the masking circuit 255-2 can prevent the generation of the fourth latch clock signal LCB-OD.

[0081] Figure 9 This is a diagram illustrating the construction of an even / odd number sensing circuit 255-1 according to an embodiment of the present disclosure. The even / odd number sensing circuit 255-1 may include a first flag signal generation circuit 310 and a second flag signal generation circuit 320.

[0082] The first flag signal generation circuit 310 may include a first even-number sensing circuit 311 and a first odd-number sensing circuit 312. The first even-number sensing circuit 311 may be implemented using inverters 311-1 and 311-2 and flip-flops (F / F) 311-3. The first even-number sensing circuit 311 may generate a first even-number flag signal EV-FL1, which is switched when a pulse of the command clock signal MCLK with a logic low level (first logic level) is generated. The first even-number flag signal EV-FL1 may be configured to be initialized to a logic high level. The first odd-number sensing circuit 312 may be implemented using flip-flops (F / F) 312-1. The first odd-number sensing circuit 312 may latch the first even-number flag signal EV-FL1. The first odd-number sensing circuit 312 may output the first even-number flag signal EV-FL1 latched when a pulse of the command clock signal MCLK with a logic low level (first logic level) is generated, as the first odd-number flag signal OD-FL1. The first odd-number sensing circuit 312 can generate a first odd-number flag signal OD-FL1, which is switched when a pulse of the command clock signal MCLK with a logic low level (first logic level) is generated. The first odd-number flag signal OD-FL1 can be set to be initialized to a logic low level. The first flag signal generation circuit 310 can generate a first even-number flag signal EV-FL1 and a first odd-number flag signal OD-FL1, which are switched when a pulse of the command clock signal MCLK with a logic low level (first logic level) is generated.

[0083] The second flag signal generation circuit 320 may include a second even-number sensing circuit 321 and a second odd-number sensing circuit 322. The second even-number sensing circuit 321 may be implemented using inverters 321-1 and 321-2 and flip-flops (F / F) 321-3. The second even-number sensing circuit 321 may generate a second even-number flag signal EV-FL2, which is switched when a pulse of the inverted command clock signal MCLKB with a logic low level (first logic level) is generated. The second even-number flag signal EV-FL2 ​​may be configured to be initialized to a logic low level. The second odd-number sensing circuit 322 may be implemented using flip-flops (F / F) 322-1. The second odd-number sensing circuit 322 may latch the second even-number flag signal EV-FL2. The second odd-number sensing circuit 322 may output the second even-number flag signal EV-FL2 ​​latched when a pulse of the inverted command clock signal MCLKB with a logic low level (first logic level) is generated, as the second odd-number flag signal OD-FL2. The second odd-number sensing circuit 322 can generate a second odd-number flag signal OD-FL2, which is switched when a pulse of the inverted command clock signal MCLKB with a logic low level (first logic level) is generated. The second odd-number flag signal OD-FL2 can be set to be initialized to a logic low level. The second flag signal generation circuit 320 can generate a second even-number flag signal EV-FL2 ​​and a second odd-number flag signal OD-FL2, which are switched when a pulse of the inverted command clock signal MCLKB with a logic low level (first logic level) is generated.

[0084] Figure 10 This is a circuit diagram illustrating the construction of a masking circuit 255-2 according to an embodiment of the present disclosure. The masking circuit 255-2 may include a first logic circuit 330 and a second logic circuit 340.

[0085] The first logic circuit 330 can be implemented using AND gates 331 and 332. AND gate 331 generates the first latch clock signal LC-EV by performing a bitwise AND operation on the command clock signal MCLK and the first even-number flag signal EV-FL1. AND gate 331 can also generate the first latch clock signal LC-EV based on the logic level of the command clock signal MCLK and the first even-number flag signal EV-FL1. AND gate 332 generates the second latch clock signal LC-OD by performing a bitwise AND operation on the command clock signal MCLK and the first odd-number flag signal OD-FL1. AND gate 332 can also generate the second latch clock signal LC-OD based on the logic level of the command clock signal MCLK and the first odd-number flag signal OD-FL1.

[0086] When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic high level is generated, the first logic circuit 330 can generate a first latch clock signal LC-EV with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 can generate a first latch clock signal LC-EV with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 can prevent the generation of the first latch clock signal LC-EV. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic high level is generated, the first logic circuit 330 can generate a second latch clock signal LC-OD with a logic high level. When a command clock signal MCLKd pulse with a logic high level is generated and a first odd flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 can generate a second latch clock signal LC-OD with a logic low level. When a command clock signal MCLK pulse with a logic high level is generated and a first odd flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 can prevent the generation of the second latch clock signal LC-OD.

[0087] The second logic circuit 340 can be implemented using AND gates 341 and 342. AND gate 341 generates the third latch clock signal LCB-EV by performing a bitwise AND operation on the inverted command clock signal MCLKB and the second even-number flag signal EV-FL2. AND gate 341 can also generate the third latch clock signal LCB-EV based on the logic level of the inverted command clock signal MCLKB and the second even-number flag signal EV-FL2. AND gate 342 generates the fourth latch clock signal LCB-OD by performing a bitwise AND operation on the inverted command clock signal MCLKB and the second odd-number flag signal OD-FL2. AND gate 342 can also generate the fourth latch clock signal LCB-OD based on the logic level of the inverted command clock signal MCLKB and the second odd-number flag signal OD-FL2.

[0088] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic high level is generated, the second logic circuit 340 can generate a third latch clock signal LCB-EV with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 can generate a third latch clock signal LCB-EV with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 can prevent the generation of the third latch clock signal LCB-EV. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic high level is generated, the second logic circuit 340 can generate a fourth latch clock signal LCB-OD with a logic high level. When the pulse of the inverted command clock signal MCLKB with a logic high level is generated and the second odd flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 can generate the fourth latch clock signal LCB-OD with a logic low level. When the pulse of the inverted command clock signal MCLKB with a logic high level is generated and the second odd flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 can prevent the generation of the fourth latch clock signal LCB-OD.

[0089] For reference Figure 11 and Figure 12 As an example, according to an embodiment of this disclosure, the operation of generating first to eighth transmission command addresses TD1 to TD8 with a second valid data window by increasing the first valid data window of the rising command address CAR and the valid data window of the falling command address CAF by means of the inverted clock signal CLKB in the interface region of the base chip 120 with a long load is described below.

[0090] First, refer to Figure 11 Describes the operation of generating the first to fourth latch clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD based on the pulse of the inverted clock signal CLKB in the interface area.

[0091] At timing T11, after the power-down operation PD begins, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK initialized to logic low (first logic level). After the power-down operation PD begins, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB initialized to logic high (second logic level).

[0092] At timing T12, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0093] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even number flag signal EV-FL2 ​​whose level changes from logic low to logic high.

[0094] When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a first latch clock signal LC-EV with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 generates a second latch clock signal LC-OD with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the second latch clock signal LC-OD.

[0095] In timing T13, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0096] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic high to logic low. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic low to logic high.

[0097] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a third latch clock signal LCB-EV with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 generates a fourth latch clock signal LCB-OD with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 prevents the generation of the fourth latch clock signal LCB-OD.

[0098] At timing T14, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0099] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even-number flag signal EV-FL2 ​​whose level changes from logic high to logic low. When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 generates a second odd-number flag signal OD-FL2 whose level changes from logic low to logic high.

[0100] When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a second latch clock signal LC-OD with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 generates a first latch clock signal LC-EV with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the first latch clock signal LC-EV.

[0101] At timing T15, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0102] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic low to logic high. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic high to logic low.

[0103] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a fourth latch clock signal LCB-OD with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 generates a third latch clock signal LCB-EV with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 prevents the generation of the third latch clock signal LCB-EV.

[0104] At timing T16, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0105] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even number flag signal EV-FL2 ​​whose level changes from logic low to logic high.

[0106] When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a first latch clock signal LC-EV with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 generates a second latch clock signal LC-OD with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the second latch clock signal LC-OD.

[0107] At timing T17, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0108] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic high to logic low. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic low to logic high.

[0109] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a third latch clock signal LCB-EV with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 generates a fourth latch clock signal LCB-OD with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 prevents the generation of the fourth latch clock signal LCB-OD.

[0110] At timing T18, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0111] When the pulse of the inverted command clock signal MCLKB transitions from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even-number flag signal EV-FL2 ​​whose level transitions from logic high to logic low. When the pulse of the inverted command clock signal MCLKB transitions from logic high to logic low, the second flag signal generation circuit 320 generates a second odd-number flag signal OD-FL2 whose level transitions from logic low to logic high.

[0112] When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a second latch clock signal LC-OD with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 generates a first latch clock signal LC-EV with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the first latch clock signal LC-EV.

[0113] In timing T19, when the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the inverted clock signal CLKB changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0114] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic low to logic high. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic high to logic low.

[0115] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a fourth latch clock signal LCB-OD with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 generates a third latch clock signal LCB-EV with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 prevents the generation of the third latch clock signal LCB-EV.

[0116] By increasing the first valid data window of the rising command address CAR and the valid data window of the falling command address CAF based on the first to fourth latch clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD in the interface region, an operation reference with a second valid data window is generated for the first to eighth transmission command addresses TD1 to TD8. Figure 12 It is described as follows.

[0117] At timing T21, the command address input circuit 270 generates a first transfer command address TD1 by latching the rising command address CAR with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The command address input circuit 270 generates a second transfer command address TD2 by latching the falling command address CAF with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The first transfer command address TD1 is derived from the first bit ECA of the external command address. <1> Generate. The second transmission command address TD2 is generated from the second bit ECA of the external command address. <2> Generation. Timing T21 is set to... Figure 11 The timing is the same as that of timing T12.

[0118] At timing T22, the command address input circuit 270 generates the third transfer command address TD3 by latching the rising command address CAR with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The command address input circuit 270 generates the fourth transfer command address TD4 by latching the falling command address CAF with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The third transfer command address TD3 is derived from the third bit ECA of the external command address. <3> Generate. The fourth transmission command address TD4 is generated from the fourth bit (ECA) of the external command address. <4> Generation. Timing T22 is set to... Figure 11 The timing is the same as that of timing T13 in the original text.

[0119] At timing T23, the command address input circuit 270 generates the fifth transfer command address TD5 by latching the rising command address CAR with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The command address input circuit 270 generates the sixth transfer command address TD6 by latching the falling command address CAF with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The fifth transfer command address TD5 is derived from the fifth bit ECA of the external command address. <5> Generate. The sixth transmission command address TD6 is generated from the sixth bit of the external command address, ECA. <6> Generation. Timing T23 is set to... Figure 11 The timing is the same as that of timing T14 in the original text.

[0120] At timing T24, the command address input circuit 270 generates the seventh transfer command address TD7 by latching the rising command address CAR with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The command address input circuit 270 generates the eighth transfer command address TD8 by latching the falling command address CAF with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The seventh transfer command address TD7 is derived from the seventh bit ECA of the external command address. <7> Generate. The eighth transmission command address TD8 is generated from the eighth bit of the external command address (ECA). <8> Generate. Timing T24 is set to... Figure 11 The timing is the same as that of timing T15.

[0121] At timing T25, the command address input circuit 270 generates a first transfer command address TD1 by latching the rising command address CAR with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The command address input circuit 270 generates a second transfer command address TD2 by latching the falling command address CAF with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The first transfer command address TD1 is derived from the ninth bit ECA of the external command address. <9> Generate. The second transmission command address TD2 is generated from the tenth bit (ECA) of the external command address. <10> Generate. Timing T25 is set to... Figure 11 The timing is the same as that of timing T16 in the original text.

[0122] At timing T26, the command address input circuit 270 generates the third transfer command address TD3 by latching the rising command address CAR with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The command address input circuit 270 generates the fourth transfer command address TD4 by latching the falling command address CAF with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The third transfer command address TD3 is derived from the eleventh bit ECA of the external command address. <11> Generate. The fourth transmission command address TD4 is generated from the twelfth bit (ECA) of the external command address. <12> Generation. Timing T26 is set to... Figure 11 The timing is the same as that of timing T17 in the system.

[0123] At timing T27, the command address input circuit 270 generates the fifth transfer command address TD5 by latching the rising command address CAR with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The command address input circuit 270 generates the sixth transfer command address TD6 by latching the falling command address CAF with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The fifth transfer command address TD5 is derived from the thirteenth bit ECA of the external command address. <13> Generate. The sixth transmission command address TD6 is generated from the fourteenth bit of the external command address, ECA. <14> Generate. Timing T27 is set to... Figure 11 The timing is the same as that of timing T18.

[0124] At timing T28, the command address input circuit 270 generates the seventh transfer command address TD7 by latching the rising command address CAR with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The command address input circuit 270 generates the eighth transfer command address TD8 by latching the falling command address CAF with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The seventh transfer command address TD7 is derived from the fifteenth bit ECA of the external command address. <15> Generate. The eighth transmission command address TD8 is generated from the sixteenth bit of the external command address, ECA. <16> Generate. Timing T28 is set to... Figure 11 The timing is the same as that of timing T19.

[0125] like Figure 12As shown, the first transmission command address TD1 and the second transmission command address TD2 are generated during timings T21 to T25 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO. The third transmission command address TD3 and the fourth transmission command address TD4 are generated during timings T22 to T26 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO. The fifth transmission command address TD5 and the sixth transmission command address TD6 are generated during timings T23 to T27 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO. The seventh transmission command address TD7 and the eighth transmission command address TD8 are generated during timings T24 to T28 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO.

[0126] As described above, the storage device 17 of the storage system 1 according to an embodiment of the present disclosure generates a command address by increasing the effective data window of the command address in the interface region of the base chip 120 with a long load, and provides the command address with the increased effective data window to multiple core chips without the need for a repeater to transmit the command address, thereby reducing the power consumption used in the repeater. Since the base chip 120 generates the command address by increasing the effective data window of the command address without using a divider clock for latching and transmitting the command address, and provides the command address with the increased effective data window to multiple core chips, the storage device 17 of the storage system 1 can ensure the margin of the latching circuit.

[0127] The following is for reference. Figure 13 and Figure 14 As an example, according to an embodiment of the present disclosure, the operation of generating first to eighth transmission command addresses TD1 to TD8 with a second valid data window is described in the interface region of a base chip 120 with a long load by increasing the first valid data window of the rising command address CAR and the valid data window of the falling command address CAF with the aid of a clock signal CLK.

[0128] First, the operation reference for generating the first to fourth latch clock signals LC-EV, LC-OD, LCB-EV, and LCB-OD based on the pulse of the clock signal CLK in the interface area. Figure 13 Describe it.

[0129] At timing T31, after the power-down operation PD begins, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK initialized to logic low (first logic level). After the power-down operation PD begins, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB initialized to logic high (second logic level).

[0130] In timing T32, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0131] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even number flag signal EV-FL2 ​​whose level changes from logic low to logic high.

[0132] When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a first latch clock signal LC-EV with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 generates a second latch clock signal LC-OD with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the second latch clock signal LC-OD.

[0133] In timing T33, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0134] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic high to logic low. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic low to logic high.

[0135] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a third latch clock signal LCB-EV with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 generates a fourth latch clock signal LCB-OD with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 prevents the generation of the fourth latch clock signal LCB-OD.

[0136] In timing T34, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0137] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even-number flag signal EV-FL2 ​​whose level changes from logic high to logic low. When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 generates a second odd-number flag signal OD-FL2 whose level changes from logic low to logic high.

[0138] When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a second latch clock signal LC-OD with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 generates a first latch clock signal LC-EV with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the first latch clock signal LC-EV.

[0139] At timing T35, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0140] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic low to logic high. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic high to logic low.

[0141] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a fourth latch clock signal LCB-OD with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 generates a third latch clock signal LCB-EV with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 prevents the generation of the third latch clock signal LCB-EV.

[0142] In timing T36, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0143] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even number flag signal EV-FL2 ​​whose level changes from logic low to logic high.

[0144] When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a first latch clock signal LC-EV with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 generates a second latch clock signal LC-OD with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the second latch clock signal LC-OD.

[0145] In timing T37, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0146] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic high to logic low. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic low to logic high.

[0147] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a third latch clock signal LCB-EV with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 generates a fourth latch clock signal LCB-OD with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic low level is generated, the second logic circuit 340 prevents the generation of the fourth latch clock signal LCB-OD.

[0148] In timing T38, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic low to logic high. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic high to logic low.

[0149] When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 of the even-odd number sensing circuit 255-1 generates a second even-number flag signal EV-FL2 ​​whose level changes from logic high to logic low. When the pulse level of the inverted command clock signal MCLKB changes from logic high to logic low, the second flag signal generation circuit 320 generates a second odd-number flag signal OD-FL2 whose level changes from logic low to logic high.

[0150] When a pulse of the command clock signal MCLK with a logic high level is generated and a first odd-number flag signal OD-FL1 with a logic high level is generated, the first logic circuit 330 of the masking circuit 255-2 generates a second latch clock signal LC-OD with a logic high level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 generates a first latch clock signal LC-EV with a logic low level. When a pulse of the command clock signal MCLK with a logic high level is generated and a first even-number flag signal EV-FL1 with a logic low level is generated, the first logic circuit 330 prevents the generation of the first latch clock signal LC-EV.

[0151] In timing T39, when the pulse level of the clock signal CLK changes from logic low to logic high, the first command clock signal generation circuit 251-1 of the command clock signal generation circuit 251 generates a command clock signal MCLK whose pulse level changes from logic high to logic low. When the pulse level of the clock signal CLK changes from logic low to logic high, the second command clock signal generation circuit 251-3 of the command clock signal generation circuit 251 generates an inverted command clock signal MCLKB whose pulse level changes from logic low to logic high.

[0152] When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 of the even-odd number sensing circuit 255-1 generates a first even-number flag signal EV-FL1 whose level changes from logic low to logic high. When the pulse level of the command clock signal MCLK changes from logic high to logic low, the first flag signal generation circuit 310 generates a first odd-number flag signal OD-FL1 whose level changes from logic high to logic low.

[0153] When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second odd-number flag signal OD-FL2 with a logic high level is generated, the second logic circuit 340 of the masking circuit 255-2 generates a fourth latch clock signal LCB-OD with a logic high level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 generates a third latch clock signal LCB-EV with a logic low level. When a pulse of the inverted command clock signal MCLKB with a logic high level is generated and a second even-number flag signal EV-FL2 ​​with a logic low level is generated, the second logic circuit 340 prevents the generation of the third latch clock signal LCB-EV.

[0154] The following is for reference. Figure 14 The description describes the operation of generating first to eighth transmission command addresses TD1 to TD8 with a second valid data window by increasing the first valid data window of the rising command address CAR and the valid data window of the falling command address CAF based on the first to fourth latch clock signals LC-EV, LC-OD, LCB-EV and LCB-OD in the interface area.

[0155] At timing T41, the command address input circuit 270 generates a first transfer command address TD1 by latching the rising command address CAR with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The command address input circuit 270 generates a second transfer command address TD2 by latching the falling command address CAF with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The first transfer command address TD1 is derived from the first bit ECA of the external command address. <1> Generate. The second transmission command address TD2 is generated from the second bit ECA of the external command address. <2> Generation. Timing T21 is set to... Figure 11 The timing is the same as that of timing T12.

[0156] At timing T42, the command address input circuit 270 generates the third transfer command address TD3 by latching the rising command address CAR with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The command address input circuit 270 generates the fourth transfer command address TD4 by latching the falling command address CAF with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The third transfer command address TD3 is derived from the third bit ECA of the external command address. <3> Generate. The fourth transmission command address TD4 is generated from the fourth bit (ECA) of the external command address. <4> Generate. Timing T42 is set to... Figure 13 The timing is the same as that of T33 in the original.

[0157] At timing T43, the command address input circuit 270 generates the fifth transfer command address TD5 by latching the rising command address CAR with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The command address input circuit 270 generates the sixth transfer command address TD6 by latching the falling command address CAF with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The fifth transfer command address TD5 is derived from the fifth bit ECA of the external command address. <5> Generate. The sixth transmission command address TD6 is generated from the sixth bit of the external command address, ECA. <6> Generate. Timing T43 is set to... Figure 13 The timing is the same as that of T34 in the original text.

[0158] At timing T44, the command address input circuit 270 generates the seventh transfer command address TD7 by latching the rising command address CAR with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The command address input circuit 270 generates the eighth transfer command address TD8 by latching the falling command address CAF with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The seventh transfer command address TD7 is derived from the seventh bit ECA of the external command address. <7> Generate. The eighth transmission command address TD8 is generated from the eighth bit of the external command address (ECA). <8> Generate. Timing T44 is set to... Figure 13 The timing is the same as that of T35 in the system.

[0159] At timing T45, the command address input circuit 270 generates a first transfer command address TD1 by latching the rising command address CAR with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The command address input circuit 270 generates a second transfer command address TD2 by latching the falling command address CAF with a first valid data window, synchronized with the first latch clock signal LC-EV generated at a logic high level. The first transfer command address TD1 is derived from the ninth bit ECA of the external command address. <9> Generate. The second transmission command address TD2 is generated from the tenth bit (ECA) of the external command address. <10> Generate. Timing T45 is set to... Figure 13 The timing is the same as that of timing T36 in the original text.

[0160] At timing T46, the command address input circuit 270 generates the third transfer command address TD3 by latching the rising command address CAR with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The command address input circuit 270 generates the fourth transfer command address TD4 by latching the falling command address CAF with a first valid data window, synchronized with the third latch clock signal LCB-EV generated at a logic high level. The third transfer command address TD3 is derived from the eleventh bit ECA of the external command address. <11> Generate. The fourth transmission command address TD4 is generated from the twelfth bit (ECA) of the external command address. <12> Generate. Timing T46 is set to... Figure 13 The timing is the same as that of timing T37 in the system.

[0161] At timing T47, the command address input circuit 270 generates the fifth transfer command address TD5 by latching the rising command address CAR with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The command address input circuit 270 generates the sixth transfer command address TD6 by latching the falling command address CAF with a first valid data window, synchronized with the second latch clock signal LC-OD generated at a logic high level. The fifth transfer command address TD5 is derived from the thirteenth bit ECA of the external command address. <13> Generate. The sixth transmission command address TD6 is generated from the fourteenth bit of the external command address, ECA. <14> Generate. Timing T47 is set to... Figure 13 The timing is the same as that of T38 in the system.

[0162] At timing T48, the command address input circuit 270 generates the seventh transfer command address TD7 by latching the rising command address CAR with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The command address input circuit 270 generates the eighth transfer command address TD8 by latching the falling command address CAF with a first valid data window, synchronized with the fourth latch clock signal LCB-OD generated at a logic high level. The seventh transfer command address TD7 is derived from the fifteenth bit ECA of the external command address. <15> Generate. The eighth transmission command address TD8 is generated from the sixteenth bit of the external command address, ECA. <16> Generate. Timing T48 is set to... Figure 13 The timing is the same as that of T39 in the original.

[0163] like Figure 14As shown, the first transmission command address TD1 and the second transmission command address TD2 are generated during timings T41 to T45 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO. The third transmission command address TD3 and the fourth transmission command address TD4 are generated during timings T42 to T46 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO. The fifth transmission command address TD5 and the sixth transmission command address TD6 are generated during timings T43 to T47 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO. The seventh transmission command address TD7 and the eighth transmission command address TD8 are generated during timings T44 to T48 (i.e., the second valid data window) and output to the via region 290 via the command input / output line MIO.

[0164] According to an embodiment of the present disclosure, the storage device 17 of the storage system 1 generates a command address by increasing the effective data window of the command address in the interface region of the base chip 120 with a long load, and provides the command address with the increased effective data window to multiple core chips without the need for a repeater to transmit the command address, thereby reducing the power consumption used in the repeater. Since the base chip 120 generates the command address by increasing the effective data window of the command address without using a divider clock for latching and transmitting the command address, and provides the command address with the increased effective data window to multiple core chips, the storage device 17 of the storage system 1 can ensure the margin of the latching circuit.

[0165] Figure 15 This is a diagram illustrating the arrangement of the interface region PHY and via region TSV included in the base chip 120 according to an embodiment of the present disclosure.

[0166] The first via region 1st TSV can be set on the top side TOP of the base chip 120 on the Y-axis.

[0167] The first via region 1st TSV can be configured to contain multiple vias. The first via region 1st TSV can output the first to eighth transmission command addresses TD1 to TD8 (i.e., the second valid data window) to multiple core chips 121-1 to 121-L through multiple vias.

[0168] The first interface region 1st PHY can be set along the first direction DIR1 based on the first via region 1st TSV. The first direction DIR1 can be set to a direction downward from the top side TOP.

[0169] The first interface region 1st PHY may include a first command input / output line MIO1 with a long load. The first interface region 1st PHY may include a clock buffer circuit 210, an address buffer circuit 230, a frequency divider circuit 250, and a command address input circuit 270. The command address input circuit 270 can output the first to eighth transmission command addresses TD1 to TD8 (i.e., the second valid data window) to the first via region 1st TSV through the first command input / output line MIO1 with a long load.

[0170] The second interface area 2nd PHY can be set from the first interface area 1st PHY along the first direction DIR1.

[0171] The second interface region 2nd PHY may include a second command input / output line MIO2 with a long load. The second interface region 2nd PHY may include a clock buffer circuit 210, an address buffer circuit 230, a frequency divider circuit 250, and a command address input circuit 270. The command address input circuit 270 can output the first to eighth transmission command addresses TD1 to TD8 (i.e., the second valid data window) to the second via region 2nd TSV via the second command input / output line MIO2 with a long load.

[0172] The second via region 2nd TSV can be set from the second interface region 2nd PHY along the first direction DIR1.

[0173] The second via region 2nd TSV can be configured to contain multiple vias. The second via region 2nd TSV can output the first to eighth transmission command addresses TD1 to TD8 (i.e., the second valid data window) to multiple core chips 121-1 to 121-L through multiple vias.

[0174] According to one embodiment, the first via region 1st TSV can be disposed on the bottom BOTTOM of the base chip 120 along the Y-axis. When the first via region 1st TSV is disposed on the bottom BOTTOM of the base chip 120 along the Y-axis, the first interface region 1st PHY, the second interface region 2nd PHY, and the second via region 2nd TSV can be sequentially disposed based on the second direction DIR2 of the first via region 1st TSV. The second direction DIR2 can be set to an upward direction from the bottom BOTTOM.

[0175] According to one embodiment, the first via region 1st TSV can be positioned on the left LEFT of the base chip 120 along the X-axis. When the first via region 1st TSV is positioned on the left LEFT of the base chip 120 along the X-axis, the first interface region 1st PHY, the second interface region 2nd PHY, and the second via region 2nd TSV can be sequentially positioned along a third direction DIR3 based on the first via region 1st TSV. The third direction DIR3 can be set to the direction from the left LEFT to the right.

[0176] According to one embodiment, the first via region 1st TSV can be positioned on the right side of the base chip 120 along the X-axis. When the first via region 1st TSV is positioned on the right side of the base chip 120 along the X-axis, the first interface region 1st PHY, the second interface region 2nd PHY, and the second via region 2nd TSV can be sequentially positioned along a fourth direction DIR4 based on the first via region 1st TSV. The fourth direction DIR4 can be set to a direction from the right side to the left.

[0177] The positions of the first via region 1st TSV, the first interface region 1st PHY, the second interface region 2nd PHY, and the second via region 2nd TSV may differ depending on the embodiment.

[0178] As described above, the storage device 17 of the storage system 1 according to an embodiment of the present disclosure generates a command address by increasing the effective data window of the command address in the interface region of the base chip 120 with a long load, and provides the command address with the increased effective data window to multiple core chips without the need for a repeater to transmit the command address, thereby reducing the power consumption used in the repeater. According to an embodiment of the present disclosure, since the base chip 120 generates the command address by increasing the effective data window of the command address without using a divider clock for latching and transmitting the command address, and provides the command address with the increased effective data window to multiple core chips, the storage device 17 of the storage system 1 can ensure the margin of the latching circuit.

Claims

1. A semiconductor chip, comprising: A frequency divider circuit generates multiple latching clock signals based on a command clock signal generated synchronously with the clock signal and an inverted command clock signal. as well as The command address input circuit generates a first set of transmission command addresses with a second valid data window by synchronously latching the input rising command address and falling command address with a first valid data window with the first set of latch clock signals among the plurality of latch clock signals. And by synchronously latching the input rising command address and the falling command address having the first valid data window with the second set of latch clock signals among the plurality of latch clock signals, a second set of transmission command addresses with the second valid data window is generated.

2. The semiconductor chip according to claim 1, wherein, The first set of transmission command addresses and the second set of transmission command addresses are output to the via through the command input / output line.

3. The semiconductor chip according to claim 1, wherein, The clock signal includes an inverted clock signal.

4. The semiconductor chip according to claim 1, wherein: The first valid data window is set to the first period of the clock signal, and The second valid data window is set to the fourth cycle of the clock signal.

5. The semiconductor chip according to claim 1, wherein: When the pulse of the command clock signal is generated, the frequency divider circuit prevents the generation of one of the latch clock signals from the first group and the second group, and When the pulse of the inverted command clock signal is generated, the frequency divider circuit prevents the generation of one of the first group of latch clock signals and the second group of latch clock signals.

6. The semiconductor chip according to claim 1, wherein, The frequency divider circuit includes: A command clock signal generation circuit generates the command clock signal and the inverted command clock signal, wherein the command clock signal and the inverted command clock signal are generated synchronously with the clock signal; and A latch clock signal generation circuit generates a first set of latch clock signals and a second set of latch clock signals, which are generated based on the pulses of the command clock signal and the pulses of the inverted command clock signal.

7. The semiconductor chip according to claim 6, wherein, The command clock signal generation circuit includes: A first command clock signal generation circuit generates the command clock signal, which is initialized to a first logic level by a power-down signal and switched synchronously with the inverted clock signal; and The second command clock signal generation circuit generates the inverted command clock signal, which is initialized to a second logic level by the power-down signal and switched synchronously with the inverted clock signal.

8. The semiconductor chip according to claim 7, wherein, The first command clock signal generation circuit includes: A first initialization circuit, wherein: when the power-down signal is enabled, the command clock signal is initialized to the first logic level by driving the command clock signal with ground voltage; and A first trigger flip-flop causes the command clock signal to switch when the inverted clock signal is generated.

9. The semiconductor chip according to claim 7, wherein, The second command clock signal generation circuit includes: The second initialization circuit, wherein: when the power-down signal is enabled, it initializes the inverted command clock signal to the second logic level by driving the inverted command clock signal with the power supply voltage; and The second trigger causes the inverted command clock signal to switch when the inverted clock signal is generated.

10. The semiconductor chip according to claim 6, wherein, The latch clock signal generation circuit includes: An even / odd number sensing circuit, which generates a first even number flag signal, a second even number flag signal, a first odd number flag signal, and a second odd number flag signal by detecting the timing sequence of the pulses of the command clock signal and the pulses of the inverted command clock signal input; and The masking circuit generates the first set of latch clock signals and the second set of latch clock signals based on the logic levels of the first even-number flag signal and the second even-number flag signal, and the logic levels of the first odd-number flag signal and the second odd-number flag signal, when the pulse of the command clock signal and the pulse of the inverted command clock signal are generated.

11. The semiconductor chip according to claim 10, wherein, The even / odd number sensing circuit includes: A first flag signal generation circuit generates a first even-numbered flag signal and a first odd-numbered flag signal, wherein the first even-numbered flag signal and the first odd-numbered flag signal are generated based on pulses of the command clock signal; and The second flag signal generation circuit generates the second even flag signal and the second odd flag signal, which are generated based on the pulses of the inverted command clock signal.

12. The semiconductor chip according to claim 11, wherein, The first flag signal generation circuit includes: A first even-number sensing circuit generates a first even-number flag signal, the first even-number flag signal being switched when the command clock signal having a first logic level is generated; and A first odd-number sensing circuit generates a first odd-number flag signal, which is switched by latching a first even-number flag signal when a command clock signal having the first logic level is generated.

13. The semiconductor chip according to claim 11, wherein, The second flag signal generation circuit includes: A second even-number sensing circuit generates a second even-number flag signal, which is switched when the inverted command clock signal having a first logic level is generated; and The second odd-number sensing circuit generates the second odd-number flag signal, which is switched by latching the second even-number flag signal when the inverted command clock signal having the first logic level is generated.

14. The semiconductor chip according to claim 10, wherein, The masking circuit includes: A first logic circuit, wherein, upon generation of a pulse of the command clock signal, based on the logic level of the first even-number flag signal and the logic level of the first odd-number flag signal, generates one of the first set of latch clock signals and one of the second set of latch clock signals; and The second logic circuit generates one of the first set of latch clock signals and one of the second set of latch clock signals based on the logic level of the second even-number flag signal and the logic level of the second odd-number flag signal when the pulse of the inverted command clock signal is generated.

15. A storage device, comprising: The base chip, in its interface region, generates rising and falling command addresses with a first valid data window by synchronously latching an external command address with a clock signal generated from an external clock signal and an inverted clock signal; generates multiple transmission command addresses with a second valid data window by synchronously latching the rising and falling command addresses with multiple latching clock signals generated based on pulses of the inverted clock signal; and outputs the multiple transmission command addresses to the core chip through a via region. The core chip outputs data to the base chip by receiving the multiple transmission command addresses.

16. The storage device according to claim 15, wherein, The interface area outputs the multiple transmission command addresses through command input / output lines with long loads.

17. The storage device according to claim 15, wherein, The interface area includes: A frequency divider circuit generates the plurality of latched clock signals, which are generated based on pulses of a command clock signal generated synchronously with the inverted clock signal and pulses of the inverted command clock signal; and The command address input circuit generates a first set of transmission command addresses with a second valid data window by synchronously latching the input rising command address and the falling command address having the first valid data window with a first set of latch clock signals among the plurality of latch clock signals; and generates a second set of transmission command addresses with the second valid data window by synchronously latching the input rising command address and the falling command address having the first valid data window with a second set of latch clock signals among the plurality of latch clock signals.

18. The storage device according to claim 17, wherein, The frequency divider circuit includes: A command clock signal generation circuit, which generates the command clock signal and the inverted command clock signal synchronously with the inverted clock signal; and A latch clock signal generation circuit generates the plurality of latch clock signals based on pulses of the command clock signal and pulses of the inverted command clock signal.

19. The storage device according to claim 18, wherein, The command clock signal generation circuit includes: A first command clock signal generation circuit generates the command clock signal, which is initialized to a first logic level by a power-down signal and switched synchronously with the inverted clock signal; and The second command clock signal generation circuit generates the inverted command clock signal, which is initialized to a second logic level by the power-down signal and switched synchronously with the inverted clock signal.

20. The storage device according to claim 19, wherein, The first command clock signal generation circuit includes: A first initialization circuit, wherein: when the power-down signal is enabled, the command clock signal is initialized to the first logic level by driving the command clock signal with ground voltage; and A first trigger flip-flop causes the command clock signal to switch when the inverted clock signal is generated.

21. The storage device according to claim 19, wherein, The second command clock signal generation circuit includes: The second initialization circuit, wherein: when the power-down signal is enabled, it initializes the inverted command clock signal to the second logic level by driving the inverted command clock signal with the power supply voltage; and The second trigger causes the inverted command clock signal to switch when the inverted clock signal is generated.

22. The storage device according to claim 18, wherein, The latch clock signal generation circuit includes: An even / odd number sensing circuit, which generates a first even number flag signal, a second even number flag signal, a first odd number flag signal, and a second odd number flag signal by detecting the timing sequence of the pulses of the command clock signal and the pulses of the inverted command clock signal input; and A masking circuit that, when the pulse of the command clock signal and the pulse of the inverted command clock signal are generated, generates the plurality of latch clock signals based on the logic levels of the first even-number flag signal and the second even-number flag signal, and the logic levels of the first odd-number flag signal and the second odd-number flag signal.

23. The storage device according to claim 22, wherein, The even / odd number sensing circuit includes: A first flag signal generation circuit generates a first even-numbered flag signal and a first odd-numbered flag signal, wherein the first even-numbered flag signal and the first odd-numbered flag signal are generated based on pulses of the command clock signal; and The second flag signal generation circuit generates the second even flag signal and the second odd flag signal, which are generated based on the pulses of the inverted command clock signal.

24. The storage device according to claim 23, wherein, The first flag signal generation circuit includes: A first even-number sensing circuit generates a first even-number flag signal, the first even-number flag signal being switched when the command clock signal having a first logic level is generated; and A first odd-number sensing circuit generates a first odd-number flag signal, which is switched by latching a first even-number flag signal when a command clock signal having the first logic level is generated.

25. The storage device according to claim 23, wherein, The second flag signal generation circuit includes: A second even-number sensing circuit generates a second even-number flag signal, which is switched when the inverted command clock signal having a first logic level is generated; and The second odd-number sensing circuit generates the second odd-number flag signal, which is switched by latching the second even-number flag signal when the inverted command clock signal having the first logic level is generated.

26. The storage device according to claim 22, wherein, The masking circuit includes: A first logic circuit, wherein, upon generation of a pulse of the command clock signal, based on the logic level of the first even-number flag signal and the logic level of the first odd-number flag signal, generates one of the first set of latch clock signals and one of the second set of latch clock signals; and The second logic circuit generates one of the first set of latch clock signals and one of the second set of latch clock signals based on the logic level of the second even-number flag signal and the logic level of the second odd-number flag signal when the pulse of the inverted command clock signal is generated.

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